diff --git a/master/master/lib/logger.c b/master/master/lib/logger.c --- a/master/master/lib/logger.c +++ b/master/master/lib/logger.c @@ -33,7 +33,7 @@ void logger_setup() PORTA |= 0b00000001; return; } -return; + //check for SD exist/power/ready END /* open first partition */ @@ -93,7 +93,9 @@ return; //simplified version of console BEGIN - char buffer[24]; + char buffer[24] = "Omg this is cool, haha!"; + buffer[23] = 0xd; + buffer[24] = 0xa; /* search file in current directory and open it */ struct fat_file_struct* fd = open_file_in_dir(fs, dd, "data.csv"); //logger.h @@ -111,18 +113,7 @@ return; fat_close_file(fd); return; } - - buffer[0] = 'H'; - buffer[1] = 'e'; - buffer[2] = 'l'; - buffer[3] = 'l'; - buffer[4] = 'o'; - buffer[5] = 'w'; - buffer[6] = 'o'; - buffer[7] = 'r'; - buffer[8] = 'l'; - buffer[9] = 'd'; - + /* read text from the shell and write it to the file */ uint8_t data_len = sizeof(buffer); diff --git a/master/master/lib/sd/sd_raw.c b/master/master/lib/sd/sd_raw.c --- a/master/master/lib/sd/sd_raw.c +++ b/master/master/lib/sd/sd_raw.c @@ -183,23 +183,25 @@ uint8_t sd_raw_init() configure_pin_miso(); unselect_card(); + + // initialize SPI with lowest frequency; max. 400kHz during identification mode of card + SPCR0 = (0 << SPIE0) | // SPI Interrupt Enable + (1 << SPE0) | // SPI Enable + (0 << DORD0) | // Data Order: MSB first + (1 << MSTR0) | // Master mode + (0 << CPOL0) | // Clock Polarity: SCK low when idle + (0 << CPHA0) | // Clock Phase: sample on rising SCK edge + (1 << SPR10); // Clock Frequency: f_OSC / 128 + //(1 << SPR00); // commentnig this out means /64, which gives over 100khz as required + SPSR0 &= ~(1 << SPI2X0); // No doubled clock frequency - /* initialize SPI with lowest frequency; max. 400kHz during identification mode of card */ - SPCR0 = (0 << SPIE0) | /* SPI Interrupt Enable */ - (1 << SPE0) | /* SPI Enable */ - (0 << DORD0) | /* Data Order: MSB first */ - (1 << MSTR0) | /* Master mode */ - (0 << CPOL0) | /* Clock Polarity: SCK low when idle */ - (0 << CPHA0) | /* Clock Phase: sample on rising SCK edge */ - (1 << SPR10); /* Clock Frequency: f_OSC / 128 */ - //(1 << SPR00); // commentnig this out means /64, which gives over 100khz as required - SPSR0 &= ~(1 << SPI2X0); /* No doubled clock frequency */ -// transmit a char - while ( ! ( SPSR0 & ( 1 << SPIF0 ))); // wait for completion of - SPDR0 = 'c'; // begin transmission - +/* + while(1) { + SPDR0 = 'a'; //Load byte to Data register + while(!(SPSR0 & (1<