seniordesign-firmware Changeset - c273f4602167

Changeset - c273f4602167

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ethanzonca@CL-SEC241-08.cedarville.edu - 12 years ago 2012-10-29 20:38:23
ethanzonca@CL-SEC241-08.cedarville.edu

AFSK is now properly transmitting the first bit of each byte requested to be sent (or so I think...)

2 files changed with 119 insertions and 34 deletions:

master/master/lib/afsk.c

117

master/master/lib/afsk.h

0 comments (0 inline, 0 general)

master/master/lib/afsk.c

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@@ @@ -20,11 +20,13 @@ @@
 #define F_CPU 11059200
 #include <stdint.h>
 #include <stdbool.h>
 #include <avr/io.h>
 #include <avr/interrupt.h>
 #include <util/delay.h>
 #include <avr/pgmspace.h>
 PROGMEM extern const uint8_t afsk_sine_table[512] = {
 , 129, 130, 132, 133, 135, 136, 138, 139, 141, 143, 144, 146, 147, 149, 150, 152, 153, 155, 156, 158,
 , 161, 163, 164, 166, 167, 168, 170, 171, 173, 174, 176, 177, 179, 180, 182, 183, 184, 186, 187, 188,
@@ @@ -90,46 +92,128 @@ void afsk_setup() { @@
 	DDRD = 0xff;
 	PORTD = 0xff;
 	// todo: init radio, maybe in main
 	sei();
+}
 void afsk_test() {
 	afsk_timer_start();
 	_delay_ms(3);
 	phasedelta = 1800;
 	_delay_ms(3);
 	phasedelta = 3300;
 	_delay_ms(3);
 	phasedelta = 1800;
 	_delay_ms(3);
 	phasedelta = 3300;
 	_delay_ms(3);
 	phasedelta = 1800;
 	_delay_ms(3);
 	phasedelta = 3300;
 	_delay_ms(3);
 	phasedelta = 1800;
 	_delay_ms(3);
 	phasedelta = 3300;
 	_delay_ms(3);
 	phasedelta = 1800;
 	_delay_ms(3);
 	phasedelta = 3300;
 	_delay_ms(3);
 	phasedelta = 1800;
 	_delay_ms(3);
 	phasedelta = 3300;
 	afsk_timer_stop();
 	_delay_ms(400);
 	uint8_t flap[32] = "somethingawesomesomethingawesome";
 	afsk_send(flap, 32);
 	afsk_start();
 	while(afsk_busy());
 	_delay_ms(500);
+}
 // constants
 #define MODEM_CLOCK_RATE F_CPU
 #define PLAYBACK_RATE MODEM_CLOCK_RATE / 256  // Fast PWM
 #define BAUD_RATE 1200
 //#define SAMPLES_PER_BAUD PLAYBACK_RATE / BAUD_RATE // = 36
 #define SAMPLES_PER_BAUD 36
 // phase offset of 1800 gives ~1900 Hz
 // phase offset of 3300 gives ~2200 Hz
 ISR(TIMER2_OVF_vect) {
 	phase = (phase + phasedelta);
 	OCR2B = afsk_read_sample((phase >> 7) & (TABLE_SIZE - 1));
 	return;
 #define PHASE_DELTA_1200 1800
 #define PHASE_DELTA_2200 2200
 // Module globals
 volatile unsigned char current_byte;
 volatile unsigned char current_sample_in_baud;    // 1 bit = SAMPLES_PER_BAUD samples
 volatile bool go = false;
 volatile unsigned int packet_pos;                 // Next bit to be sent out
 volatile unsigned int afsk_packet_size = 10;
 volatile const uint8_t *afsk_packet;
 void afsk_send(const uint8_t *buffer, int len)
+{
 	afsk_packet_size = len;
 	afsk_packet = buffer;
+}
 int afsk_busy()
+{
 	return go;
+}
 void afsk_start()
+{
 	phasedelta = PHASE_DELTA_1200;
 	phase = 0;
 	packet_pos = 0;
 	current_sample_in_baud = 0;
 	go = true;
 	// Key the radio
 	afsk_ptt_on();
 	// Start transmission
 	afsk_timer_start();
+}
 afsk_ptt_off() {
+}
 afsk_ptt_on() {
+}
 ISR(TIMER2_OVF_vect)
+{
 	if (go) {
 		// If done sending packet
 		if (packet_pos == afsk_packet_size) {
 			go = false;         // End of transmission
 			afsk_timer_stop();  // Disable modem
 			afsk_ptt_off();    // Release PTT
 			return; // done
+		}
 		// If sent SAMPLES_PER_BAUD already, go to the next bit
 		if (current_sample_in_baud == 0) {    // Load up next bit
 			if ((packet_pos & 7) == 0) {          // Load up next byte
 				current_byte = afsk_packet[packet_pos >> 3];
+			}
 			else {
 				current_byte = current_byte / 2;  // ">>1" forces int conversion
+			}
 			if ((current_byte & 1) == 0) {
 				// Toggle tone (1200 <> 2200)
 				phasedelta ^= (PHASE_DELTA_1200 ^ PHASE_DELTA_2200);
+			}
+		}
 		phase += phasedelta;
 		uint8_t s = afsk_read_sample((phase >> 7) & (TABLE_SIZE - 1));
 		afsk_output_sample(s);
 		if(++current_sample_in_baud == SAMPLES_PER_BAUD) {
 			// sounds fun when this is commented out... but why??!?!
 			//current_sample_in_baud = 0;
 			packet_pos++;
+		}
+	}
+}
 void afsk_output_sample(uint8_t s) {
 	OCR2B = s;
+}
 void afsk_timer_start()
@@ @@ -144,7 +228,8 @@ void afsk_timer_start() @@
 void afsk_timer_stop()
+{
 	// Output 0v (after DC coupling)
 	// Resting duty cycle
 	// Output 0v (could be 255/2, which is 0v after coupling... doesn't really matter)
 	OCR2B = 0x00;
 	// Disable playback interrupt

master/master/lib/afsk.h

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Show inline comments

@@ @@ -11,7 +11,7 @@ @@
 void afsk_setup();
 void afsk_test();
 void afsk_timer_start();
 void afsk_timer_stop();
 void afsk_start();
 void afsk_stop();
 #endif /* AFSK_H_ */
@@ \ No newline at end of file @@

0 comments (0 inline, 0 general)