Changeset - dc66341db814
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0 5 2
ethanzonca@CL-SEC241-08.cedarville.edu - 13 years ago 2012-11-19 20:10:19
ethanzonca@CL-SEC241-08.cedarville.edu
Added watchdog timer library, additional logger testing
7 files changed with 77 insertions and 31 deletions:
0 comments (0 inline, 0 general)
master/master/lib/afsk.c
Show inline comments
 
@@ -32,202 +32,195 @@ PROGMEM extern const uint8_t afsk_sine_t
 
  133, 132, 130, 129, 127, 125, 124, 122, 121, 119, 118, 116, 115, 113, 111, 110, 108, 107, 105, 104, 102, 
 
  101,  99,  98,  96,  95,  93,  91,  90,  88,  87,  86,  84,  83,  81,  80,  78,  77,  75,  74,  72,  71, 
 
   70,  68,  67,  66,  64,  63,  61,  60,  59,  57,  56,  55,  54,  52,  51,  50,  49,  47,  46,  45,  44, 
 
   43,  41,  40,  39,  38,  37,  36,  35,  34,  33,  31,  30,  29,  28,  27,  26,  26,  25,  24,  23,  22, 
 
   21,  20,  19,  18,  18,  17,  16,  15,  15,  14,  13,  12,  12,  11,  10,  10,   9,   9,   8,   7,   7, 
 
    6,   6,   5,   5,   5,   4,   4,   3,   3,   3,   2,   2,   2,   1,   1,   1,   1,   0,   0,   0,   0, 
 
    0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   1,   1,   1,   1, 
 
    2,   2,   2,   3,   3,   3,   4,   4,   5,   5,   5,   6,   6,   7,   7,   8,   9,   9,  10,  10,  11, 
 
   12,  12,  13,  14,  15,  15,  16,  17,  18,  18,  19,  20,  21,  22,  23,  24,  25,  26,  26,  27,  28, 
 
   29,  30,  31,  33,  34,  35,  36,  37,  38,  39,  40,  41,  43,  44,  45,  46,  47,  49,  50,  51,  52, 
 
   54,  55,  56,  57,  59,  60,  61,  63,  64,  66,  67,  68,  70,  71,  72,  74,  75,  77,  78,  80,  81, 
 
   83,  84,  86,  87,  88,  90,  91,  93,  95,  96,  98,  99, 101, 102, 104, 105, 107, 108, 110, 111, 113, 
 
  115, 116, 118, 119, 121, 122, 124, 125
 
};
 

	
 
static inline uint8_t afsk_read_sample(int phase)
 
{
 
  return pgm_read_byte_near(afsk_sine_table + phase);
 
}
 

	
 
volatile uint16_t phase = 10;
 
volatile uint16_t phasedelta = 3300;
 
extern const uint16_t TABLE_SIZE = sizeof(afsk_sine_table);
 

	
 
// constants
 
#define MODEM_CLOCK_RATE F_CPU
 
#define PLAYBACK_RATE MODEM_CLOCK_RATE / 256  // Fast PWM
 

	
 
#define BAUD_RATE 1200
 
//#define SAMPLES_PER_BAUD PLAYBACK_RATE / BAUD_RATE // = 36
 
//#define SAMPLES_PER_BAUD 36
 
#define SAMPLES_PER_BAUD 36
 

	
 

	
 
// phase offset of 1800 gives ~1900 Hz
 
// phase offset of 3300 gives ~2200 Hz
 
#define PHASE_DELTA_1200 1800
 
#define PHASE_DELTA_2200 2200
 

	
 
// Module globals
 
volatile unsigned char current_byte;
 
volatile unsigned char current_sample_in_baud;    // 1 bit = SAMPLES_PER_BAUD samples
 
volatile bool go = false;                 
 

	
 
volatile unsigned int packet_pos;                 // Next bit to be sent out
 

	
 

	
 
volatile unsigned int afsk_packet_size = 10;
 
volatile const uint8_t *afsk_packet;
 

	
 

	
 

	
 

	
 

	
 

	
 
void afsk_ptt_off() {
 
	// turn ptt off
 
}
 

	
 
void afsk_ptt_on() {
 
	// turn the ptt on... possibly delay based on spec
 
}
 

	
 

	
 

	
 

	
 

	
 

	
 

	
 
ISR(TIMER2_OVF_vect) 
 
{
 
	if (go) {
 

	
 
		// If done sending packet
 
		if (packet_pos == afsk_packet_size) {
 
			go = false;         // End of transmission
 
			afsk_timer_stop();  // Disable modem
 
			afsk_ptt_off();    // Release PTT
 
			return; // done
 
		}
 

	
 
		// If sent SAMPLES_PER_BAUD already, go to the next bit
 
		if (current_sample_in_baud == 0) {    // Load up next bit
 
			if ((packet_pos & 7) == 0) {          // Load up next byte
 
				current_byte = afsk_packet[packet_pos >> 3];
 
			}				
 
			else {
 
				current_byte = current_byte / 2;  // ">>1" forces int conversion
 
			}			
 
			if ((current_byte & 1) == 0) {
 
				// Toggle tone (1200 <> 2200)
 
				phasedelta ^= (PHASE_DELTA_1200 ^ PHASE_DELTA_2200);
 
			}
 
		}
 
	
 
		phase += phasedelta;
 
		uint8_t s = afsk_read_sample((phase >> 7) & (TABLE_SIZE - 1));
 
		afsk_output_sample(s);
 

	
 
		if(++current_sample_in_baud == SAMPLES_PER_BAUD) {
 
			// sounds fun when this is commented out... but why??!?!
 
			current_sample_in_baud = 0;
 
			packet_pos++;
 
		}
 
		
 
	}
 
}	
 

	
 
void afsk_output_sample(uint8_t s) {
 
	OCR2B = s;
 
}
 

	
 
void afsk_timer_start()
 
{
 
	// Clear the overflow flag, so that the interrupt doesn't go off
 
	// immediately and overrun the next one (p.163).
 
	TIFR2 |= _BV(TOV2);       // Yeah, writing a 1 clears the flag.
 

	
 
	// Enable interrupt when TCNT2 reaches TOP (0xFF) (p.151, 163)
 
	TIMSK2 |= _BV(TOIE2);
 
}
 

	
 
void afsk_timer_stop()
 
{
 
	// Resting duty cycle
 
	// Output 0v (could be 255/2, which is 0v after coupling... doesn't really matter)
 
	OCR2B = 0x80;
 

	
 
	// Disable playback interrupt
 
	TIMSK2 &= ~_BV(TOIE2);
 
}
 

	
 

	
 

	
 

	
 

	
 
// External
 

	
 
void afsk_start()
 
{
 
	phasedelta = PHASE_DELTA_1200;
 
	phase = 0;
 
	packet_pos = 0;
 
	current_sample_in_baud = 0;
 
	go = true;
 

	
 
	// Key the radio
 
	afsk_ptt_on();
 

	
 
	// Start transmission
 
	afsk_timer_start();
 
}
 

	
 
int afsk_busy()
 
{
 
	return go;
 
}
 

	
 
void afsk_send(const uint8_t *buffer, int len)
 
{
 
	afsk_packet_size = len;
 
	afsk_packet = buffer;
 
}
 

	
 

	
 
void afsk_setup() {
 
	
 
	// Source timer2 from clkIO (datasheet p.164)
 
	ASSR &= ~(_BV(EXCLK) | _BV(AS2));
 

	
 
	// Set fast PWM mode with TOP = 0xff: WGM22:0 = 3  (p.150)
 
	TCCR2A |= _BV(WGM21) | _BV(WGM20);
 
	TCCR2B &= ~_BV(WGM22);
 

	
 
	// Do non-inverting PWM on pin OC2B (arduino pin 3) (p.159).
 
	// OC2A (arduino pin 11) stays in normal port operation:
 
	// COM2B1=1, COM2B0=0, COM2A1=0, COM2A0=0
 
	TCCR2A = (TCCR2A | _BV(COM2B1)) & ~(_BV(COM2B0) | _BV(COM2A1) | _BV(COM2A0));
 

	
 
	// No prescaler (p.162)
 
	TCCR2B = (TCCR2B & ~(_BV(CS22) | _BV(CS21))) | _BV(CS20);
 
	
 
	// Enable interrupt when TCNT2 reaches TOP (0xFF) (p.151, 163)
 
	//TIMSK2 |= _BV(TOIE2);
 
	TIMSK2 |= 0b00000001;
 
	
 
	DDRD = 0xff;
 
	PORTD = 0xff;
 
	
 
	// todo: init radio, maybe in main
 
	
 
	sei();
 
}
 

	
 

	
 
void afsk_test() {
 
	uint8_t flap[26] = {"abcdefghijklmnopqrstuvwxyz"};
 
	afsk_send(flap, sizeof(flap)*8);
 
	afsk_start();
 
	
 
	while(afsk_busy());
 
	_delay_ms(500);
 
}
 
}
 
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master/master/lib/led.c
Show inline comments
 
/*
 
 * led.c
 
 *
 
 * Created: 10/25/2012 3:34:03 PM
 
 *  Author: ethanzonca
 
 */ 
 
 
#include <avr/io.h>
 
 
void led_setup() {
 
	// Configure ports/pins for LEDs
 
	DDRA = 0xff;
 
	PORTA = 0x00;
 
}
 
 
void led_on(uint8_t led) {
 
	// Turn the specified LED on
 
	PORTA |= led;
 
	PORTA |= (1<<led);
 
}
 
 
void led_off(uint8_t led) {
 
	// Turn the specified LED off
 
	PORTA &= ~(led);
 
	PORTA &= ~(1<<led);
 
}
 
 
void led_toggle(uint8_t led) {
 
	// Toggle the specified LED 
 
}
 
\ No newline at end of file
master/master/lib/led.h
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/*
 
 * led.h
 
 *
 
 * Created: 10/25/2012 3:34:10 PM
 
 *  Author: ethanzonca
 
 */ 
 
 
 
#ifndef LED_H_
 
#define LED_H_
 
 
#define POWER 1
 
#define ERROR 2
 
#define STAT 2
 
#define POWER PB2
 
#define ERROR PB1
 
#define STAT PB0
 
#define OK 2
 
 
void led_setup();
 
void led_on(uint8_t led);
 
void led_off(uint8_t led);
 
void led_toggle(uint8_t led);
 
 
 
#endif /* LED_H_ */
master/master/lib/watchdog.c
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new file 100644
 
/*
 
 * watchdog.c
 
 *
 
 * Created: 11/19/2012 6:50:51 PM
 
 *  Author: ethanzonca
 
 */ 
 
 
 
#include <avr/io.h>
 
#include <avr/interrupt.h>
 
#include <avr/wdt.h>
 
 
//initialize watchdog
 
void watchdog_setup(void)
 
{
 
	
 
	cli();
 
	wdt_reset();
 
	// Set change enable bit, enable the WDT
 
	WDTCSR = (1<<WDCE)|(1<<WDE);
 
	// Start watchdog, 4 second timeout
 
	WDTCSR = (1<<WDE)|(1<<WDP3)|(1<<WDP0);
 
	sei();
 
}
 
 
// ISR for watchdog timeout. Not currently used, interrupt is disabled.
 
ISR(WDT_vect)
 
{
 
	PORTA = 0xff;
 
}
master/master/lib/watchdog.h
Show inline comments
 
new file 100644
 
/*
 
 * watchdog.h
 
 *
 
 * Created: 11/19/2012 6:50:58 PM
 
 *  Author: ethanzonca
 
 */ 
 
 
#ifndef WATCHDOG_H
 
#define WATCHDOG_H
 
 
void watchdog_setup(void);
 
 
#endif
 
\ No newline at end of file
master/master/master.c
Show inline comments
 
/*
 
 * Master Firmware
 
 *
 
 * Wireless Observational Modular Aerial Network
 
 * 
 
 * Ethan Zonca
 
 * Matthew Kanning
 
 * Kyle Ripperger
 
 * Matthew Kroening
 
 *
 
 */
 

	
 

	
 
#include "config.h"
 

	
 
#include <avr/io.h>
 
#include <util/delay.h>
 
#include <avr/wdt.h>
 

	
 
#include "lib/serial.h"
 
#include "lib/aprs.h"
 
#include "lib/afsk.h"
 
#include "lib/led.h"
 
#include "lib/logger.h"
 

	
 
#include "lib/watchdog.h"
 
#include "lib/sd/sd_raw_config.h"
 

	
 
void micro_setup() {
 
	// Generic microcontroller config options
 

	
 
}
 

	
 

	
 
int main(void)
 
{
 
	// Initialize
 
	// Initialize. If this takes more than 4 seconds, be sure to reset the WDT
 
	micro_setup();
 
	watchdog_setup();
 
	led_setup();
 

	
 
	//serial_setup(); // Config serial ports
 
	serial_setup(); // Config serial ports
 
	logger_setup(); // this takes a few ms
 
	afsk_setup(); // can take a few ms
 
    
 
	led_on(POWER);
 
	
 
	logger_setup(); // this takes a few ms
 
	
 
	afsk_setup();
 
	while(afsk_busy());
 
    
 
	led_on(4);
 
	uint16_t ctr1 = 0;
 
	uint16_t ctr2 = 255;
 
		
 
	char logbuf[32];
 
	
 
	while(1)
 
    {
 
		led_on(2);
 
		logger_log("123,43,1,2,4,3\n");
 
		led_off(2);
 
		led_on(STAT);
 
		sprintf(logbuf, "%d,%d,%d,%d,%d,%d\n", ctr1,5*ctr1,ctr2, 12*ctr2,43*ctr1,5*ctr2);
 
		logger_log(logbuf);
 
		led_off(STAT);
 
		
 
		// Wait for transmission to complete before starting another.
 
		// Hopefully this will never delay because it should issue on a timed schedule. Software timers!
 
		while(afsk_busy());
 
		aprs_send();
 

	
 
        //serial_SendCommand('0','A',0,0);
 
		aprs_send(); // non-blocking
 
		
 
		ctr1++;
 
		ctr2-=6;
 
		wdt_reset();
 
    }
 
}
 
\ No newline at end of file
master/master/master.cproj
Show inline comments
 
@@ -12,203 +12,209 @@
 
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