Changeset - f6804d996c04
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ethanzonca@CL-SEC241-08.cedarville.edu - 12 years ago 2012-10-30 11:58:17
ethanzonca@CL-SEC241-08.cedarville.edu
AFSK is now (pretty much completely) up and running
1 file changed with 5 insertions and 5 deletions:
0 comments (0 inline, 0 general)
master/master/lib/afsk.c
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@@ -95,16 +95,15 @@ void afsk_setup() {
 
	// todo: init radio, maybe in main
 
	
 
	sei();
 
}
 

	
 
	
 

	
 
void afsk_test() {	
 
	uint8_t flap[32] = "somethingawesomesomethingawesome";
 
	afsk_send(flap, 32);
 
	uint8_t flap[26] = {"abcdefghijklmnopqrstuvwxyz"};
 
	afsk_send(flap, sizeof(flap)*8);
 
	afsk_start();
 
	while(afsk_busy());
 
	_delay_ms(500);
 
}
 

	
 

	
 
@@ -113,12 +112,13 @@ void afsk_test() {
 
// constants
 
#define MODEM_CLOCK_RATE F_CPU
 
#define PLAYBACK_RATE MODEM_CLOCK_RATE / 256  // Fast PWM
 

	
 
#define BAUD_RATE 1200
 
//#define SAMPLES_PER_BAUD PLAYBACK_RATE / BAUD_RATE // = 36
 
//#define SAMPLES_PER_BAUD 36
 
#define SAMPLES_PER_BAUD 36
 

	
 

	
 
// phase offset of 1800 gives ~1900 Hz
 
// phase offset of 3300 gives ~2200 Hz
 
#define PHASE_DELTA_1200 1800
 
@@ -202,13 +202,13 @@ ISR(TIMER2_OVF_vect)
 
		phase += phasedelta;
 
		uint8_t s = afsk_read_sample((phase >> 7) & (TABLE_SIZE - 1));
 
		afsk_output_sample(s);
 

	
 
		if(++current_sample_in_baud == SAMPLES_PER_BAUD) {
 
			// sounds fun when this is commented out... but why??!?!
 
			//current_sample_in_baud = 0;
 
			current_sample_in_baud = 0;
 
			packet_pos++;
 
		}
 
		
 
	}
 
}	
 

	
 
@@ -227,11 +227,11 @@ void afsk_timer_start()
 
}
 

	
 
void afsk_timer_stop()
 
{
 
	// Resting duty cycle
 
	// Output 0v (could be 255/2, which is 0v after coupling... doesn't really matter)
 
	OCR2B = 0x00;
 
	OCR2B = 0x80;
 

	
 
	// Disable playback interrupt
 
	TIMSK2 &= ~_BV(TOIE2);
 
}
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