rlMinMicroViaOuter = 4mil

rlMaxMicroViaOuter = 20mil

rlMinMicroViaInner = 4mil

rlMaxMicroViaInner = 20mil

psTop = -1

psBottom = -1

psFirst = -1

psElongationLong = 100

psElongationOffset = 100

mvStopFrame = 1.000000

mvCreamFrame = 0.000000

mlMinStopFrame = 4mil

mlMaxStopFrame = 4mil

mlMinCreamFrame = 0mil

mlMaxCreamFrame = 0mil

mlViaStopLimit = 0mil

srRoundness = 0.000000

srMinRoundness = 0mil

srMaxRoundness = 0mil

slThermalIsolate = 10mil

slThermalsForVias = 0

dpMaxLengthDifference = 10mm

dpGapFactor = 2.500000

checkGrid = 0

checkFont = 1

checkRestrict = 1

useDiameter = 13

maxErrors = 50

<wire x1="-0.5842" y1="-0.6858" x2="-0.6604" y2="-0.8128" width="0.127" layer="21"/>

<wire x1="-0.6604" y1="-0.8128" x2="-0.9144" y2="-0.8128" width="0.127" layer="21"/>

<wire x1="-0.9144" y1="-0.8128" x2="-1.016" y2="-0.6858" width="0.127" layer="21"/>

<wire x1="-1.016" y1="-0.6858" x2="-1.3462" y2="-0.6858" width="0.127" layer="21"/>

<wire x1="-1.3462" y1="-0.6858" x2="-1.4478" y2="-0.8128" width="0.127" layer="21"/>

<wire x1="-1.4478" y1="-0.8128" x2="-1.6002" y2="-0.8128" width="0.127" layer="21"/>

<wire x1="-1.6002" y1="-0.8128" x2="-1.6002" y2="-0.4953" width="0.127" layer="21"/>

</package>

</packages>

</library>

</libraries>

<attributes>

</attributes>

<variantdefs>

</variantdefs>

<classes>

<class number="0" name="default" width="0.2032" drill="0">

<clearance class="0" value="0.2032"/>

</class>

<class number="1" name="power" width="0.508" drill="0">

</class>

<class number="2" name="whatisthis" width="0.508" drill="0">

</class>

</classes>

<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;

<p>

Die Standard-Design-Rules sind so gewählt, dass sie für 

die meisten Anwendungen passen. Sollte ihre Platine 

besondere Anforderungen haben, treffen Sie die erforderlichen

Einstellungen hier und speichern die Design Rules unter 

einem neuen Namen ab.</description>

<description language="en">&lt;b&gt;Laen's PCB Order Design Rules&lt;/b&gt;

<p>

Please make sure your boards conform to these design rules.</description>

<param name="layerSetup" value="(1*16)"/>

<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>

<param name="mtIsolate" value="1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>

<param name="mdWireWire" value="6mil"/>

<param name="mdWirePad" value="6mil"/>

<param name="mdWireVia" value="6mil"/>

<param name="mdPadPad" value="6mil"/>

<param name="mdPadVia" value="6mil"/>

<param name="mdViaVia" value="6mil"/>

<param name="mdSmdPad" value="6mil"/>

<param name="mdSmdVia" value="6mil"/>

<param name="mdSmdSmd" value="6mil"/>

<param name="mdViaViaSameLayer" value="8mil"/>

<param name="mnLayersViaInSmd" value="2"/>