+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAbs Vector Absolute Value
+ *
+ * Computes the absolute value of a vector on an element-by-element basis.
+ *
+ *
+ * pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
+ *
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ /* read sample from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+
+ /* find absolute value */
+ in1 = fabsf(in1);
+
+ /* read sample from source */
+ in4 = *(pSrc + 3);
+
+ /* find absolute value */
+ in2 = fabsf(in2);
+
+ /* read sample from source */
+ *pDst = in1;
+
+ /* find absolute value */
+ in3 = fabsf(in3);
+
+ /* find absolute value */
+ in4 = fabsf(in4);
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+
+ /* Update source pointer to process next sampels */
+ pSrc += 4u;
+
+ /* Update destination pointer to process next sampels */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ *pDst++ = fabsf(*pSrc++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
@@ -0,0 +1,179 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q15.c
+*
+* Description: Q15 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *simd;
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1; /* Input value1 */
+ q15_t in2; /* Input value2 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ simd = __SIMD32_CONST(pDst);
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read two inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+ /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
+#ifndef ARM_MATH_BIG_ENDIAN
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ pDst = (q15_t *)simd;
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in1 = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary input variable */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q31.c
+*
+* Description: Q31 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
+ *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
+ *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
+ *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q7.c
+*
+* Description: Q7 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in; /* Input value1 */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read inputs */
+ in1 = (q31_t) * pSrc;
+ in2 = (q31_t) * (pSrc + 1);
+ in3 = (q31_t) * (pSrc + 2);
+
+ /* find absolute value */
+ out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
+
+ /* read input */
+ in4 = (q31_t) * (pSrc + 3);
+
+ /* find absolute value */
+ out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
+
+ /* store result to destination */
+ *pDst = (q7_t) out1;
+
+ /* find absolute value */
+ out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
+
+ /* find absolute value */
+ out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
+
+ /* store result to destination */
+ *(pDst + 1) = (q7_t) out2;
+
+ /* store result to destination */
+ *(pDst + 2) = (q7_t) out3;
+
+ /* store result to destination */
+ *(pDst + 3) = (q7_t) out4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif // #define ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Store the Absolute result in the destination buffer */
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_f32.c
+*
+* Description: Floating-point vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAdd Vector Addition
+ *
+ * Element-by-element addition of two vectors.
+ *
+ *
+ * pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize.
+ *
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+
+ /* read four inputs from sourceA and four inputs from sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* C = A + B */
+ /* add and store result to destination */
+ *pDst = inA1 + inB1;
+ *(pDst + 1) = inA2 + inB2;
+ *(pDst + 2) = inA3 + inB3;
+ *(pDst + 3) = inA4 + inB4;
+
+ /* update pointers to process next samples */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q15.c
+*
+* Description: Q15 vector addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QADD16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QADD16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q31.c
+*
+* Description: Q31 vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QADD(inA1, inB1);
+ *pDst++ = __QADD(inA2, inB2);
+ *pDst++ = __QADD(inA3, inB3);
+ *pDst++ = __QADD(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q7.c
+*
+* Description: Q7 vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_f32.c
+*
+* Description: Floating-point dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup dot_prod Vector Dot Product
+ *
+ * Computes the dot product of two vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ *
+ * sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+ *
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+
+void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer */
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ /* Store the result back in the destination buffer */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q15.c
+*
+* Description: Q15 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these
+ * results are added to a 64-bit accumulator in 34.30 format.
+ * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator
+ * there is no risk of overflow.
+ * The return result is in 34.30 format.
+ */
+
+void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the result in the destination buffer in 34.30 format */
+ *result = sum;
+
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q31.c
+*
+* Description: Q31 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these
+ * are truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * There are 15 guard bits in the accumulator and there is no risk of overflow as long as
+ * the length of the vectors is less than 2^16 elements.
+ * The return result is in 16.48 format.
+ */
+
+void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ sum += ((q63_t) inA1 * inB1) >> 14u;
+ sum += ((q63_t) inA2 * inB2) >> 14u;
+ sum += ((q63_t) inA3 * inB3) >> 14u;
+ sum += ((q63_t) inA4 * inB4) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result in the destination buffer in 16.48 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q7.c
+*
+* Description: Q7 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these
+ * results are added to an accumulator in 18.14 format.
+ * Nonsaturating additions are used and there is no danger of wrap around as long as
+ * the vectors are less than 2^18 elements long.
+ * The return result is in 18.14 format.
+ */
+
+void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result)
+{
+ uint32_t blkCnt; /* loop counter */
+
+ q31_t sum = 0; /* Temporary variables to store output */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t input1, input2; /* Temporary variables to store input */
+ q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */
+
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read 4 samples at a time from sourceA */
+ input1 = *__SIMD32(pSrcA)++;
+ /* read 4 samples at a time from sourceB */
+ input2 = *__SIMD32(pSrcB)++;
+
+ /* extract two q7_t samples to q15_t samples */
+ inA1 = __SXTB16(__ROR(input1, 8));
+ /* extract reminaing two samples */
+ inA2 = __SXTB16(input1);
+ /* extract two q7_t samples to q15_t samples */
+ inB1 = __SXTB16(__ROR(input2, 8));
+ /* extract reminaing two samples */
+ inB2 = __SXTB16(input2);
+
+ /* multiply and accumulate two samples at a time */
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ /* Store the result in the destination buffer in 18.14 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
@@ -0,0 +1,174 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_f32.c
+*
+* Description: Floating-point vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicMult Vector Multiplication
+ *
+ * Element-by-element multiplication of two vectors.
+ *
+ *
+ * pDst[n] = pSrcA[n] * pSrcB[n], 0 <= n < blockSize.
+ *
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ float32_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ /* read sample from sourceA */
+ inA1 = *pSrcA;
+ /* read sample from sourceB */
+ inB1 = *pSrcB;
+ /* read sample from sourceA */
+ inA2 = *(pSrcA + 1);
+ /* read sample from sourceB */
+ inB2 = *(pSrcB + 1);
+
+ /* out = sourceA * sourceB */
+ out1 = inA1 * inB1;
+
+ /* read sample from sourceA */
+ inA3 = *(pSrcA + 2);
+ /* read sample from sourceB */
+ inB3 = *(pSrcB + 2);
+
+ /* out = sourceA * sourceB */
+ out2 = inA2 * inB2;
+
+ /* read sample from sourceA */
+ inA4 = *(pSrcA + 3);
+
+ /* store result to destination buffer */
+ *pDst = out1;
+
+ /* read sample from sourceB */
+ inB4 = *(pSrcB + 3);
+
+ /* out = sourceA * sourceB */
+ out3 = inA3 * inB3;
+
+ /* store result to destination buffer */
+ *(pDst + 1) = out2;
+
+ /* out = sourceA * sourceB */
+ out4 = inA4 * inB4;
+ /* store result to destination buffer */
+ *(pDst + 2) = out3;
+ /* store result to destination buffer */
+ *(pDst + 3) = out4;
+
+
+ /* update pointers to process next samples */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q15.c
+*
+* Description: Q15 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
+ q15_t out1, out2, out3, out4; /* temporary output variables */
+ q31_t mul1, mul2, mul3, mul4; /* temporary variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read two samples at a time from sourceA */
+ inA1 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB1 = *__SIMD32(pSrcB)++;
+ /* read two samples at a time from sourceA */
+ inA2 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB2 = *__SIMD32(pSrcB)++;
+
+ /* multiply mul = sourceA * sourceB */
+ mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
+ mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
+
+ /* saturate result to 16 bit */
+ out1 = (q15_t) __SSAT(mul1 >> 15, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15, 16);
+
+ /* store the result */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q31.c
+*
+* Description: Q31 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ q31_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB2) >> 32;
+ out3 = ((q63_t) inA3 * inB3) >> 32;
+ out4 = ((q63_t) inA4 * inB4) >> 32;
+
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ *pDst++ = out1 << 1u;
+ *pDst++ = out2 << 1u;
+ *pDst++ = out3 << 1u;
+ *pDst++ = out4 << 1u;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inB1 = *pSrcB++;
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out1 = __SSAT(out1, 31);
+ *pDst++ = out1 << 1u;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ *pDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q7.c
+*
+* Description: Q7 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q7 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in temporary variables */
+ out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_f32.c
+*
+* Description: Negates floating-point vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup negate Vector Negate
+ *
+ * Negates the elements of a vector.
+ *
+ *
+ * pDst[n] = -pSrc[n], 0 <= n < blockSize.
+ *
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* negate the input */
+ in1 = -in1;
+ in2 = -in2;
+ in3 = -in3;
+ in4 = -in4;
+
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q15.c
+*
+* Description: Negates Q15 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q15_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Read two inputs at a time */
+ in1 = _SIMD32_OFFSET(pSrc);
+ in2 = _SIMD32_OFFSET(pSrc + 2);
+
+ /* negate two samples at a time */
+ in1 = __QSUB16(0, in1);
+
+ /* negate two samples at a time */
+ in2 = __QSUB16(0, in2);
+
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst) = in1;
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst + 2) = in2;
+
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q31.c
+*
+* Description: Negates Q31 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t in; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QSUB(0, in1);
+ *pDst++ = __QSUB(0, in2);
+ *pDst++ = __QSUB(0, in3);
+ *pDst++ = __QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q7.c
+*
+* Description: Negates Q7 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t input; /* Input values1-4 */
+ q31_t zero = 0x00000000;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Read four inputs */
+ input = *__SIMD32(pSrc)++;
+
+ /* Store the Negated results in the destination buffer in a single cycle by packing the results */
+ *__SIMD32(pDst)++ = __QSUB8(zero, input);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */ \
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_f32.c
+*
+* Description: Floating-point vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup offset Vector Offset
+ *
+ * Adds a constant offset to each element of a vector.
+ *
+ *
+ * pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
+ *
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ /* read samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* add offset to input */
+ in1 = in1 + offset;
+
+ /* read samples from source */
+ in3 = *(pSrc + 2);
+
+ /* add offset to input */
+ in2 = in2 + offset;
+
+ /* read samples from source */
+ in4 = *(pSrc + 3);
+
+ /* add offset to input */
+ in3 = in3 + offset;
+
+ /* store result to destination */
+ *pDst = in1;
+
+ /* add offset to input */
+ in4 = in4 + offset;
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) + offset;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q15.c
+*
+* Description: Q15 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PKHBT(offset, offset, 16);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q31.c
+*
+* Description: Q31 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QADD(in1, offset);
+ *pDst++ = __QADD(in2, offset);
+ *pDst++ = __QADD(in3, offset);
+ *pDst++ = __QADD(in4, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = __QADD(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q7.c
+*
+* Description: Q7 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PACKq7(offset, offset, offset, offset);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_f32.c
+*
+* Description: Multiplies a floating-point vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup scale Vector Scale
+ *
+ * Multiply a vector by a scalar value. For floating-point data, the algorithm used is:
+ *
+ *
+ * pDst[n] = pSrc[n] * scale, 0 <= n < blockSize.
+ *
+ *
+ * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by
+ * a fractional multiplication scaleFract and an arithmetic shift shift.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The algorithm used with fixed-point data is:
+ *
+ *
+ * pDst[n] = (pSrc[n] * scaleFract) << shift, 0 <= n < blockSize.
+ *
+ *
+ * The overall scale factor applied to the fixed-point data is
+ *
+ * scale = scaleFract * 2^shift.
+ *
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variabels */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the results in the destination buffer. */
+ /* read input samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* multiply with scaling factor */
+ in1 = in1 * scale;
+
+ /* read input sample from source */
+ in3 = *(pSrc + 2);
+
+ /* multiply with scaling factor */
+ in2 = in2 * scale;
+
+ /* read input sample from source */
+ in4 = *(pSrc + 3);
+
+ /* multiply with scaling factor */
+ in3 = in3 * scale;
+ in4 = in4 * scale;
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) * scale;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q15.c
+*
+* Description: Multiplies a Q15 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The input data *pSrc and scaleFract are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+
+void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 15 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t in1, in2, in3, in4;
+ q31_t inA1, inA2; /* Temporary variables */
+ q31_t out1, out2, out3, out4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading 2 inputs from memory */
+ inA1 = *__SIMD32(pSrc)++;
+ inA2 = *__SIMD32(pSrc)++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the 2 results in the destination buffer
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+ /* apply shifting */
+ out1 = out1 >> kShift;
+ out2 = out2 >> kShift;
+ out3 = out3 >> kShift;
+ out4 = out4 >> kShift;
+
+ /* saturate the output */
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ /* store the result to destination */
+ *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q31.c
+*
+* Description: Multiplies a Q31 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The input data *pSrc and scaleFract are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = shift + 1; /* Shift to apply after scaling */
+ int8_t sign = (kShift & 0x80);
+ uint32_t blkCnt; /* loop counter */
+ q31_t in, out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variabels */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 << kShift;
+ out2 = in2 << kShift;
+
+ /* saturate the results. */
+ if(in1 != (out1 >> kShift))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> kShift))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ out3 = in3 << kShift;
+ out4 = in4 << kShift;
+
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ if(in3 != (out3 >> kShift))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> kShift))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ /* Store result destination */
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 >> -kShift;
+ out2 = in2 >> -kShift;
+
+ out3 = in3 >> -kShift;
+ out4 = in4 >> -kShift;
+
+ /* Store result destination */
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ if(sign == 0)
+ {
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in << kShift;
+
+ if(in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in >> -kShift;
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q7.c
+*
+* Description: Multiplies a Q7 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The input data *pSrc and scaleFract are in 1.7 format.
+ * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.
+ */
+
+void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 7 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading 4 inputs from memory */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the results in the temporary variables. */
+ out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
+ out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
+ out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
+ out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
+
+ /* Packing the individual outputs into 32bit and storing in
+ * destination buffer in single write */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q15.c
+*
+* Description: Shifts the elements of a Q15 vector by a specified number of bits.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ /* C = A << shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q31.c
+*
+* Description: Shifts the elements of a Q31 vector by a specified number of bits.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+/**
+ * @defgroup shift Vector Shift
+ *
+ * Shifts the elements of a fixed-point vector by a specified number of bits.
+ * There are separate functions for Q7, Q15, and Q31 data types.
+ * The underlying algorithm used is:
+ *
+ *
+ * pDst[n] = pSrc[n] << shift, 0 <= n < blockSize.
+ *
+ *
+ * If shift is positive then the elements of the vector are shifted to the left.
+ * If shift is negative then the elements of the vector are shifted to the right.
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+ q31_t out1, out2, out3, out4; /* Temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ out1 = in1 << shiftBits;
+ in3 = *(pSrc + 2);
+ out2 = in2 << shiftBits;
+ in4 = *(pSrc + 3);
+ if(in1 != (out1 >> shiftBits))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> shiftBits))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ *pDst = out1;
+ out3 = in3 << shiftBits;
+ *(pDst + 1) = out2;
+ out4 = in4 << shiftBits;
+
+ if(in3 != (out3 >> shiftBits))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> shiftBits))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update destination pointer to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ *pDst = (in1 >> -shiftBits);
+ *(pDst + 1) = (in2 >> -shiftBits);
+ *(pDst + 2) = (in3 >> -shiftBits);
+ *(pDst + 3) = (in4 >> -shiftBits);
+
+
+ pSrc += 4u;
+ pDst += 4u;
+
+ blkCnt--;
+ }
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A (>> or <<) shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+ (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
@@ -0,0 +1,220 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q7.c
+*
+* Description: Processing function for the Q7 Shifting
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
+ */
+
+void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1; /* Input value1 */
+ q7_t in2; /* Input value2 */
+ q7_t in3; /* Input value3 */
+ q7_t in4; /* Input value4 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
+ __SSAT((in2 << shiftBits), 8),
+ __SSAT((in3 << shiftBits), 8),
+ __SSAT((in4 << shiftBits), 8));
+ /* Update source pointer to process next sampels */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ shiftBits = -shiftBits;
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
+ (in3 >> shiftBits), (in4 >> shiftBits));
+
+
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ in1 = *pSrc++;
+ *pDst++ = (in1 >> shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_f32.c
+*
+* Description: Floating-point vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicSub Vector Subtraction
+ *
+ * Element-by-element subtraction of two vectors.
+ *
+ *
+ * pDst[n] = pSrcA[n] - pSrcB[n], 0 <= n < blockSize.
+ *
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ /* Read 4 input samples from sourceA and sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* dst = srcA - srcB */
+ /* subtract and store the result */
+ *pDst = inA1 - inB1;
+ *(pDst + 1) = inA2 - inB2;
+ *(pDst + 2) = inA3 - inB3;
+ *(pDst + 3) = inA4 - inB4;
+
+
+ /* Update pointers to process next sampels */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q15.c
+*
+* Description: Q15 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2;
+ q31_t inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer two samples at a time. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q31.c
+*
+* Description: Q31 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QSUB(inA1, inB1);
+ *pDst++ = __QSUB(inA2, inB2);
+ *pDst++ = __QSUB(inA3, inB3);
+ *pDst++ = __QSUB(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q7.c
+*
+* Description: Q7 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
@@ -0,0 +1,27251 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.c
+*
+* Description: This file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup CFFT_CIFFT Complex FFT Tables
+ * @{
+ */
+
+/**
+* \par
+* Pseudo code for Generation of Bit reversal Table is
+* \par
+* for(l=1;l <= N/4;l++)
+* {
+* for(i=0;i> 1;
+* }
+* \par
+* where N = 4096 logN2 = 12
+* \par
+* N is the maximum FFT Size supported
+*/
+
+/*
+* @brief Table for bit reversal process
+*/
+const uint16_t armBitRevTable[1024] = {
+ 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x80, 0x480, 0x280,
+ 0x680, 0x180, 0x580, 0x380, 0x780, 0x40, 0x440, 0x240, 0x640, 0x140,
+ 0x540, 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0,
+ 0x7c0, 0x20, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0xa0,
+ 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, 0x260,
+ 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, 0x4e0, 0x2e0, 0x6e0, 0x1e0,
+ 0x5e0, 0x3e0, 0x7e0, 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310,
+ 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x50,
+ 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0,
+ 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, 0x630, 0x130,
+ 0x530, 0x330, 0x730, 0xb0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0,
+ 0x7b0, 0x70, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0xf0,
+ 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x8, 0x408, 0x208,
+ 0x608, 0x108, 0x508, 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188,
+ 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348,
+ 0x748, 0xc8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28,
+ 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, 0x4a8, 0x2a8,
+ 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x68, 0x468, 0x268, 0x668, 0x168,
+ 0x568, 0x368, 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8,
+ 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x98,
+ 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258,
+ 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, 0x2d8, 0x6d8, 0x1d8,
+ 0x5d8, 0x3d8, 0x7d8, 0x38, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338,
+ 0x738, 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x78,
+ 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0xf8, 0x4f8, 0x2f8,
+ 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, 0x104,
+ 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384,
+ 0x784, 0x44, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4,
+ 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x24, 0x424, 0x224,
+ 0x624, 0x124, 0x524, 0x324, 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4,
+ 0x5a4, 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364,
+ 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14,
+ 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, 0x294,
+ 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, 0x454, 0x254, 0x654, 0x154,
+ 0x554, 0x354, 0x754, 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4,
+ 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0xb4,
+ 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274,
+ 0x674, 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, 0x6f4, 0x1f4,
+ 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c,
+ 0x70c, 0x8c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x4c,
+ 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0xcc, 0x4cc, 0x2cc,
+ 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c,
+ 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac,
+ 0x7ac, 0x6c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec,
+ 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, 0x41c, 0x21c,
+ 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x9c, 0x49c, 0x29c, 0x69c, 0x19c,
+ 0x59c, 0x39c, 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c,
+ 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x3c,
+ 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc,
+ 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, 0x27c, 0x67c, 0x17c,
+ 0x57c, 0x37c, 0x77c, 0xfc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc,
+ 0x7fc, 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x82,
+ 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x42, 0x442, 0x242,
+ 0x642, 0x142, 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, 0x1c2,
+ 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322,
+ 0x722, 0xa2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62,
+ 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0xe2, 0x4e2, 0x2e2,
+ 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112,
+ 0x512, 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392,
+ 0x792, 0x52, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0xd2,
+ 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, 0x232,
+ 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, 0x4b2, 0x2b2, 0x6b2, 0x1b2,
+ 0x5b2, 0x3b2, 0x7b2, 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372,
+ 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0xa,
+ 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a,
+ 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, 0x64a, 0x14a,
+ 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca,
+ 0x7ca, 0x2a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0xaa,
+ 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x6a, 0x46a, 0x26a,
+ 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea,
+ 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a,
+ 0x71a, 0x9a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a,
+ 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, 0x4da, 0x2da,
+ 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x3a, 0x43a, 0x23a, 0x63a, 0x13a,
+ 0x53a, 0x33a, 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba,
+ 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0xfa,
+ 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206,
+ 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, 0x286, 0x686, 0x186,
+ 0x586, 0x386, 0x786, 0x46, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346,
+ 0x746, 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x26,
+ 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0xa6, 0x4a6, 0x2a6,
+ 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666, 0x166,
+ 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6,
+ 0x7e6, 0x16, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96,
+ 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x56, 0x456, 0x256,
+ 0x656, 0x156, 0x556, 0x356, 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6,
+ 0x5d6, 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336,
+ 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76,
+ 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, 0x2f6,
+ 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, 0x40e, 0x20e, 0x60e, 0x10e,
+ 0x50e, 0x30e, 0x70e, 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e,
+ 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0xce,
+ 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e,
+ 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, 0x6ae, 0x1ae,
+ 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e,
+ 0x76e, 0xee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x1e,
+ 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x9e, 0x49e, 0x29e,
+ 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e,
+ 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de,
+ 0x7de, 0x3e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe,
+ 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, 0x47e, 0x27e,
+ 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe,
+ 0x5fe, 0x3fe, 0x7fe, 0x1
+};
+
+
+/*
+* @brief Floating-point Twiddle factors Table Generation
+*/
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 16 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_16[32] = {
+ 1.000000000f, 0.000000000f,
+ 0.923879533f, 0.382683432f,
+ 0.707106781f, 0.707106781f,
+ 0.382683432f, 0.923879533f,
+ 0.000000000f, 1.000000000f,
+ -0.382683432f, 0.923879533f,
+ -0.707106781f, 0.707106781f,
+ -0.923879533f, 0.382683432f,
+ -1.000000000f, 0.000000000f,
+ -0.923879533f, -0.382683432f,
+ -0.707106781f, -0.707106781f,
+ -0.382683432f, -0.923879533f,
+ -0.000000000f, -1.000000000f,
+ 0.382683432f, -0.923879533f,
+ 0.707106781f, -0.707106781f,
+ 0.923879533f, -0.382683432f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 32 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_32[64] = {
+ 1.000000000f, 0.000000000f,
+ 0.980785280f, 0.195090322f,
+ 0.923879533f, 0.382683432f,
+ 0.831469612f, 0.555570233f,
+ 0.707106781f, 0.707106781f,
+ 0.555570233f, 0.831469612f,
+ 0.382683432f, 0.923879533f,
+ 0.195090322f, 0.980785280f,
+ 0.000000000f, 1.000000000f,
+ -0.195090322f, 0.980785280f,
+ -0.382683432f, 0.923879533f,
+ -0.555570233f, 0.831469612f,
+ -0.707106781f, 0.707106781f,
+ -0.831469612f, 0.555570233f,
+ -0.923879533f, 0.382683432f,
+ -0.980785280f, 0.195090322f,
+ -1.000000000f, 0.000000000f,
+ -0.980785280f, -0.195090322f,
+ -0.923879533f, -0.382683432f,
+ -0.831469612f, -0.555570233f,
+ -0.707106781f, -0.707106781f,
+ -0.555570233f, -0.831469612f,
+ -0.382683432f, -0.923879533f,
+ -0.195090322f, -0.980785280f,
+ -0.000000000f, -1.000000000f,
+ 0.195090322f, -0.980785280f,
+ 0.382683432f, -0.923879533f,
+ 0.555570233f, -0.831469612f,
+ 0.707106781f, -0.707106781f,
+ 0.831469612f, -0.555570233f,
+ 0.923879533f, -0.382683432f,
+ 0.980785280f, -0.195090322f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 64 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_64[128] = {
+ 1.000000000f, 0.000000000f,
+ 0.995184727f, 0.098017140f,
+ 0.980785280f, 0.195090322f,
+ 0.956940336f, 0.290284677f,
+ 0.923879533f, 0.382683432f,
+ 0.881921264f, 0.471396737f,
+ 0.831469612f, 0.555570233f,
+ 0.773010453f, 0.634393284f,
+ 0.707106781f, 0.707106781f,
+ 0.634393284f, 0.773010453f,
+ 0.555570233f, 0.831469612f,
+ 0.471396737f, 0.881921264f,
+ 0.382683432f, 0.923879533f,
+ 0.290284677f, 0.956940336f,
+ 0.195090322f, 0.980785280f,
+ 0.098017140f, 0.995184727f,
+ 0.000000000f, 1.000000000f,
+ -0.098017140f, 0.995184727f,
+ -0.195090322f, 0.980785280f,
+ -0.290284677f, 0.956940336f,
+ -0.382683432f, 0.923879533f,
+ -0.471396737f, 0.881921264f,
+ -0.555570233f, 0.831469612f,
+ -0.634393284f, 0.773010453f,
+ -0.707106781f, 0.707106781f,
+ -0.773010453f, 0.634393284f,
+ -0.831469612f, 0.555570233f,
+ -0.881921264f, 0.471396737f,
+ -0.923879533f, 0.382683432f,
+ -0.956940336f, 0.290284677f,
+ -0.980785280f, 0.195090322f,
+ -0.995184727f, 0.098017140f,
+ -1.000000000f, 0.000000000f,
+ -0.995184727f, -0.098017140f,
+ -0.980785280f, -0.195090322f,
+ -0.956940336f, -0.290284677f,
+ -0.923879533f, -0.382683432f,
+ -0.881921264f, -0.471396737f,
+ -0.831469612f, -0.555570233f,
+ -0.773010453f, -0.634393284f,
+ -0.707106781f, -0.707106781f,
+ -0.634393284f, -0.773010453f,
+ -0.555570233f, -0.831469612f,
+ -0.471396737f, -0.881921264f,
+ -0.382683432f, -0.923879533f,
+ -0.290284677f, -0.956940336f,
+ -0.195090322f, -0.980785280f,
+ -0.098017140f, -0.995184727f,
+ -0.000000000f, -1.000000000f,
+ 0.098017140f, -0.995184727f,
+ 0.195090322f, -0.980785280f,
+ 0.290284677f, -0.956940336f,
+ 0.382683432f, -0.923879533f,
+ 0.471396737f, -0.881921264f,
+ 0.555570233f, -0.831469612f,
+ 0.634393284f, -0.773010453f,
+ 0.707106781f, -0.707106781f,
+ 0.773010453f, -0.634393284f,
+ 0.831469612f, -0.555570233f,
+ 0.881921264f, -0.471396737f,
+ 0.923879533f, -0.382683432f,
+ 0.956940336f, -0.290284677f,
+ 0.980785280f, -0.195090322f,
+ 0.995184727f, -0.098017140f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 128 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+
+const float32_t twiddleCoef_128[256] = {
+ 1.000000000f , 0.000000000f ,
+ 0.998795456f , 0.049067674f ,
+ 0.995184727f , 0.098017140f ,
+ 0.989176510f , 0.146730474f ,
+ 0.980785280f , 0.195090322f ,
+ 0.970031253f , 0.242980180f ,
+ 0.956940336f , 0.290284677f ,
+ 0.941544065f , 0.336889853f ,
+ 0.923879533f , 0.382683432f ,
+ 0.903989293f , 0.427555093f ,
+ 0.881921264f , 0.471396737f ,
+ 0.857728610f , 0.514102744f ,
+ 0.831469612f , 0.555570233f ,
+ 0.803207531f , 0.595699304f ,
+ 0.773010453f , 0.634393284f ,
+ 0.740951125f , 0.671558955f ,
+ 0.707106781f , 0.707106781f ,
+ 0.671558955f , 0.740951125f ,
+ 0.634393284f , 0.773010453f ,
+ 0.595699304f , 0.803207531f ,
+ 0.555570233f , 0.831469612f ,
+ 0.514102744f , 0.857728610f ,
+ 0.471396737f , 0.881921264f ,
+ 0.427555093f , 0.903989293f ,
+ 0.382683432f , 0.923879533f ,
+ 0.336889853f , 0.941544065f ,
+ 0.290284677f , 0.956940336f ,
+ 0.242980180f , 0.970031253f ,
+ 0.195090322f , 0.980785280f ,
+ 0.146730474f , 0.989176510f ,
+ 0.098017140f , 0.995184727f ,
+ 0.049067674f , 0.998795456f ,
+ 0.000000000f , 1.000000000f ,
+ -0.049067674f , 0.998795456f ,
+ -0.098017140f , 0.995184727f ,
+ -0.146730474f , 0.989176510f ,
+ -0.195090322f , 0.980785280f ,
+ -0.242980180f , 0.970031253f ,
+ -0.290284677f , 0.956940336f ,
+ -0.336889853f , 0.941544065f ,
+ -0.382683432f , 0.923879533f ,
+ -0.427555093f , 0.903989293f ,
+ -0.471396737f , 0.881921264f ,
+ -0.514102744f , 0.857728610f ,
+ -0.555570233f , 0.831469612f ,
+ -0.595699304f , 0.803207531f ,
+ -0.634393284f , 0.773010453f ,
+ -0.671558955f , 0.740951125f ,
+ -0.707106781f , 0.707106781f ,
+ -0.740951125f , 0.671558955f ,
+ -0.773010453f , 0.634393284f ,
+ -0.803207531f , 0.595699304f ,
+ -0.831469612f , 0.555570233f ,
+ -0.857728610f , 0.514102744f ,
+ -0.881921264f , 0.471396737f ,
+ -0.903989293f , 0.427555093f ,
+ -0.923879533f , 0.382683432f ,
+ -0.941544065f , 0.336889853f ,
+ -0.956940336f , 0.290284677f ,
+ -0.970031253f , 0.242980180f ,
+ -0.980785280f , 0.195090322f ,
+ -0.989176510f , 0.146730474f ,
+ -0.995184727f , 0.098017140f ,
+ -0.998795456f , 0.049067674f ,
+ -1.000000000f , 0.000000000f ,
+ -0.998795456f , -0.049067674f ,
+ -0.995184727f , -0.098017140f ,
+ -0.989176510f , -0.146730474f ,
+ -0.980785280f , -0.195090322f ,
+ -0.970031253f , -0.242980180f ,
+ -0.956940336f , -0.290284677f ,
+ -0.941544065f , -0.336889853f ,
+ -0.923879533f , -0.382683432f ,
+ -0.903989293f , -0.427555093f ,
+ -0.881921264f , -0.471396737f ,
+ -0.857728610f , -0.514102744f ,
+ -0.831469612f , -0.555570233f ,
+ -0.803207531f , -0.595699304f ,
+ -0.773010453f , -0.634393284f ,
+ -0.740951125f , -0.671558955f ,
+ -0.707106781f , -0.707106781f ,
+ -0.671558955f , -0.740951125f ,
+ -0.634393284f , -0.773010453f ,
+ -0.595699304f , -0.803207531f ,
+ -0.555570233f , -0.831469612f ,
+ -0.514102744f , -0.857728610f ,
+ -0.471396737f , -0.881921264f ,
+ -0.427555093f , -0.903989293f ,
+ -0.382683432f , -0.923879533f ,
+ -0.336889853f , -0.941544065f ,
+ -0.290284677f , -0.956940336f ,
+ -0.242980180f , -0.970031253f ,
+ -0.195090322f , -0.980785280f ,
+ -0.146730474f , -0.989176510f ,
+ -0.098017140f , -0.995184727f ,
+ -0.049067674f , -0.998795456f ,
+ -0.000000000f , -1.000000000f ,
+ 0.049067674f , -0.998795456f ,
+ 0.098017140f , -0.995184727f ,
+ 0.146730474f , -0.989176510f ,
+ 0.195090322f , -0.980785280f ,
+ 0.242980180f , -0.970031253f ,
+ 0.290284677f , -0.956940336f ,
+ 0.336889853f , -0.941544065f ,
+ 0.382683432f , -0.923879533f ,
+ 0.427555093f , -0.903989293f ,
+ 0.471396737f , -0.881921264f ,
+ 0.514102744f , -0.857728610f ,
+ 0.555570233f , -0.831469612f ,
+ 0.595699304f , -0.803207531f ,
+ 0.634393284f , -0.773010453f ,
+ 0.671558955f , -0.740951125f ,
+ 0.707106781f , -0.707106781f ,
+ 0.740951125f , -0.671558955f ,
+ 0.773010453f , -0.634393284f ,
+ 0.803207531f , -0.595699304f ,
+ 0.831469612f , -0.555570233f ,
+ 0.857728610f , -0.514102744f ,
+ 0.881921264f , -0.471396737f ,
+ 0.903989293f , -0.427555093f ,
+ 0.923879533f , -0.382683432f ,
+ 0.941544065f , -0.336889853f ,
+ 0.956940336f , -0.290284677f ,
+ 0.970031253f , -0.242980180f ,
+ 0.980785280f , -0.195090322f ,
+ 0.989176510f , -0.146730474f ,
+ 0.995184727f , -0.098017140f ,
+ 0.998795456f , -0.049067674f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 256 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_256[512] = {
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, 0.024541229f,
+ 0.998795456f, 0.049067674f,
+ 0.997290457f, 0.073564564f,
+ 0.995184727f, 0.098017140f,
+ 0.992479535f, 0.122410675f,
+ 0.989176510f, 0.146730474f,
+ 0.985277642f, 0.170961889f,
+ 0.980785280f, 0.195090322f,
+ 0.975702130f, 0.219101240f,
+ 0.970031253f, 0.242980180f,
+ 0.963776066f, 0.266712757f,
+ 0.956940336f, 0.290284677f,
+ 0.949528181f, 0.313681740f,
+ 0.941544065f, 0.336889853f,
+ 0.932992799f, 0.359895037f,
+ 0.923879533f, 0.382683432f,
+ 0.914209756f, 0.405241314f,
+ 0.903989293f, 0.427555093f,
+ 0.893224301f, 0.449611330f,
+ 0.881921264f, 0.471396737f,
+ 0.870086991f, 0.492898192f,
+ 0.857728610f, 0.514102744f,
+ 0.844853565f, 0.534997620f,
+ 0.831469612f, 0.555570233f,
+ 0.817584813f, 0.575808191f,
+ 0.803207531f, 0.595699304f,
+ 0.788346428f, 0.615231591f,
+ 0.773010453f, 0.634393284f,
+ 0.757208847f, 0.653172843f,
+ 0.740951125f, 0.671558955f,
+ 0.724247083f, 0.689540545f,
+ 0.707106781f, 0.707106781f,
+ 0.689540545f, 0.724247083f,
+ 0.671558955f, 0.740951125f,
+ 0.653172843f, 0.757208847f,
+ 0.634393284f, 0.773010453f,
+ 0.615231591f, 0.788346428f,
+ 0.595699304f, 0.803207531f,
+ 0.575808191f, 0.817584813f,
+ 0.555570233f, 0.831469612f,
+ 0.534997620f, 0.844853565f,
+ 0.514102744f, 0.857728610f,
+ 0.492898192f, 0.870086991f,
+ 0.471396737f, 0.881921264f,
+ 0.449611330f, 0.893224301f,
+ 0.427555093f, 0.903989293f,
+ 0.405241314f, 0.914209756f,
+ 0.382683432f, 0.923879533f,
+ 0.359895037f, 0.932992799f,
+ 0.336889853f, 0.941544065f,
+ 0.313681740f, 0.949528181f,
+ 0.290284677f, 0.956940336f,
+ 0.266712757f, 0.963776066f,
+ 0.242980180f, 0.970031253f,
+ 0.219101240f, 0.975702130f,
+ 0.195090322f, 0.980785280f,
+ 0.170961889f, 0.985277642f,
+ 0.146730474f, 0.989176510f,
+ 0.122410675f, 0.992479535f,
+ 0.098017140f, 0.995184727f,
+ 0.073564564f, 0.997290457f,
+ 0.049067674f, 0.998795456f,
+ 0.024541229f, 0.999698819f,
+ 0.000000000f, 1.000000000f,
+ -0.024541229f, 0.999698819f,
+ -0.049067674f, 0.998795456f,
+ -0.073564564f, 0.997290457f,
+ -0.098017140f, 0.995184727f,
+ -0.122410675f, 0.992479535f,
+ -0.146730474f, 0.989176510f,
+ -0.170961889f, 0.985277642f,
+ -0.195090322f, 0.980785280f,
+ -0.219101240f, 0.975702130f,
+ -0.242980180f, 0.970031253f,
+ -0.266712757f, 0.963776066f,
+ -0.290284677f, 0.956940336f,
+ -0.313681740f, 0.949528181f,
+ -0.336889853f, 0.941544065f,
+ -0.359895037f, 0.932992799f,
+ -0.382683432f, 0.923879533f,
+ -0.405241314f, 0.914209756f,
+ -0.427555093f, 0.903989293f,
+ -0.449611330f, 0.893224301f,
+ -0.471396737f, 0.881921264f,
+ -0.492898192f, 0.870086991f,
+ -0.514102744f, 0.857728610f,
+ -0.534997620f, 0.844853565f,
+ -0.555570233f, 0.831469612f,
+ -0.575808191f, 0.817584813f,
+ -0.595699304f, 0.803207531f,
+ -0.615231591f, 0.788346428f,
+ -0.634393284f, 0.773010453f,
+ -0.653172843f, 0.757208847f,
+ -0.671558955f, 0.740951125f,
+ -0.689540545f, 0.724247083f,
+ -0.707106781f, 0.707106781f,
+ -0.724247083f, 0.689540545f,
+ -0.740951125f, 0.671558955f,
+ -0.757208847f, 0.653172843f,
+ -0.773010453f, 0.634393284f,
+ -0.788346428f, 0.615231591f,
+ -0.803207531f, 0.595699304f,
+ -0.817584813f, 0.575808191f,
+ -0.831469612f, 0.555570233f,
+ -0.844853565f, 0.534997620f,
+ -0.857728610f, 0.514102744f,
+ -0.870086991f, 0.492898192f,
+ -0.881921264f, 0.471396737f,
+ -0.893224301f, 0.449611330f,
+ -0.903989293f, 0.427555093f,
+ -0.914209756f, 0.405241314f,
+ -0.923879533f, 0.382683432f,
+ -0.932992799f, 0.359895037f,
+ -0.941544065f, 0.336889853f,
+ -0.949528181f, 0.313681740f,
+ -0.956940336f, 0.290284677f,
+ -0.963776066f, 0.266712757f,
+ -0.970031253f, 0.242980180f,
+ -0.975702130f, 0.219101240f,
+ -0.980785280f, 0.195090322f,
+ -0.985277642f, 0.170961889f,
+ -0.989176510f, 0.146730474f,
+ -0.992479535f, 0.122410675f,
+ -0.995184727f, 0.098017140f,
+ -0.997290457f, 0.073564564f,
+ -0.998795456f, 0.049067674f,
+ -0.999698819f, 0.024541229f,
+ -1.000000000f, 0.000000000f,
+ -0.999698819f, -0.024541229f,
+ -0.998795456f, -0.049067674f,
+ -0.997290457f, -0.073564564f,
+ -0.995184727f, -0.098017140f,
+ -0.992479535f, -0.122410675f,
+ -0.989176510f, -0.146730474f,
+ -0.985277642f, -0.170961889f,
+ -0.980785280f, -0.195090322f,
+ -0.975702130f, -0.219101240f,
+ -0.970031253f, -0.242980180f,
+ -0.963776066f, -0.266712757f,
+ -0.956940336f, -0.290284677f,
+ -0.949528181f, -0.313681740f,
+ -0.941544065f, -0.336889853f,
+ -0.932992799f, -0.359895037f,
+ -0.923879533f, -0.382683432f,
+ -0.914209756f, -0.405241314f,
+ -0.903989293f, -0.427555093f,
+ -0.893224301f, -0.449611330f,
+ -0.881921264f, -0.471396737f,
+ -0.870086991f, -0.492898192f,
+ -0.857728610f, -0.514102744f,
+ -0.844853565f, -0.534997620f,
+ -0.831469612f, -0.555570233f,
+ -0.817584813f, -0.575808191f,
+ -0.803207531f, -0.595699304f,
+ -0.788346428f, -0.615231591f,
+ -0.773010453f, -0.634393284f,
+ -0.757208847f, -0.653172843f,
+ -0.740951125f, -0.671558955f,
+ -0.724247083f, -0.689540545f,
+ -0.707106781f, -0.707106781f,
+ -0.689540545f, -0.724247083f,
+ -0.671558955f, -0.740951125f,
+ -0.653172843f, -0.757208847f,
+ -0.634393284f, -0.773010453f,
+ -0.615231591f, -0.788346428f,
+ -0.595699304f, -0.803207531f,
+ -0.575808191f, -0.817584813f,
+ -0.555570233f, -0.831469612f,
+ -0.534997620f, -0.844853565f,
+ -0.514102744f, -0.857728610f,
+ -0.492898192f, -0.870086991f,
+ -0.471396737f, -0.881921264f,
+ -0.449611330f, -0.893224301f,
+ -0.427555093f, -0.903989293f,
+ -0.405241314f, -0.914209756f,
+ -0.382683432f, -0.923879533f,
+ -0.359895037f, -0.932992799f,
+ -0.336889853f, -0.941544065f,
+ -0.313681740f, -0.949528181f,
+ -0.290284677f, -0.956940336f,
+ -0.266712757f, -0.963776066f,
+ -0.242980180f, -0.970031253f,
+ -0.219101240f, -0.975702130f,
+ -0.195090322f, -0.980785280f,
+ -0.170961889f, -0.985277642f,
+ -0.146730474f, -0.989176510f,
+ -0.122410675f, -0.992479535f,
+ -0.098017140f, -0.995184727f,
+ -0.073564564f, -0.997290457f,
+ -0.049067674f, -0.998795456f,
+ -0.024541229f, -0.999698819f,
+ -0.000000000f, -1.000000000f,
+ 0.024541229f, -0.999698819f,
+ 0.049067674f, -0.998795456f,
+ 0.073564564f, -0.997290457f,
+ 0.098017140f, -0.995184727f,
+ 0.122410675f, -0.992479535f,
+ 0.146730474f, -0.989176510f,
+ 0.170961889f, -0.985277642f,
+ 0.195090322f, -0.980785280f,
+ 0.219101240f, -0.975702130f,
+ 0.242980180f, -0.970031253f,
+ 0.266712757f, -0.963776066f,
+ 0.290284677f, -0.956940336f,
+ 0.313681740f, -0.949528181f,
+ 0.336889853f, -0.941544065f,
+ 0.359895037f, -0.932992799f,
+ 0.382683432f, -0.923879533f,
+ 0.405241314f, -0.914209756f,
+ 0.427555093f, -0.903989293f,
+ 0.449611330f, -0.893224301f,
+ 0.471396737f, -0.881921264f,
+ 0.492898192f, -0.870086991f,
+ 0.514102744f, -0.857728610f,
+ 0.534997620f, -0.844853565f,
+ 0.555570233f, -0.831469612f,
+ 0.575808191f, -0.817584813f,
+ 0.595699304f, -0.803207531f,
+ 0.615231591f, -0.788346428f,
+ 0.634393284f, -0.773010453f,
+ 0.653172843f, -0.757208847f,
+ 0.671558955f, -0.740951125f,
+ 0.689540545f, -0.724247083f,
+ 0.707106781f, -0.707106781f,
+ 0.724247083f, -0.689540545f,
+ 0.740951125f, -0.671558955f,
+ 0.757208847f, -0.653172843f,
+ 0.773010453f, -0.634393284f,
+ 0.788346428f, -0.615231591f,
+ 0.803207531f, -0.595699304f,
+ 0.817584813f, -0.575808191f,
+ 0.831469612f, -0.555570233f,
+ 0.844853565f, -0.534997620f,
+ 0.857728610f, -0.514102744f,
+ 0.870086991f, -0.492898192f,
+ 0.881921264f, -0.471396737f,
+ 0.893224301f, -0.449611330f,
+ 0.903989293f, -0.427555093f,
+ 0.914209756f, -0.405241314f,
+ 0.923879533f, -0.382683432f,
+ 0.932992799f, -0.359895037f,
+ 0.941544065f, -0.336889853f,
+ 0.949528181f, -0.313681740f,
+ 0.956940336f, -0.290284677f,
+ 0.963776066f, -0.266712757f,
+ 0.970031253f, -0.242980180f,
+ 0.975702130f, -0.219101240f,
+ 0.980785280f, -0.195090322f,
+ 0.985277642f, -0.170961889f,
+ 0.989176510f, -0.146730474f,
+ 0.992479535f, -0.122410675f,
+ 0.995184727f, -0.098017140f,
+ 0.997290457f, -0.073564564f,
+ 0.998795456f, -0.049067674f,
+ 0.999698819f, -0.024541229f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 512 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_512[1024] = {
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, 0.012271538f,
+ 0.999698819f, 0.024541229f,
+ 0.999322385f, 0.036807223f,
+ 0.998795456f, 0.049067674f,
+ 0.998118113f, 0.061320736f,
+ 0.997290457f, 0.073564564f,
+ 0.996312612f, 0.085797312f,
+ 0.995184727f, 0.098017140f,
+ 0.993906970f, 0.110222207f,
+ 0.992479535f, 0.122410675f,
+ 0.990902635f, 0.134580709f,
+ 0.989176510f, 0.146730474f,
+ 0.987301418f, 0.158858143f,
+ 0.985277642f, 0.170961889f,
+ 0.983105487f, 0.183039888f,
+ 0.980785280f, 0.195090322f,
+ 0.978317371f, 0.207111376f,
+ 0.975702130f, 0.219101240f,
+ 0.972939952f, 0.231058108f,
+ 0.970031253f, 0.242980180f,
+ 0.966976471f, 0.254865660f,
+ 0.963776066f, 0.266712757f,
+ 0.960430519f, 0.278519689f,
+ 0.956940336f, 0.290284677f,
+ 0.953306040f, 0.302005949f,
+ 0.949528181f, 0.313681740f,
+ 0.945607325f, 0.325310292f,
+ 0.941544065f, 0.336889853f,
+ 0.937339012f, 0.348418680f,
+ 0.932992799f, 0.359895037f,
+ 0.928506080f, 0.371317194f,
+ 0.923879533f, 0.382683432f,
+ 0.919113852f, 0.393992040f,
+ 0.914209756f, 0.405241314f,
+ 0.909167983f, 0.416429560f,
+ 0.903989293f, 0.427555093f,
+ 0.898674466f, 0.438616239f,
+ 0.893224301f, 0.449611330f,
+ 0.887639620f, 0.460538711f,
+ 0.881921264f, 0.471396737f,
+ 0.876070094f, 0.482183772f,
+ 0.870086991f, 0.492898192f,
+ 0.863972856f, 0.503538384f,
+ 0.857728610f, 0.514102744f,
+ 0.851355193f, 0.524589683f,
+ 0.844853565f, 0.534997620f,
+ 0.838224706f, 0.545324988f,
+ 0.831469612f, 0.555570233f,
+ 0.824589303f, 0.565731811f,
+ 0.817584813f, 0.575808191f,
+ 0.810457198f, 0.585797857f,
+ 0.803207531f, 0.595699304f,
+ 0.795836905f, 0.605511041f,
+ 0.788346428f, 0.615231591f,
+ 0.780737229f, 0.624859488f,
+ 0.773010453f, 0.634393284f,
+ 0.765167266f, 0.643831543f,
+ 0.757208847f, 0.653172843f,
+ 0.749136395f, 0.662415778f,
+ 0.740951125f, 0.671558955f,
+ 0.732654272f, 0.680600998f,
+ 0.724247083f, 0.689540545f,
+ 0.715730825f, 0.698376249f,
+ 0.707106781f, 0.707106781f,
+ 0.698376249f, 0.715730825f,
+ 0.689540545f, 0.724247083f,
+ 0.680600998f, 0.732654272f,
+ 0.671558955f, 0.740951125f,
+ 0.662415778f, 0.749136395f,
+ 0.653172843f, 0.757208847f,
+ 0.643831543f, 0.765167266f,
+ 0.634393284f, 0.773010453f,
+ 0.624859488f, 0.780737229f,
+ 0.615231591f, 0.788346428f,
+ 0.605511041f, 0.795836905f,
+ 0.595699304f, 0.803207531f,
+ 0.585797857f, 0.810457198f,
+ 0.575808191f, 0.817584813f,
+ 0.565731811f, 0.824589303f,
+ 0.555570233f, 0.831469612f,
+ 0.545324988f, 0.838224706f,
+ 0.534997620f, 0.844853565f,
+ 0.524589683f, 0.851355193f,
+ 0.514102744f, 0.857728610f,
+ 0.503538384f, 0.863972856f,
+ 0.492898192f, 0.870086991f,
+ 0.482183772f, 0.876070094f,
+ 0.471396737f, 0.881921264f,
+ 0.460538711f, 0.887639620f,
+ 0.449611330f, 0.893224301f,
+ 0.438616239f, 0.898674466f,
+ 0.427555093f, 0.903989293f,
+ 0.416429560f, 0.909167983f,
+ 0.405241314f, 0.914209756f,
+ 0.393992040f, 0.919113852f,
+ 0.382683432f, 0.923879533f,
+ 0.371317194f, 0.928506080f,
+ 0.359895037f, 0.932992799f,
+ 0.348418680f, 0.937339012f,
+ 0.336889853f, 0.941544065f,
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+ 0.998795456f, -0.049067674f,
+ 0.999322385f, -0.036807223f,
+ 0.999698819f, -0.024541229f,
+ 0.999924702f, -0.012271538f
+};
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 1024 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_1024[2048] = {
+1.000000000f , 0.000000000f ,
+0.999981175f , 0.006135885f ,
+0.999924702f , 0.012271538f ,
+0.999830582f , 0.018406730f ,
+0.999698819f , 0.024541229f ,
+0.999529418f , 0.030674803f ,
+0.999322385f , 0.036807223f ,
+0.999077728f , 0.042938257f ,
+0.998795456f , 0.049067674f ,
+0.998475581f , 0.055195244f ,
+0.998118113f , 0.061320736f ,
+0.997723067f , 0.067443920f ,
+0.997290457f , 0.073564564f ,
+0.996820299f , 0.079682438f ,
+0.996312612f , 0.085797312f ,
+0.995767414f , 0.091908956f ,
+0.995184727f , 0.098017140f ,
+0.994564571f , 0.104121634f ,
+0.993906970f , 0.110222207f ,
+0.993211949f , 0.116318631f ,
+0.992479535f , 0.122410675f ,
+0.991709754f , 0.128498111f ,
+0.990902635f , 0.134580709f ,
+0.990058210f , 0.140658239f ,
+0.989176510f , 0.146730474f ,
+0.988257568f , 0.152797185f ,
+0.987301418f , 0.158858143f ,
+0.986308097f , 0.164913120f ,
+0.985277642f , 0.170961889f ,
+0.984210092f , 0.177004220f ,
+0.983105487f , 0.183039888f ,
+0.981963869f , 0.189068664f ,
+0.980785280f , 0.195090322f ,
+0.979569766f , 0.201104635f ,
+0.978317371f , 0.207111376f ,
+0.977028143f , 0.213110320f ,
+0.975702130f , 0.219101240f ,
+0.974339383f , 0.225083911f ,
+0.972939952f , 0.231058108f ,
+0.971503891f , 0.237023606f ,
+0.970031253f , 0.242980180f ,
+0.968522094f , 0.248927606f ,
+0.966976471f , 0.254865660f ,
+0.965394442f , 0.260794118f ,
+0.963776066f , 0.266712757f ,
+0.962121404f , 0.272621355f ,
+0.960430519f , 0.278519689f ,
+0.958703475f , 0.284407537f ,
+0.956940336f , 0.290284677f ,
+0.955141168f , 0.296150888f ,
+0.953306040f , 0.302005949f ,
+0.951435021f , 0.307849640f ,
+0.949528181f , 0.313681740f ,
+0.947585591f , 0.319502031f ,
+0.945607325f , 0.325310292f ,
+0.943593458f , 0.331106306f ,
+0.941544065f , 0.336889853f ,
+0.939459224f , 0.342660717f ,
+0.937339012f , 0.348418680f ,
+0.935183510f , 0.354163525f ,
+0.932992799f , 0.359895037f ,
+0.930766961f , 0.365612998f ,
+0.928506080f , 0.371317194f ,
+0.926210242f , 0.377007410f ,
+0.923879533f , 0.382683432f ,
+0.921514039f , 0.388345047f ,
+0.919113852f , 0.393992040f ,
+0.916679060f , 0.399624200f ,
+0.914209756f , 0.405241314f ,
+0.911706032f , 0.410843171f ,
+0.909167983f , 0.416429560f ,
+0.906595705f , 0.422000271f ,
+0.903989293f , 0.427555093f ,
+0.901348847f , 0.433093819f ,
+0.898674466f , 0.438616239f ,
+0.895966250f , 0.444122145f ,
+0.893224301f , 0.449611330f ,
+0.890448723f , 0.455083587f ,
+0.887639620f , 0.460538711f ,
+0.884797098f , 0.465976496f ,
+0.881921264f , 0.471396737f ,
+0.879012226f , 0.476799230f ,
+0.876070094f , 0.482183772f ,
+0.873094978f , 0.487550160f ,
+0.870086991f , 0.492898192f ,
+0.867046246f , 0.498227667f ,
+0.863972856f , 0.503538384f ,
+0.860866939f , 0.508830143f ,
+0.857728610f , 0.514102744f ,
+0.854557988f , 0.519355990f ,
+0.851355193f , 0.524589683f ,
+0.848120345f , 0.529803625f ,
+0.844853565f , 0.534997620f ,
+0.841554977f , 0.540171473f ,
+0.838224706f , 0.545324988f ,
+0.834862875f , 0.550457973f ,
+0.831469612f , 0.555570233f ,
+0.828045045f , 0.560661576f ,
+0.824589303f , 0.565731811f ,
+0.821102515f , 0.570780746f ,
+0.817584813f , 0.575808191f ,
+0.814036330f , 0.580813958f ,
+0.810457198f , 0.585797857f ,
+0.806847554f , 0.590759702f ,
+0.803207531f , 0.595699304f ,
+0.799537269f , 0.600616479f ,
+0.795836905f , 0.605511041f ,
+0.792106577f , 0.610382806f ,
+0.788346428f , 0.615231591f ,
+0.784556597f , 0.620057212f ,
+0.780737229f , 0.624859488f ,
+0.776888466f , 0.629638239f ,
+0.773010453f , 0.634393284f ,
+0.769103338f , 0.639124445f ,
+0.765167266f , 0.643831543f ,
+0.761202385f , 0.648514401f ,
+0.757208847f , 0.653172843f ,
+0.753186799f , 0.657806693f ,
+0.749136395f , 0.662415778f ,
+0.745057785f , 0.666999922f ,
+0.740951125f , 0.671558955f ,
+0.736816569f , 0.676092704f ,
+0.732654272f , 0.680600998f ,
+0.728464390f , 0.685083668f ,
+0.724247083f , 0.689540545f ,
+0.720002508f , 0.693971461f ,
+0.715730825f , 0.698376249f ,
+0.711432196f , 0.702754744f ,
+0.707106781f , 0.707106781f ,
+0.702754744f , 0.711432196f ,
+0.698376249f , 0.715730825f ,
+0.693971461f , 0.720002508f ,
+0.689540545f , 0.724247083f ,
+0.685083668f , 0.728464390f ,
+0.680600998f , 0.732654272f ,
+0.676092704f , 0.736816569f ,
+0.671558955f , 0.740951125f ,
+0.666999922f , 0.745057785f ,
+0.662415778f , 0.749136395f ,
+0.657806693f , 0.753186799f ,
+0.653172843f , 0.757208847f ,
+0.648514401f , 0.761202385f ,
+0.643831543f , 0.765167266f ,
+0.639124445f , 0.769103338f ,
+0.634393284f , 0.773010453f ,
+0.629638239f , 0.776888466f ,
+0.624859488f , 0.780737229f ,
+0.620057212f , 0.784556597f ,
+0.615231591f , 0.788346428f ,
+0.610382806f , 0.792106577f ,
+0.605511041f , 0.795836905f ,
+0.600616479f , 0.799537269f ,
+0.595699304f , 0.803207531f ,
+0.590759702f , 0.806847554f ,
+0.585797857f , 0.810457198f ,
+0.580813958f , 0.814036330f ,
+0.575808191f , 0.817584813f ,
+0.570780746f , 0.821102515f ,
+0.565731811f , 0.824589303f ,
+0.560661576f , 0.828045045f ,
+0.555570233f , 0.831469612f ,
+0.550457973f , 0.834862875f ,
+0.545324988f , 0.838224706f ,
+0.540171473f , 0.841554977f ,
+0.534997620f , 0.844853565f ,
+0.529803625f , 0.848120345f ,
+0.524589683f , 0.851355193f ,
+0.519355990f , 0.854557988f ,
+0.514102744f , 0.857728610f ,
+0.508830143f , 0.860866939f ,
+0.503538384f , 0.863972856f ,
+0.498227667f , 0.867046246f ,
+0.492898192f , 0.870086991f ,
+0.487550160f , 0.873094978f ,
+0.482183772f , 0.876070094f ,
+0.476799230f , 0.879012226f ,
+0.471396737f , 0.881921264f ,
+0.465976496f , 0.884797098f ,
+0.460538711f , 0.887639620f ,
+0.455083587f , 0.890448723f ,
+0.449611330f , 0.893224301f ,
+0.444122145f , 0.895966250f ,
+0.438616239f , 0.898674466f ,
+0.433093819f , 0.901348847f ,
+0.427555093f , 0.903989293f ,
+0.422000271f , 0.906595705f ,
+0.416429560f , 0.909167983f ,
+0.410843171f , 0.911706032f ,
+0.405241314f , 0.914209756f ,
+0.399624200f , 0.916679060f ,
+0.393992040f , 0.919113852f ,
+0.388345047f , 0.921514039f ,
+0.382683432f , 0.923879533f ,
+0.377007410f , 0.926210242f ,
+0.371317194f , 0.928506080f ,
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+0.354163525f , 0.935183510f ,
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+0.336889853f , 0.941544065f ,
+0.331106306f , 0.943593458f ,
+0.325310292f , 0.945607325f ,
+0.319502031f , 0.947585591f ,
+0.313681740f , 0.949528181f ,
+0.307849640f , 0.951435021f ,
+0.302005949f , 0.953306040f ,
+0.296150888f , 0.955141168f ,
+0.290284677f , 0.956940336f ,
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+0.393992040f , -0.919113852f ,
+0.399624200f , -0.916679060f ,
+0.405241314f , -0.914209756f ,
+0.410843171f , -0.911706032f ,
+0.416429560f , -0.909167983f ,
+0.422000271f , -0.906595705f ,
+0.427555093f , -0.903989293f ,
+0.433093819f , -0.901348847f ,
+0.438616239f , -0.898674466f ,
+0.444122145f , -0.895966250f ,
+0.449611330f , -0.893224301f ,
+0.455083587f , -0.890448723f ,
+0.460538711f , -0.887639620f ,
+0.465976496f , -0.884797098f ,
+0.471396737f , -0.881921264f ,
+0.476799230f , -0.879012226f ,
+0.482183772f , -0.876070094f ,
+0.487550160f , -0.873094978f ,
+0.492898192f , -0.870086991f ,
+0.498227667f , -0.867046246f ,
+0.503538384f , -0.863972856f ,
+0.508830143f , -0.860866939f ,
+0.514102744f , -0.857728610f ,
+0.519355990f , -0.854557988f ,
+0.524589683f , -0.851355193f ,
+0.529803625f , -0.848120345f ,
+0.534997620f , -0.844853565f ,
+0.540171473f , -0.841554977f ,
+0.545324988f , -0.838224706f ,
+0.550457973f , -0.834862875f ,
+0.555570233f , -0.831469612f ,
+0.560661576f , -0.828045045f ,
+0.565731811f , -0.824589303f ,
+0.570780746f , -0.821102515f ,
+0.575808191f , -0.817584813f ,
+0.580813958f , -0.814036330f ,
+0.585797857f , -0.810457198f ,
+0.590759702f , -0.806847554f ,
+0.595699304f , -0.803207531f ,
+0.600616479f , -0.799537269f ,
+0.605511041f , -0.795836905f ,
+0.610382806f , -0.792106577f ,
+0.615231591f , -0.788346428f ,
+0.620057212f , -0.784556597f ,
+0.624859488f , -0.780737229f ,
+0.629638239f , -0.776888466f ,
+0.634393284f , -0.773010453f ,
+0.639124445f , -0.769103338f ,
+0.643831543f , -0.765167266f ,
+0.648514401f , -0.761202385f ,
+0.653172843f , -0.757208847f ,
+0.657806693f , -0.753186799f ,
+0.662415778f , -0.749136395f ,
+0.666999922f , -0.745057785f ,
+0.671558955f , -0.740951125f ,
+0.676092704f , -0.736816569f ,
+0.680600998f , -0.732654272f ,
+0.685083668f , -0.728464390f ,
+0.689540545f , -0.724247083f ,
+0.693971461f , -0.720002508f ,
+0.698376249f , -0.715730825f ,
+0.702754744f , -0.711432196f ,
+0.707106781f , -0.707106781f ,
+0.711432196f , -0.702754744f ,
+0.715730825f , -0.698376249f ,
+0.720002508f , -0.693971461f ,
+0.724247083f , -0.689540545f ,
+0.728464390f , -0.685083668f ,
+0.732654272f , -0.680600998f ,
+0.736816569f , -0.676092704f ,
+0.740951125f , -0.671558955f ,
+0.745057785f , -0.666999922f ,
+0.749136395f , -0.662415778f ,
+0.753186799f , -0.657806693f ,
+0.757208847f , -0.653172843f ,
+0.761202385f , -0.648514401f ,
+0.765167266f , -0.643831543f ,
+0.769103338f , -0.639124445f ,
+0.773010453f , -0.634393284f ,
+0.776888466f , -0.629638239f ,
+0.780737229f , -0.624859488f ,
+0.784556597f , -0.620057212f ,
+0.788346428f , -0.615231591f ,
+0.792106577f , -0.610382806f ,
+0.795836905f , -0.605511041f ,
+0.799537269f , -0.600616479f ,
+0.803207531f , -0.595699304f ,
+0.806847554f , -0.590759702f ,
+0.810457198f , -0.585797857f ,
+0.814036330f , -0.580813958f ,
+0.817584813f , -0.575808191f ,
+0.821102515f , -0.570780746f ,
+0.824589303f , -0.565731811f ,
+0.828045045f , -0.560661576f ,
+0.831469612f , -0.555570233f ,
+0.834862875f , -0.550457973f ,
+0.838224706f , -0.545324988f ,
+0.841554977f , -0.540171473f ,
+0.844853565f , -0.534997620f ,
+0.848120345f , -0.529803625f ,
+0.851355193f , -0.524589683f ,
+0.854557988f , -0.519355990f ,
+0.857728610f , -0.514102744f ,
+0.860866939f , -0.508830143f ,
+0.863972856f , -0.503538384f ,
+0.867046246f , -0.498227667f ,
+0.870086991f , -0.492898192f ,
+0.873094978f , -0.487550160f ,
+0.876070094f , -0.482183772f ,
+0.879012226f , -0.476799230f ,
+0.881921264f , -0.471396737f ,
+0.884797098f , -0.465976496f ,
+0.887639620f , -0.460538711f ,
+0.890448723f , -0.455083587f ,
+0.893224301f , -0.449611330f ,
+0.895966250f , -0.444122145f ,
+0.898674466f , -0.438616239f ,
+0.901348847f , -0.433093819f ,
+0.903989293f , -0.427555093f ,
+0.906595705f , -0.422000271f ,
+0.909167983f , -0.416429560f ,
+0.911706032f , -0.410843171f ,
+0.914209756f , -0.405241314f ,
+0.916679060f , -0.399624200f ,
+0.919113852f , -0.393992040f ,
+0.921514039f , -0.388345047f ,
+0.923879533f , -0.382683432f ,
+0.926210242f , -0.377007410f ,
+0.928506080f , -0.371317194f ,
+0.930766961f , -0.365612998f ,
+0.932992799f , -0.359895037f ,
+0.935183510f , -0.354163525f ,
+0.937339012f , -0.348418680f ,
+0.939459224f , -0.342660717f ,
+0.941544065f , -0.336889853f ,
+0.943593458f , -0.331106306f ,
+0.945607325f , -0.325310292f ,
+0.947585591f , -0.319502031f ,
+0.949528181f , -0.313681740f ,
+0.951435021f , -0.307849640f ,
+0.953306040f , -0.302005949f ,
+0.955141168f , -0.296150888f ,
+0.956940336f , -0.290284677f ,
+0.958703475f , -0.284407537f ,
+0.960430519f , -0.278519689f ,
+0.962121404f , -0.272621355f ,
+0.963776066f , -0.266712757f ,
+0.965394442f , -0.260794118f ,
+0.966976471f , -0.254865660f ,
+0.968522094f , -0.248927606f ,
+0.970031253f , -0.242980180f ,
+0.971503891f , -0.237023606f ,
+0.972939952f , -0.231058108f ,
+0.974339383f , -0.225083911f ,
+0.975702130f , -0.219101240f ,
+0.977028143f , -0.213110320f ,
+0.978317371f , -0.207111376f ,
+0.979569766f , -0.201104635f ,
+0.980785280f , -0.195090322f ,
+0.981963869f , -0.189068664f ,
+0.983105487f , -0.183039888f ,
+0.984210092f , -0.177004220f ,
+0.985277642f , -0.170961889f ,
+0.986308097f , -0.164913120f ,
+0.987301418f , -0.158858143f ,
+0.988257568f , -0.152797185f ,
+0.989176510f , -0.146730474f ,
+0.990058210f , -0.140658239f ,
+0.990902635f , -0.134580709f ,
+0.991709754f , -0.128498111f ,
+0.992479535f , -0.122410675f ,
+0.993211949f , -0.116318631f ,
+0.993906970f , -0.110222207f ,
+0.994564571f , -0.104121634f ,
+0.995184727f , -0.098017140f ,
+0.995767414f , -0.091908956f ,
+0.996312612f , -0.085797312f ,
+0.996820299f , -0.079682438f ,
+0.997290457f , -0.073564564f ,
+0.997723067f , -0.067443920f ,
+0.998118113f , -0.061320736f ,
+0.998475581f , -0.055195244f ,
+0.998795456f , -0.049067674f ,
+0.999077728f , -0.042938257f ,
+0.999322385f , -0.036807223f ,
+0.999529418f , -0.030674803f ,
+0.999698819f , -0.024541229f ,
+0.999830582f , -0.018406730f ,
+0.999924702f , -0.012271538f ,
+0.999981175f , -0.006135885f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 2048 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_2048[4096] = {
+ 1.000000000f, 0.000000000f,
+ 0.999995294f, 0.003067957f,
+ 0.999981175f, 0.006135885f,
+ 0.999957645f, 0.009203755f,
+ 0.999924702f, 0.012271538f,
+ 0.999882347f, 0.015339206f,
+ 0.999830582f, 0.018406730f,
+ 0.999769405f, 0.021474080f,
+ 0.999698819f, 0.024541229f,
+ 0.999618822f, 0.027608146f,
+ 0.999529418f, 0.030674803f,
+ 0.999430605f, 0.033741172f,
+ 0.999322385f, 0.036807223f,
+ 0.999204759f, 0.039872928f,
+ 0.999077728f, 0.042938257f,
+ 0.998941293f, 0.046003182f,
+ 0.998795456f, 0.049067674f,
+ 0.998640218f, 0.052131705f,
+ 0.998475581f, 0.055195244f,
+ 0.998301545f, 0.058258265f,
+ 0.998118113f, 0.061320736f,
+ 0.997925286f, 0.064382631f,
+ 0.997723067f, 0.067443920f,
+ 0.997511456f, 0.070504573f,
+ 0.997290457f, 0.073564564f,
+ 0.997060070f, 0.076623861f,
+ 0.996820299f, 0.079682438f,
+ 0.996571146f, 0.082740265f,
+ 0.996312612f, 0.085797312f,
+ 0.996044701f, 0.088853553f,
+ 0.995767414f, 0.091908956f,
+ 0.995480755f, 0.094963495f,
+ 0.995184727f, 0.098017140f,
+ 0.994879331f, 0.101069863f,
+ 0.994564571f, 0.104121634f,
+ 0.994240449f, 0.107172425f,
+ 0.993906970f, 0.110222207f,
+ 0.993564136f, 0.113270952f,
+ 0.993211949f, 0.116318631f,
+ 0.992850414f, 0.119365215f,
+ 0.992479535f, 0.122410675f,
+ 0.992099313f, 0.125454983f,
+ 0.991709754f, 0.128498111f,
+ 0.991310860f, 0.131540029f,
+ 0.990902635f, 0.134580709f,
+ 0.990485084f, 0.137620122f,
+ 0.990058210f, 0.140658239f,
+ 0.989622017f, 0.143695033f,
+ 0.989176510f, 0.146730474f,
+ 0.988721692f, 0.149764535f,
+ 0.988257568f, 0.152797185f,
+ 0.987784142f, 0.155828398f,
+ 0.987301418f, 0.158858143f,
+ 0.986809402f, 0.161886394f,
+ 0.986308097f, 0.164913120f,
+ 0.985797509f, 0.167938295f,
+ 0.985277642f, 0.170961889f,
+ 0.984748502f, 0.173983873f,
+ 0.984210092f, 0.177004220f,
+ 0.983662419f, 0.180022901f,
+ 0.983105487f, 0.183039888f,
+ 0.982539302f, 0.186055152f,
+ 0.981963869f, 0.189068664f,
+ 0.981379193f, 0.192080397f,
+ 0.980785280f, 0.195090322f,
+ 0.980182136f, 0.198098411f,
+ 0.979569766f, 0.201104635f,
+ 0.978948175f, 0.204108966f,
+ 0.978317371f, 0.207111376f,
+ 0.977677358f, 0.210111837f,
+ 0.977028143f, 0.213110320f,
+ 0.976369731f, 0.216106797f,
+ 0.975702130f, 0.219101240f,
+ 0.975025345f, 0.222093621f,
+ 0.974339383f, 0.225083911f,
+ 0.973644250f, 0.228072083f,
+ 0.972939952f, 0.231058108f,
+ 0.972226497f, 0.234041959f,
+ 0.971503891f, 0.237023606f,
+ 0.970772141f, 0.240003022f,
+ 0.970031253f, 0.242980180f,
+ 0.969281235f, 0.245955050f,
+ 0.968522094f, 0.248927606f,
+ 0.967753837f, 0.251897818f,
+ 0.966976471f, 0.254865660f,
+ 0.966190003f, 0.257831102f,
+ 0.965394442f, 0.260794118f,
+ 0.964589793f, 0.263754679f,
+ 0.963776066f, 0.266712757f,
+ 0.962953267f, 0.269668326f,
+ 0.962121404f, 0.272621355f,
+ 0.961280486f, 0.275571819f,
+ 0.960430519f, 0.278519689f,
+ 0.959571513f, 0.281464938f,
+ 0.958703475f, 0.284407537f,
+ 0.957826413f, 0.287347460f,
+ 0.956940336f, 0.290284677f,
+ 0.956045251f, 0.293219163f,
+ 0.955141168f, 0.296150888f,
+ 0.954228095f, 0.299079826f,
+ 0.953306040f, 0.302005949f,
+ 0.952375013f, 0.304929230f,
+ 0.951435021f, 0.307849640f,
+ 0.950486074f, 0.310767153f,
+ 0.949528181f, 0.313681740f,
+ 0.948561350f, 0.316593376f,
+ 0.947585591f, 0.319502031f,
+ 0.946600913f, 0.322407679f,
+ 0.945607325f, 0.325310292f,
+ 0.944604837f, 0.328209844f,
+ 0.943593458f, 0.331106306f,
+ 0.942573198f, 0.333999651f,
+ 0.941544065f, 0.336889853f,
+ 0.940506071f, 0.339776884f,
+ 0.939459224f, 0.342660717f,
+ 0.938403534f, 0.345541325f,
+ 0.937339012f, 0.348418680f,
+ 0.936265667f, 0.351292756f,
+ 0.935183510f, 0.354163525f,
+ 0.934092550f, 0.357030961f,
+ 0.932992799f, 0.359895037f,
+ 0.931884266f, 0.362755724f,
+ 0.930766961f, 0.365612998f,
+ 0.929640896f, 0.368466830f,
+ 0.928506080f, 0.371317194f,
+ 0.927362526f, 0.374164063f,
+ 0.926210242f, 0.377007410f,
+ 0.925049241f, 0.379847209f,
+ 0.923879533f, 0.382683432f,
+ 0.922701128f, 0.385516054f,
+ 0.921514039f, 0.388345047f,
+ 0.920318277f, 0.391170384f,
+ 0.919113852f, 0.393992040f,
+ 0.917900776f, 0.396809987f,
+ 0.916679060f, 0.399624200f,
+ 0.915448716f, 0.402434651f,
+ 0.914209756f, 0.405241314f,
+ 0.912962190f, 0.408044163f,
+ 0.911706032f, 0.410843171f,
+ 0.910441292f, 0.413638312f,
+ 0.909167983f, 0.416429560f,
+ 0.907886116f, 0.419216888f,
+ 0.906595705f, 0.422000271f,
+ 0.905296759f, 0.424779681f,
+ 0.903989293f, 0.427555093f,
+ 0.902673318f, 0.430326481f,
+ 0.901348847f, 0.433093819f,
+ 0.900015892f, 0.435857080f,
+ 0.898674466f, 0.438616239f,
+ 0.897324581f, 0.441371269f,
+ 0.895966250f, 0.444122145f,
+ 0.894599486f, 0.446868840f,
+ 0.893224301f, 0.449611330f,
+ 0.891840709f, 0.452349587f,
+ 0.890448723f, 0.455083587f,
+ 0.889048356f, 0.457813304f,
+ 0.887639620f, 0.460538711f,
+ 0.886222530f, 0.463259784f,
+ 0.884797098f, 0.465976496f,
+ 0.883363339f, 0.468688822f,
+ 0.881921264f, 0.471396737f,
+ 0.880470889f, 0.474100215f,
+ 0.879012226f, 0.476799230f,
+ 0.877545290f, 0.479493758f,
+ 0.876070094f, 0.482183772f,
+ 0.874586652f, 0.484869248f,
+ 0.873094978f, 0.487550160f,
+ 0.871595087f, 0.490226483f,
+ 0.870086991f, 0.492898192f,
+ 0.868570706f, 0.495565262f,
+ 0.867046246f, 0.498227667f,
+ 0.865513624f, 0.500885383f,
+ 0.863972856f, 0.503538384f,
+ 0.862423956f, 0.506186645f,
+ 0.860866939f, 0.508830143f,
+ 0.859301818f, 0.511468850f,
+ 0.857728610f, 0.514102744f,
+ 0.856147328f, 0.516731799f,
+ 0.854557988f, 0.519355990f,
+ 0.852960605f, 0.521975293f,
+ 0.851355193f, 0.524589683f,
+ 0.849741768f, 0.527199135f,
+ 0.848120345f, 0.529803625f,
+ 0.846490939f, 0.532403128f,
+ 0.844853565f, 0.534997620f,
+ 0.843208240f, 0.537587076f,
+ 0.841554977f, 0.540171473f,
+ 0.839893794f, 0.542750785f,
+ 0.838224706f, 0.545324988f,
+ 0.836547727f, 0.547894059f,
+ 0.834862875f, 0.550457973f,
+ 0.833170165f, 0.553016706f,
+ 0.831469612f, 0.555570233f,
+ 0.829761234f, 0.558118531f,
+ 0.828045045f, 0.560661576f,
+ 0.826321063f, 0.563199344f,
+ 0.824589303f, 0.565731811f,
+ 0.822849781f, 0.568258953f,
+ 0.821102515f, 0.570780746f,
+ 0.819347520f, 0.573297167f,
+ 0.817584813f, 0.575808191f,
+ 0.815814411f, 0.578313796f,
+ 0.814036330f, 0.580813958f,
+ 0.812250587f, 0.583308653f,
+ 0.810457198f, 0.585797857f,
+ 0.808656182f, 0.588281548f,
+ 0.806847554f, 0.590759702f,
+ 0.805031331f, 0.593232295f,
+ 0.803207531f, 0.595699304f,
+ 0.801376172f, 0.598160707f,
+ 0.799537269f, 0.600616479f,
+ 0.797690841f, 0.603066599f,
+ 0.795836905f, 0.605511041f,
+ 0.793975478f, 0.607949785f,
+ 0.792106577f, 0.610382806f,
+ 0.790230221f, 0.612810082f,
+ 0.788346428f, 0.615231591f,
+ 0.786455214f, 0.617647308f,
+ 0.784556597f, 0.620057212f,
+ 0.782650596f, 0.622461279f,
+ 0.780737229f, 0.624859488f,
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+ 0.836547727f, -0.547894059f,
+ 0.838224706f, -0.545324988f,
+ 0.839893794f, -0.542750785f,
+ 0.841554977f, -0.540171473f,
+ 0.843208240f, -0.537587076f,
+ 0.844853565f, -0.534997620f,
+ 0.846490939f, -0.532403128f,
+ 0.848120345f, -0.529803625f,
+ 0.849741768f, -0.527199135f,
+ 0.851355193f, -0.524589683f,
+ 0.852960605f, -0.521975293f,
+ 0.854557988f, -0.519355990f,
+ 0.856147328f, -0.516731799f,
+ 0.857728610f, -0.514102744f,
+ 0.859301818f, -0.511468850f,
+ 0.860866939f, -0.508830143f,
+ 0.862423956f, -0.506186645f,
+ 0.863972856f, -0.503538384f,
+ 0.865513624f, -0.500885383f,
+ 0.867046246f, -0.498227667f,
+ 0.868570706f, -0.495565262f,
+ 0.870086991f, -0.492898192f,
+ 0.871595087f, -0.490226483f,
+ 0.873094978f, -0.487550160f,
+ 0.874586652f, -0.484869248f,
+ 0.876070094f, -0.482183772f,
+ 0.877545290f, -0.479493758f,
+ 0.879012226f, -0.476799230f,
+ 0.880470889f, -0.474100215f,
+ 0.881921264f, -0.471396737f,
+ 0.883363339f, -0.468688822f,
+ 0.884797098f, -0.465976496f,
+ 0.886222530f, -0.463259784f,
+ 0.887639620f, -0.460538711f,
+ 0.889048356f, -0.457813304f,
+ 0.890448723f, -0.455083587f,
+ 0.891840709f, -0.452349587f,
+ 0.893224301f, -0.449611330f,
+ 0.894599486f, -0.446868840f,
+ 0.895966250f, -0.444122145f,
+ 0.897324581f, -0.441371269f,
+ 0.898674466f, -0.438616239f,
+ 0.900015892f, -0.435857080f,
+ 0.901348847f, -0.433093819f,
+ 0.902673318f, -0.430326481f,
+ 0.903989293f, -0.427555093f,
+ 0.905296759f, -0.424779681f,
+ 0.906595705f, -0.422000271f,
+ 0.907886116f, -0.419216888f,
+ 0.909167983f, -0.416429560f,
+ 0.910441292f, -0.413638312f,
+ 0.911706032f, -0.410843171f,
+ 0.912962190f, -0.408044163f,
+ 0.914209756f, -0.405241314f,
+ 0.915448716f, -0.402434651f,
+ 0.916679060f, -0.399624200f,
+ 0.917900776f, -0.396809987f,
+ 0.919113852f, -0.393992040f,
+ 0.920318277f, -0.391170384f,
+ 0.921514039f, -0.388345047f,
+ 0.922701128f, -0.385516054f,
+ 0.923879533f, -0.382683432f,
+ 0.925049241f, -0.379847209f,
+ 0.926210242f, -0.377007410f,
+ 0.927362526f, -0.374164063f,
+ 0.928506080f, -0.371317194f,
+ 0.929640896f, -0.368466830f,
+ 0.930766961f, -0.365612998f,
+ 0.931884266f, -0.362755724f,
+ 0.932992799f, -0.359895037f,
+ 0.934092550f, -0.357030961f,
+ 0.935183510f, -0.354163525f,
+ 0.936265667f, -0.351292756f,
+ 0.937339012f, -0.348418680f,
+ 0.938403534f, -0.345541325f,
+ 0.939459224f, -0.342660717f,
+ 0.940506071f, -0.339776884f,
+ 0.941544065f, -0.336889853f,
+ 0.942573198f, -0.333999651f,
+ 0.943593458f, -0.331106306f,
+ 0.944604837f, -0.328209844f,
+ 0.945607325f, -0.325310292f,
+ 0.946600913f, -0.322407679f,
+ 0.947585591f, -0.319502031f,
+ 0.948561350f, -0.316593376f,
+ 0.949528181f, -0.313681740f,
+ 0.950486074f, -0.310767153f,
+ 0.951435021f, -0.307849640f,
+ 0.952375013f, -0.304929230f,
+ 0.953306040f, -0.302005949f,
+ 0.954228095f, -0.299079826f,
+ 0.955141168f, -0.296150888f,
+ 0.956045251f, -0.293219163f,
+ 0.956940336f, -0.290284677f,
+ 0.957826413f, -0.287347460f,
+ 0.958703475f, -0.284407537f,
+ 0.959571513f, -0.281464938f,
+ 0.960430519f, -0.278519689f,
+ 0.961280486f, -0.275571819f,
+ 0.962121404f, -0.272621355f,
+ 0.962953267f, -0.269668326f,
+ 0.963776066f, -0.266712757f,
+ 0.964589793f, -0.263754679f,
+ 0.965394442f, -0.260794118f,
+ 0.966190003f, -0.257831102f,
+ 0.966976471f, -0.254865660f,
+ 0.967753837f, -0.251897818f,
+ 0.968522094f, -0.248927606f,
+ 0.969281235f, -0.245955050f,
+ 0.970031253f, -0.242980180f,
+ 0.970772141f, -0.240003022f,
+ 0.971503891f, -0.237023606f,
+ 0.972226497f, -0.234041959f,
+ 0.972939952f, -0.231058108f,
+ 0.973644250f, -0.228072083f,
+ 0.974339383f, -0.225083911f,
+ 0.975025345f, -0.222093621f,
+ 0.975702130f, -0.219101240f,
+ 0.976369731f, -0.216106797f,
+ 0.977028143f, -0.213110320f,
+ 0.977677358f, -0.210111837f,
+ 0.978317371f, -0.207111376f,
+ 0.978948175f, -0.204108966f,
+ 0.979569766f, -0.201104635f,
+ 0.980182136f, -0.198098411f,
+ 0.980785280f, -0.195090322f,
+ 0.981379193f, -0.192080397f,
+ 0.981963869f, -0.189068664f,
+ 0.982539302f, -0.186055152f,
+ 0.983105487f, -0.183039888f,
+ 0.983662419f, -0.180022901f,
+ 0.984210092f, -0.177004220f,
+ 0.984748502f, -0.173983873f,
+ 0.985277642f, -0.170961889f,
+ 0.985797509f, -0.167938295f,
+ 0.986308097f, -0.164913120f,
+ 0.986809402f, -0.161886394f,
+ 0.987301418f, -0.158858143f,
+ 0.987784142f, -0.155828398f,
+ 0.988257568f, -0.152797185f,
+ 0.988721692f, -0.149764535f,
+ 0.989176510f, -0.146730474f,
+ 0.989622017f, -0.143695033f,
+ 0.990058210f, -0.140658239f,
+ 0.990485084f, -0.137620122f,
+ 0.990902635f, -0.134580709f,
+ 0.991310860f, -0.131540029f,
+ 0.991709754f, -0.128498111f,
+ 0.992099313f, -0.125454983f,
+ 0.992479535f, -0.122410675f,
+ 0.992850414f, -0.119365215f,
+ 0.993211949f, -0.116318631f,
+ 0.993564136f, -0.113270952f,
+ 0.993906970f, -0.110222207f,
+ 0.994240449f, -0.107172425f,
+ 0.994564571f, -0.104121634f,
+ 0.994879331f, -0.101069863f,
+ 0.995184727f, -0.098017140f,
+ 0.995480755f, -0.094963495f,
+ 0.995767414f, -0.091908956f,
+ 0.996044701f, -0.088853553f,
+ 0.996312612f, -0.085797312f,
+ 0.996571146f, -0.082740265f,
+ 0.996820299f, -0.079682438f,
+ 0.997060070f, -0.076623861f,
+ 0.997290457f, -0.073564564f,
+ 0.997511456f, -0.070504573f,
+ 0.997723067f, -0.067443920f,
+ 0.997925286f, -0.064382631f,
+ 0.998118113f, -0.061320736f,
+ 0.998301545f, -0.058258265f,
+ 0.998475581f, -0.055195244f,
+ 0.998640218f, -0.052131705f,
+ 0.998795456f, -0.049067674f,
+ 0.998941293f, -0.046003182f,
+ 0.999077728f, -0.042938257f,
+ 0.999204759f, -0.039872928f,
+ 0.999322385f, -0.036807223f,
+ 0.999430605f, -0.033741172f,
+ 0.999529418f, -0.030674803f,
+ 0.999618822f, -0.027608146f,
+ 0.999698819f, -0.024541229f,
+ 0.999769405f, -0.021474080f,
+ 0.999830582f, -0.018406730f,
+ 0.999882347f, -0.015339206f,
+ 0.999924702f, -0.012271538f,
+ 0.999957645f, -0.009203755f,
+ 0.999981175f, -0.006135885f,
+ 0.999995294f, -0.003067957f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_4096[8192] = {
+ 1.000000000f, 0.000000000f,
+ 0.999998823f, 0.001533980f,
+ 0.999995294f, 0.003067957f,
+ 0.999989411f, 0.004601926f,
+ 0.999981175f, 0.006135885f,
+ 0.999970586f, 0.007669829f,
+ 0.999957645f, 0.009203755f,
+ 0.999942350f, 0.010737659f,
+ 0.999924702f, 0.012271538f,
+ 0.999904701f, 0.013805389f,
+ 0.999882347f, 0.015339206f,
+ 0.999857641f, 0.016872988f,
+ 0.999830582f, 0.018406730f,
+ 0.999801170f, 0.019940429f,
+ 0.999769405f, 0.021474080f,
+ 0.999735288f, 0.023007681f,
+ 0.999698819f, 0.024541229f,
+ 0.999659997f, 0.026074718f,
+ 0.999618822f, 0.027608146f,
+ 0.999575296f, 0.029141509f,
+ 0.999529418f, 0.030674803f,
+ 0.999481187f, 0.032208025f,
+ 0.999430605f, 0.033741172f,
+ 0.999377670f, 0.035274239f,
+ 0.999322385f, 0.036807223f,
+ 0.999264747f, 0.038340120f,
+ 0.999204759f, 0.039872928f,
+ 0.999142419f, 0.041405641f,
+ 0.999077728f, 0.042938257f,
+ 0.999010686f, 0.044470772f,
+ 0.998941293f, 0.046003182f,
+ 0.998869550f, 0.047535484f,
+ 0.998795456f, 0.049067674f,
+ 0.998719012f, 0.050599749f,
+ 0.998640218f, 0.052131705f,
+ 0.998559074f, 0.053663538f,
+ 0.998475581f, 0.055195244f,
+ 0.998389737f, 0.056726821f,
+ 0.998301545f, 0.058258265f,
+ 0.998211003f, 0.059789571f,
+ 0.998118113f, 0.061320736f,
+ 0.998022874f, 0.062851758f,
+ 0.997925286f, 0.064382631f,
+ 0.997825350f, 0.065913353f,
+ 0.997723067f, 0.067443920f,
+ 0.997618435f, 0.068974328f,
+ 0.997511456f, 0.070504573f,
+ 0.997402130f, 0.072034653f,
+ 0.997290457f, 0.073564564f,
+ 0.997176437f, 0.075094301f,
+ 0.997060070f, 0.076623861f,
+ 0.996941358f, 0.078153242f,
+ 0.996820299f, 0.079682438f,
+ 0.996696895f, 0.081211447f,
+ 0.996571146f, 0.082740265f,
+ 0.996443051f, 0.084268888f,
+ 0.996312612f, 0.085797312f,
+ 0.996179829f, 0.087325535f,
+ 0.996044701f, 0.088853553f,
+ 0.995907229f, 0.090381361f,
+ 0.995767414f, 0.091908956f,
+ 0.995625256f, 0.093436336f,
+ 0.995480755f, 0.094963495f,
+ 0.995333912f, 0.096490431f,
+ 0.995184727f, 0.098017140f,
+ 0.995033199f, 0.099543619f,
+ 0.994879331f, 0.101069863f,
+ 0.994723121f, 0.102595869f,
+ 0.994564571f, 0.104121634f,
+ 0.994403680f, 0.105647154f,
+ 0.994240449f, 0.107172425f,
+ 0.994074879f, 0.108697444f,
+ 0.993906970f, 0.110222207f,
+ 0.993736722f, 0.111746711f,
+ 0.993564136f, 0.113270952f,
+ 0.993389211f, 0.114794927f,
+ 0.993211949f, 0.116318631f,
+ 0.993032350f, 0.117842062f,
+ 0.992850414f, 0.119365215f,
+ 0.992666142f, 0.120888087f,
+ 0.992479535f, 0.122410675f,
+ 0.992290591f, 0.123932975f,
+ 0.992099313f, 0.125454983f,
+ 0.991905700f, 0.126976696f,
+ 0.991709754f, 0.128498111f,
+ 0.991511473f, 0.130019223f,
+ 0.991310860f, 0.131540029f,
+ 0.991107914f, 0.133060525f,
+ 0.990902635f, 0.134580709f,
+ 0.990695025f, 0.136100575f,
+ 0.990485084f, 0.137620122f,
+ 0.990272812f, 0.139139344f,
+ 0.990058210f, 0.140658239f,
+ 0.989841278f, 0.142176804f,
+ 0.989622017f, 0.143695033f,
+ 0.989400428f, 0.145212925f,
+ 0.989176510f, 0.146730474f,
+ 0.988950265f, 0.148247679f,
+ 0.988721692f, 0.149764535f,
+ 0.988490793f, 0.151281038f,
+ 0.988257568f, 0.152797185f,
+ 0.988022017f, 0.154312973f,
+ 0.987784142f, 0.155828398f,
+ 0.987543942f, 0.157343456f,
+ 0.987301418f, 0.158858143f,
+ 0.987056571f, 0.160372457f,
+ 0.986809402f, 0.161886394f,
+ 0.986559910f, 0.163399949f,
+ 0.986308097f, 0.164913120f,
+ 0.986053963f, 0.166425904f,
+ 0.985797509f, 0.167938295f,
+ 0.985538735f, 0.169450291f,
+ 0.985277642f, 0.170961889f,
+ 0.985014231f, 0.172473084f,
+ 0.984748502f, 0.173983873f,
+ 0.984480455f, 0.175494253f,
+ 0.984210092f, 0.177004220f,
+ 0.983937413f, 0.178513771f,
+ 0.983662419f, 0.180022901f,
+ 0.983385110f, 0.181531608f,
+ 0.983105487f, 0.183039888f,
+ 0.982823551f, 0.184547737f,
+ 0.982539302f, 0.186055152f,
+ 0.982252741f, 0.187562129f,
+ 0.981963869f, 0.189068664f,
+ 0.981672686f, 0.190574755f,
+ 0.981379193f, 0.192080397f,
+ 0.981083391f, 0.193585587f,
+ 0.980785280f, 0.195090322f,
+ 0.980484862f, 0.196594598f,
+ 0.980182136f, 0.198098411f,
+ 0.979877104f, 0.199601758f,
+ 0.979569766f, 0.201104635f,
+ 0.979260123f, 0.202607039f,
+ 0.978948175f, 0.204108966f,
+ 0.978633924f, 0.205610413f,
+ 0.978317371f, 0.207111376f,
+ 0.977998515f, 0.208611852f,
+ 0.977677358f, 0.210111837f,
+ 0.977353900f, 0.211611327f,
+ 0.977028143f, 0.213110320f,
+ 0.976700086f, 0.214608811f,
+ 0.976369731f, 0.216106797f,
+ 0.976037079f, 0.217604275f,
+ 0.975702130f, 0.219101240f,
+ 0.975364885f, 0.220597690f,
+ 0.975025345f, 0.222093621f,
+ 0.974683511f, 0.223589029f,
+ 0.974339383f, 0.225083911f,
+ 0.973992962f, 0.226578264f,
+ 0.973644250f, 0.228072083f,
+ 0.973293246f, 0.229565366f,
+ 0.972939952f, 0.231058108f,
+ 0.972584369f, 0.232550307f,
+ 0.972226497f, 0.234041959f,
+ 0.971866337f, 0.235533059f,
+ 0.971503891f, 0.237023606f,
+ 0.971139158f, 0.238513595f,
+ 0.970772141f, 0.240003022f,
+ 0.970402839f, 0.241491885f,
+ 0.970031253f, 0.242980180f,
+ 0.969657385f, 0.244467903f,
+ 0.969281235f, 0.245955050f,
+ 0.968902805f, 0.247441619f,
+ 0.968522094f, 0.248927606f,
+ 0.968139105f, 0.250413007f,
+ 0.967753837f, 0.251897818f,
+ 0.967366292f, 0.253382037f,
+ 0.966976471f, 0.254865660f,
+ 0.966584374f, 0.256348682f,
+ 0.966190003f, 0.257831102f,
+ 0.965793359f, 0.259312915f,
+ 0.965394442f, 0.260794118f,
+ 0.964993253f, 0.262274707f,
+ 0.964589793f, 0.263754679f,
+ 0.964184064f, 0.265234030f,
+ 0.963776066f, 0.266712757f,
+ 0.963365800f, 0.268190857f,
+ 0.962953267f, 0.269668326f,
+ 0.962538468f, 0.271145160f,
+ 0.962121404f, 0.272621355f,
+ 0.961702077f, 0.274096910f,
+ 0.961280486f, 0.275571819f,
+ 0.960856633f, 0.277046080f,
+ 0.960430519f, 0.278519689f,
+ 0.960002146f, 0.279992643f,
+ 0.959571513f, 0.281464938f,
+ 0.959138622f, 0.282936570f,
+ 0.958703475f, 0.284407537f,
+ 0.958266071f, 0.285877835f,
+ 0.957826413f, 0.287347460f,
+ 0.957384501f, 0.288816408f,
+ 0.956940336f, 0.290284677f,
+ 0.956493919f, 0.291752263f,
+ 0.956045251f, 0.293219163f,
+ 0.955594334f, 0.294685372f,
+ 0.955141168f, 0.296150888f,
+ 0.954685755f, 0.297615707f,
+ 0.954228095f, 0.299079826f,
+ 0.953768190f, 0.300543241f,
+ 0.953306040f, 0.302005949f,
+ 0.952841648f, 0.303467947f,
+ 0.952375013f, 0.304929230f,
+ 0.951906137f, 0.306389795f,
+ 0.951435021f, 0.307849640f,
+ 0.950961666f, 0.309308760f,
+ 0.950486074f, 0.310767153f,
+ 0.950008245f, 0.312224814f,
+ 0.949528181f, 0.313681740f,
+ 0.949045882f, 0.315137929f,
+ 0.948561350f, 0.316593376f,
+ 0.948074586f, 0.318048077f,
+ 0.947585591f, 0.319502031f,
+ 0.947094366f, 0.320955232f,
+ 0.946600913f, 0.322407679f,
+ 0.946105232f, 0.323859367f,
+ 0.945607325f, 0.325310292f,
+ 0.945107193f, 0.326760452f,
+ 0.944604837f, 0.328209844f,
+ 0.944100258f, 0.329658463f,
+ 0.943593458f, 0.331106306f,
+ 0.943084437f, 0.332553370f,
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+ 0.962953267f, -0.269668326f,
+ 0.963365800f, -0.268190857f,
+ 0.963776066f, -0.266712757f,
+ 0.964184064f, -0.265234030f,
+ 0.964589793f, -0.263754679f,
+ 0.964993253f, -0.262274707f,
+ 0.965394442f, -0.260794118f,
+ 0.965793359f, -0.259312915f,
+ 0.966190003f, -0.257831102f,
+ 0.966584374f, -0.256348682f,
+ 0.966976471f, -0.254865660f,
+ 0.967366292f, -0.253382037f,
+ 0.967753837f, -0.251897818f,
+ 0.968139105f, -0.250413007f,
+ 0.968522094f, -0.248927606f,
+ 0.968902805f, -0.247441619f,
+ 0.969281235f, -0.245955050f,
+ 0.969657385f, -0.244467903f,
+ 0.970031253f, -0.242980180f,
+ 0.970402839f, -0.241491885f,
+ 0.970772141f, -0.240003022f,
+ 0.971139158f, -0.238513595f,
+ 0.971503891f, -0.237023606f,
+ 0.971866337f, -0.235533059f,
+ 0.972226497f, -0.234041959f,
+ 0.972584369f, -0.232550307f,
+ 0.972939952f, -0.231058108f,
+ 0.973293246f, -0.229565366f,
+ 0.973644250f, -0.228072083f,
+ 0.973992962f, -0.226578264f,
+ 0.974339383f, -0.225083911f,
+ 0.974683511f, -0.223589029f,
+ 0.975025345f, -0.222093621f,
+ 0.975364885f, -0.220597690f,
+ 0.975702130f, -0.219101240f,
+ 0.976037079f, -0.217604275f,
+ 0.976369731f, -0.216106797f,
+ 0.976700086f, -0.214608811f,
+ 0.977028143f, -0.213110320f,
+ 0.977353900f, -0.211611327f,
+ 0.977677358f, -0.210111837f,
+ 0.977998515f, -0.208611852f,
+ 0.978317371f, -0.207111376f,
+ 0.978633924f, -0.205610413f,
+ 0.978948175f, -0.204108966f,
+ 0.979260123f, -0.202607039f,
+ 0.979569766f, -0.201104635f,
+ 0.979877104f, -0.199601758f,
+ 0.980182136f, -0.198098411f,
+ 0.980484862f, -0.196594598f,
+ 0.980785280f, -0.195090322f,
+ 0.981083391f, -0.193585587f,
+ 0.981379193f, -0.192080397f,
+ 0.981672686f, -0.190574755f,
+ 0.981963869f, -0.189068664f,
+ 0.982252741f, -0.187562129f,
+ 0.982539302f, -0.186055152f,
+ 0.982823551f, -0.184547737f,
+ 0.983105487f, -0.183039888f,
+ 0.983385110f, -0.181531608f,
+ 0.983662419f, -0.180022901f,
+ 0.983937413f, -0.178513771f,
+ 0.984210092f, -0.177004220f,
+ 0.984480455f, -0.175494253f,
+ 0.984748502f, -0.173983873f,
+ 0.985014231f, -0.172473084f,
+ 0.985277642f, -0.170961889f,
+ 0.985538735f, -0.169450291f,
+ 0.985797509f, -0.167938295f,
+ 0.986053963f, -0.166425904f,
+ 0.986308097f, -0.164913120f,
+ 0.986559910f, -0.163399949f,
+ 0.986809402f, -0.161886394f,
+ 0.987056571f, -0.160372457f,
+ 0.987301418f, -0.158858143f,
+ 0.987543942f, -0.157343456f,
+ 0.987784142f, -0.155828398f,
+ 0.988022017f, -0.154312973f,
+ 0.988257568f, -0.152797185f,
+ 0.988490793f, -0.151281038f,
+ 0.988721692f, -0.149764535f,
+ 0.988950265f, -0.148247679f,
+ 0.989176510f, -0.146730474f,
+ 0.989400428f, -0.145212925f,
+ 0.989622017f, -0.143695033f,
+ 0.989841278f, -0.142176804f,
+ 0.990058210f, -0.140658239f,
+ 0.990272812f, -0.139139344f,
+ 0.990485084f, -0.137620122f,
+ 0.990695025f, -0.136100575f,
+ 0.990902635f, -0.134580709f,
+ 0.991107914f, -0.133060525f,
+ 0.991310860f, -0.131540029f,
+ 0.991511473f, -0.130019223f,
+ 0.991709754f, -0.128498111f,
+ 0.991905700f, -0.126976696f,
+ 0.992099313f, -0.125454983f,
+ 0.992290591f, -0.123932975f,
+ 0.992479535f, -0.122410675f,
+ 0.992666142f, -0.120888087f,
+ 0.992850414f, -0.119365215f,
+ 0.993032350f, -0.117842062f,
+ 0.993211949f, -0.116318631f,
+ 0.993389211f, -0.114794927f,
+ 0.993564136f, -0.113270952f,
+ 0.993736722f, -0.111746711f,
+ 0.993906970f, -0.110222207f,
+ 0.994074879f, -0.108697444f,
+ 0.994240449f, -0.107172425f,
+ 0.994403680f, -0.105647154f,
+ 0.994564571f, -0.104121634f,
+ 0.994723121f, -0.102595869f,
+ 0.994879331f, -0.101069863f,
+ 0.995033199f, -0.099543619f,
+ 0.995184727f, -0.098017140f,
+ 0.995333912f, -0.096490431f,
+ 0.995480755f, -0.094963495f,
+ 0.995625256f, -0.093436336f,
+ 0.995767414f, -0.091908956f,
+ 0.995907229f, -0.090381361f,
+ 0.996044701f, -0.088853553f,
+ 0.996179829f, -0.087325535f,
+ 0.996312612f, -0.085797312f,
+ 0.996443051f, -0.084268888f,
+ 0.996571146f, -0.082740265f,
+ 0.996696895f, -0.081211447f,
+ 0.996820299f, -0.079682438f,
+ 0.996941358f, -0.078153242f,
+ 0.997060070f, -0.076623861f,
+ 0.997176437f, -0.075094301f,
+ 0.997290457f, -0.073564564f,
+ 0.997402130f, -0.072034653f,
+ 0.997511456f, -0.070504573f,
+ 0.997618435f, -0.068974328f,
+ 0.997723067f, -0.067443920f,
+ 0.997825350f, -0.065913353f,
+ 0.997925286f, -0.064382631f,
+ 0.998022874f, -0.062851758f,
+ 0.998118113f, -0.061320736f,
+ 0.998211003f, -0.059789571f,
+ 0.998301545f, -0.058258265f,
+ 0.998389737f, -0.056726821f,
+ 0.998475581f, -0.055195244f,
+ 0.998559074f, -0.053663538f,
+ 0.998640218f, -0.052131705f,
+ 0.998719012f, -0.050599749f,
+ 0.998795456f, -0.049067674f,
+ 0.998869550f, -0.047535484f,
+ 0.998941293f, -0.046003182f,
+ 0.999010686f, -0.044470772f,
+ 0.999077728f, -0.042938257f,
+ 0.999142419f, -0.041405641f,
+ 0.999204759f, -0.039872928f,
+ 0.999264747f, -0.038340120f,
+ 0.999322385f, -0.036807223f,
+ 0.999377670f, -0.035274239f,
+ 0.999430605f, -0.033741172f,
+ 0.999481187f, -0.032208025f,
+ 0.999529418f, -0.030674803f,
+ 0.999575296f, -0.029141509f,
+ 0.999618822f, -0.027608146f,
+ 0.999659997f, -0.026074718f,
+ 0.999698819f, -0.024541229f,
+ 0.999735288f, -0.023007681f,
+ 0.999769405f, -0.021474080f,
+ 0.999801170f, -0.019940429f,
+ 0.999830582f, -0.018406730f,
+ 0.999857641f, -0.016872988f,
+ 0.999882347f, -0.015339206f,
+ 0.999904701f, -0.013805389f,
+ 0.999924702f, -0.012271538f,
+ 0.999942350f, -0.010737659f,
+ 0.999957645f, -0.009203755f,
+ 0.999970586f, -0.007669829f,
+ 0.999981175f, -0.006135885f,
+ 0.999989411f, -0.004601926f,
+ 0.999995294f, -0.003067957f,
+ 0.999998823f, -0.001533980f
+};
+
+/*
+* @brief Q31 Twiddle factors Table
+*/
+
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 16 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_16_q31[24] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x5A82799A, 0x5A82799A,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x00000000, 0x7FFFFFFF,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xA57D8666, 0x5A82799A,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x80000000, 0x00000000,
+ 0x89BE50C3, 0xCF043AB2,
+ 0xA57D8666, 0xA57D8666,
+ 0xCF043AB2, 0x89BE50C3
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 32 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_32_q31[48] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7D8A5F3F, 0x18F8B83C,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x6A6D98A4, 0x471CECE6,
+ 0x5A82799A, 0x5A82799A,
+ 0x471CECE6, 0x6A6D98A4,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x18F8B83C, 0x7D8A5F3F,
+ 0x00000000, 0x7FFFFFFF,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xA57D8666, 0x5A82799A,
+ 0x9592675B, 0x471CECE6,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x80000000, 0x00000000,
+ 0x8275A0C0, 0xE70747C3,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x9592675B, 0xB8E31319,
+ 0xA57D8666, 0xA57D8666,
+ 0xB8E31319, 0x9592675B,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xE70747C3, 0x8275A0C0
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 64 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_64_q31[96] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7F62368F, 0x0C8BD35E,
+ 0x7D8A5F3F, 0x18F8B83C,
+ 0x7A7D055B, 0x25280C5D,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x70E2CBC6, 0x3C56BA70,
+ 0x6A6D98A4, 0x471CECE6,
+ 0x62F201AC, 0x5133CC94,
+ 0x5A82799A, 0x5A82799A,
+ 0x5133CC94, 0x62F201AC,
+ 0x471CECE6, 0x6A6D98A4,
+ 0x3C56BA70, 0x70E2CBC6,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x25280C5D, 0x7A7D055B,
+ 0x18F8B83C, 0x7D8A5F3F,
+ 0x0C8BD35E, 0x7F62368F,
+ 0x00000000, 0x7FFFFFFF,
+ 0xF3742CA1, 0x7F62368F,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xDAD7F3A2, 0x7A7D055B,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xC3A9458F, 0x70E2CBC6,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xAECC336B, 0x62F201AC,
+ 0xA57D8666, 0x5A82799A,
+ 0x9D0DFE53, 0x5133CC94,
+ 0x9592675B, 0x471CECE6,
+ 0x8F1D343A, 0x3C56BA70,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x8582FAA4, 0x25280C5D,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x809DC970, 0x0C8BD35E,
+ 0x80000000, 0x00000000,
+ 0x809DC970, 0xF3742CA1,
+ 0x8275A0C0, 0xE70747C3,
+ 0x8582FAA4, 0xDAD7F3A2,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x8F1D343A, 0xC3A9458F,
+ 0x9592675B, 0xB8E31319,
+ 0x9D0DFE53, 0xAECC336B,
+ 0xA57D8666, 0xA57D8666,
+ 0xAECC336B, 0x9D0DFE53,
+ 0xB8E31319, 0x9592675B,
+ 0xC3A9458F, 0x8F1D343A,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xDAD7F3A2, 0x8582FAA4,
+ 0xE70747C3, 0x8275A0C0,
+ 0xF3742CA1, 0x809DC970
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 128 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_128_q31[192] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7FD8878D, 0x0647D97C,
+ 0x7F62368F, 0x0C8BD35E,
+ 0x7E9D55FC, 0x12C8106E,
+ 0x7D8A5F3F, 0x18F8B83C,
+ 0x7C29FBEE, 0x1F19F97B,
+ 0x7A7D055B, 0x25280C5D,
+ 0x78848413, 0x2B1F34EB,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x73B5EBD0, 0x36BA2013,
+ 0x70E2CBC6, 0x3C56BA70,
+ 0x6DCA0D14, 0x41CE1E64,
+ 0x6A6D98A4, 0x471CECE6,
+ 0x66CF811F, 0x4C3FDFF3,
+ 0x62F201AC, 0x5133CC94,
+ 0x5ED77C89, 0x55F5A4D2,
+ 0x5A82799A, 0x5A82799A,
+ 0x55F5A4D2, 0x5ED77C89,
+ 0x5133CC94, 0x62F201AC,
+ 0x4C3FDFF3, 0x66CF811F,
+ 0x471CECE6, 0x6A6D98A4,
+ 0x41CE1E64, 0x6DCA0D14,
+ 0x3C56BA70, 0x70E2CBC6,
+ 0x36BA2013, 0x73B5EBD0,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x2B1F34EB, 0x78848413,
+ 0x25280C5D, 0x7A7D055B,
+ 0x1F19F97B, 0x7C29FBEE,
+ 0x18F8B83C, 0x7D8A5F3F,
+ 0x12C8106E, 0x7E9D55FC,
+ 0x0C8BD35E, 0x7F62368F,
+ 0x0647D97C, 0x7FD8878D,
+ 0x00000000, 0x7FFFFFFF,
+ 0xF9B82683, 0x7FD8878D,
+ 0xF3742CA1, 0x7F62368F,
+ 0xED37EF91, 0x7E9D55FC,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xE0E60684, 0x7C29FBEE,
+ 0xDAD7F3A2, 0x7A7D055B,
+ 0xD4E0CB14, 0x78848413,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xC945DFEC, 0x73B5EBD0,
+ 0xC3A9458F, 0x70E2CBC6,
+ 0xBE31E19B, 0x6DCA0D14,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xB3C0200C, 0x66CF811F,
+ 0xAECC336B, 0x62F201AC,
+ 0xAA0A5B2D, 0x5ED77C89,
+ 0xA57D8666, 0x5A82799A,
+ 0xA1288376, 0x55F5A4D2,
+ 0x9D0DFE53, 0x5133CC94,
+ 0x99307EE0, 0x4C3FDFF3,
+ 0x9592675B, 0x471CECE6,
+ 0x9235F2EB, 0x41CE1E64,
+ 0x8F1D343A, 0x3C56BA70,
+ 0x8C4A142F, 0x36BA2013,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x877B7BEC, 0x2B1F34EB,
+ 0x8582FAA4, 0x25280C5D,
+ 0x83D60411, 0x1F19F97B,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x8162AA03, 0x12C8106E,
+ 0x809DC970, 0x0C8BD35E,
+ 0x80277872, 0x0647D97C,
+ 0x80000000, 0x00000000,
+ 0x80277872, 0xF9B82683,
+ 0x809DC970, 0xF3742CA1,
+ 0x8162AA03, 0xED37EF91,
+ 0x8275A0C0, 0xE70747C3,
+ 0x83D60411, 0xE0E60684,
+ 0x8582FAA4, 0xDAD7F3A2,
+ 0x877B7BEC, 0xD4E0CB14,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x8C4A142F, 0xC945DFEC,
+ 0x8F1D343A, 0xC3A9458F,
+ 0x9235F2EB, 0xBE31E19B,
+ 0x9592675B, 0xB8E31319,
+ 0x99307EE0, 0xB3C0200C,
+ 0x9D0DFE53, 0xAECC336B,
+ 0xA1288376, 0xAA0A5B2D,
+ 0xA57D8666, 0xA57D8666,
+ 0xAA0A5B2D, 0xA1288376,
+ 0xAECC336B, 0x9D0DFE53,
+ 0xB3C0200C, 0x99307EE0,
+ 0xB8E31319, 0x9592675B,
+ 0xBE31E19B, 0x9235F2EB,
+ 0xC3A9458F, 0x8F1D343A,
+ 0xC945DFEC, 0x8C4A142F,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xD4E0CB14, 0x877B7BEC,
+ 0xDAD7F3A2, 0x8582FAA4,
+ 0xE0E60684, 0x83D60411,
+ 0xE70747C3, 0x8275A0C0,
+ 0xED37EF91, 0x8162AA03,
+ 0xF3742CA1, 0x809DC970,
+ 0xF9B82683, 0x80277872
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 256 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_256_q31[384] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7FF62182, 0x03242ABF,
+ 0x7FD8878D, 0x0647D97C,
+ 0x7FA736B4, 0x096A9049,
+ 0x7F62368F, 0x0C8BD35E,
+ 0x7F0991C3, 0x0FAB272B,
+ 0x7E9D55FC, 0x12C8106E,
+ 0x7E1D93E9, 0x15E21444,
+ 0x7D8A5F3F, 0x18F8B83C,
+ 0x7CE3CEB1, 0x1C0B826A,
+ 0x7C29FBEE, 0x1F19F97B,
+ 0x7B5D039D, 0x2223A4C5,
+ 0x7A7D055B, 0x25280C5D,
+ 0x798A23B1, 0x2826B928,
+ 0x78848413, 0x2B1F34EB,
+ 0x776C4EDB, 0x2E110A62,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x7504D345, 0x33DEF287,
+ 0x73B5EBD0, 0x36BA2013,
+ 0x72552C84, 0x398CDD32,
+ 0x70E2CBC6, 0x3C56BA70,
+ 0x6F5F02B1, 0x3F1749B7,
+ 0x6DCA0D14, 0x41CE1E64,
+ 0x6C242960, 0x447ACD50,
+ 0x6A6D98A4, 0x471CECE6,
+ 0x68A69E81, 0x49B41533,
+ 0x66CF811F, 0x4C3FDFF3,
+ 0x64E88926, 0x4EBFE8A4,
+ 0x62F201AC, 0x5133CC94,
+ 0x60EC3830, 0x539B2AEF,
+ 0x5ED77C89, 0x55F5A4D2,
+ 0x5CB420DF, 0x5842DD54,
+ 0x5A82799A, 0x5A82799A,
+ 0x5842DD54, 0x5CB420DF,
+ 0x55F5A4D2, 0x5ED77C89,
+ 0x539B2AEF, 0x60EC3830,
+ 0x5133CC94, 0x62F201AC,
+ 0x4EBFE8A4, 0x64E88926,
+ 0x4C3FDFF3, 0x66CF811F,
+ 0x49B41533, 0x68A69E81,
+ 0x471CECE6, 0x6A6D98A4,
+ 0x447ACD50, 0x6C242960,
+ 0x41CE1E64, 0x6DCA0D14,
+ 0x3F1749B7, 0x6F5F02B1,
+ 0x3C56BA70, 0x70E2CBC6,
+ 0x398CDD32, 0x72552C84,
+ 0x36BA2013, 0x73B5EBD0,
+ 0x33DEF287, 0x7504D345,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x2E110A62, 0x776C4EDB,
+ 0x2B1F34EB, 0x78848413,
+ 0x2826B928, 0x798A23B1,
+ 0x25280C5D, 0x7A7D055B,
+ 0x2223A4C5, 0x7B5D039D,
+ 0x1F19F97B, 0x7C29FBEE,
+ 0x1C0B826A, 0x7CE3CEB1,
+ 0x18F8B83C, 0x7D8A5F3F,
+ 0x15E21444, 0x7E1D93E9,
+ 0x12C8106E, 0x7E9D55FC,
+ 0x0FAB272B, 0x7F0991C3,
+ 0x0C8BD35E, 0x7F62368F,
+ 0x096A9049, 0x7FA736B4,
+ 0x0647D97C, 0x7FD8878D,
+ 0x03242ABF, 0x7FF62182,
+ 0x00000000, 0x7FFFFFFF,
+ 0xFCDBD541, 0x7FF62182,
+ 0xF9B82683, 0x7FD8878D,
+ 0xF6956FB6, 0x7FA736B4,
+ 0xF3742CA1, 0x7F62368F,
+ 0xF054D8D4, 0x7F0991C3,
+ 0xED37EF91, 0x7E9D55FC,
+ 0xEA1DEBBB, 0x7E1D93E9,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xE3F47D95, 0x7CE3CEB1,
+ 0xE0E60684, 0x7C29FBEE,
+ 0xDDDC5B3A, 0x7B5D039D,
+ 0xDAD7F3A2, 0x7A7D055B,
+ 0xD7D946D7, 0x798A23B1,
+ 0xD4E0CB14, 0x78848413,
+ 0xD1EEF59E, 0x776C4EDB,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xCC210D78, 0x7504D345,
+ 0xC945DFEC, 0x73B5EBD0,
+ 0xC67322CD, 0x72552C84,
+ 0xC3A9458F, 0x70E2CBC6,
+ 0xC0E8B648, 0x6F5F02B1,
+ 0xBE31E19B, 0x6DCA0D14,
+ 0xBB8532AF, 0x6C242960,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xB64BEACC, 0x68A69E81,
+ 0xB3C0200C, 0x66CF811F,
+ 0xB140175B, 0x64E88926,
+ 0xAECC336B, 0x62F201AC,
+ 0xAC64D510, 0x60EC3830,
+ 0xAA0A5B2D, 0x5ED77C89,
+ 0xA7BD22AB, 0x5CB420DF,
+ 0xA57D8666, 0x5A82799A,
+ 0xA34BDF20, 0x5842DD54,
+ 0xA1288376, 0x55F5A4D2,
+ 0x9F13C7D0, 0x539B2AEF,
+ 0x9D0DFE53, 0x5133CC94,
+ 0x9B1776D9, 0x4EBFE8A4,
+ 0x99307EE0, 0x4C3FDFF3,
+ 0x9759617E, 0x49B41533,
+ 0x9592675B, 0x471CECE6,
+ 0x93DBD69F, 0x447ACD50,
+ 0x9235F2EB, 0x41CE1E64,
+ 0x90A0FD4E, 0x3F1749B7,
+ 0x8F1D343A, 0x3C56BA70,
+ 0x8DAAD37B, 0x398CDD32,
+ 0x8C4A142F, 0x36BA2013,
+ 0x8AFB2CBA, 0x33DEF287,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x8893B124, 0x2E110A62,
+ 0x877B7BEC, 0x2B1F34EB,
+ 0x8675DC4E, 0x2826B928,
+ 0x8582FAA4, 0x25280C5D,
+ 0x84A2FC62, 0x2223A4C5,
+ 0x83D60411, 0x1F19F97B,
+ 0x831C314E, 0x1C0B826A,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x81E26C16, 0x15E21444,
+ 0x8162AA03, 0x12C8106E,
+ 0x80F66E3C, 0x0FAB272B,
+ 0x809DC970, 0x0C8BD35E,
+ 0x8058C94C, 0x096A9049,
+ 0x80277872, 0x0647D97C,
+ 0x8009DE7D, 0x03242ABF,
+ 0x80000000, 0x00000000,
+ 0x8009DE7D, 0xFCDBD541,
+ 0x80277872, 0xF9B82683,
+ 0x8058C94C, 0xF6956FB6,
+ 0x809DC970, 0xF3742CA1,
+ 0x80F66E3C, 0xF054D8D4,
+ 0x8162AA03, 0xED37EF91,
+ 0x81E26C16, 0xEA1DEBBB,
+ 0x8275A0C0, 0xE70747C3,
+ 0x831C314E, 0xE3F47D95,
+ 0x83D60411, 0xE0E60684,
+ 0x84A2FC62, 0xDDDC5B3A,
+ 0x8582FAA4, 0xDAD7F3A2,
+ 0x8675DC4E, 0xD7D946D7,
+ 0x877B7BEC, 0xD4E0CB14,
+ 0x8893B124, 0xD1EEF59E,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x8AFB2CBA, 0xCC210D78,
+ 0x8C4A142F, 0xC945DFEC,
+ 0x8DAAD37B, 0xC67322CD,
+ 0x8F1D343A, 0xC3A9458F,
+ 0x90A0FD4E, 0xC0E8B648,
+ 0x9235F2EB, 0xBE31E19B,
+ 0x93DBD69F, 0xBB8532AF,
+ 0x9592675B, 0xB8E31319,
+ 0x9759617E, 0xB64BEACC,
+ 0x99307EE0, 0xB3C0200C,
+ 0x9B1776D9, 0xB140175B,
+ 0x9D0DFE53, 0xAECC336B,
+ 0x9F13C7D0, 0xAC64D510,
+ 0xA1288376, 0xAA0A5B2D,
+ 0xA34BDF20, 0xA7BD22AB,
+ 0xA57D8666, 0xA57D8666,
+ 0xA7BD22AB, 0xA34BDF20,
+ 0xAA0A5B2D, 0xA1288376,
+ 0xAC64D510, 0x9F13C7D0,
+ 0xAECC336B, 0x9D0DFE53,
+ 0xB140175B, 0x9B1776D9,
+ 0xB3C0200C, 0x99307EE0,
+ 0xB64BEACC, 0x9759617E,
+ 0xB8E31319, 0x9592675B,
+ 0xBB8532AF, 0x93DBD69F,
+ 0xBE31E19B, 0x9235F2EB,
+ 0xC0E8B648, 0x90A0FD4E,
+ 0xC3A9458F, 0x8F1D343A,
+ 0xC67322CD, 0x8DAAD37B,
+ 0xC945DFEC, 0x8C4A142F,
+ 0xCC210D78, 0x8AFB2CBA,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xD1EEF59E, 0x8893B124,
+ 0xD4E0CB14, 0x877B7BEC,
+ 0xD7D946D7, 0x8675DC4E,
+ 0xDAD7F3A2, 0x8582FAA4,
+ 0xDDDC5B3A, 0x84A2FC62,
+ 0xE0E60684, 0x83D60411,
+ 0xE3F47D95, 0x831C314E,
+ 0xE70747C3, 0x8275A0C0,
+ 0xEA1DEBBB, 0x81E26C16,
+ 0xED37EF91, 0x8162AA03,
+ 0xF054D8D4, 0x80F66E3C,
+ 0xF3742CA1, 0x809DC970,
+ 0xF6956FB6, 0x8058C94C,
+ 0xF9B82683, 0x80277872,
+ 0xFCDBD541, 0x8009DE7D
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 512 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_512_q31[768] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7FFD885A, 0x01921D1F,
+ 0x7FF62182, 0x03242ABF,
+ 0x7FE9CBC0, 0x04B6195D,
+ 0x7FD8878D, 0x0647D97C,
+ 0x7FC25596, 0x07D95B9E,
+ 0x7FA736B4, 0x096A9049,
+ 0x7F872BF3, 0x0AFB6805,
+ 0x7F62368F, 0x0C8BD35E,
+ 0x7F3857F5, 0x0E1BC2E3,
+ 0x7F0991C3, 0x0FAB272B,
+ 0x7ED5E5C6, 0x1139F0CE,
+ 0x7E9D55FC, 0x12C8106E,
+ 0x7E5FE493, 0x145576B1,
+ 0x7E1D93E9, 0x15E21444,
+ 0x7DD6668E, 0x176DD9DE,
+ 0x7D8A5F3F, 0x18F8B83C,
+ 0x7D3980EC, 0x1A82A025,
+ 0x7CE3CEB1, 0x1C0B826A,
+ 0x7C894BDD, 0x1D934FE5,
+ 0x7C29FBEE, 0x1F19F97B,
+ 0x7BC5E28F, 0x209F701C,
+ 0x7B5D039D, 0x2223A4C5,
+ 0x7AEF6323, 0x23A6887E,
+ 0x7A7D055B, 0x25280C5D,
+ 0x7A05EEAD, 0x26A82185,
+ 0x798A23B1, 0x2826B928,
+ 0x7909A92C, 0x29A3C484,
+ 0x78848413, 0x2B1F34EB,
+ 0x77FAB988, 0x2C98FBBA,
+ 0x776C4EDB, 0x2E110A62,
+ 0x76D94988, 0x2F875262,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x75A585CF, 0x326E54C7,
+ 0x7504D345, 0x33DEF287,
+ 0x745F9DD1, 0x354D9056,
+ 0x73B5EBD0, 0x36BA2013,
+ 0x7307C3D0, 0x382493B0,
+ 0x72552C84, 0x398CDD32,
+ 0x719E2CD2, 0x3AF2EEB7,
+ 0x70E2CBC6, 0x3C56BA70,
+ 0x70231099, 0x3DB832A5,
+ 0x6F5F02B1, 0x3F1749B7,
+ 0x6E96A99C, 0x4073F21D,
+ 0x6DCA0D14, 0x41CE1E64,
+ 0x6CF934FB, 0x4325C135,
+ 0x6C242960, 0x447ACD50,
+ 0x6B4AF278, 0x45CD358F,
+ 0x6A6D98A4, 0x471CECE6,
+ 0x698C246C, 0x4869E664,
+ 0x68A69E81, 0x49B41533,
+ 0x67BD0FBC, 0x4AFB6C97,
+ 0x66CF811F, 0x4C3FDFF3,
+ 0x65DDFBD3, 0x4D8162C4,
+ 0x64E88926, 0x4EBFE8A4,
+ 0x63EF328F, 0x4FFB654D,
+ 0x62F201AC, 0x5133CC94,
+ 0x61F1003E, 0x5269126E,
+ 0x60EC3830, 0x539B2AEF,
+ 0x5FE3B38D, 0x54CA0A4A,
+ 0x5ED77C89, 0x55F5A4D2,
+ 0x5DC79D7C, 0x571DEEF9,
+ 0x5CB420DF, 0x5842DD54,
+ 0x5B9D1153, 0x59646497,
+ 0x5A82799A, 0x5A82799A,
+ 0x59646497, 0x5B9D1153,
+ 0x5842DD54, 0x5CB420DF,
+ 0x571DEEF9, 0x5DC79D7C,
+ 0x55F5A4D2, 0x5ED77C89,
+ 0x54CA0A4A, 0x5FE3B38D,
+ 0x539B2AEF, 0x60EC3830,
+ 0x5269126E, 0x61F1003E,
+ 0x5133CC94, 0x62F201AC,
+ 0x4FFB654D, 0x63EF328F,
+ 0x4EBFE8A4, 0x64E88926,
+ 0x4D8162C4, 0x65DDFBD3,
+ 0x4C3FDFF3, 0x66CF811F,
+ 0x4AFB6C97, 0x67BD0FBC,
+ 0x49B41533, 0x68A69E81,
+ 0x4869E664, 0x698C246C,
+ 0x471CECE6, 0x6A6D98A4,
+ 0x45CD358F, 0x6B4AF278,
+ 0x447ACD50, 0x6C242960,
+ 0x4325C135, 0x6CF934FB,
+ 0x41CE1E64, 0x6DCA0D14,
+ 0x4073F21D, 0x6E96A99C,
+ 0x3F1749B7, 0x6F5F02B1,
+ 0x3DB832A5, 0x70231099,
+ 0x3C56BA70, 0x70E2CBC6,
+ 0x3AF2EEB7, 0x719E2CD2,
+ 0x398CDD32, 0x72552C84,
+ 0x382493B0, 0x7307C3D0,
+ 0x36BA2013, 0x73B5EBD0,
+ 0x354D9056, 0x745F9DD1,
+ 0x33DEF287, 0x7504D345,
+ 0x326E54C7, 0x75A585CF,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x2F875262, 0x76D94988,
+ 0x2E110A62, 0x776C4EDB,
+ 0x2C98FBBA, 0x77FAB988,
+ 0x2B1F34EB, 0x78848413,
+ 0x29A3C484, 0x7909A92C,
+ 0x2826B928, 0x798A23B1,
+ 0x26A82185, 0x7A05EEAD,
+ 0x25280C5D, 0x7A7D055B,
+ 0x23A6887E, 0x7AEF6323,
+ 0x2223A4C5, 0x7B5D039D,
+ 0x209F701C, 0x7BC5E28F,
+ 0x1F19F97B, 0x7C29FBEE,
+ 0x1D934FE5, 0x7C894BDD,
+ 0x1C0B826A, 0x7CE3CEB1,
+ 0x1A82A025, 0x7D3980EC,
+ 0x18F8B83C, 0x7D8A5F3F,
+ 0x176DD9DE, 0x7DD6668E,
+ 0x15E21444, 0x7E1D93E9,
+ 0x145576B1, 0x7E5FE493,
+ 0x12C8106E, 0x7E9D55FC,
+ 0x1139F0CE, 0x7ED5E5C6,
+ 0x0FAB272B, 0x7F0991C3,
+ 0x0E1BC2E3, 0x7F3857F5,
+ 0x0C8BD35E, 0x7F62368F,
+ 0x0AFB6805, 0x7F872BF3,
+ 0x096A9049, 0x7FA736B4,
+ 0x07D95B9E, 0x7FC25596,
+ 0x0647D97C, 0x7FD8878D,
+ 0x04B6195D, 0x7FE9CBC0,
+ 0x03242ABF, 0x7FF62182,
+ 0x01921D1F, 0x7FFD885A,
+ 0x00000000, 0x7FFFFFFF,
+ 0xFE6DE2E0, 0x7FFD885A,
+ 0xFCDBD541, 0x7FF62182,
+ 0xFB49E6A2, 0x7FE9CBC0,
+ 0xF9B82683, 0x7FD8878D,
+ 0xF826A461, 0x7FC25596,
+ 0xF6956FB6, 0x7FA736B4,
+ 0xF50497FA, 0x7F872BF3,
+ 0xF3742CA1, 0x7F62368F,
+ 0xF1E43D1C, 0x7F3857F5,
+ 0xF054D8D4, 0x7F0991C3,
+ 0xEEC60F31, 0x7ED5E5C6,
+ 0xED37EF91, 0x7E9D55FC,
+ 0xEBAA894E, 0x7E5FE493,
+ 0xEA1DEBBB, 0x7E1D93E9,
+ 0xE8922621, 0x7DD6668E,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xE57D5FDA, 0x7D3980EC,
+ 0xE3F47D95, 0x7CE3CEB1,
+ 0xE26CB01A, 0x7C894BDD,
+ 0xE0E60684, 0x7C29FBEE,
+ 0xDF608FE3, 0x7BC5E28F,
+ 0xDDDC5B3A, 0x7B5D039D,
+ 0xDC597781, 0x7AEF6323,
+ 0xDAD7F3A2, 0x7A7D055B,
+ 0xD957DE7A, 0x7A05EEAD,
+ 0xD7D946D7, 0x798A23B1,
+ 0xD65C3B7B, 0x7909A92C,
+ 0xD4E0CB14, 0x78848413,
+ 0xD3670445, 0x77FAB988,
+ 0xD1EEF59E, 0x776C4EDB,
+ 0xD078AD9D, 0x76D94988,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xCD91AB38, 0x75A585CF,
+ 0xCC210D78, 0x7504D345,
+ 0xCAB26FA9, 0x745F9DD1,
+ 0xC945DFEC, 0x73B5EBD0,
+ 0xC7DB6C50, 0x7307C3D0,
+ 0xC67322CD, 0x72552C84,
+ 0xC50D1148, 0x719E2CD2,
+ 0xC3A9458F, 0x70E2CBC6,
+ 0xC247CD5A, 0x70231099,
+ 0xC0E8B648, 0x6F5F02B1,
+ 0xBF8C0DE2, 0x6E96A99C,
+ 0xBE31E19B, 0x6DCA0D14,
+ 0xBCDA3ECA, 0x6CF934FB,
+ 0xBB8532AF, 0x6C242960,
+ 0xBA32CA70, 0x6B4AF278,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xB796199B, 0x698C246C,
+ 0xB64BEACC, 0x68A69E81,
+ 0xB5049368, 0x67BD0FBC,
+ 0xB3C0200C, 0x66CF811F,
+ 0xB27E9D3B, 0x65DDFBD3,
+ 0xB140175B, 0x64E88926,
+ 0xB0049AB2, 0x63EF328F,
+ 0xAECC336B, 0x62F201AC,
+ 0xAD96ED91, 0x61F1003E,
+ 0xAC64D510, 0x60EC3830,
+ 0xAB35F5B5, 0x5FE3B38D,
+ 0xAA0A5B2D, 0x5ED77C89,
+ 0xA8E21106, 0x5DC79D7C,
+ 0xA7BD22AB, 0x5CB420DF,
+ 0xA69B9B68, 0x5B9D1153,
+ 0xA57D8666, 0x5A82799A,
+ 0xA462EEAC, 0x59646497,
+ 0xA34BDF20, 0x5842DD54,
+ 0xA2386283, 0x571DEEF9,
+ 0xA1288376, 0x55F5A4D2,
+ 0xA01C4C72, 0x54CA0A4A,
+ 0x9F13C7D0, 0x539B2AEF,
+ 0x9E0EFFC1, 0x5269126E,
+ 0x9D0DFE53, 0x5133CC94,
+ 0x9C10CD70, 0x4FFB654D,
+ 0x9B1776D9, 0x4EBFE8A4,
+ 0x9A22042C, 0x4D8162C4,
+ 0x99307EE0, 0x4C3FDFF3,
+ 0x9842F043, 0x4AFB6C97,
+ 0x9759617E, 0x49B41533,
+ 0x9673DB94, 0x4869E664,
+ 0x9592675B, 0x471CECE6,
+ 0x94B50D87, 0x45CD358F,
+ 0x93DBD69F, 0x447ACD50,
+ 0x9306CB04, 0x4325C135,
+ 0x9235F2EB, 0x41CE1E64,
+ 0x91695663, 0x4073F21D,
+ 0x90A0FD4E, 0x3F1749B7,
+ 0x8FDCEF66, 0x3DB832A5,
+ 0x8F1D343A, 0x3C56BA70,
+ 0x8E61D32D, 0x3AF2EEB7,
+ 0x8DAAD37B, 0x398CDD32,
+ 0x8CF83C30, 0x382493B0,
+ 0x8C4A142F, 0x36BA2013,
+ 0x8BA0622F, 0x354D9056,
+ 0x8AFB2CBA, 0x33DEF287,
+ 0x8A5A7A30, 0x326E54C7,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x8926B677, 0x2F875262,
+ 0x8893B124, 0x2E110A62,
+ 0x88054677, 0x2C98FBBA,
+ 0x877B7BEC, 0x2B1F34EB,
+ 0x86F656D3, 0x29A3C484,
+ 0x8675DC4E, 0x2826B928,
+ 0x85FA1152, 0x26A82185,
+ 0x8582FAA4, 0x25280C5D,
+ 0x85109CDC, 0x23A6887E,
+ 0x84A2FC62, 0x2223A4C5,
+ 0x843A1D70, 0x209F701C,
+ 0x83D60411, 0x1F19F97B,
+ 0x8376B422, 0x1D934FE5,
+ 0x831C314E, 0x1C0B826A,
+ 0x82C67F13, 0x1A82A025,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x82299971, 0x176DD9DE,
+ 0x81E26C16, 0x15E21444,
+ 0x81A01B6C, 0x145576B1,
+ 0x8162AA03, 0x12C8106E,
+ 0x812A1A39, 0x1139F0CE,
+ 0x80F66E3C, 0x0FAB272B,
+ 0x80C7A80A, 0x0E1BC2E3,
+ 0x809DC970, 0x0C8BD35E,
+ 0x8078D40D, 0x0AFB6805,
+ 0x8058C94C, 0x096A9049,
+ 0x803DAA69, 0x07D95B9E,
+ 0x80277872, 0x0647D97C,
+ 0x80163440, 0x04B6195D,
+ 0x8009DE7D, 0x03242ABF,
+ 0x800277A5, 0x01921D1F,
+ 0x80000000, 0x00000000,
+ 0x800277A5, 0xFE6DE2E0,
+ 0x8009DE7D, 0xFCDBD541,
+ 0x80163440, 0xFB49E6A2,
+ 0x80277872, 0xF9B82683,
+ 0x803DAA69, 0xF826A461,
+ 0x8058C94C, 0xF6956FB6,
+ 0x8078D40D, 0xF50497FA,
+ 0x809DC970, 0xF3742CA1,
+ 0x80C7A80A, 0xF1E43D1C,
+ 0x80F66E3C, 0xF054D8D4,
+ 0x812A1A39, 0xEEC60F31,
+ 0x8162AA03, 0xED37EF91,
+ 0x81A01B6C, 0xEBAA894E,
+ 0x81E26C16, 0xEA1DEBBB,
+ 0x82299971, 0xE8922621,
+ 0x8275A0C0, 0xE70747C3,
+ 0x82C67F13, 0xE57D5FDA,
+ 0x831C314E, 0xE3F47D95,
+ 0x8376B422, 0xE26CB01A,
+ 0x83D60411, 0xE0E60684,
+ 0x843A1D70, 0xDF608FE3,
+ 0x84A2FC62, 0xDDDC5B3A,
+ 0x85109CDC, 0xDC597781,
+ 0x8582FAA4, 0xDAD7F3A2,
+ 0x85FA1152, 0xD957DE7A,
+ 0x8675DC4E, 0xD7D946D7,
+ 0x86F656D3, 0xD65C3B7B,
+ 0x877B7BEC, 0xD4E0CB14,
+ 0x88054677, 0xD3670445,
+ 0x8893B124, 0xD1EEF59E,
+ 0x8926B677, 0xD078AD9D,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x8A5A7A30, 0xCD91AB38,
+ 0x8AFB2CBA, 0xCC210D78,
+ 0x8BA0622F, 0xCAB26FA9,
+ 0x8C4A142F, 0xC945DFEC,
+ 0x8CF83C30, 0xC7DB6C50,
+ 0x8DAAD37B, 0xC67322CD,
+ 0x8E61D32D, 0xC50D1148,
+ 0x8F1D343A, 0xC3A9458F,
+ 0x8FDCEF66, 0xC247CD5A,
+ 0x90A0FD4E, 0xC0E8B648,
+ 0x91695663, 0xBF8C0DE2,
+ 0x9235F2EB, 0xBE31E19B,
+ 0x9306CB04, 0xBCDA3ECA,
+ 0x93DBD69F, 0xBB8532AF,
+ 0x94B50D87, 0xBA32CA70,
+ 0x9592675B, 0xB8E31319,
+ 0x9673DB94, 0xB796199B,
+ 0x9759617E, 0xB64BEACC,
+ 0x9842F043, 0xB5049368,
+ 0x99307EE0, 0xB3C0200C,
+ 0x9A22042C, 0xB27E9D3B,
+ 0x9B1776D9, 0xB140175B,
+ 0x9C10CD70, 0xB0049AB2,
+ 0x9D0DFE53, 0xAECC336B,
+ 0x9E0EFFC1, 0xAD96ED91,
+ 0x9F13C7D0, 0xAC64D510,
+ 0xA01C4C72, 0xAB35F5B5,
+ 0xA1288376, 0xAA0A5B2D,
+ 0xA2386283, 0xA8E21106,
+ 0xA34BDF20, 0xA7BD22AB,
+ 0xA462EEAC, 0xA69B9B68,
+ 0xA57D8666, 0xA57D8666,
+ 0xA69B9B68, 0xA462EEAC,
+ 0xA7BD22AB, 0xA34BDF20,
+ 0xA8E21106, 0xA2386283,
+ 0xAA0A5B2D, 0xA1288376,
+ 0xAB35F5B5, 0xA01C4C72,
+ 0xAC64D510, 0x9F13C7D0,
+ 0xAD96ED91, 0x9E0EFFC1,
+ 0xAECC336B, 0x9D0DFE53,
+ 0xB0049AB2, 0x9C10CD70,
+ 0xB140175B, 0x9B1776D9,
+ 0xB27E9D3B, 0x9A22042C,
+ 0xB3C0200C, 0x99307EE0,
+ 0xB5049368, 0x9842F043,
+ 0xB64BEACC, 0x9759617E,
+ 0xB796199B, 0x9673DB94,
+ 0xB8E31319, 0x9592675B,
+ 0xBA32CA70, 0x94B50D87,
+ 0xBB8532AF, 0x93DBD69F,
+ 0xBCDA3ECA, 0x9306CB04,
+ 0xBE31E19B, 0x9235F2EB,
+ 0xBF8C0DE2, 0x91695663,
+ 0xC0E8B648, 0x90A0FD4E,
+ 0xC247CD5A, 0x8FDCEF66,
+ 0xC3A9458F, 0x8F1D343A,
+ 0xC50D1148, 0x8E61D32D,
+ 0xC67322CD, 0x8DAAD37B,
+ 0xC7DB6C50, 0x8CF83C30,
+ 0xC945DFEC, 0x8C4A142F,
+ 0xCAB26FA9, 0x8BA0622F,
+ 0xCC210D78, 0x8AFB2CBA,
+ 0xCD91AB38, 0x8A5A7A30,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xD078AD9D, 0x8926B677,
+ 0xD1EEF59E, 0x8893B124,
+ 0xD3670445, 0x88054677,
+ 0xD4E0CB14, 0x877B7BEC,
+ 0xD65C3B7B, 0x86F656D3,
+ 0xD7D946D7, 0x8675DC4E,
+ 0xD957DE7A, 0x85FA1152,
+ 0xDAD7F3A2, 0x8582FAA4,
+ 0xDC597781, 0x85109CDC,
+ 0xDDDC5B3A, 0x84A2FC62,
+ 0xDF608FE3, 0x843A1D70,
+ 0xE0E60684, 0x83D60411,
+ 0xE26CB01A, 0x8376B422,
+ 0xE3F47D95, 0x831C314E,
+ 0xE57D5FDA, 0x82C67F13,
+ 0xE70747C3, 0x8275A0C0,
+ 0xE8922621, 0x82299971,
+ 0xEA1DEBBB, 0x81E26C16,
+ 0xEBAA894E, 0x81A01B6C,
+ 0xED37EF91, 0x8162AA03,
+ 0xEEC60F31, 0x812A1A39,
+ 0xF054D8D4, 0x80F66E3C,
+ 0xF1E43D1C, 0x80C7A80A,
+ 0xF3742CA1, 0x809DC970,
+ 0xF50497FA, 0x8078D40D,
+ 0xF6956FB6, 0x8058C94C,
+ 0xF826A461, 0x803DAA69,
+ 0xF9B82683, 0x80277872,
+ 0xFB49E6A2, 0x80163440,
+ 0xFCDBD541, 0x8009DE7D,
+ 0xFE6DE2E0, 0x800277A5
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 1024 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_1024_q31[1536] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7FFF6216, 0x00C90F88,
+ 0x7FFD885A, 0x01921D1F,
+ 0x7FFA72D1, 0x025B26D7,
+ 0x7FF62182, 0x03242ABF,
+ 0x7FF09477, 0x03ED26E6,
+ 0x7FE9CBC0, 0x04B6195D,
+ 0x7FE1C76B, 0x057F0034,
+ 0x7FD8878D, 0x0647D97C,
+ 0x7FCE0C3E, 0x0710A344,
+ 0x7FC25596, 0x07D95B9E,
+ 0x7FB563B2, 0x08A2009A,
+ 0x7FA736B4, 0x096A9049,
+ 0x7F97CEBC, 0x0A3308BC,
+ 0x7F872BF3, 0x0AFB6805,
+ 0x7F754E7F, 0x0BC3AC35,
+ 0x7F62368F, 0x0C8BD35E,
+ 0x7F4DE450, 0x0D53DB92,
+ 0x7F3857F5, 0x0E1BC2E3,
+ 0x7F2191B4, 0x0EE38765,
+ 0x7F0991C3, 0x0FAB272B,
+ 0x7EF0585F, 0x1072A047,
+ 0x7ED5E5C6, 0x1139F0CE,
+ 0x7EBA3A39, 0x120116D4,
+ 0x7E9D55FC, 0x12C8106E,
+ 0x7E7F3956, 0x138EDBB0,
+ 0x7E5FE493, 0x145576B1,
+ 0x7E3F57FE, 0x151BDF85,
+ 0x7E1D93E9, 0x15E21444,
+ 0x7DFA98A7, 0x16A81305,
+ 0x7DD6668E, 0x176DD9DE,
+ 0x7DB0FDF7, 0x183366E8,
+ 0x7D8A5F3F, 0x18F8B83C,
+ 0x7D628AC5, 0x19BDCBF2,
+ 0x7D3980EC, 0x1A82A025,
+ 0x7D0F4218, 0x1B4732EF,
+ 0x7CE3CEB1, 0x1C0B826A,
+ 0x7CB72724, 0x1CCF8CB3,
+ 0x7C894BDD, 0x1D934FE5,
+ 0x7C5A3D4F, 0x1E56CA1E,
+ 0x7C29FBEE, 0x1F19F97B,
+ 0x7BF88830, 0x1FDCDC1A,
+ 0x7BC5E28F, 0x209F701C,
+ 0x7B920B89, 0x2161B39F,
+ 0x7B5D039D, 0x2223A4C5,
+ 0x7B26CB4F, 0x22E541AE,
+ 0x7AEF6323, 0x23A6887E,
+ 0x7AB6CBA3, 0x24677757,
+ 0x7A7D055B, 0x25280C5D,
+ 0x7A4210D8, 0x25E845B5,
+ 0x7A05EEAD, 0x26A82185,
+ 0x79C89F6D, 0x27679DF4,
+ 0x798A23B1, 0x2826B928,
+ 0x794A7C11, 0x28E5714A,
+ 0x7909A92C, 0x29A3C484,
+ 0x78C7ABA1, 0x2A61B101,
+ 0x78848413, 0x2B1F34EB,
+ 0x78403328, 0x2BDC4E6F,
+ 0x77FAB988, 0x2C98FBBA,
+ 0x77B417DF, 0x2D553AFB,
+ 0x776C4EDB, 0x2E110A62,
+ 0x77235F2D, 0x2ECC681E,
+ 0x76D94988, 0x2F875262,
+ 0x768E0EA5, 0x3041C760,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x75F42C0A, 0x31B54A5D,
+ 0x75A585CF, 0x326E54C7,
+ 0x7555BD4B, 0x3326E2C2,
+ 0x7504D345, 0x33DEF287,
+ 0x74B2C883, 0x3496824F,
+ 0x745F9DD1, 0x354D9056,
+ 0x740B53FA, 0x36041AD9,
+ 0x73B5EBD0, 0x36BA2013,
+ 0x735F6626, 0x376F9E46,
+ 0x7307C3D0, 0x382493B0,
+ 0x72AF05A6, 0x38D8FE93,
+ 0x72552C84, 0x398CDD32,
+ 0x71FA3948, 0x3A402DD1,
+ 0x719E2CD2, 0x3AF2EEB7,
+ 0x71410804, 0x3BA51E29,
+ 0x70E2CBC6, 0x3C56BA70,
+ 0x708378FE, 0x3D07C1D5,
+ 0x70231099, 0x3DB832A5,
+ 0x6FC19385, 0x3E680B2C,
+ 0x6F5F02B1, 0x3F1749B7,
+ 0x6EFB5F12, 0x3FC5EC97,
+ 0x6E96A99C, 0x4073F21D,
+ 0x6E30E349, 0x4121589A,
+ 0x6DCA0D14, 0x41CE1E64,
+ 0x6D6227FA, 0x427A41D0,
+ 0x6CF934FB, 0x4325C135,
+ 0x6C8F351C, 0x43D09AEC,
+ 0x6C242960, 0x447ACD50,
+ 0x6BB812D0, 0x452456BC,
+ 0x6B4AF278, 0x45CD358F,
+ 0x6ADCC964, 0x46756827,
+ 0x6A6D98A4, 0x471CECE6,
+ 0x69FD614A, 0x47C3C22E,
+ 0x698C246C, 0x4869E664,
+ 0x6919E320, 0x490F57EE,
+ 0x68A69E81, 0x49B41533,
+ 0x683257AA, 0x4A581C9D,
+ 0x67BD0FBC, 0x4AFB6C97,
+ 0x6746C7D7, 0x4B9E038F,
+ 0x66CF811F, 0x4C3FDFF3,
+ 0x66573CBB, 0x4CE10034,
+ 0x65DDFBD3, 0x4D8162C4,
+ 0x6563BF92, 0x4E210617,
+ 0x64E88926, 0x4EBFE8A4,
+ 0x646C59BF, 0x4F5E08E3,
+ 0x63EF328F, 0x4FFB654D,
+ 0x637114CC, 0x5097FC5E,
+ 0x62F201AC, 0x5133CC94,
+ 0x6271FA69, 0x51CED46E,
+ 0x61F1003E, 0x5269126E,
+ 0x616F146B, 0x53028517,
+ 0x60EC3830, 0x539B2AEF,
+ 0x60686CCE, 0x5433027D,
+ 0x5FE3B38D, 0x54CA0A4A,
+ 0x5F5E0DB3, 0x556040E2,
+ 0x5ED77C89, 0x55F5A4D2,
+ 0x5E50015D, 0x568A34A9,
+ 0x5DC79D7C, 0x571DEEF9,
+ 0x5D3E5236, 0x57B0D256,
+ 0x5CB420DF, 0x5842DD54,
+ 0x5C290ACC, 0x58D40E8C,
+ 0x5B9D1153, 0x59646497,
+ 0x5B1035CF, 0x59F3DE12,
+ 0x5A82799A, 0x5A82799A,
+ 0x59F3DE12, 0x5B1035CF,
+ 0x59646497, 0x5B9D1153,
+ 0x58D40E8C, 0x5C290ACC,
+ 0x5842DD54, 0x5CB420DF,
+ 0x57B0D256, 0x5D3E5236,
+ 0x571DEEF9, 0x5DC79D7C,
+ 0x568A34A9, 0x5E50015D,
+ 0x55F5A4D2, 0x5ED77C89,
+ 0x556040E2, 0x5F5E0DB3,
+ 0x54CA0A4A, 0x5FE3B38D,
+ 0x5433027D, 0x60686CCE,
+ 0x539B2AEF, 0x60EC3830,
+ 0x53028517, 0x616F146B,
+ 0x5269126E, 0x61F1003E,
+ 0x51CED46E, 0x6271FA69,
+ 0x5133CC94, 0x62F201AC,
+ 0x5097FC5E, 0x637114CC,
+ 0x4FFB654D, 0x63EF328F,
+ 0x4F5E08E3, 0x646C59BF,
+ 0x4EBFE8A4, 0x64E88926,
+ 0x4E210617, 0x6563BF92,
+ 0x4D8162C4, 0x65DDFBD3,
+ 0x4CE10034, 0x66573CBB,
+ 0x4C3FDFF3, 0x66CF811F,
+ 0x4B9E038F, 0x6746C7D7,
+ 0x4AFB6C97, 0x67BD0FBC,
+ 0x4A581C9D, 0x683257AA,
+ 0x49B41533, 0x68A69E81,
+ 0x490F57EE, 0x6919E320,
+ 0x4869E664, 0x698C246C,
+ 0x47C3C22E, 0x69FD614A,
+ 0x471CECE6, 0x6A6D98A4,
+ 0x46756827, 0x6ADCC964,
+ 0x45CD358F, 0x6B4AF278,
+ 0x452456BC, 0x6BB812D0,
+ 0x447ACD50, 0x6C242960,
+ 0x43D09AEC, 0x6C8F351C,
+ 0x4325C135, 0x6CF934FB,
+ 0x427A41D0, 0x6D6227FA,
+ 0x41CE1E64, 0x6DCA0D14,
+ 0x4121589A, 0x6E30E349,
+ 0x4073F21D, 0x6E96A99C,
+ 0x3FC5EC97, 0x6EFB5F12,
+ 0x3F1749B7, 0x6F5F02B1,
+ 0x3E680B2C, 0x6FC19385,
+ 0x3DB832A5, 0x70231099,
+ 0x3D07C1D5, 0x708378FE,
+ 0x3C56BA70, 0x70E2CBC6,
+ 0x3BA51E29, 0x71410804,
+ 0x3AF2EEB7, 0x719E2CD2,
+ 0x3A402DD1, 0x71FA3948,
+ 0x398CDD32, 0x72552C84,
+ 0x38D8FE93, 0x72AF05A6,
+ 0x382493B0, 0x7307C3D0,
+ 0x376F9E46, 0x735F6626,
+ 0x36BA2013, 0x73B5EBD0,
+ 0x36041AD9, 0x740B53FA,
+ 0x354D9056, 0x745F9DD1,
+ 0x3496824F, 0x74B2C883,
+ 0x33DEF287, 0x7504D345,
+ 0x3326E2C2, 0x7555BD4B,
+ 0x326E54C7, 0x75A585CF,
+ 0x31B54A5D, 0x75F42C0A,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x3041C760, 0x768E0EA5,
+ 0x2F875262, 0x76D94988,
+ 0x2ECC681E, 0x77235F2D,
+ 0x2E110A62, 0x776C4EDB,
+ 0x2D553AFB, 0x77B417DF,
+ 0x2C98FBBA, 0x77FAB988,
+ 0x2BDC4E6F, 0x78403328,
+ 0x2B1F34EB, 0x78848413,
+ 0x2A61B101, 0x78C7ABA1,
+ 0x29A3C484, 0x7909A92C,
+ 0x28E5714A, 0x794A7C11,
+ 0x2826B928, 0x798A23B1,
+ 0x27679DF4, 0x79C89F6D,
+ 0x26A82185, 0x7A05EEAD,
+ 0x25E845B5, 0x7A4210D8,
+ 0x25280C5D, 0x7A7D055B,
+ 0x24677757, 0x7AB6CBA3,
+ 0x23A6887E, 0x7AEF6323,
+ 0x22E541AE, 0x7B26CB4F,
+ 0x2223A4C5, 0x7B5D039D,
+ 0x2161B39F, 0x7B920B89,
+ 0x209F701C, 0x7BC5E28F,
+ 0x1FDCDC1A, 0x7BF88830,
+ 0x1F19F97B, 0x7C29FBEE,
+ 0x1E56CA1E, 0x7C5A3D4F,
+ 0x1D934FE5, 0x7C894BDD,
+ 0x1CCF8CB3, 0x7CB72724,
+ 0x1C0B826A, 0x7CE3CEB1,
+ 0x1B4732EF, 0x7D0F4218,
+ 0x1A82A025, 0x7D3980EC,
+ 0x19BDCBF2, 0x7D628AC5,
+ 0x18F8B83C, 0x7D8A5F3F,
+ 0x183366E8, 0x7DB0FDF7,
+ 0x176DD9DE, 0x7DD6668E,
+ 0x16A81305, 0x7DFA98A7,
+ 0x15E21444, 0x7E1D93E9,
+ 0x151BDF85, 0x7E3F57FE,
+ 0x145576B1, 0x7E5FE493,
+ 0x138EDBB0, 0x7E7F3956,
+ 0x12C8106E, 0x7E9D55FC,
+ 0x120116D4, 0x7EBA3A39,
+ 0x1139F0CE, 0x7ED5E5C6,
+ 0x1072A047, 0x7EF0585F,
+ 0x0FAB272B, 0x7F0991C3,
+ 0x0EE38765, 0x7F2191B4,
+ 0x0E1BC2E3, 0x7F3857F5,
+ 0x0D53DB92, 0x7F4DE450,
+ 0x0C8BD35E, 0x7F62368F,
+ 0x0BC3AC35, 0x7F754E7F,
+ 0x0AFB6805, 0x7F872BF3,
+ 0x0A3308BC, 0x7F97CEBC,
+ 0x096A9049, 0x7FA736B4,
+ 0x08A2009A, 0x7FB563B2,
+ 0x07D95B9E, 0x7FC25596,
+ 0x0710A344, 0x7FCE0C3E,
+ 0x0647D97C, 0x7FD8878D,
+ 0x057F0034, 0x7FE1C76B,
+ 0x04B6195D, 0x7FE9CBC0,
+ 0x03ED26E6, 0x7FF09477,
+ 0x03242ABF, 0x7FF62182,
+ 0x025B26D7, 0x7FFA72D1,
+ 0x01921D1F, 0x7FFD885A,
+ 0x00C90F88, 0x7FFF6216,
+ 0x00000000, 0x7FFFFFFF,
+ 0xFF36F078, 0x7FFF6216,
+ 0xFE6DE2E0, 0x7FFD885A,
+ 0xFDA4D928, 0x7FFA72D1,
+ 0xFCDBD541, 0x7FF62182,
+ 0xFC12D919, 0x7FF09477,
+ 0xFB49E6A2, 0x7FE9CBC0,
+ 0xFA80FFCB, 0x7FE1C76B,
+ 0xF9B82683, 0x7FD8878D,
+ 0xF8EF5CBB, 0x7FCE0C3E,
+ 0xF826A461, 0x7FC25596,
+ 0xF75DFF65, 0x7FB563B2,
+ 0xF6956FB6, 0x7FA736B4,
+ 0xF5CCF743, 0x7F97CEBC,
+ 0xF50497FA, 0x7F872BF3,
+ 0xF43C53CA, 0x7F754E7F,
+ 0xF3742CA1, 0x7F62368F,
+ 0xF2AC246D, 0x7F4DE450,
+ 0xF1E43D1C, 0x7F3857F5,
+ 0xF11C789A, 0x7F2191B4,
+ 0xF054D8D4, 0x7F0991C3,
+ 0xEF8D5FB8, 0x7EF0585F,
+ 0xEEC60F31, 0x7ED5E5C6,
+ 0xEDFEE92B, 0x7EBA3A39,
+ 0xED37EF91, 0x7E9D55FC,
+ 0xEC71244F, 0x7E7F3956,
+ 0xEBAA894E, 0x7E5FE493,
+ 0xEAE4207A, 0x7E3F57FE,
+ 0xEA1DEBBB, 0x7E1D93E9,
+ 0xE957ECFB, 0x7DFA98A7,
+ 0xE8922621, 0x7DD6668E,
+ 0xE7CC9917, 0x7DB0FDF7,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xE642340D, 0x7D628AC5,
+ 0xE57D5FDA, 0x7D3980EC,
+ 0xE4B8CD10, 0x7D0F4218,
+ 0xE3F47D95, 0x7CE3CEB1,
+ 0xE330734C, 0x7CB72724,
+ 0xE26CB01A, 0x7C894BDD,
+ 0xE1A935E1, 0x7C5A3D4F,
+ 0xE0E60684, 0x7C29FBEE,
+ 0xE02323E5, 0x7BF88830,
+ 0xDF608FE3, 0x7BC5E28F,
+ 0xDE9E4C60, 0x7B920B89,
+ 0xDDDC5B3A, 0x7B5D039D,
+ 0xDD1ABE51, 0x7B26CB4F,
+ 0xDC597781, 0x7AEF6323,
+ 0xDB9888A8, 0x7AB6CBA3,
+ 0xDAD7F3A2, 0x7A7D055B,
+ 0xDA17BA4A, 0x7A4210D8,
+ 0xD957DE7A, 0x7A05EEAD,
+ 0xD898620C, 0x79C89F6D,
+ 0xD7D946D7, 0x798A23B1,
+ 0xD71A8EB5, 0x794A7C11,
+ 0xD65C3B7B, 0x7909A92C,
+ 0xD59E4EFE, 0x78C7ABA1,
+ 0xD4E0CB14, 0x78848413,
+ 0xD423B190, 0x78403328,
+ 0xD3670445, 0x77FAB988,
+ 0xD2AAC504, 0x77B417DF,
+ 0xD1EEF59E, 0x776C4EDB,
+ 0xD13397E1, 0x77235F2D,
+ 0xD078AD9D, 0x76D94988,
+ 0xCFBE389F, 0x768E0EA5,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xCE4AB5A2, 0x75F42C0A,
+ 0xCD91AB38, 0x75A585CF,
+ 0xCCD91D3D, 0x7555BD4B,
+ 0xCC210D78, 0x7504D345,
+ 0xCB697DB0, 0x74B2C883,
+ 0xCAB26FA9, 0x745F9DD1,
+ 0xC9FBE527, 0x740B53FA,
+ 0xC945DFEC, 0x73B5EBD0,
+ 0xC89061BA, 0x735F6626,
+ 0xC7DB6C50, 0x7307C3D0,
+ 0xC727016C, 0x72AF05A6,
+ 0xC67322CD, 0x72552C84,
+ 0xC5BFD22E, 0x71FA3948,
+ 0xC50D1148, 0x719E2CD2,
+ 0xC45AE1D7, 0x71410804,
+ 0xC3A9458F, 0x70E2CBC6,
+ 0xC2F83E2A, 0x708378FE,
+ 0xC247CD5A, 0x70231099,
+ 0xC197F4D3, 0x6FC19385,
+ 0xC0E8B648, 0x6F5F02B1,
+ 0xC03A1368, 0x6EFB5F12,
+ 0xBF8C0DE2, 0x6E96A99C,
+ 0xBEDEA765, 0x6E30E349,
+ 0xBE31E19B, 0x6DCA0D14,
+ 0xBD85BE2F, 0x6D6227FA,
+ 0xBCDA3ECA, 0x6CF934FB,
+ 0xBC2F6513, 0x6C8F351C,
+ 0xBB8532AF, 0x6C242960,
+ 0xBADBA943, 0x6BB812D0,
+ 0xBA32CA70, 0x6B4AF278,
+ 0xB98A97D8, 0x6ADCC964,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xB83C3DD1, 0x69FD614A,
+ 0xB796199B, 0x698C246C,
+ 0xB6F0A811, 0x6919E320,
+ 0xB64BEACC, 0x68A69E81,
+ 0xB5A7E362, 0x683257AA,
+ 0xB5049368, 0x67BD0FBC,
+ 0xB461FC70, 0x6746C7D7,
+ 0xB3C0200C, 0x66CF811F,
+ 0xB31EFFCB, 0x66573CBB,
+ 0xB27E9D3B, 0x65DDFBD3,
+ 0xB1DEF9E8, 0x6563BF92,
+ 0xB140175B, 0x64E88926,
+ 0xB0A1F71C, 0x646C59BF,
+ 0xB0049AB2, 0x63EF328F,
+ 0xAF6803A1, 0x637114CC,
+ 0xAECC336B, 0x62F201AC,
+ 0xAE312B91, 0x6271FA69,
+ 0xAD96ED91, 0x61F1003E,
+ 0xACFD7AE8, 0x616F146B,
+ 0xAC64D510, 0x60EC3830,
+ 0xABCCFD82, 0x60686CCE,
+ 0xAB35F5B5, 0x5FE3B38D,
+ 0xAA9FBF1D, 0x5F5E0DB3,
+ 0xAA0A5B2D, 0x5ED77C89,
+ 0xA975CB56, 0x5E50015D,
+ 0xA8E21106, 0x5DC79D7C,
+ 0xA84F2DA9, 0x5D3E5236,
+ 0xA7BD22AB, 0x5CB420DF,
+ 0xA72BF173, 0x5C290ACC,
+ 0xA69B9B68, 0x5B9D1153,
+ 0xA60C21ED, 0x5B1035CF,
+ 0xA57D8666, 0x5A82799A,
+ 0xA4EFCA31, 0x59F3DE12,
+ 0xA462EEAC, 0x59646497,
+ 0xA3D6F533, 0x58D40E8C,
+ 0xA34BDF20, 0x5842DD54,
+ 0xA2C1ADC9, 0x57B0D256,
+ 0xA2386283, 0x571DEEF9,
+ 0xA1AFFEA2, 0x568A34A9,
+ 0xA1288376, 0x55F5A4D2,
+ 0xA0A1F24C, 0x556040E2,
+ 0xA01C4C72, 0x54CA0A4A,
+ 0x9F979331, 0x5433027D,
+ 0x9F13C7D0, 0x539B2AEF,
+ 0x9E90EB94, 0x53028517,
+ 0x9E0EFFC1, 0x5269126E,
+ 0x9D8E0596, 0x51CED46E,
+ 0x9D0DFE53, 0x5133CC94,
+ 0x9C8EEB33, 0x5097FC5E,
+ 0x9C10CD70, 0x4FFB654D,
+ 0x9B93A640, 0x4F5E08E3,
+ 0x9B1776D9, 0x4EBFE8A4,
+ 0x9A9C406D, 0x4E210617,
+ 0x9A22042C, 0x4D8162C4,
+ 0x99A8C344, 0x4CE10034,
+ 0x99307EE0, 0x4C3FDFF3,
+ 0x98B93828, 0x4B9E038F,
+ 0x9842F043, 0x4AFB6C97,
+ 0x97CDA855, 0x4A581C9D,
+ 0x9759617E, 0x49B41533,
+ 0x96E61CDF, 0x490F57EE,
+ 0x9673DB94, 0x4869E664,
+ 0x96029EB5, 0x47C3C22E,
+ 0x9592675B, 0x471CECE6,
+ 0x9523369B, 0x46756827,
+ 0x94B50D87, 0x45CD358F,
+ 0x9447ED2F, 0x452456BC,
+ 0x93DBD69F, 0x447ACD50,
+ 0x9370CAE4, 0x43D09AEC,
+ 0x9306CB04, 0x4325C135,
+ 0x929DD805, 0x427A41D0,
+ 0x9235F2EB, 0x41CE1E64,
+ 0x91CF1CB6, 0x4121589A,
+ 0x91695663, 0x4073F21D,
+ 0x9104A0ED, 0x3FC5EC97,
+ 0x90A0FD4E, 0x3F1749B7,
+ 0x903E6C7A, 0x3E680B2C,
+ 0x8FDCEF66, 0x3DB832A5,
+ 0x8F7C8701, 0x3D07C1D5,
+ 0x8F1D343A, 0x3C56BA70,
+ 0x8EBEF7FB, 0x3BA51E29,
+ 0x8E61D32D, 0x3AF2EEB7,
+ 0x8E05C6B7, 0x3A402DD1,
+ 0x8DAAD37B, 0x398CDD32,
+ 0x8D50FA59, 0x38D8FE93,
+ 0x8CF83C30, 0x382493B0,
+ 0x8CA099D9, 0x376F9E46,
+ 0x8C4A142F, 0x36BA2013,
+ 0x8BF4AC05, 0x36041AD9,
+ 0x8BA0622F, 0x354D9056,
+ 0x8B4D377C, 0x3496824F,
+ 0x8AFB2CBA, 0x33DEF287,
+ 0x8AAA42B4, 0x3326E2C2,
+ 0x8A5A7A30, 0x326E54C7,
+ 0x8A0BD3F5, 0x31B54A5D,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x8971F15A, 0x3041C760,
+ 0x8926B677, 0x2F875262,
+ 0x88DCA0D3, 0x2ECC681E,
+ 0x8893B124, 0x2E110A62,
+ 0x884BE820, 0x2D553AFB,
+ 0x88054677, 0x2C98FBBA,
+ 0x87BFCCD7, 0x2BDC4E6F,
+ 0x877B7BEC, 0x2B1F34EB,
+ 0x8738545E, 0x2A61B101,
+ 0x86F656D3, 0x29A3C484,
+ 0x86B583EE, 0x28E5714A,
+ 0x8675DC4E, 0x2826B928,
+ 0x86376092, 0x27679DF4,
+ 0x85FA1152, 0x26A82185,
+ 0x85BDEF27, 0x25E845B5,
+ 0x8582FAA4, 0x25280C5D,
+ 0x8549345C, 0x24677757,
+ 0x85109CDC, 0x23A6887E,
+ 0x84D934B0, 0x22E541AE,
+ 0x84A2FC62, 0x2223A4C5,
+ 0x846DF476, 0x2161B39F,
+ 0x843A1D70, 0x209F701C,
+ 0x840777CF, 0x1FDCDC1A,
+ 0x83D60411, 0x1F19F97B,
+ 0x83A5C2B0, 0x1E56CA1E,
+ 0x8376B422, 0x1D934FE5,
+ 0x8348D8DB, 0x1CCF8CB3,
+ 0x831C314E, 0x1C0B826A,
+ 0x82F0BDE8, 0x1B4732EF,
+ 0x82C67F13, 0x1A82A025,
+ 0x829D753A, 0x19BDCBF2,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x824F0208, 0x183366E8,
+ 0x82299971, 0x176DD9DE,
+ 0x82056758, 0x16A81305,
+ 0x81E26C16, 0x15E21444,
+ 0x81C0A801, 0x151BDF85,
+ 0x81A01B6C, 0x145576B1,
+ 0x8180C6A9, 0x138EDBB0,
+ 0x8162AA03, 0x12C8106E,
+ 0x8145C5C6, 0x120116D4,
+ 0x812A1A39, 0x1139F0CE,
+ 0x810FA7A0, 0x1072A047,
+ 0x80F66E3C, 0x0FAB272B,
+ 0x80DE6E4C, 0x0EE38765,
+ 0x80C7A80A, 0x0E1BC2E3,
+ 0x80B21BAF, 0x0D53DB92,
+ 0x809DC970, 0x0C8BD35E,
+ 0x808AB180, 0x0BC3AC35,
+ 0x8078D40D, 0x0AFB6805,
+ 0x80683143, 0x0A3308BC,
+ 0x8058C94C, 0x096A9049,
+ 0x804A9C4D, 0x08A2009A,
+ 0x803DAA69, 0x07D95B9E,
+ 0x8031F3C1, 0x0710A344,
+ 0x80277872, 0x0647D97C,
+ 0x801E3894, 0x057F0034,
+ 0x80163440, 0x04B6195D,
+ 0x800F6B88, 0x03ED26E6,
+ 0x8009DE7D, 0x03242ABF,
+ 0x80058D2E, 0x025B26D7,
+ 0x800277A5, 0x01921D1F,
+ 0x80009DE9, 0x00C90F88,
+ 0x80000000, 0x00000000,
+ 0x80009DE9, 0xFF36F078,
+ 0x800277A5, 0xFE6DE2E0,
+ 0x80058D2E, 0xFDA4D928,
+ 0x8009DE7D, 0xFCDBD541,
+ 0x800F6B88, 0xFC12D919,
+ 0x80163440, 0xFB49E6A2,
+ 0x801E3894, 0xFA80FFCB,
+ 0x80277872, 0xF9B82683,
+ 0x8031F3C1, 0xF8EF5CBB,
+ 0x803DAA69, 0xF826A461,
+ 0x804A9C4D, 0xF75DFF65,
+ 0x8058C94C, 0xF6956FB6,
+ 0x80683143, 0xF5CCF743,
+ 0x8078D40D, 0xF50497FA,
+ 0x808AB180, 0xF43C53CA,
+ 0x809DC970, 0xF3742CA1,
+ 0x80B21BAF, 0xF2AC246D,
+ 0x80C7A80A, 0xF1E43D1C,
+ 0x80DE6E4C, 0xF11C789A,
+ 0x80F66E3C, 0xF054D8D4,
+ 0x810FA7A0, 0xEF8D5FB8,
+ 0x812A1A39, 0xEEC60F31,
+ 0x8145C5C6, 0xEDFEE92B,
+ 0x8162AA03, 0xED37EF91,
+ 0x8180C6A9, 0xEC71244F,
+ 0x81A01B6C, 0xEBAA894E,
+ 0x81C0A801, 0xEAE4207A,
+ 0x81E26C16, 0xEA1DEBBB,
+ 0x82056758, 0xE957ECFB,
+ 0x82299971, 0xE8922621,
+ 0x824F0208, 0xE7CC9917,
+ 0x8275A0C0, 0xE70747C3,
+ 0x829D753A, 0xE642340D,
+ 0x82C67F13, 0xE57D5FDA,
+ 0x82F0BDE8, 0xE4B8CD10,
+ 0x831C314E, 0xE3F47D95,
+ 0x8348D8DB, 0xE330734C,
+ 0x8376B422, 0xE26CB01A,
+ 0x83A5C2B0, 0xE1A935E1,
+ 0x83D60411, 0xE0E60684,
+ 0x840777CF, 0xE02323E5,
+ 0x843A1D70, 0xDF608FE3,
+ 0x846DF476, 0xDE9E4C60,
+ 0x84A2FC62, 0xDDDC5B3A,
+ 0x84D934B0, 0xDD1ABE51,
+ 0x85109CDC, 0xDC597781,
+ 0x8549345C, 0xDB9888A8,
+ 0x8582FAA4, 0xDAD7F3A2,
+ 0x85BDEF27, 0xDA17BA4A,
+ 0x85FA1152, 0xD957DE7A,
+ 0x86376092, 0xD898620C,
+ 0x8675DC4E, 0xD7D946D7,
+ 0x86B583EE, 0xD71A8EB5,
+ 0x86F656D3, 0xD65C3B7B,
+ 0x8738545E, 0xD59E4EFE,
+ 0x877B7BEC, 0xD4E0CB14,
+ 0x87BFCCD7, 0xD423B190,
+ 0x88054677, 0xD3670445,
+ 0x884BE820, 0xD2AAC504,
+ 0x8893B124, 0xD1EEF59E,
+ 0x88DCA0D3, 0xD13397E1,
+ 0x8926B677, 0xD078AD9D,
+ 0x8971F15A, 0xCFBE389F,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x8A0BD3F5, 0xCE4AB5A2,
+ 0x8A5A7A30, 0xCD91AB38,
+ 0x8AAA42B4, 0xCCD91D3D,
+ 0x8AFB2CBA, 0xCC210D78,
+ 0x8B4D377C, 0xCB697DB0,
+ 0x8BA0622F, 0xCAB26FA9,
+ 0x8BF4AC05, 0xC9FBE527,
+ 0x8C4A142F, 0xC945DFEC,
+ 0x8CA099D9, 0xC89061BA,
+ 0x8CF83C30, 0xC7DB6C50,
+ 0x8D50FA59, 0xC727016C,
+ 0x8DAAD37B, 0xC67322CD,
+ 0x8E05C6B7, 0xC5BFD22E,
+ 0x8E61D32D, 0xC50D1148,
+ 0x8EBEF7FB, 0xC45AE1D7,
+ 0x8F1D343A, 0xC3A9458F,
+ 0x8F7C8701, 0xC2F83E2A,
+ 0x8FDCEF66, 0xC247CD5A,
+ 0x903E6C7A, 0xC197F4D3,
+ 0x90A0FD4E, 0xC0E8B648,
+ 0x9104A0ED, 0xC03A1368,
+ 0x91695663, 0xBF8C0DE2,
+ 0x91CF1CB6, 0xBEDEA765,
+ 0x9235F2EB, 0xBE31E19B,
+ 0x929DD805, 0xBD85BE2F,
+ 0x9306CB04, 0xBCDA3ECA,
+ 0x9370CAE4, 0xBC2F6513,
+ 0x93DBD69F, 0xBB8532AF,
+ 0x9447ED2F, 0xBADBA943,
+ 0x94B50D87, 0xBA32CA70,
+ 0x9523369B, 0xB98A97D8,
+ 0x9592675B, 0xB8E31319,
+ 0x96029EB5, 0xB83C3DD1,
+ 0x9673DB94, 0xB796199B,
+ 0x96E61CDF, 0xB6F0A811,
+ 0x9759617E, 0xB64BEACC,
+ 0x97CDA855, 0xB5A7E362,
+ 0x9842F043, 0xB5049368,
+ 0x98B93828, 0xB461FC70,
+ 0x99307EE0, 0xB3C0200C,
+ 0x99A8C344, 0xB31EFFCB,
+ 0x9A22042C, 0xB27E9D3B,
+ 0x9A9C406D, 0xB1DEF9E8,
+ 0x9B1776D9, 0xB140175B,
+ 0x9B93A640, 0xB0A1F71C,
+ 0x9C10CD70, 0xB0049AB2,
+ 0x9C8EEB33, 0xAF6803A1,
+ 0x9D0DFE53, 0xAECC336B,
+ 0x9D8E0596, 0xAE312B91,
+ 0x9E0EFFC1, 0xAD96ED91,
+ 0x9E90EB94, 0xACFD7AE8,
+ 0x9F13C7D0, 0xAC64D510,
+ 0x9F979331, 0xABCCFD82,
+ 0xA01C4C72, 0xAB35F5B5,
+ 0xA0A1F24C, 0xAA9FBF1D,
+ 0xA1288376, 0xAA0A5B2D,
+ 0xA1AFFEA2, 0xA975CB56,
+ 0xA2386283, 0xA8E21106,
+ 0xA2C1ADC9, 0xA84F2DA9,
+ 0xA34BDF20, 0xA7BD22AB,
+ 0xA3D6F533, 0xA72BF173,
+ 0xA462EEAC, 0xA69B9B68,
+ 0xA4EFCA31, 0xA60C21ED,
+ 0xA57D8666, 0xA57D8666,
+ 0xA60C21ED, 0xA4EFCA31,
+ 0xA69B9B68, 0xA462EEAC,
+ 0xA72BF173, 0xA3D6F533,
+ 0xA7BD22AB, 0xA34BDF20,
+ 0xA84F2DA9, 0xA2C1ADC9,
+ 0xA8E21106, 0xA2386283,
+ 0xA975CB56, 0xA1AFFEA2,
+ 0xAA0A5B2D, 0xA1288376,
+ 0xAA9FBF1D, 0xA0A1F24C,
+ 0xAB35F5B5, 0xA01C4C72,
+ 0xABCCFD82, 0x9F979331,
+ 0xAC64D510, 0x9F13C7D0,
+ 0xACFD7AE8, 0x9E90EB94,
+ 0xAD96ED91, 0x9E0EFFC1,
+ 0xAE312B91, 0x9D8E0596,
+ 0xAECC336B, 0x9D0DFE53,
+ 0xAF6803A1, 0x9C8EEB33,
+ 0xB0049AB2, 0x9C10CD70,
+ 0xB0A1F71C, 0x9B93A640,
+ 0xB140175B, 0x9B1776D9,
+ 0xB1DEF9E8, 0x9A9C406D,
+ 0xB27E9D3B, 0x9A22042C,
+ 0xB31EFFCB, 0x99A8C344,
+ 0xB3C0200C, 0x99307EE0,
+ 0xB461FC70, 0x98B93828,
+ 0xB5049368, 0x9842F043,
+ 0xB5A7E362, 0x97CDA855,
+ 0xB64BEACC, 0x9759617E,
+ 0xB6F0A811, 0x96E61CDF,
+ 0xB796199B, 0x9673DB94,
+ 0xB83C3DD1, 0x96029EB5,
+ 0xB8E31319, 0x9592675B,
+ 0xB98A97D8, 0x9523369B,
+ 0xBA32CA70, 0x94B50D87,
+ 0xBADBA943, 0x9447ED2F,
+ 0xBB8532AF, 0x93DBD69F,
+ 0xBC2F6513, 0x9370CAE4,
+ 0xBCDA3ECA, 0x9306CB04,
+ 0xBD85BE2F, 0x929DD805,
+ 0xBE31E19B, 0x9235F2EB,
+ 0xBEDEA765, 0x91CF1CB6,
+ 0xBF8C0DE2, 0x91695663,
+ 0xC03A1368, 0x9104A0ED,
+ 0xC0E8B648, 0x90A0FD4E,
+ 0xC197F4D3, 0x903E6C7A,
+ 0xC247CD5A, 0x8FDCEF66,
+ 0xC2F83E2A, 0x8F7C8701,
+ 0xC3A9458F, 0x8F1D343A,
+ 0xC45AE1D7, 0x8EBEF7FB,
+ 0xC50D1148, 0x8E61D32D,
+ 0xC5BFD22E, 0x8E05C6B7,
+ 0xC67322CD, 0x8DAAD37B,
+ 0xC727016C, 0x8D50FA59,
+ 0xC7DB6C50, 0x8CF83C30,
+ 0xC89061BA, 0x8CA099D9,
+ 0xC945DFEC, 0x8C4A142F,
+ 0xC9FBE527, 0x8BF4AC05,
+ 0xCAB26FA9, 0x8BA0622F,
+ 0xCB697DB0, 0x8B4D377C,
+ 0xCC210D78, 0x8AFB2CBA,
+ 0xCCD91D3D, 0x8AAA42B4,
+ 0xCD91AB38, 0x8A5A7A30,
+ 0xCE4AB5A2, 0x8A0BD3F5,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xCFBE389F, 0x8971F15A,
+ 0xD078AD9D, 0x8926B677,
+ 0xD13397E1, 0x88DCA0D3,
+ 0xD1EEF59E, 0x8893B124,
+ 0xD2AAC504, 0x884BE820,
+ 0xD3670445, 0x88054677,
+ 0xD423B190, 0x87BFCCD7,
+ 0xD4E0CB14, 0x877B7BEC,
+ 0xD59E4EFE, 0x8738545E,
+ 0xD65C3B7B, 0x86F656D3,
+ 0xD71A8EB5, 0x86B583EE,
+ 0xD7D946D7, 0x8675DC4E,
+ 0xD898620C, 0x86376092,
+ 0xD957DE7A, 0x85FA1152,
+ 0xDA17BA4A, 0x85BDEF27,
+ 0xDAD7F3A2, 0x8582FAA4,
+ 0xDB9888A8, 0x8549345C,
+ 0xDC597781, 0x85109CDC,
+ 0xDD1ABE51, 0x84D934B0,
+ 0xDDDC5B3A, 0x84A2FC62,
+ 0xDE9E4C60, 0x846DF476,
+ 0xDF608FE3, 0x843A1D70,
+ 0xE02323E5, 0x840777CF,
+ 0xE0E60684, 0x83D60411,
+ 0xE1A935E1, 0x83A5C2B0,
+ 0xE26CB01A, 0x8376B422,
+ 0xE330734C, 0x8348D8DB,
+ 0xE3F47D95, 0x831C314E,
+ 0xE4B8CD10, 0x82F0BDE8,
+ 0xE57D5FDA, 0x82C67F13,
+ 0xE642340D, 0x829D753A,
+ 0xE70747C3, 0x8275A0C0,
+ 0xE7CC9917, 0x824F0208,
+ 0xE8922621, 0x82299971,
+ 0xE957ECFB, 0x82056758,
+ 0xEA1DEBBB, 0x81E26C16,
+ 0xEAE4207A, 0x81C0A801,
+ 0xEBAA894E, 0x81A01B6C,
+ 0xEC71244F, 0x8180C6A9,
+ 0xED37EF91, 0x8162AA03,
+ 0xEDFEE92B, 0x8145C5C6,
+ 0xEEC60F31, 0x812A1A39,
+ 0xEF8D5FB8, 0x810FA7A0,
+ 0xF054D8D4, 0x80F66E3C,
+ 0xF11C789A, 0x80DE6E4C,
+ 0xF1E43D1C, 0x80C7A80A,
+ 0xF2AC246D, 0x80B21BAF,
+ 0xF3742CA1, 0x809DC970,
+ 0xF43C53CA, 0x808AB180,
+ 0xF50497FA, 0x8078D40D,
+ 0xF5CCF743, 0x80683143,
+ 0xF6956FB6, 0x8058C94C,
+ 0xF75DFF65, 0x804A9C4D,
+ 0xF826A461, 0x803DAA69,
+ 0xF8EF5CBB, 0x8031F3C1,
+ 0xF9B82683, 0x80277872,
+ 0xFA80FFCB, 0x801E3894,
+ 0xFB49E6A2, 0x80163440,
+ 0xFC12D919, 0x800F6B88,
+ 0xFCDBD541, 0x8009DE7D,
+ 0xFDA4D928, 0x80058D2E,
+ 0xFE6DE2E0, 0x800277A5,
+ 0xFF36F078, 0x80009DE9
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 2048 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_2048_q31[3072] = {
+ 0x7FFFFFFF, 0x00000000,
+ 0x7FFFD885, 0x006487E3,
+ 0x7FFF6216, 0x00C90F88,
+ 0x7FFE9CB2, 0x012D96B0,
+ 0x7FFD885A, 0x01921D1F,
+ 0x7FFC250F, 0x01F6A296,
+ 0x7FFA72D1, 0x025B26D7,
+ 0x7FF871A1, 0x02BFA9A4,
+ 0x7FF62182, 0x03242ABF,
+ 0x7FF38273, 0x0388A9E9,
+ 0x7FF09477, 0x03ED26E6,
+ 0x7FED5790, 0x0451A176,
+ 0x7FE9CBC0, 0x04B6195D,
+ 0x7FE5F108, 0x051A8E5C,
+ 0x7FE1C76B, 0x057F0034,
+ 0x7FDD4EEC, 0x05E36EA9,
+ 0x7FD8878D, 0x0647D97C,
+ 0x7FD37152, 0x06AC406F,
+ 0x7FCE0C3E, 0x0710A344,
+ 0x7FC85853, 0x077501BE,
+ 0x7FC25596, 0x07D95B9E,
+ 0x7FBC040A, 0x083DB0A7,
+ 0x7FB563B2, 0x08A2009A,
+ 0x7FAE7494, 0x09064B3A,
+ 0x7FA736B4, 0x096A9049,
+ 0x7F9FAA15, 0x09CECF89,
+ 0x7F97CEBC, 0x0A3308BC,
+ 0x7F8FA4AF, 0x0A973BA5,
+ 0x7F872BF3, 0x0AFB6805,
+ 0x7F7E648B, 0x0B5F8D9F,
+ 0x7F754E7F, 0x0BC3AC35,
+ 0x7F6BE9D4, 0x0C27C389,
+ 0x7F62368F, 0x0C8BD35E,
+ 0x7F5834B6, 0x0CEFDB75,
+ 0x7F4DE450, 0x0D53DB92,
+ 0x7F434563, 0x0DB7D376,
+ 0x7F3857F5, 0x0E1BC2E3,
+ 0x7F2D1C0E, 0x0E7FA99D,
+ 0x7F2191B4, 0x0EE38765,
+ 0x7F15B8EE, 0x0F475BFE,
+ 0x7F0991C3, 0x0FAB272B,
+ 0x7EFD1C3C, 0x100EE8AD,
+ 0x7EF0585F, 0x1072A047,
+ 0x7EE34635, 0x10D64DBC,
+ 0x7ED5E5C6, 0x1139F0CE,
+ 0x7EC8371A, 0x119D8940,
+ 0x7EBA3A39, 0x120116D4,
+ 0x7EABEF2C, 0x1264994E,
+ 0x7E9D55FC, 0x12C8106E,
+ 0x7E8E6EB1, 0x132B7BF9,
+ 0x7E7F3956, 0x138EDBB0,
+ 0x7E6FB5F3, 0x13F22F57,
+ 0x7E5FE493, 0x145576B1,
+ 0x7E4FC53E, 0x14B8B17F,
+ 0x7E3F57FE, 0x151BDF85,
+ 0x7E2E9CDF, 0x157F0086,
+ 0x7E1D93E9, 0x15E21444,
+ 0x7E0C3D29, 0x16451A83,
+ 0x7DFA98A7, 0x16A81305,
+ 0x7DE8A670, 0x170AFD8D,
+ 0x7DD6668E, 0x176DD9DE,
+ 0x7DC3D90D, 0x17D0A7BB,
+ 0x7DB0FDF7, 0x183366E8,
+ 0x7D9DD55A, 0x18961727,
+ 0x7D8A5F3F, 0x18F8B83C,
+ 0x7D769BB5, 0x195B49E9,
+ 0x7D628AC5, 0x19BDCBF2,
+ 0x7D4E2C7E, 0x1A203E1B,
+ 0x7D3980EC, 0x1A82A025,
+ 0x7D24881A, 0x1AE4F1D6,
+ 0x7D0F4218, 0x1B4732EF,
+ 0x7CF9AEF0, 0x1BA96334,
+ 0x7CE3CEB1, 0x1C0B826A,
+ 0x7CCDA168, 0x1C6D9053,
+ 0x7CB72724, 0x1CCF8CB3,
+ 0x7CA05FF1, 0x1D31774D,
+ 0x7C894BDD, 0x1D934FE5,
+ 0x7C71EAF8, 0x1DF5163F,
+ 0x7C5A3D4F, 0x1E56CA1E,
+ 0x7C4242F2, 0x1EB86B46,
+ 0x7C29FBEE, 0x1F19F97B,
+ 0x7C116853, 0x1F7B7480,
+ 0x7BF88830, 0x1FDCDC1A,
+ 0x7BDF5B94, 0x203E300D,
+ 0x7BC5E28F, 0x209F701C,
+ 0x7BAC1D31, 0x21009C0B,
+ 0x7B920B89, 0x2161B39F,
+ 0x7B77ADA8, 0x21C2B69C,
+ 0x7B5D039D, 0x2223A4C5,
+ 0x7B420D7A, 0x22847DDF,
+ 0x7B26CB4F, 0x22E541AE,
+ 0x7B0B3D2C, 0x2345EFF7,
+ 0x7AEF6323, 0x23A6887E,
+ 0x7AD33D45, 0x24070B07,
+ 0x7AB6CBA3, 0x24677757,
+ 0x7A9A0E4F, 0x24C7CD32,
+ 0x7A7D055B, 0x25280C5D,
+ 0x7A5FB0D8, 0x2588349D,
+ 0x7A4210D8, 0x25E845B5,
+ 0x7A24256E, 0x26483F6C,
+ 0x7A05EEAD, 0x26A82185,
+ 0x79E76CA6, 0x2707EBC6,
+ 0x79C89F6D, 0x27679DF4,
+ 0x79A98715, 0x27C737D2,
+ 0x798A23B1, 0x2826B928,
+ 0x796A7554, 0x288621B9,
+ 0x794A7C11, 0x28E5714A,
+ 0x792A37FE, 0x2944A7A2,
+ 0x7909A92C, 0x29A3C484,
+ 0x78E8CFB1, 0x2A02C7B8,
+ 0x78C7ABA1, 0x2A61B101,
+ 0x78A63D10, 0x2AC08025,
+ 0x78848413, 0x2B1F34EB,
+ 0x786280BF, 0x2B7DCF17,
+ 0x78403328, 0x2BDC4E6F,
+ 0x781D9B64, 0x2C3AB2B9,
+ 0x77FAB988, 0x2C98FBBA,
+ 0x77D78DAA, 0x2CF72939,
+ 0x77B417DF, 0x2D553AFB,
+ 0x7790583D, 0x2DB330C7,
+ 0x776C4EDB, 0x2E110A62,
+ 0x7747FBCE, 0x2E6EC792,
+ 0x77235F2D, 0x2ECC681E,
+ 0x76FE790E, 0x2F29EBCC,
+ 0x76D94988, 0x2F875262,
+ 0x76B3D0B3, 0x2FE49BA6,
+ 0x768E0EA5, 0x3041C760,
+ 0x76680376, 0x309ED555,
+ 0x7641AF3C, 0x30FBC54D,
+ 0x761B1211, 0x3158970D,
+ 0x75F42C0A, 0x31B54A5D,
+ 0x75CCFD42, 0x3211DF03,
+ 0x75A585CF, 0x326E54C7,
+ 0x757DC5CA, 0x32CAAB6F,
+ 0x7555BD4B, 0x3326E2C2,
+ 0x752D6C6C, 0x3382FA88,
+ 0x7504D345, 0x33DEF287,
+ 0x74DBF1EF, 0x343ACA87,
+ 0x74B2C883, 0x3496824F,
+ 0x7489571B, 0x34F219A7,
+ 0x745F9DD1, 0x354D9056,
+ 0x74359CBD, 0x35A8E624,
+ 0x740B53FA, 0x36041AD9,
+ 0x73E0C3A3, 0x365F2E3B,
+ 0x73B5EBD0, 0x36BA2013,
+ 0x738ACC9E, 0x3714F02A,
+ 0x735F6626, 0x376F9E46,
+ 0x7333B883, 0x37CA2A30,
+ 0x7307C3D0, 0x382493B0,
+ 0x72DB8828, 0x387EDA8E,
+ 0x72AF05A6, 0x38D8FE93,
+ 0x72823C66, 0x3932FF87,
+ 0x72552C84, 0x398CDD32,
+ 0x7227D61C, 0x39E6975D,
+ 0x71FA3948, 0x3A402DD1,
+ 0x71CC5626, 0x3A99A057,
+ 0x719E2CD2, 0x3AF2EEB7,
+ 0x716FBD68, 0x3B4C18BA,
+ 0x71410804, 0x3BA51E29,
+ 0x71120CC5, 0x3BFDFECD,
+ 0x70E2CBC6, 0x3C56BA70,
+ 0x70B34524, 0x3CAF50DA,
+ 0x708378FE, 0x3D07C1D5,
+ 0x70536771, 0x3D600D2B,
+ 0x70231099, 0x3DB832A5,
+ 0x6FF27496, 0x3E10320D,
+ 0x6FC19385, 0x3E680B2C,
+ 0x6F906D84, 0x3EBFBDCC,
+ 0x6F5F02B1, 0x3F1749B7,
+ 0x6F2D532C, 0x3F6EAEB8,
+ 0x6EFB5F12, 0x3FC5EC97,
+ 0x6EC92682, 0x401D0320,
+ 0x6E96A99C, 0x4073F21D,
+ 0x6E63E87F, 0x40CAB957,
+ 0x6E30E349, 0x4121589A,
+ 0x6DFD9A1B, 0x4177CFB0,
+ 0x6DCA0D14, 0x41CE1E64,
+ 0x6D963C54, 0x42244480,
+ 0x6D6227FA, 0x427A41D0,
+ 0x6D2DD027, 0x42D0161E,
+ 0x6CF934FB, 0x4325C135,
+ 0x6CC45697, 0x437B42E1,
+ 0x6C8F351C, 0x43D09AEC,
+ 0x6C59D0A9, 0x4425C923,
+ 0x6C242960, 0x447ACD50,
+ 0x6BEE3F62, 0x44CFA73F,
+ 0x6BB812D0, 0x452456BC,
+ 0x6B81A3CD, 0x4578DB93,
+ 0x6B4AF278, 0x45CD358F,
+ 0x6B13FEF5, 0x4621647C,
+ 0x6ADCC964, 0x46756827,
+ 0x6AA551E8, 0x46C9405C,
+ 0x6A6D98A4, 0x471CECE6,
+ 0x6A359DB9, 0x47706D93,
+ 0x69FD614A, 0x47C3C22E,
+ 0x69C4E37A, 0x4816EA85,
+ 0x698C246C, 0x4869E664,
+ 0x69532442, 0x48BCB598,
+ 0x6919E320, 0x490F57EE,
+ 0x68E06129, 0x4961CD32,
+ 0x68A69E81, 0x49B41533,
+ 0x686C9B4B, 0x4A062FBD,
+ 0x683257AA, 0x4A581C9D,
+ 0x67F7D3C4, 0x4AA9DBA1,
+ 0x67BD0FBC, 0x4AFB6C97,
+ 0x67820BB6, 0x4B4CCF4D,
+ 0x6746C7D7, 0x4B9E038F,
+ 0x670B4443, 0x4BEF092D,
+ 0x66CF811F, 0x4C3FDFF3,
+ 0x66937E90, 0x4C9087B1,
+ 0x66573CBB, 0x4CE10034,
+ 0x661ABBC5, 0x4D31494B,
+ 0x65DDFBD3, 0x4D8162C4,
+ 0x65A0FD0B, 0x4DD14C6E,
+ 0x6563BF92, 0x4E210617,
+ 0x6526438E, 0x4E708F8F,
+ 0x64E88926, 0x4EBFE8A4,
+ 0x64AA907F, 0x4F0F1126,
+ 0x646C59BF, 0x4F5E08E3,
+ 0x642DE50D, 0x4FACCFAB,
+ 0x63EF328F, 0x4FFB654D,
+ 0x63B0426D, 0x5049C999,
+ 0x637114CC, 0x5097FC5E,
+ 0x6331A9D4, 0x50E5FD6C,
+ 0x62F201AC, 0x5133CC94,
+ 0x62B21C7B, 0x518169A4,
+ 0x6271FA69, 0x51CED46E,
+ 0x62319B9D, 0x521C0CC1,
+ 0x61F1003E, 0x5269126E,
+ 0x61B02876, 0x52B5E545,
+ 0x616F146B, 0x53028517,
+ 0x612DC446, 0x534EF1B5,
+ 0x60EC3830, 0x539B2AEF,
+ 0x60AA704F, 0x53E73097,
+ 0x60686CCE, 0x5433027D,
+ 0x60262DD5, 0x547EA073,
+ 0x5FE3B38D, 0x54CA0A4A,
+ 0x5FA0FE1E, 0x55153FD4,
+ 0x5F5E0DB3, 0x556040E2,
+ 0x5F1AE273, 0x55AB0D46,
+ 0x5ED77C89, 0x55F5A4D2,
+ 0x5E93DC1F, 0x56400757,
+ 0x5E50015D, 0x568A34A9,
+ 0x5E0BEC6E, 0x56D42C99,
+ 0x5DC79D7C, 0x571DEEF9,
+ 0x5D8314B0, 0x57677B9D,
+ 0x5D3E5236, 0x57B0D256,
+ 0x5CF95638, 0x57F9F2F7,
+ 0x5CB420DF, 0x5842DD54,
+ 0x5C6EB258, 0x588B913F,
+ 0x5C290ACC, 0x58D40E8C,
+ 0x5BE32A67, 0x591C550E,
+ 0x5B9D1153, 0x59646497,
+ 0x5B56BFBD, 0x59AC3CFD,
+ 0x5B1035CF, 0x59F3DE12,
+ 0x5AC973B4, 0x5A3B47AA,
+ 0x5A82799A, 0x5A82799A,
+ 0x5A3B47AA, 0x5AC973B4,
+ 0x59F3DE12, 0x5B1035CF,
+ 0x59AC3CFD, 0x5B56BFBD,
+ 0x59646497, 0x5B9D1153,
+ 0x591C550E, 0x5BE32A67,
+ 0x58D40E8C, 0x5C290ACC,
+ 0x588B913F, 0x5C6EB258,
+ 0x5842DD54, 0x5CB420DF,
+ 0x57F9F2F7, 0x5CF95638,
+ 0x57B0D256, 0x5D3E5236,
+ 0x57677B9D, 0x5D8314B0,
+ 0x571DEEF9, 0x5DC79D7C,
+ 0x56D42C99, 0x5E0BEC6E,
+ 0x568A34A9, 0x5E50015D,
+ 0x56400757, 0x5E93DC1F,
+ 0x55F5A4D2, 0x5ED77C89,
+ 0x55AB0D46, 0x5F1AE273,
+ 0x556040E2, 0x5F5E0DB3,
+ 0x55153FD4, 0x5FA0FE1E,
+ 0x54CA0A4A, 0x5FE3B38D,
+ 0x547EA073, 0x60262DD5,
+ 0x5433027D, 0x60686CCE,
+ 0x53E73097, 0x60AA704F,
+ 0x539B2AEF, 0x60EC3830,
+ 0x534EF1B5, 0x612DC446,
+ 0x53028517, 0x616F146B,
+ 0x52B5E545, 0x61B02876,
+ 0x5269126E, 0x61F1003E,
+ 0x521C0CC1, 0x62319B9D,
+ 0x51CED46E, 0x6271FA69,
+ 0x518169A4, 0x62B21C7B,
+ 0x5133CC94, 0x62F201AC,
+ 0x50E5FD6C, 0x6331A9D4,
+ 0x5097FC5E, 0x637114CC,
+ 0x5049C999, 0x63B0426D,
+ 0x4FFB654D, 0x63EF328F,
+ 0x4FACCFAB, 0x642DE50D,
+ 0x4F5E08E3, 0x646C59BF,
+ 0x4F0F1126, 0x64AA907F,
+ 0x4EBFE8A4, 0x64E88926,
+ 0x4E708F8F, 0x6526438E,
+ 0x4E210617, 0x6563BF92,
+ 0x4DD14C6E, 0x65A0FD0B,
+ 0x4D8162C4, 0x65DDFBD3,
+ 0x4D31494B, 0x661ABBC5,
+ 0x4CE10034, 0x66573CBB,
+ 0x4C9087B1, 0x66937E90,
+ 0x4C3FDFF3, 0x66CF811F,
+ 0x4BEF092D, 0x670B4443,
+ 0x4B9E038F, 0x6746C7D7,
+ 0x4B4CCF4D, 0x67820BB6,
+ 0x4AFB6C97, 0x67BD0FBC,
+ 0x4AA9DBA1, 0x67F7D3C4,
+ 0x4A581C9D, 0x683257AA,
+ 0x4A062FBD, 0x686C9B4B,
+ 0x49B41533, 0x68A69E81,
+ 0x4961CD32, 0x68E06129,
+ 0x490F57EE, 0x6919E320,
+ 0x48BCB598, 0x69532442,
+ 0x4869E664, 0x698C246C,
+ 0x4816EA85, 0x69C4E37A,
+ 0x47C3C22E, 0x69FD614A,
+ 0x47706D93, 0x6A359DB9,
+ 0x471CECE6, 0x6A6D98A4,
+ 0x46C9405C, 0x6AA551E8,
+ 0x46756827, 0x6ADCC964,
+ 0x4621647C, 0x6B13FEF5,
+ 0x45CD358F, 0x6B4AF278,
+ 0x4578DB93, 0x6B81A3CD,
+ 0x452456BC, 0x6BB812D0,
+ 0x44CFA73F, 0x6BEE3F62,
+ 0x447ACD50, 0x6C242960,
+ 0x4425C923, 0x6C59D0A9,
+ 0x43D09AEC, 0x6C8F351C,
+ 0x437B42E1, 0x6CC45697,
+ 0x4325C135, 0x6CF934FB,
+ 0x42D0161E, 0x6D2DD027,
+ 0x427A41D0, 0x6D6227FA,
+ 0x42244480, 0x6D963C54,
+ 0x41CE1E64, 0x6DCA0D14,
+ 0x4177CFB0, 0x6DFD9A1B,
+ 0x4121589A, 0x6E30E349,
+ 0x40CAB957, 0x6E63E87F,
+ 0x4073F21D, 0x6E96A99C,
+ 0x401D0320, 0x6EC92682,
+ 0x3FC5EC97, 0x6EFB5F12,
+ 0x3F6EAEB8, 0x6F2D532C,
+ 0x3F1749B7, 0x6F5F02B1,
+ 0x3EBFBDCC, 0x6F906D84,
+ 0x3E680B2C, 0x6FC19385,
+ 0x3E10320D, 0x6FF27496,
+ 0x3DB832A5, 0x70231099,
+ 0x3D600D2B, 0x70536771,
+ 0x3D07C1D5, 0x708378FE,
+ 0x3CAF50DA, 0x70B34524,
+ 0x3C56BA70, 0x70E2CBC6,
+ 0x3BFDFECD, 0x71120CC5,
+ 0x3BA51E29, 0x71410804,
+ 0x3B4C18BA, 0x716FBD68,
+ 0x3AF2EEB7, 0x719E2CD2,
+ 0x3A99A057, 0x71CC5626,
+ 0x3A402DD1, 0x71FA3948,
+ 0x39E6975D, 0x7227D61C,
+ 0x398CDD32, 0x72552C84,
+ 0x3932FF87, 0x72823C66,
+ 0x38D8FE93, 0x72AF05A6,
+ 0x387EDA8E, 0x72DB8828,
+ 0x382493B0, 0x7307C3D0,
+ 0x37CA2A30, 0x7333B883,
+ 0x376F9E46, 0x735F6626,
+ 0x3714F02A, 0x738ACC9E,
+ 0x36BA2013, 0x73B5EBD0,
+ 0x365F2E3B, 0x73E0C3A3,
+ 0x36041AD9, 0x740B53FA,
+ 0x35A8E624, 0x74359CBD,
+ 0x354D9056, 0x745F9DD1,
+ 0x34F219A7, 0x7489571B,
+ 0x3496824F, 0x74B2C883,
+ 0x343ACA87, 0x74DBF1EF,
+ 0x33DEF287, 0x7504D345,
+ 0x3382FA88, 0x752D6C6C,
+ 0x3326E2C2, 0x7555BD4B,
+ 0x32CAAB6F, 0x757DC5CA,
+ 0x326E54C7, 0x75A585CF,
+ 0x3211DF03, 0x75CCFD42,
+ 0x31B54A5D, 0x75F42C0A,
+ 0x3158970D, 0x761B1211,
+ 0x30FBC54D, 0x7641AF3C,
+ 0x309ED555, 0x76680376,
+ 0x3041C760, 0x768E0EA5,
+ 0x2FE49BA6, 0x76B3D0B3,
+ 0x2F875262, 0x76D94988,
+ 0x2F29EBCC, 0x76FE790E,
+ 0x2ECC681E, 0x77235F2D,
+ 0x2E6EC792, 0x7747FBCE,
+ 0x2E110A62, 0x776C4EDB,
+ 0x2DB330C7, 0x7790583D,
+ 0x2D553AFB, 0x77B417DF,
+ 0x2CF72939, 0x77D78DAA,
+ 0x2C98FBBA, 0x77FAB988,
+ 0x2C3AB2B9, 0x781D9B64,
+ 0x2BDC4E6F, 0x78403328,
+ 0x2B7DCF17, 0x786280BF,
+ 0x2B1F34EB, 0x78848413,
+ 0x2AC08025, 0x78A63D10,
+ 0x2A61B101, 0x78C7ABA1,
+ 0x2A02C7B8, 0x78E8CFB1,
+ 0x29A3C484, 0x7909A92C,
+ 0x2944A7A2, 0x792A37FE,
+ 0x28E5714A, 0x794A7C11,
+ 0x288621B9, 0x796A7554,
+ 0x2826B928, 0x798A23B1,
+ 0x27C737D2, 0x79A98715,
+ 0x27679DF4, 0x79C89F6D,
+ 0x2707EBC6, 0x79E76CA6,
+ 0x26A82185, 0x7A05EEAD,
+ 0x26483F6C, 0x7A24256E,
+ 0x25E845B5, 0x7A4210D8,
+ 0x2588349D, 0x7A5FB0D8,
+ 0x25280C5D, 0x7A7D055B,
+ 0x24C7CD32, 0x7A9A0E4F,
+ 0x24677757, 0x7AB6CBA3,
+ 0x24070B07, 0x7AD33D45,
+ 0x23A6887E, 0x7AEF6323,
+ 0x2345EFF7, 0x7B0B3D2C,
+ 0x22E541AE, 0x7B26CB4F,
+ 0x22847DDF, 0x7B420D7A,
+ 0x2223A4C5, 0x7B5D039D,
+ 0x21C2B69C, 0x7B77ADA8,
+ 0x2161B39F, 0x7B920B89,
+ 0x21009C0B, 0x7BAC1D31,
+ 0x209F701C, 0x7BC5E28F,
+ 0x203E300D, 0x7BDF5B94,
+ 0x1FDCDC1A, 0x7BF88830,
+ 0x1F7B7480, 0x7C116853,
+ 0x1F19F97B, 0x7C29FBEE,
+ 0x1EB86B46, 0x7C4242F2,
+ 0x1E56CA1E, 0x7C5A3D4F,
+ 0x1DF5163F, 0x7C71EAF8,
+ 0x1D934FE5, 0x7C894BDD,
+ 0x1D31774D, 0x7CA05FF1,
+ 0x1CCF8CB3, 0x7CB72724,
+ 0x1C6D9053, 0x7CCDA168,
+ 0x1C0B826A, 0x7CE3CEB1,
+ 0x1BA96334, 0x7CF9AEF0,
+ 0x1B4732EF, 0x7D0F4218,
+ 0x1AE4F1D6, 0x7D24881A,
+ 0x1A82A025, 0x7D3980EC,
+ 0x1A203E1B, 0x7D4E2C7E,
+ 0x19BDCBF2, 0x7D628AC5,
+ 0x195B49E9, 0x7D769BB5,
+ 0x18F8B83C, 0x7D8A5F3F,
+ 0x18961727, 0x7D9DD55A,
+ 0x183366E8, 0x7DB0FDF7,
+ 0x17D0A7BB, 0x7DC3D90D,
+ 0x176DD9DE, 0x7DD6668E,
+ 0x170AFD8D, 0x7DE8A670,
+ 0x16A81305, 0x7DFA98A7,
+ 0x16451A83, 0x7E0C3D29,
+ 0x15E21444, 0x7E1D93E9,
+ 0x157F0086, 0x7E2E9CDF,
+ 0x151BDF85, 0x7E3F57FE,
+ 0x14B8B17F, 0x7E4FC53E,
+ 0x145576B1, 0x7E5FE493,
+ 0x13F22F57, 0x7E6FB5F3,
+ 0x138EDBB0, 0x7E7F3956,
+ 0x132B7BF9, 0x7E8E6EB1,
+ 0x12C8106E, 0x7E9D55FC,
+ 0x1264994E, 0x7EABEF2C,
+ 0x120116D4, 0x7EBA3A39,
+ 0x119D8940, 0x7EC8371A,
+ 0x1139F0CE, 0x7ED5E5C6,
+ 0x10D64DBC, 0x7EE34635,
+ 0x1072A047, 0x7EF0585F,
+ 0x100EE8AD, 0x7EFD1C3C,
+ 0x0FAB272B, 0x7F0991C3,
+ 0x0F475BFE, 0x7F15B8EE,
+ 0x0EE38765, 0x7F2191B4,
+ 0x0E7FA99D, 0x7F2D1C0E,
+ 0x0E1BC2E3, 0x7F3857F5,
+ 0x0DB7D376, 0x7F434563,
+ 0x0D53DB92, 0x7F4DE450,
+ 0x0CEFDB75, 0x7F5834B6,
+ 0x0C8BD35E, 0x7F62368F,
+ 0x0C27C389, 0x7F6BE9D4,
+ 0x0BC3AC35, 0x7F754E7F,
+ 0x0B5F8D9F, 0x7F7E648B,
+ 0x0AFB6805, 0x7F872BF3,
+ 0x0A973BA5, 0x7F8FA4AF,
+ 0x0A3308BC, 0x7F97CEBC,
+ 0x09CECF89, 0x7F9FAA15,
+ 0x096A9049, 0x7FA736B4,
+ 0x09064B3A, 0x7FAE7494,
+ 0x08A2009A, 0x7FB563B2,
+ 0x083DB0A7, 0x7FBC040A,
+ 0x07D95B9E, 0x7FC25596,
+ 0x077501BE, 0x7FC85853,
+ 0x0710A344, 0x7FCE0C3E,
+ 0x06AC406F, 0x7FD37152,
+ 0x0647D97C, 0x7FD8878D,
+ 0x05E36EA9, 0x7FDD4EEC,
+ 0x057F0034, 0x7FE1C76B,
+ 0x051A8E5C, 0x7FE5F108,
+ 0x04B6195D, 0x7FE9CBC0,
+ 0x0451A176, 0x7FED5790,
+ 0x03ED26E6, 0x7FF09477,
+ 0x0388A9E9, 0x7FF38273,
+ 0x03242ABF, 0x7FF62182,
+ 0x02BFA9A4, 0x7FF871A1,
+ 0x025B26D7, 0x7FFA72D1,
+ 0x01F6A296, 0x7FFC250F,
+ 0x01921D1F, 0x7FFD885A,
+ 0x012D96B0, 0x7FFE9CB2,
+ 0x00C90F88, 0x7FFF6216,
+ 0x006487E3, 0x7FFFD885,
+ 0x00000000, 0x7FFFFFFF,
+ 0xFF9B781D, 0x7FFFD885,
+ 0xFF36F078, 0x7FFF6216,
+ 0xFED2694F, 0x7FFE9CB2,
+ 0xFE6DE2E0, 0x7FFD885A,
+ 0xFE095D69, 0x7FFC250F,
+ 0xFDA4D928, 0x7FFA72D1,
+ 0xFD40565B, 0x7FF871A1,
+ 0xFCDBD541, 0x7FF62182,
+ 0xFC775616, 0x7FF38273,
+ 0xFC12D919, 0x7FF09477,
+ 0xFBAE5E89, 0x7FED5790,
+ 0xFB49E6A2, 0x7FE9CBC0,
+ 0xFAE571A4, 0x7FE5F108,
+ 0xFA80FFCB, 0x7FE1C76B,
+ 0xFA1C9156, 0x7FDD4EEC,
+ 0xF9B82683, 0x7FD8878D,
+ 0xF953BF90, 0x7FD37152,
+ 0xF8EF5CBB, 0x7FCE0C3E,
+ 0xF88AFE41, 0x7FC85853,
+ 0xF826A461, 0x7FC25596,
+ 0xF7C24F58, 0x7FBC040A,
+ 0xF75DFF65, 0x7FB563B2,
+ 0xF6F9B4C5, 0x7FAE7494,
+ 0xF6956FB6, 0x7FA736B4,
+ 0xF6313076, 0x7F9FAA15,
+ 0xF5CCF743, 0x7F97CEBC,
+ 0xF568C45A, 0x7F8FA4AF,
+ 0xF50497FA, 0x7F872BF3,
+ 0xF4A07260, 0x7F7E648B,
+ 0xF43C53CA, 0x7F754E7F,
+ 0xF3D83C76, 0x7F6BE9D4,
+ 0xF3742CA1, 0x7F62368F,
+ 0xF310248A, 0x7F5834B6,
+ 0xF2AC246D, 0x7F4DE450,
+ 0xF2482C89, 0x7F434563,
+ 0xF1E43D1C, 0x7F3857F5,
+ 0xF1805662, 0x7F2D1C0E,
+ 0xF11C789A, 0x7F2191B4,
+ 0xF0B8A401, 0x7F15B8EE,
+ 0xF054D8D4, 0x7F0991C3,
+ 0xEFF11752, 0x7EFD1C3C,
+ 0xEF8D5FB8, 0x7EF0585F,
+ 0xEF29B243, 0x7EE34635,
+ 0xEEC60F31, 0x7ED5E5C6,
+ 0xEE6276BF, 0x7EC8371A,
+ 0xEDFEE92B, 0x7EBA3A39,
+ 0xED9B66B2, 0x7EABEF2C,
+ 0xED37EF91, 0x7E9D55FC,
+ 0xECD48406, 0x7E8E6EB1,
+ 0xEC71244F, 0x7E7F3956,
+ 0xEC0DD0A8, 0x7E6FB5F3,
+ 0xEBAA894E, 0x7E5FE493,
+ 0xEB474E80, 0x7E4FC53E,
+ 0xEAE4207A, 0x7E3F57FE,
+ 0xEA80FF79, 0x7E2E9CDF,
+ 0xEA1DEBBB, 0x7E1D93E9,
+ 0xE9BAE57C, 0x7E0C3D29,
+ 0xE957ECFB, 0x7DFA98A7,
+ 0xE8F50273, 0x7DE8A670,
+ 0xE8922621, 0x7DD6668E,
+ 0xE82F5844, 0x7DC3D90D,
+ 0xE7CC9917, 0x7DB0FDF7,
+ 0xE769E8D8, 0x7D9DD55A,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xE6A4B616, 0x7D769BB5,
+ 0xE642340D, 0x7D628AC5,
+ 0xE5DFC1E4, 0x7D4E2C7E,
+ 0xE57D5FDA, 0x7D3980EC,
+ 0xE51B0E2A, 0x7D24881A,
+ 0xE4B8CD10, 0x7D0F4218,
+ 0xE4569CCB, 0x7CF9AEF0,
+ 0xE3F47D95, 0x7CE3CEB1,
+ 0xE3926FAC, 0x7CCDA168,
+ 0xE330734C, 0x7CB72724,
+ 0xE2CE88B2, 0x7CA05FF1,
+ 0xE26CB01A, 0x7C894BDD,
+ 0xE20AE9C1, 0x7C71EAF8,
+ 0xE1A935E1, 0x7C5A3D4F,
+ 0xE14794B9, 0x7C4242F2,
+ 0xE0E60684, 0x7C29FBEE,
+ 0xE0848B7F, 0x7C116853,
+ 0xE02323E5, 0x7BF88830,
+ 0xDFC1CFF2, 0x7BDF5B94,
+ 0xDF608FE3, 0x7BC5E28F,
+ 0xDEFF63F4, 0x7BAC1D31,
+ 0xDE9E4C60, 0x7B920B89,
+ 0xDE3D4963, 0x7B77ADA8,
+ 0xDDDC5B3A, 0x7B5D039D,
+ 0xDD7B8220, 0x7B420D7A,
+ 0xDD1ABE51, 0x7B26CB4F,
+ 0xDCBA1008, 0x7B0B3D2C,
+ 0xDC597781, 0x7AEF6323,
+ 0xDBF8F4F8, 0x7AD33D45,
+ 0xDB9888A8, 0x7AB6CBA3,
+ 0xDB3832CD, 0x7A9A0E4F,
+ 0xDAD7F3A2, 0x7A7D055B,
+ 0xDA77CB62, 0x7A5FB0D8,
+ 0xDA17BA4A, 0x7A4210D8,
+ 0xD9B7C093, 0x7A24256E,
+ 0xD957DE7A, 0x7A05EEAD,
+ 0xD8F81439, 0x79E76CA6,
+ 0xD898620C, 0x79C89F6D,
+ 0xD838C82D, 0x79A98715,
+ 0xD7D946D7, 0x798A23B1,
+ 0xD779DE46, 0x796A7554,
+ 0xD71A8EB5, 0x794A7C11,
+ 0xD6BB585D, 0x792A37FE,
+ 0xD65C3B7B, 0x7909A92C,
+ 0xD5FD3847, 0x78E8CFB1,
+ 0xD59E4EFE, 0x78C7ABA1,
+ 0xD53F7FDA, 0x78A63D10,
+ 0xD4E0CB14, 0x78848413,
+ 0xD48230E8, 0x786280BF,
+ 0xD423B190, 0x78403328,
+ 0xD3C54D46, 0x781D9B64,
+ 0xD3670445, 0x77FAB988,
+ 0xD308D6C6, 0x77D78DAA,
+ 0xD2AAC504, 0x77B417DF,
+ 0xD24CCF38, 0x7790583D,
+ 0xD1EEF59E, 0x776C4EDB,
+ 0xD191386D, 0x7747FBCE,
+ 0xD13397E1, 0x77235F2D,
+ 0xD0D61433, 0x76FE790E,
+ 0xD078AD9D, 0x76D94988,
+ 0xD01B6459, 0x76B3D0B3,
+ 0xCFBE389F, 0x768E0EA5,
+ 0xCF612AAA, 0x76680376,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xCEA768F2, 0x761B1211,
+ 0xCE4AB5A2, 0x75F42C0A,
+ 0xCDEE20FC, 0x75CCFD42,
+ 0xCD91AB38, 0x75A585CF,
+ 0xCD355490, 0x757DC5CA,
+ 0xCCD91D3D, 0x7555BD4B,
+ 0xCC7D0577, 0x752D6C6C,
+ 0xCC210D78, 0x7504D345,
+ 0xCBC53578, 0x74DBF1EF,
+ 0xCB697DB0, 0x74B2C883,
+ 0xCB0DE658, 0x7489571B,
+ 0xCAB26FA9, 0x745F9DD1,
+ 0xCA5719DB, 0x74359CBD,
+ 0xC9FBE527, 0x740B53FA,
+ 0xC9A0D1C4, 0x73E0C3A3,
+ 0xC945DFEC, 0x73B5EBD0,
+ 0xC8EB0FD6, 0x738ACC9E,
+ 0xC89061BA, 0x735F6626,
+ 0xC835D5D0, 0x7333B883,
+ 0xC7DB6C50, 0x7307C3D0,
+ 0xC7812571, 0x72DB8828,
+ 0xC727016C, 0x72AF05A6,
+ 0xC6CD0079, 0x72823C66,
+ 0xC67322CD, 0x72552C84,
+ 0xC61968A2, 0x7227D61C,
+ 0xC5BFD22E, 0x71FA3948,
+ 0xC5665FA8, 0x71CC5626,
+ 0xC50D1148, 0x719E2CD2,
+ 0xC4B3E746, 0x716FBD68,
+ 0xC45AE1D7, 0x71410804,
+ 0xC4020132, 0x71120CC5,
+ 0xC3A9458F, 0x70E2CBC6,
+ 0xC350AF25, 0x70B34524,
+ 0xC2F83E2A, 0x708378FE,
+ 0xC29FF2D4, 0x70536771,
+ 0xC247CD5A, 0x70231099,
+ 0xC1EFCDF2, 0x6FF27496,
+ 0xC197F4D3, 0x6FC19385,
+ 0xC1404233, 0x6F906D84,
+ 0xC0E8B648, 0x6F5F02B1,
+ 0xC0915147, 0x6F2D532C,
+ 0xC03A1368, 0x6EFB5F12,
+ 0xBFE2FCDF, 0x6EC92682,
+ 0xBF8C0DE2, 0x6E96A99C,
+ 0xBF3546A8, 0x6E63E87F,
+ 0xBEDEA765, 0x6E30E349,
+ 0xBE88304F, 0x6DFD9A1B,
+ 0xBE31E19B, 0x6DCA0D14,
+ 0xBDDBBB7F, 0x6D963C54,
+ 0xBD85BE2F, 0x6D6227FA,
+ 0xBD2FE9E1, 0x6D2DD027,
+ 0xBCDA3ECA, 0x6CF934FB,
+ 0xBC84BD1E, 0x6CC45697,
+ 0xBC2F6513, 0x6C8F351C,
+ 0xBBDA36DC, 0x6C59D0A9,
+ 0xBB8532AF, 0x6C242960,
+ 0xBB3058C0, 0x6BEE3F62,
+ 0xBADBA943, 0x6BB812D0,
+ 0xBA87246C, 0x6B81A3CD,
+ 0xBA32CA70, 0x6B4AF278,
+ 0xB9DE9B83, 0x6B13FEF5,
+ 0xB98A97D8, 0x6ADCC964,
+ 0xB936BFA3, 0x6AA551E8,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xB88F926C, 0x6A359DB9,
+ 0xB83C3DD1, 0x69FD614A,
+ 0xB7E9157A, 0x69C4E37A,
+ 0xB796199B, 0x698C246C,
+ 0xB7434A67, 0x69532442,
+ 0xB6F0A811, 0x6919E320,
+ 0xB69E32CD, 0x68E06129,
+ 0xB64BEACC, 0x68A69E81,
+ 0xB5F9D042, 0x686C9B4B,
+ 0xB5A7E362, 0x683257AA,
+ 0xB556245E, 0x67F7D3C4,
+ 0xB5049368, 0x67BD0FBC,
+ 0xB4B330B2, 0x67820BB6,
+ 0xB461FC70, 0x6746C7D7,
+ 0xB410F6D2, 0x670B4443,
+ 0xB3C0200C, 0x66CF811F,
+ 0xB36F784E, 0x66937E90,
+ 0xB31EFFCB, 0x66573CBB,
+ 0xB2CEB6B5, 0x661ABBC5,
+ 0xB27E9D3B, 0x65DDFBD3,
+ 0xB22EB392, 0x65A0FD0B,
+ 0xB1DEF9E8, 0x6563BF92,
+ 0xB18F7070, 0x6526438E,
+ 0xB140175B, 0x64E88926,
+ 0xB0F0EEDA, 0x64AA907F,
+ 0xB0A1F71C, 0x646C59BF,
+ 0xB0533055, 0x642DE50D,
+ 0xB0049AB2, 0x63EF328F,
+ 0xAFB63667, 0x63B0426D,
+ 0xAF6803A1, 0x637114CC,
+ 0xAF1A0293, 0x6331A9D4,
+ 0xAECC336B, 0x62F201AC,
+ 0xAE7E965B, 0x62B21C7B,
+ 0xAE312B91, 0x6271FA69,
+ 0xADE3F33E, 0x62319B9D,
+ 0xAD96ED91, 0x61F1003E,
+ 0xAD4A1ABA, 0x61B02876,
+ 0xACFD7AE8, 0x616F146B,
+ 0xACB10E4A, 0x612DC446,
+ 0xAC64D510, 0x60EC3830,
+ 0xAC18CF68, 0x60AA704F,
+ 0xABCCFD82, 0x60686CCE,
+ 0xAB815F8C, 0x60262DD5,
+ 0xAB35F5B5, 0x5FE3B38D,
+ 0xAAEAC02B, 0x5FA0FE1E,
+ 0xAA9FBF1D, 0x5F5E0DB3,
+ 0xAA54F2B9, 0x5F1AE273,
+ 0xAA0A5B2D, 0x5ED77C89,
+ 0xA9BFF8A8, 0x5E93DC1F,
+ 0xA975CB56, 0x5E50015D,
+ 0xA92BD366, 0x5E0BEC6E,
+ 0xA8E21106, 0x5DC79D7C,
+ 0xA8988463, 0x5D8314B0,
+ 0xA84F2DA9, 0x5D3E5236,
+ 0xA8060D08, 0x5CF95638,
+ 0xA7BD22AB, 0x5CB420DF,
+ 0xA7746EC0, 0x5C6EB258,
+ 0xA72BF173, 0x5C290ACC,
+ 0xA6E3AAF2, 0x5BE32A67,
+ 0xA69B9B68, 0x5B9D1153,
+ 0xA653C302, 0x5B56BFBD,
+ 0xA60C21ED, 0x5B1035CF,
+ 0xA5C4B855, 0x5AC973B4,
+ 0xA57D8666, 0x5A82799A,
+ 0xA5368C4B, 0x5A3B47AA,
+ 0xA4EFCA31, 0x59F3DE12,
+ 0xA4A94042, 0x59AC3CFD,
+ 0xA462EEAC, 0x59646497,
+ 0xA41CD598, 0x591C550E,
+ 0xA3D6F533, 0x58D40E8C,
+ 0xA3914DA7, 0x588B913F,
+ 0xA34BDF20, 0x5842DD54,
+ 0xA306A9C7, 0x57F9F2F7,
+ 0xA2C1ADC9, 0x57B0D256,
+ 0xA27CEB4F, 0x57677B9D,
+ 0xA2386283, 0x571DEEF9,
+ 0xA1F41391, 0x56D42C99,
+ 0xA1AFFEA2, 0x568A34A9,
+ 0xA16C23E1, 0x56400757,
+ 0xA1288376, 0x55F5A4D2,
+ 0xA0E51D8C, 0x55AB0D46,
+ 0xA0A1F24C, 0x556040E2,
+ 0xA05F01E1, 0x55153FD4,
+ 0xA01C4C72, 0x54CA0A4A,
+ 0x9FD9D22A, 0x547EA073,
+ 0x9F979331, 0x5433027D,
+ 0x9F558FB0, 0x53E73097,
+ 0x9F13C7D0, 0x539B2AEF,
+ 0x9ED23BB9, 0x534EF1B5,
+ 0x9E90EB94, 0x53028517,
+ 0x9E4FD789, 0x52B5E545,
+ 0x9E0EFFC1, 0x5269126E,
+ 0x9DCE6462, 0x521C0CC1,
+ 0x9D8E0596, 0x51CED46E,
+ 0x9D4DE384, 0x518169A4,
+ 0x9D0DFE53, 0x5133CC94,
+ 0x9CCE562B, 0x50E5FD6C,
+ 0x9C8EEB33, 0x5097FC5E,
+ 0x9C4FBD92, 0x5049C999,
+ 0x9C10CD70, 0x4FFB654D,
+ 0x9BD21AF2, 0x4FACCFAB,
+ 0x9B93A640, 0x4F5E08E3,
+ 0x9B556F80, 0x4F0F1126,
+ 0x9B1776D9, 0x4EBFE8A4,
+ 0x9AD9BC71, 0x4E708F8F,
+ 0x9A9C406D, 0x4E210617,
+ 0x9A5F02F5, 0x4DD14C6E,
+ 0x9A22042C, 0x4D8162C4,
+ 0x99E5443A, 0x4D31494B,
+ 0x99A8C344, 0x4CE10034,
+ 0x996C816F, 0x4C9087B1,
+ 0x99307EE0, 0x4C3FDFF3,
+ 0x98F4BBBC, 0x4BEF092D,
+ 0x98B93828, 0x4B9E038F,
+ 0x987DF449, 0x4B4CCF4D,
+ 0x9842F043, 0x4AFB6C97,
+ 0x98082C3B, 0x4AA9DBA1,
+ 0x97CDA855, 0x4A581C9D,
+ 0x979364B5, 0x4A062FBD,
+ 0x9759617E, 0x49B41533,
+ 0x971F9ED6, 0x4961CD32,
+ 0x96E61CDF, 0x490F57EE,
+ 0x96ACDBBD, 0x48BCB598,
+ 0x9673DB94, 0x4869E664,
+ 0x963B1C85, 0x4816EA85,
+ 0x96029EB5, 0x47C3C22E,
+ 0x95CA6246, 0x47706D93,
+ 0x9592675B, 0x471CECE6,
+ 0x955AAE17, 0x46C9405C,
+ 0x9523369B, 0x46756827,
+ 0x94EC010B, 0x4621647C,
+ 0x94B50D87, 0x45CD358F,
+ 0x947E5C32, 0x4578DB93,
+ 0x9447ED2F, 0x452456BC,
+ 0x9411C09D, 0x44CFA73F,
+ 0x93DBD69F, 0x447ACD50,
+ 0x93A62F56, 0x4425C923,
+ 0x9370CAE4, 0x43D09AEC,
+ 0x933BA968, 0x437B42E1,
+ 0x9306CB04, 0x4325C135,
+ 0x92D22FD8, 0x42D0161E,
+ 0x929DD805, 0x427A41D0,
+ 0x9269C3AC, 0x42244480,
+ 0x9235F2EB, 0x41CE1E64,
+ 0x920265E4, 0x4177CFB0,
+ 0x91CF1CB6, 0x4121589A,
+ 0x919C1780, 0x40CAB957,
+ 0x91695663, 0x4073F21D,
+ 0x9136D97D, 0x401D0320,
+ 0x9104A0ED, 0x3FC5EC97,
+ 0x90D2ACD3, 0x3F6EAEB8,
+ 0x90A0FD4E, 0x3F1749B7,
+ 0x906F927B, 0x3EBFBDCC,
+ 0x903E6C7A, 0x3E680B2C,
+ 0x900D8B69, 0x3E10320D,
+ 0x8FDCEF66, 0x3DB832A5,
+ 0x8FAC988E, 0x3D600D2B,
+ 0x8F7C8701, 0x3D07C1D5,
+ 0x8F4CBADB, 0x3CAF50DA,
+ 0x8F1D343A, 0x3C56BA70,
+ 0x8EEDF33B, 0x3BFDFECD,
+ 0x8EBEF7FB, 0x3BA51E29,
+ 0x8E904298, 0x3B4C18BA,
+ 0x8E61D32D, 0x3AF2EEB7,
+ 0x8E33A9D9, 0x3A99A057,
+ 0x8E05C6B7, 0x3A402DD1,
+ 0x8DD829E4, 0x39E6975D,
+ 0x8DAAD37B, 0x398CDD32,
+ 0x8D7DC399, 0x3932FF87,
+ 0x8D50FA59, 0x38D8FE93,
+ 0x8D2477D8, 0x387EDA8E,
+ 0x8CF83C30, 0x382493B0,
+ 0x8CCC477D, 0x37CA2A30,
+ 0x8CA099D9, 0x376F9E46,
+ 0x8C753361, 0x3714F02A,
+ 0x8C4A142F, 0x36BA2013,
+ 0x8C1F3C5C, 0x365F2E3B,
+ 0x8BF4AC05, 0x36041AD9,
+ 0x8BCA6342, 0x35A8E624,
+ 0x8BA0622F, 0x354D9056,
+ 0x8B76A8E4, 0x34F219A7,
+ 0x8B4D377C, 0x3496824F,
+ 0x8B240E10, 0x343ACA87,
+ 0x8AFB2CBA, 0x33DEF287,
+ 0x8AD29393, 0x3382FA88,
+ 0x8AAA42B4, 0x3326E2C2,
+ 0x8A823A35, 0x32CAAB6F,
+ 0x8A5A7A30, 0x326E54C7,
+ 0x8A3302BD, 0x3211DF03,
+ 0x8A0BD3F5, 0x31B54A5D,
+ 0x89E4EDEE, 0x3158970D,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x8997FC89, 0x309ED555,
+ 0x8971F15A, 0x3041C760,
+ 0x894C2F4C, 0x2FE49BA6,
+ 0x8926B677, 0x2F875262,
+ 0x890186F1, 0x2F29EBCC,
+ 0x88DCA0D3, 0x2ECC681E,
+ 0x88B80431, 0x2E6EC792,
+ 0x8893B124, 0x2E110A62,
+ 0x886FA7C2, 0x2DB330C7,
+ 0x884BE820, 0x2D553AFB,
+ 0x88287255, 0x2CF72939,
+ 0x88054677, 0x2C98FBBA,
+ 0x87E2649B, 0x2C3AB2B9,
+ 0x87BFCCD7, 0x2BDC4E6F,
+ 0x879D7F40, 0x2B7DCF17,
+ 0x877B7BEC, 0x2B1F34EB,
+ 0x8759C2EF, 0x2AC08025,
+ 0x8738545E, 0x2A61B101,
+ 0x8717304E, 0x2A02C7B8,
+ 0x86F656D3, 0x29A3C484,
+ 0x86D5C802, 0x2944A7A2,
+ 0x86B583EE, 0x28E5714A,
+ 0x86958AAB, 0x288621B9,
+ 0x8675DC4E, 0x2826B928,
+ 0x865678EA, 0x27C737D2,
+ 0x86376092, 0x27679DF4,
+ 0x86189359, 0x2707EBC6,
+ 0x85FA1152, 0x26A82185,
+ 0x85DBDA91, 0x26483F6C,
+ 0x85BDEF27, 0x25E845B5,
+ 0x85A04F28, 0x2588349D,
+ 0x8582FAA4, 0x25280C5D,
+ 0x8565F1B0, 0x24C7CD32,
+ 0x8549345C, 0x24677757,
+ 0x852CC2BA, 0x24070B07,
+ 0x85109CDC, 0x23A6887E,
+ 0x84F4C2D3, 0x2345EFF7,
+ 0x84D934B0, 0x22E541AE,
+ 0x84BDF285, 0x22847DDF,
+ 0x84A2FC62, 0x2223A4C5,
+ 0x84885257, 0x21C2B69C,
+ 0x846DF476, 0x2161B39F,
+ 0x8453E2CE, 0x21009C0B,
+ 0x843A1D70, 0x209F701C,
+ 0x8420A46B, 0x203E300D,
+ 0x840777CF, 0x1FDCDC1A,
+ 0x83EE97AC, 0x1F7B7480,
+ 0x83D60411, 0x1F19F97B,
+ 0x83BDBD0D, 0x1EB86B46,
+ 0x83A5C2B0, 0x1E56CA1E,
+ 0x838E1507, 0x1DF5163F,
+ 0x8376B422, 0x1D934FE5,
+ 0x835FA00E, 0x1D31774D,
+ 0x8348D8DB, 0x1CCF8CB3,
+ 0x83325E97, 0x1C6D9053,
+ 0x831C314E, 0x1C0B826A,
+ 0x8306510F, 0x1BA96334,
+ 0x82F0BDE8, 0x1B4732EF,
+ 0x82DB77E5, 0x1AE4F1D6,
+ 0x82C67F13, 0x1A82A025,
+ 0x82B1D381, 0x1A203E1B,
+ 0x829D753A, 0x19BDCBF2,
+ 0x8289644A, 0x195B49E9,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x82622AA5, 0x18961727,
+ 0x824F0208, 0x183366E8,
+ 0x823C26F2, 0x17D0A7BB,
+ 0x82299971, 0x176DD9DE,
+ 0x8217598F, 0x170AFD8D,
+ 0x82056758, 0x16A81305,
+ 0x81F3C2D7, 0x16451A83,
+ 0x81E26C16, 0x15E21444,
+ 0x81D16320, 0x157F0086,
+ 0x81C0A801, 0x151BDF85,
+ 0x81B03AC1, 0x14B8B17F,
+ 0x81A01B6C, 0x145576B1,
+ 0x81904A0C, 0x13F22F57,
+ 0x8180C6A9, 0x138EDBB0,
+ 0x8171914E, 0x132B7BF9,
+ 0x8162AA03, 0x12C8106E,
+ 0x815410D3, 0x1264994E,
+ 0x8145C5C6, 0x120116D4,
+ 0x8137C8E6, 0x119D8940,
+ 0x812A1A39, 0x1139F0CE,
+ 0x811CB9CA, 0x10D64DBC,
+ 0x810FA7A0, 0x1072A047,
+ 0x8102E3C3, 0x100EE8AD,
+ 0x80F66E3C, 0x0FAB272B,
+ 0x80EA4712, 0x0F475BFE,
+ 0x80DE6E4C, 0x0EE38765,
+ 0x80D2E3F1, 0x0E7FA99D,
+ 0x80C7A80A, 0x0E1BC2E3,
+ 0x80BCBA9C, 0x0DB7D376,
+ 0x80B21BAF, 0x0D53DB92,
+ 0x80A7CB49, 0x0CEFDB75,
+ 0x809DC970, 0x0C8BD35E,
+ 0x8094162B, 0x0C27C389,
+ 0x808AB180, 0x0BC3AC35,
+ 0x80819B74, 0x0B5F8D9F,
+ 0x8078D40D, 0x0AFB6805,
+ 0x80705B50, 0x0A973BA5,
+ 0x80683143, 0x0A3308BC,
+ 0x806055EA, 0x09CECF89,
+ 0x8058C94C, 0x096A9049,
+ 0x80518B6B, 0x09064B3A,
+ 0x804A9C4D, 0x08A2009A,
+ 0x8043FBF6, 0x083DB0A7,
+ 0x803DAA69, 0x07D95B9E,
+ 0x8037A7AC, 0x077501BE,
+ 0x8031F3C1, 0x0710A344,
+ 0x802C8EAD, 0x06AC406F,
+ 0x80277872, 0x0647D97C,
+ 0x8022B113, 0x05E36EA9,
+ 0x801E3894, 0x057F0034,
+ 0x801A0EF7, 0x051A8E5C,
+ 0x80163440, 0x04B6195D,
+ 0x8012A86F, 0x0451A176,
+ 0x800F6B88, 0x03ED26E6,
+ 0x800C7D8C, 0x0388A9E9,
+ 0x8009DE7D, 0x03242ABF,
+ 0x80078E5E, 0x02BFA9A4,
+ 0x80058D2E, 0x025B26D7,
+ 0x8003DAF0, 0x01F6A296,
+ 0x800277A5, 0x01921D1F,
+ 0x8001634D, 0x012D96B0,
+ 0x80009DE9, 0x00C90F88,
+ 0x8000277A, 0x006487E3,
+ 0x80000000, 0x00000000,
+ 0x8000277A, 0xFF9B781D,
+ 0x80009DE9, 0xFF36F078,
+ 0x8001634D, 0xFED2694F,
+ 0x800277A5, 0xFE6DE2E0,
+ 0x8003DAF0, 0xFE095D69,
+ 0x80058D2E, 0xFDA4D928,
+ 0x80078E5E, 0xFD40565B,
+ 0x8009DE7D, 0xFCDBD541,
+ 0x800C7D8C, 0xFC775616,
+ 0x800F6B88, 0xFC12D919,
+ 0x8012A86F, 0xFBAE5E89,
+ 0x80163440, 0xFB49E6A2,
+ 0x801A0EF7, 0xFAE571A4,
+ 0x801E3894, 0xFA80FFCB,
+ 0x8022B113, 0xFA1C9156,
+ 0x80277872, 0xF9B82683,
+ 0x802C8EAD, 0xF953BF90,
+ 0x8031F3C1, 0xF8EF5CBB,
+ 0x8037A7AC, 0xF88AFE41,
+ 0x803DAA69, 0xF826A461,
+ 0x8043FBF6, 0xF7C24F58,
+ 0x804A9C4D, 0xF75DFF65,
+ 0x80518B6B, 0xF6F9B4C5,
+ 0x8058C94C, 0xF6956FB6,
+ 0x806055EA, 0xF6313076,
+ 0x80683143, 0xF5CCF743,
+ 0x80705B50, 0xF568C45A,
+ 0x8078D40D, 0xF50497FA,
+ 0x80819B74, 0xF4A07260,
+ 0x808AB180, 0xF43C53CA,
+ 0x8094162B, 0xF3D83C76,
+ 0x809DC970, 0xF3742CA1,
+ 0x80A7CB49, 0xF310248A,
+ 0x80B21BAF, 0xF2AC246D,
+ 0x80BCBA9C, 0xF2482C89,
+ 0x80C7A80A, 0xF1E43D1C,
+ 0x80D2E3F1, 0xF1805662,
+ 0x80DE6E4C, 0xF11C789A,
+ 0x80EA4712, 0xF0B8A401,
+ 0x80F66E3C, 0xF054D8D4,
+ 0x8102E3C3, 0xEFF11752,
+ 0x810FA7A0, 0xEF8D5FB8,
+ 0x811CB9CA, 0xEF29B243,
+ 0x812A1A39, 0xEEC60F31,
+ 0x8137C8E6, 0xEE6276BF,
+ 0x8145C5C6, 0xEDFEE92B,
+ 0x815410D3, 0xED9B66B2,
+ 0x8162AA03, 0xED37EF91,
+ 0x8171914E, 0xECD48406,
+ 0x8180C6A9, 0xEC71244F,
+ 0x81904A0C, 0xEC0DD0A8,
+ 0x81A01B6C, 0xEBAA894E,
+ 0x81B03AC1, 0xEB474E80,
+ 0x81C0A801, 0xEAE4207A,
+ 0x81D16320, 0xEA80FF79,
+ 0x81E26C16, 0xEA1DEBBB,
+ 0x81F3C2D7, 0xE9BAE57C,
+ 0x82056758, 0xE957ECFB,
+ 0x8217598F, 0xE8F50273,
+ 0x82299971, 0xE8922621,
+ 0x823C26F2, 0xE82F5844,
+ 0x824F0208, 0xE7CC9917,
+ 0x82622AA5, 0xE769E8D8,
+ 0x8275A0C0, 0xE70747C3,
+ 0x8289644A, 0xE6A4B616,
+ 0x829D753A, 0xE642340D,
+ 0x82B1D381, 0xE5DFC1E4,
+ 0x82C67F13, 0xE57D5FDA,
+ 0x82DB77E5, 0xE51B0E2A,
+ 0x82F0BDE8, 0xE4B8CD10,
+ 0x8306510F, 0xE4569CCB,
+ 0x831C314E, 0xE3F47D95,
+ 0x83325E97, 0xE3926FAC,
+ 0x8348D8DB, 0xE330734C,
+ 0x835FA00E, 0xE2CE88B2,
+ 0x8376B422, 0xE26CB01A,
+ 0x838E1507, 0xE20AE9C1,
+ 0x83A5C2B0, 0xE1A935E1,
+ 0x83BDBD0D, 0xE14794B9,
+ 0x83D60411, 0xE0E60684,
+ 0x83EE97AC, 0xE0848B7F,
+ 0x840777CF, 0xE02323E5,
+ 0x8420A46B, 0xDFC1CFF2,
+ 0x843A1D70, 0xDF608FE3,
+ 0x8453E2CE, 0xDEFF63F4,
+ 0x846DF476, 0xDE9E4C60,
+ 0x84885257, 0xDE3D4963,
+ 0x84A2FC62, 0xDDDC5B3A,
+ 0x84BDF285, 0xDD7B8220,
+ 0x84D934B0, 0xDD1ABE51,
+ 0x84F4C2D3, 0xDCBA1008,
+ 0x85109CDC, 0xDC597781,
+ 0x852CC2BA, 0xDBF8F4F8,
+ 0x8549345C, 0xDB9888A8,
+ 0x8565F1B0, 0xDB3832CD,
+ 0x8582FAA4, 0xDAD7F3A2,
+ 0x85A04F28, 0xDA77CB62,
+ 0x85BDEF27, 0xDA17BA4A,
+ 0x85DBDA91, 0xD9B7C093,
+ 0x85FA1152, 0xD957DE7A,
+ 0x86189359, 0xD8F81439,
+ 0x86376092, 0xD898620C,
+ 0x865678EA, 0xD838C82D,
+ 0x8675DC4E, 0xD7D946D7,
+ 0x86958AAB, 0xD779DE46,
+ 0x86B583EE, 0xD71A8EB5,
+ 0x86D5C802, 0xD6BB585D,
+ 0x86F656D3, 0xD65C3B7B,
+ 0x8717304E, 0xD5FD3847,
+ 0x8738545E, 0xD59E4EFE,
+ 0x8759C2EF, 0xD53F7FDA,
+ 0x877B7BEC, 0xD4E0CB14,
+ 0x879D7F40, 0xD48230E8,
+ 0x87BFCCD7, 0xD423B190,
+ 0x87E2649B, 0xD3C54D46,
+ 0x88054677, 0xD3670445,
+ 0x88287255, 0xD308D6C6,
+ 0x884BE820, 0xD2AAC504,
+ 0x886FA7C2, 0xD24CCF38,
+ 0x8893B124, 0xD1EEF59E,
+ 0x88B80431, 0xD191386D,
+ 0x88DCA0D3, 0xD13397E1,
+ 0x890186F1, 0xD0D61433,
+ 0x8926B677, 0xD078AD9D,
+ 0x894C2F4C, 0xD01B6459,
+ 0x8971F15A, 0xCFBE389F,
+ 0x8997FC89, 0xCF612AAA,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x89E4EDEE, 0xCEA768F2,
+ 0x8A0BD3F5, 0xCE4AB5A2,
+ 0x8A3302BD, 0xCDEE20FC,
+ 0x8A5A7A30, 0xCD91AB38,
+ 0x8A823A35, 0xCD355490,
+ 0x8AAA42B4, 0xCCD91D3D,
+ 0x8AD29393, 0xCC7D0577,
+ 0x8AFB2CBA, 0xCC210D78,
+ 0x8B240E10, 0xCBC53578,
+ 0x8B4D377C, 0xCB697DB0,
+ 0x8B76A8E4, 0xCB0DE658,
+ 0x8BA0622F, 0xCAB26FA9,
+ 0x8BCA6342, 0xCA5719DB,
+ 0x8BF4AC05, 0xC9FBE527,
+ 0x8C1F3C5C, 0xC9A0D1C4,
+ 0x8C4A142F, 0xC945DFEC,
+ 0x8C753361, 0xC8EB0FD6,
+ 0x8CA099D9, 0xC89061BA,
+ 0x8CCC477D, 0xC835D5D0,
+ 0x8CF83C30, 0xC7DB6C50,
+ 0x8D2477D8, 0xC7812571,
+ 0x8D50FA59, 0xC727016C,
+ 0x8D7DC399, 0xC6CD0079,
+ 0x8DAAD37B, 0xC67322CD,
+ 0x8DD829E4, 0xC61968A2,
+ 0x8E05C6B7, 0xC5BFD22E,
+ 0x8E33A9D9, 0xC5665FA8,
+ 0x8E61D32D, 0xC50D1148,
+ 0x8E904298, 0xC4B3E746,
+ 0x8EBEF7FB, 0xC45AE1D7,
+ 0x8EEDF33B, 0xC4020132,
+ 0x8F1D343A, 0xC3A9458F,
+ 0x8F4CBADB, 0xC350AF25,
+ 0x8F7C8701, 0xC2F83E2A,
+ 0x8FAC988E, 0xC29FF2D4,
+ 0x8FDCEF66, 0xC247CD5A,
+ 0x900D8B69, 0xC1EFCDF2,
+ 0x903E6C7A, 0xC197F4D3,
+ 0x906F927B, 0xC1404233,
+ 0x90A0FD4E, 0xC0E8B648,
+ 0x90D2ACD3, 0xC0915147,
+ 0x9104A0ED, 0xC03A1368,
+ 0x9136D97D, 0xBFE2FCDF,
+ 0x91695663, 0xBF8C0DE2,
+ 0x919C1780, 0xBF3546A8,
+ 0x91CF1CB6, 0xBEDEA765,
+ 0x920265E4, 0xBE88304F,
+ 0x9235F2EB, 0xBE31E19B,
+ 0x9269C3AC, 0xBDDBBB7F,
+ 0x929DD805, 0xBD85BE2F,
+ 0x92D22FD8, 0xBD2FE9E1,
+ 0x9306CB04, 0xBCDA3ECA,
+ 0x933BA968, 0xBC84BD1E,
+ 0x9370CAE4, 0xBC2F6513,
+ 0x93A62F56, 0xBBDA36DC,
+ 0x93DBD69F, 0xBB8532AF,
+ 0x9411C09D, 0xBB3058C0,
+ 0x9447ED2F, 0xBADBA943,
+ 0x947E5C32, 0xBA87246C,
+ 0x94B50D87, 0xBA32CA70,
+ 0x94EC010B, 0xB9DE9B83,
+ 0x9523369B, 0xB98A97D8,
+ 0x955AAE17, 0xB936BFA3,
+ 0x9592675B, 0xB8E31319,
+ 0x95CA6246, 0xB88F926C,
+ 0x96029EB5, 0xB83C3DD1,
+ 0x963B1C85, 0xB7E9157A,
+ 0x9673DB94, 0xB796199B,
+ 0x96ACDBBD, 0xB7434A67,
+ 0x96E61CDF, 0xB6F0A811,
+ 0x971F9ED6, 0xB69E32CD,
+ 0x9759617E, 0xB64BEACC,
+ 0x979364B5, 0xB5F9D042,
+ 0x97CDA855, 0xB5A7E362,
+ 0x98082C3B, 0xB556245E,
+ 0x9842F043, 0xB5049368,
+ 0x987DF449, 0xB4B330B2,
+ 0x98B93828, 0xB461FC70,
+ 0x98F4BBBC, 0xB410F6D2,
+ 0x99307EE0, 0xB3C0200C,
+ 0x996C816F, 0xB36F784E,
+ 0x99A8C344, 0xB31EFFCB,
+ 0x99E5443A, 0xB2CEB6B5,
+ 0x9A22042C, 0xB27E9D3B,
+ 0x9A5F02F5, 0xB22EB392,
+ 0x9A9C406D, 0xB1DEF9E8,
+ 0x9AD9BC71, 0xB18F7070,
+ 0x9B1776D9, 0xB140175B,
+ 0x9B556F80, 0xB0F0EEDA,
+ 0x9B93A640, 0xB0A1F71C,
+ 0x9BD21AF2, 0xB0533055,
+ 0x9C10CD70, 0xB0049AB2,
+ 0x9C4FBD92, 0xAFB63667,
+ 0x9C8EEB33, 0xAF6803A1,
+ 0x9CCE562B, 0xAF1A0293,
+ 0x9D0DFE53, 0xAECC336B,
+ 0x9D4DE384, 0xAE7E965B,
+ 0x9D8E0596, 0xAE312B91,
+ 0x9DCE6462, 0xADE3F33E,
+ 0x9E0EFFC1, 0xAD96ED91,
+ 0x9E4FD789, 0xAD4A1ABA,
+ 0x9E90EB94, 0xACFD7AE8,
+ 0x9ED23BB9, 0xACB10E4A,
+ 0x9F13C7D0, 0xAC64D510,
+ 0x9F558FB0, 0xAC18CF68,
+ 0x9F979331, 0xABCCFD82,
+ 0x9FD9D22A, 0xAB815F8C,
+ 0xA01C4C72, 0xAB35F5B5,
+ 0xA05F01E1, 0xAAEAC02B,
+ 0xA0A1F24C, 0xAA9FBF1D,
+ 0xA0E51D8C, 0xAA54F2B9,
+ 0xA1288376, 0xAA0A5B2D,
+ 0xA16C23E1, 0xA9BFF8A8,
+ 0xA1AFFEA2, 0xA975CB56,
+ 0xA1F41391, 0xA92BD366,
+ 0xA2386283, 0xA8E21106,
+ 0xA27CEB4F, 0xA8988463,
+ 0xA2C1ADC9, 0xA84F2DA9,
+ 0xA306A9C7, 0xA8060D08,
+ 0xA34BDF20, 0xA7BD22AB,
+ 0xA3914DA7, 0xA7746EC0,
+ 0xA3D6F533, 0xA72BF173,
+ 0xA41CD598, 0xA6E3AAF2,
+ 0xA462EEAC, 0xA69B9B68,
+ 0xA4A94042, 0xA653C302,
+ 0xA4EFCA31, 0xA60C21ED,
+ 0xA5368C4B, 0xA5C4B855,
+ 0xA57D8666, 0xA57D8666,
+ 0xA5C4B855, 0xA5368C4B,
+ 0xA60C21ED, 0xA4EFCA31,
+ 0xA653C302, 0xA4A94042,
+ 0xA69B9B68, 0xA462EEAC,
+ 0xA6E3AAF2, 0xA41CD598,
+ 0xA72BF173, 0xA3D6F533,
+ 0xA7746EC0, 0xA3914DA7,
+ 0xA7BD22AB, 0xA34BDF20,
+ 0xA8060D08, 0xA306A9C7,
+ 0xA84F2DA9, 0xA2C1ADC9,
+ 0xA8988463, 0xA27CEB4F,
+ 0xA8E21106, 0xA2386283,
+ 0xA92BD366, 0xA1F41391,
+ 0xA975CB56, 0xA1AFFEA2,
+ 0xA9BFF8A8, 0xA16C23E1,
+ 0xAA0A5B2D, 0xA1288376,
+ 0xAA54F2B9, 0xA0E51D8C,
+ 0xAA9FBF1D, 0xA0A1F24C,
+ 0xAAEAC02B, 0xA05F01E1,
+ 0xAB35F5B5, 0xA01C4C72,
+ 0xAB815F8C, 0x9FD9D22A,
+ 0xABCCFD82, 0x9F979331,
+ 0xAC18CF68, 0x9F558FB0,
+ 0xAC64D510, 0x9F13C7D0,
+ 0xACB10E4A, 0x9ED23BB9,
+ 0xACFD7AE8, 0x9E90EB94,
+ 0xAD4A1ABA, 0x9E4FD789,
+ 0xAD96ED91, 0x9E0EFFC1,
+ 0xADE3F33E, 0x9DCE6462,
+ 0xAE312B91, 0x9D8E0596,
+ 0xAE7E965B, 0x9D4DE384,
+ 0xAECC336B, 0x9D0DFE53,
+ 0xAF1A0293, 0x9CCE562B,
+ 0xAF6803A1, 0x9C8EEB33,
+ 0xAFB63667, 0x9C4FBD92,
+ 0xB0049AB2, 0x9C10CD70,
+ 0xB0533055, 0x9BD21AF2,
+ 0xB0A1F71C, 0x9B93A640,
+ 0xB0F0EEDA, 0x9B556F80,
+ 0xB140175B, 0x9B1776D9,
+ 0xB18F7070, 0x9AD9BC71,
+ 0xB1DEF9E8, 0x9A9C406D,
+ 0xB22EB392, 0x9A5F02F5,
+ 0xB27E9D3B, 0x9A22042C,
+ 0xB2CEB6B5, 0x99E5443A,
+ 0xB31EFFCB, 0x99A8C344,
+ 0xB36F784E, 0x996C816F,
+ 0xB3C0200C, 0x99307EE0,
+ 0xB410F6D2, 0x98F4BBBC,
+ 0xB461FC70, 0x98B93828,
+ 0xB4B330B2, 0x987DF449,
+ 0xB5049368, 0x9842F043,
+ 0xB556245E, 0x98082C3B,
+ 0xB5A7E362, 0x97CDA855,
+ 0xB5F9D042, 0x979364B5,
+ 0xB64BEACC, 0x9759617E,
+ 0xB69E32CD, 0x971F9ED6,
+ 0xB6F0A811, 0x96E61CDF,
+ 0xB7434A67, 0x96ACDBBD,
+ 0xB796199B, 0x9673DB94,
+ 0xB7E9157A, 0x963B1C85,
+ 0xB83C3DD1, 0x96029EB5,
+ 0xB88F926C, 0x95CA6246,
+ 0xB8E31319, 0x9592675B,
+ 0xB936BFA3, 0x955AAE17,
+ 0xB98A97D8, 0x9523369B,
+ 0xB9DE9B83, 0x94EC010B,
+ 0xBA32CA70, 0x94B50D87,
+ 0xBA87246C, 0x947E5C32,
+ 0xBADBA943, 0x9447ED2F,
+ 0xBB3058C0, 0x9411C09D,
+ 0xBB8532AF, 0x93DBD69F,
+ 0xBBDA36DC, 0x93A62F56,
+ 0xBC2F6513, 0x9370CAE4,
+ 0xBC84BD1E, 0x933BA968,
+ 0xBCDA3ECA, 0x9306CB04,
+ 0xBD2FE9E1, 0x92D22FD8,
+ 0xBD85BE2F, 0x929DD805,
+ 0xBDDBBB7F, 0x9269C3AC,
+ 0xBE31E19B, 0x9235F2EB,
+ 0xBE88304F, 0x920265E4,
+ 0xBEDEA765, 0x91CF1CB6,
+ 0xBF3546A8, 0x919C1780,
+ 0xBF8C0DE2, 0x91695663,
+ 0xBFE2FCDF, 0x9136D97D,
+ 0xC03A1368, 0x9104A0ED,
+ 0xC0915147, 0x90D2ACD3,
+ 0xC0E8B648, 0x90A0FD4E,
+ 0xC1404233, 0x906F927B,
+ 0xC197F4D3, 0x903E6C7A,
+ 0xC1EFCDF2, 0x900D8B69,
+ 0xC247CD5A, 0x8FDCEF66,
+ 0xC29FF2D4, 0x8FAC988E,
+ 0xC2F83E2A, 0x8F7C8701,
+ 0xC350AF25, 0x8F4CBADB,
+ 0xC3A9458F, 0x8F1D343A,
+ 0xC4020132, 0x8EEDF33B,
+ 0xC45AE1D7, 0x8EBEF7FB,
+ 0xC4B3E746, 0x8E904298,
+ 0xC50D1148, 0x8E61D32D,
+ 0xC5665FA8, 0x8E33A9D9,
+ 0xC5BFD22E, 0x8E05C6B7,
+ 0xC61968A2, 0x8DD829E4,
+ 0xC67322CD, 0x8DAAD37B,
+ 0xC6CD0079, 0x8D7DC399,
+ 0xC727016C, 0x8D50FA59,
+ 0xC7812571, 0x8D2477D8,
+ 0xC7DB6C50, 0x8CF83C30,
+ 0xC835D5D0, 0x8CCC477D,
+ 0xC89061BA, 0x8CA099D9,
+ 0xC8EB0FD6, 0x8C753361,
+ 0xC945DFEC, 0x8C4A142F,
+ 0xC9A0D1C4, 0x8C1F3C5C,
+ 0xC9FBE527, 0x8BF4AC05,
+ 0xCA5719DB, 0x8BCA6342,
+ 0xCAB26FA9, 0x8BA0622F,
+ 0xCB0DE658, 0x8B76A8E4,
+ 0xCB697DB0, 0x8B4D377C,
+ 0xCBC53578, 0x8B240E10,
+ 0xCC210D78, 0x8AFB2CBA,
+ 0xCC7D0577, 0x8AD29393,
+ 0xCCD91D3D, 0x8AAA42B4,
+ 0xCD355490, 0x8A823A35,
+ 0xCD91AB38, 0x8A5A7A30,
+ 0xCDEE20FC, 0x8A3302BD,
+ 0xCE4AB5A2, 0x8A0BD3F5,
+ 0xCEA768F2, 0x89E4EDEE,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xCF612AAA, 0x8997FC89,
+ 0xCFBE389F, 0x8971F15A,
+ 0xD01B6459, 0x894C2F4C,
+ 0xD078AD9D, 0x8926B677,
+ 0xD0D61433, 0x890186F1,
+ 0xD13397E1, 0x88DCA0D3,
+ 0xD191386D, 0x88B80431,
+ 0xD1EEF59E, 0x8893B124,
+ 0xD24CCF38, 0x886FA7C2,
+ 0xD2AAC504, 0x884BE820,
+ 0xD308D6C6, 0x88287255,
+ 0xD3670445, 0x88054677,
+ 0xD3C54D46, 0x87E2649B,
+ 0xD423B190, 0x87BFCCD7,
+ 0xD48230E8, 0x879D7F40,
+ 0xD4E0CB14, 0x877B7BEC,
+ 0xD53F7FDA, 0x8759C2EF,
+ 0xD59E4EFE, 0x8738545E,
+ 0xD5FD3847, 0x8717304E,
+ 0xD65C3B7B, 0x86F656D3,
+ 0xD6BB585D, 0x86D5C802,
+ 0xD71A8EB5, 0x86B583EE,
+ 0xD779DE46, 0x86958AAB,
+ 0xD7D946D7, 0x8675DC4E,
+ 0xD838C82D, 0x865678EA,
+ 0xD898620C, 0x86376092,
+ 0xD8F81439, 0x86189359,
+ 0xD957DE7A, 0x85FA1152,
+ 0xD9B7C093, 0x85DBDA91,
+ 0xDA17BA4A, 0x85BDEF27,
+ 0xDA77CB62, 0x85A04F28,
+ 0xDAD7F3A2, 0x8582FAA4,
+ 0xDB3832CD, 0x8565F1B0,
+ 0xDB9888A8, 0x8549345C,
+ 0xDBF8F4F8, 0x852CC2BA,
+ 0xDC597781, 0x85109CDC,
+ 0xDCBA1008, 0x84F4C2D3,
+ 0xDD1ABE51, 0x84D934B0,
+ 0xDD7B8220, 0x84BDF285,
+ 0xDDDC5B3A, 0x84A2FC62,
+ 0xDE3D4963, 0x84885257,
+ 0xDE9E4C60, 0x846DF476,
+ 0xDEFF63F4, 0x8453E2CE,
+ 0xDF608FE3, 0x843A1D70,
+ 0xDFC1CFF2, 0x8420A46B,
+ 0xE02323E5, 0x840777CF,
+ 0xE0848B7F, 0x83EE97AC,
+ 0xE0E60684, 0x83D60411,
+ 0xE14794B9, 0x83BDBD0D,
+ 0xE1A935E1, 0x83A5C2B0,
+ 0xE20AE9C1, 0x838E1507,
+ 0xE26CB01A, 0x8376B422,
+ 0xE2CE88B2, 0x835FA00E,
+ 0xE330734C, 0x8348D8DB,
+ 0xE3926FAC, 0x83325E97,
+ 0xE3F47D95, 0x831C314E,
+ 0xE4569CCB, 0x8306510F,
+ 0xE4B8CD10, 0x82F0BDE8,
+ 0xE51B0E2A, 0x82DB77E5,
+ 0xE57D5FDA, 0x82C67F13,
+ 0xE5DFC1E4, 0x82B1D381,
+ 0xE642340D, 0x829D753A,
+ 0xE6A4B616, 0x8289644A,
+ 0xE70747C3, 0x8275A0C0,
+ 0xE769E8D8, 0x82622AA5,
+ 0xE7CC9917, 0x824F0208,
+ 0xE82F5844, 0x823C26F2,
+ 0xE8922621, 0x82299971,
+ 0xE8F50273, 0x8217598F,
+ 0xE957ECFB, 0x82056758,
+ 0xE9BAE57C, 0x81F3C2D7,
+ 0xEA1DEBBB, 0x81E26C16,
+ 0xEA80FF79, 0x81D16320,
+ 0xEAE4207A, 0x81C0A801,
+ 0xEB474E80, 0x81B03AC1,
+ 0xEBAA894E, 0x81A01B6C,
+ 0xEC0DD0A8, 0x81904A0C,
+ 0xEC71244F, 0x8180C6A9,
+ 0xECD48406, 0x8171914E,
+ 0xED37EF91, 0x8162AA03,
+ 0xED9B66B2, 0x815410D3,
+ 0xEDFEE92B, 0x8145C5C6,
+ 0xEE6276BF, 0x8137C8E6,
+ 0xEEC60F31, 0x812A1A39,
+ 0xEF29B243, 0x811CB9CA,
+ 0xEF8D5FB8, 0x810FA7A0,
+ 0xEFF11752, 0x8102E3C3,
+ 0xF054D8D4, 0x80F66E3C,
+ 0xF0B8A401, 0x80EA4712,
+ 0xF11C789A, 0x80DE6E4C,
+ 0xF1805662, 0x80D2E3F1,
+ 0xF1E43D1C, 0x80C7A80A,
+ 0xF2482C89, 0x80BCBA9C,
+ 0xF2AC246D, 0x80B21BAF,
+ 0xF310248A, 0x80A7CB49,
+ 0xF3742CA1, 0x809DC970,
+ 0xF3D83C76, 0x8094162B,
+ 0xF43C53CA, 0x808AB180,
+ 0xF4A07260, 0x80819B74,
+ 0xF50497FA, 0x8078D40D,
+ 0xF568C45A, 0x80705B50,
+ 0xF5CCF743, 0x80683143,
+ 0xF6313076, 0x806055EA,
+ 0xF6956FB6, 0x8058C94C,
+ 0xF6F9B4C5, 0x80518B6B,
+ 0xF75DFF65, 0x804A9C4D,
+ 0xF7C24F58, 0x8043FBF6,
+ 0xF826A461, 0x803DAA69,
+ 0xF88AFE41, 0x8037A7AC,
+ 0xF8EF5CBB, 0x8031F3C1,
+ 0xF953BF90, 0x802C8EAD,
+ 0xF9B82683, 0x80277872,
+ 0xFA1C9156, 0x8022B113,
+ 0xFA80FFCB, 0x801E3894,
+ 0xFAE571A4, 0x801A0EF7,
+ 0xFB49E6A2, 0x80163440,
+ 0xFBAE5E89, 0x8012A86F,
+ 0xFC12D919, 0x800F6B88,
+ 0xFC775616, 0x800C7D8C,
+ 0xFCDBD541, 0x8009DE7D,
+ 0xFD40565B, 0x80078E5E,
+ 0xFDA4D928, 0x80058D2E,
+ 0xFE095D69, 0x8003DAF0,
+ 0xFE6DE2E0, 0x800277A5,
+ 0xFED2694F, 0x8001634D,
+ 0xFF36F078, 0x80009DE9,
+ 0xFF9B781D, 0x8000277A
+};
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+const q31_t twiddleCoef_4096_q31[6144] =
+{
+ 0x7FFFFFFF, 0x00000000,
+ 0x7FFFF621, 0x003243F5,
+ 0x7FFFD885, 0x006487E3,
+ 0x7FFFA72C, 0x0096CBC1,
+ 0x7FFF6216, 0x00C90F88,
+ 0x7FFF0942, 0x00FB532F,
+ 0x7FFE9CB2, 0x012D96B0,
+ 0x7FFE1C64, 0x015FDA03,
+ 0x7FFD885A, 0x01921D1F,
+ 0x7FFCE093, 0x01C45FFE,
+ 0x7FFC250F, 0x01F6A296,
+ 0x7FFB55CE, 0x0228E4E1,
+ 0x7FFA72D1, 0x025B26D7,
+ 0x7FF97C17, 0x028D6870,
+ 0x7FF871A1, 0x02BFA9A4,
+ 0x7FF7536F, 0x02F1EA6B,
+ 0x7FF62182, 0x03242ABF,
+ 0x7FF4DBD8, 0x03566A96,
+ 0x7FF38273, 0x0388A9E9,
+ 0x7FF21553, 0x03BAE8B1,
+ 0x7FF09477, 0x03ED26E6,
+ 0x7FEEFFE1, 0x041F647F,
+ 0x7FED5790, 0x0451A176,
+ 0x7FEB9B85, 0x0483DDC3,
+ 0x7FE9CBC0, 0x04B6195D,
+ 0x7FE7E840, 0x04E8543D,
+ 0x7FE5F108, 0x051A8E5C,
+ 0x7FE3E616, 0x054CC7B0,
+ 0x7FE1C76B, 0x057F0034,
+ 0x7FDF9508, 0x05B137DF,
+ 0x7FDD4EEC, 0x05E36EA9,
+ 0x7FDAF518, 0x0615A48A,
+ 0x7FD8878D, 0x0647D97C,
+ 0x7FD6064B, 0x067A0D75,
+ 0x7FD37152, 0x06AC406F,
+ 0x7FD0C8A3, 0x06DE7261,
+ 0x7FCE0C3E, 0x0710A344,
+ 0x7FCB3C23, 0x0742D310,
+ 0x7FC85853, 0x077501BE,
+ 0x7FC560CF, 0x07A72F45,
+ 0x7FC25596, 0x07D95B9E,
+ 0x7FBF36A9, 0x080B86C1,
+ 0x7FBC040A, 0x083DB0A7,
+ 0x7FB8BDB7, 0x086FD947,
+ 0x7FB563B2, 0x08A2009A,
+ 0x7FB1F5FC, 0x08D42698,
+ 0x7FAE7494, 0x09064B3A,
+ 0x7FAADF7C, 0x09386E77,
+ 0x7FA736B4, 0x096A9049,
+ 0x7FA37A3C, 0x099CB0A7,
+ 0x7F9FAA15, 0x09CECF89,
+ 0x7F9BC63F, 0x0A00ECE8,
+ 0x7F97CEBC, 0x0A3308BC,
+ 0x7F93C38C, 0x0A6522FE,
+ 0x7F8FA4AF, 0x0A973BA5,
+ 0x7F8B7226, 0x0AC952AA,
+ 0x7F872BF3, 0x0AFB6805,
+ 0x7F82D214, 0x0B2D7BAE,
+ 0x7F7E648B, 0x0B5F8D9F,
+ 0x7F79E35A, 0x0B919DCE,
+ 0x7F754E7F, 0x0BC3AC35,
+ 0x7F70A5FD, 0x0BF5B8CB,
+ 0x7F6BE9D4, 0x0C27C389,
+ 0x7F671A04, 0x0C59CC67,
+ 0x7F62368F, 0x0C8BD35E,
+ 0x7F5D3F75, 0x0CBDD865,
+ 0x7F5834B6, 0x0CEFDB75,
+ 0x7F531654, 0x0D21DC87,
+ 0x7F4DE450, 0x0D53DB92,
+ 0x7F489EAA, 0x0D85D88F,
+ 0x7F434563, 0x0DB7D376,
+ 0x7F3DD87C, 0x0DE9CC3F,
+ 0x7F3857F5, 0x0E1BC2E3,
+ 0x7F32C3D0, 0x0E4DB75B,
+ 0x7F2D1C0E, 0x0E7FA99D,
+ 0x7F2760AF, 0x0EB199A3,
+ 0x7F2191B4, 0x0EE38765,
+ 0x7F1BAF1E, 0x0F1572DC,
+ 0x7F15B8EE, 0x0F475BFE,
+ 0x7F0FAF24, 0x0F7942C6,
+ 0x7F0991C3, 0x0FAB272B,
+ 0x7F0360CB, 0x0FDD0925,
+ 0x7EFD1C3C, 0x100EE8AD,
+ 0x7EF6C418, 0x1040C5BB,
+ 0x7EF0585F, 0x1072A047,
+ 0x7EE9D913, 0x10A4784A,
+ 0x7EE34635, 0x10D64DBC,
+ 0x7EDC9FC6, 0x11082096,
+ 0x7ED5E5C6, 0x1139F0CE,
+ 0x7ECF1837, 0x116BBE5F,
+ 0x7EC8371A, 0x119D8940,
+ 0x7EC1426F, 0x11CF516A,
+ 0x7EBA3A39, 0x120116D4,
+ 0x7EB31E77, 0x1232D978,
+ 0x7EABEF2C, 0x1264994E,
+ 0x7EA4AC58, 0x1296564D,
+ 0x7E9D55FC, 0x12C8106E,
+ 0x7E95EC19, 0x12F9C7AA,
+ 0x7E8E6EB1, 0x132B7BF9,
+ 0x7E86DDC5, 0x135D2D53,
+ 0x7E7F3956, 0x138EDBB0,
+ 0x7E778165, 0x13C0870A,
+ 0x7E6FB5F3, 0x13F22F57,
+ 0x7E67D702, 0x1423D492,
+ 0x7E5FE493, 0x145576B1,
+ 0x7E57DEA6, 0x148715AD,
+ 0x7E4FC53E, 0x14B8B17F,
+ 0x7E47985B, 0x14EA4A1F,
+ 0x7E3F57FE, 0x151BDF85,
+ 0x7E37042A, 0x154D71AA,
+ 0x7E2E9CDF, 0x157F0086,
+ 0x7E26221E, 0x15B08C11,
+ 0x7E1D93E9, 0x15E21444,
+ 0x7E14F242, 0x16139917,
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+ 0x0AC952AA, 0x7F8B7226,
+ 0x0A973BA5, 0x7F8FA4AF,
+ 0x0A6522FE, 0x7F93C38C,
+ 0x0A3308BC, 0x7F97CEBC,
+ 0x0A00ECE8, 0x7F9BC63F,
+ 0x09CECF89, 0x7F9FAA15,
+ 0x099CB0A7, 0x7FA37A3C,
+ 0x096A9049, 0x7FA736B4,
+ 0x09386E77, 0x7FAADF7C,
+ 0x09064B3A, 0x7FAE7494,
+ 0x08D42698, 0x7FB1F5FC,
+ 0x08A2009A, 0x7FB563B2,
+ 0x086FD947, 0x7FB8BDB7,
+ 0x083DB0A7, 0x7FBC040A,
+ 0x080B86C1, 0x7FBF36A9,
+ 0x07D95B9E, 0x7FC25596,
+ 0x07A72F45, 0x7FC560CF,
+ 0x077501BE, 0x7FC85853,
+ 0x0742D310, 0x7FCB3C23,
+ 0x0710A344, 0x7FCE0C3E,
+ 0x06DE7261, 0x7FD0C8A3,
+ 0x06AC406F, 0x7FD37152,
+ 0x067A0D75, 0x7FD6064B,
+ 0x0647D97C, 0x7FD8878D,
+ 0x0615A48A, 0x7FDAF518,
+ 0x05E36EA9, 0x7FDD4EEC,
+ 0x05B137DF, 0x7FDF9508,
+ 0x057F0034, 0x7FE1C76B,
+ 0x054CC7B0, 0x7FE3E616,
+ 0x051A8E5C, 0x7FE5F108,
+ 0x04E8543D, 0x7FE7E840,
+ 0x04B6195D, 0x7FE9CBC0,
+ 0x0483DDC3, 0x7FEB9B85,
+ 0x0451A176, 0x7FED5790,
+ 0x041F647F, 0x7FEEFFE1,
+ 0x03ED26E6, 0x7FF09477,
+ 0x03BAE8B1, 0x7FF21553,
+ 0x0388A9E9, 0x7FF38273,
+ 0x03566A96, 0x7FF4DBD8,
+ 0x03242ABF, 0x7FF62182,
+ 0x02F1EA6B, 0x7FF7536F,
+ 0x02BFA9A4, 0x7FF871A1,
+ 0x028D6870, 0x7FF97C17,
+ 0x025B26D7, 0x7FFA72D1,
+ 0x0228E4E1, 0x7FFB55CE,
+ 0x01F6A296, 0x7FFC250F,
+ 0x01C45FFE, 0x7FFCE093,
+ 0x01921D1F, 0x7FFD885A,
+ 0x015FDA03, 0x7FFE1C64,
+ 0x012D96B0, 0x7FFE9CB2,
+ 0x00FB532F, 0x7FFF0942,
+ 0x00C90F88, 0x7FFF6216,
+ 0x0096CBC1, 0x7FFFA72C,
+ 0x006487E3, 0x7FFFD885,
+ 0x003243F5, 0x7FFFF621,
+ 0x00000000, 0x7FFFFFFF,
+ 0xFFCDBC0A, 0x7FFFF621,
+ 0xFF9B781D, 0x7FFFD885,
+ 0xFF69343E, 0x7FFFA72C,
+ 0xFF36F078, 0x7FFF6216,
+ 0xFF04ACD0, 0x7FFF0942,
+ 0xFED2694F, 0x7FFE9CB2,
+ 0xFEA025FC, 0x7FFE1C64,
+ 0xFE6DE2E0, 0x7FFD885A,
+ 0xFE3BA001, 0x7FFCE093,
+ 0xFE095D69, 0x7FFC250F,
+ 0xFDD71B1E, 0x7FFB55CE,
+ 0xFDA4D928, 0x7FFA72D1,
+ 0xFD72978F, 0x7FF97C17,
+ 0xFD40565B, 0x7FF871A1,
+ 0xFD0E1594, 0x7FF7536F,
+ 0xFCDBD541, 0x7FF62182,
+ 0xFCA99569, 0x7FF4DBD8,
+ 0xFC775616, 0x7FF38273,
+ 0xFC45174E, 0x7FF21553,
+ 0xFC12D919, 0x7FF09477,
+ 0xFBE09B80, 0x7FEEFFE1,
+ 0xFBAE5E89, 0x7FED5790,
+ 0xFB7C223C, 0x7FEB9B85,
+ 0xFB49E6A2, 0x7FE9CBC0,
+ 0xFB17ABC2, 0x7FE7E840,
+ 0xFAE571A4, 0x7FE5F108,
+ 0xFAB3384F, 0x7FE3E616,
+ 0xFA80FFCB, 0x7FE1C76B,
+ 0xFA4EC820, 0x7FDF9508,
+ 0xFA1C9156, 0x7FDD4EEC,
+ 0xF9EA5B75, 0x7FDAF518,
+ 0xF9B82683, 0x7FD8878D,
+ 0xF985F28A, 0x7FD6064B,
+ 0xF953BF90, 0x7FD37152,
+ 0xF9218D9E, 0x7FD0C8A3,
+ 0xF8EF5CBB, 0x7FCE0C3E,
+ 0xF8BD2CEF, 0x7FCB3C23,
+ 0xF88AFE41, 0x7FC85853,
+ 0xF858D0BA, 0x7FC560CF,
+ 0xF826A461, 0x7FC25596,
+ 0xF7F4793E, 0x7FBF36A9,
+ 0xF7C24F58, 0x7FBC040A,
+ 0xF79026B8, 0x7FB8BDB7,
+ 0xF75DFF65, 0x7FB563B2,
+ 0xF72BD967, 0x7FB1F5FC,
+ 0xF6F9B4C5, 0x7FAE7494,
+ 0xF6C79188, 0x7FAADF7C,
+ 0xF6956FB6, 0x7FA736B4,
+ 0xF6634F58, 0x7FA37A3C,
+ 0xF6313076, 0x7F9FAA15,
+ 0xF5FF1317, 0x7F9BC63F,
+ 0xF5CCF743, 0x7F97CEBC,
+ 0xF59ADD01, 0x7F93C38C,
+ 0xF568C45A, 0x7F8FA4AF,
+ 0xF536AD55, 0x7F8B7226,
+ 0xF50497FA, 0x7F872BF3,
+ 0xF4D28451, 0x7F82D214,
+ 0xF4A07260, 0x7F7E648B,
+ 0xF46E6231, 0x7F79E35A,
+ 0xF43C53CA, 0x7F754E7F,
+ 0xF40A4734, 0x7F70A5FD,
+ 0xF3D83C76, 0x7F6BE9D4,
+ 0xF3A63398, 0x7F671A04,
+ 0xF3742CA1, 0x7F62368F,
+ 0xF342279A, 0x7F5D3F75,
+ 0xF310248A, 0x7F5834B6,
+ 0xF2DE2378, 0x7F531654,
+ 0xF2AC246D, 0x7F4DE450,
+ 0xF27A2770, 0x7F489EAA,
+ 0xF2482C89, 0x7F434563,
+ 0xF21633C0, 0x7F3DD87C,
+ 0xF1E43D1C, 0x7F3857F5,
+ 0xF1B248A5, 0x7F32C3D0,
+ 0xF1805662, 0x7F2D1C0E,
+ 0xF14E665C, 0x7F2760AF,
+ 0xF11C789A, 0x7F2191B4,
+ 0xF0EA8D23, 0x7F1BAF1E,
+ 0xF0B8A401, 0x7F15B8EE,
+ 0xF086BD39, 0x7F0FAF24,
+ 0xF054D8D4, 0x7F0991C3,
+ 0xF022F6DA, 0x7F0360CB,
+ 0xEFF11752, 0x7EFD1C3C,
+ 0xEFBF3A44, 0x7EF6C418,
+ 0xEF8D5FB8, 0x7EF0585F,
+ 0xEF5B87B5, 0x7EE9D913,
+ 0xEF29B243, 0x7EE34635,
+ 0xEEF7DF6A, 0x7EDC9FC6,
+ 0xEEC60F31, 0x7ED5E5C6,
+ 0xEE9441A0, 0x7ECF1837,
+ 0xEE6276BF, 0x7EC8371A,
+ 0xEE30AE95, 0x7EC1426F,
+ 0xEDFEE92B, 0x7EBA3A39,
+ 0xEDCD2687, 0x7EB31E77,
+ 0xED9B66B2, 0x7EABEF2C,
+ 0xED69A9B2, 0x7EA4AC58,
+ 0xED37EF91, 0x7E9D55FC,
+ 0xED063855, 0x7E95EC19,
+ 0xECD48406, 0x7E8E6EB1,
+ 0xECA2D2AC, 0x7E86DDC5,
+ 0xEC71244F, 0x7E7F3956,
+ 0xEC3F78F5, 0x7E778165,
+ 0xEC0DD0A8, 0x7E6FB5F3,
+ 0xEBDC2B6D, 0x7E67D702,
+ 0xEBAA894E, 0x7E5FE493,
+ 0xEB78EA52, 0x7E57DEA6,
+ 0xEB474E80, 0x7E4FC53E,
+ 0xEB15B5E0, 0x7E47985B,
+ 0xEAE4207A, 0x7E3F57FE,
+ 0xEAB28E55, 0x7E37042A,
+ 0xEA80FF79, 0x7E2E9CDF,
+ 0xEA4F73EE, 0x7E26221E,
+ 0xEA1DEBBB, 0x7E1D93E9,
+ 0xE9EC66E8, 0x7E14F242,
+ 0xE9BAE57C, 0x7E0C3D29,
+ 0xE9896780, 0x7E03749F,
+ 0xE957ECFB, 0x7DFA98A7,
+ 0xE92675F4, 0x7DF1A942,
+ 0xE8F50273, 0x7DE8A670,
+ 0xE8C3927F, 0x7DDF9034,
+ 0xE8922621, 0x7DD6668E,
+ 0xE860BD60, 0x7DCD2981,
+ 0xE82F5844, 0x7DC3D90D,
+ 0xE7FDF6D3, 0x7DBA7534,
+ 0xE7CC9917, 0x7DB0FDF7,
+ 0xE79B3F16, 0x7DA77359,
+ 0xE769E8D8, 0x7D9DD55A,
+ 0xE7389664, 0x7D9423FB,
+ 0xE70747C3, 0x7D8A5F3F,
+ 0xE6D5FCFC, 0x7D808727,
+ 0xE6A4B616, 0x7D769BB5,
+ 0xE6737319, 0x7D6C9CE9,
+ 0xE642340D, 0x7D628AC5,
+ 0xE610F8F9, 0x7D58654C,
+ 0xE5DFC1E4, 0x7D4E2C7E,
+ 0xE5AE8ED8, 0x7D43E05E,
+ 0xE57D5FDA, 0x7D3980EC,
+ 0xE54C34F3, 0x7D2F0E2A,
+ 0xE51B0E2A, 0x7D24881A,
+ 0xE4E9EB86, 0x7D19EEBE,
+ 0xE4B8CD10, 0x7D0F4218,
+ 0xE487B2CF, 0x7D048228,
+ 0xE4569CCB, 0x7CF9AEF0,
+ 0xE4258B0A, 0x7CEEC873,
+ 0xE3F47D95, 0x7CE3CEB1,
+ 0xE3C37473, 0x7CD8C1AD,
+ 0xE3926FAC, 0x7CCDA168,
+ 0xE3616F47, 0x7CC26DE5,
+ 0xE330734C, 0x7CB72724,
+ 0xE2FF7BC3, 0x7CABCD27,
+ 0xE2CE88B2, 0x7CA05FF1,
+ 0xE29D9A22, 0x7C94DF82,
+ 0xE26CB01A, 0x7C894BDD,
+ 0xE23BCAA2, 0x7C7DA504,
+ 0xE20AE9C1, 0x7C71EAF8,
+ 0xE1DA0D7E, 0x7C661DBB,
+ 0xE1A935E1, 0x7C5A3D4F,
+ 0xE17862F3, 0x7C4E49B6,
+ 0xE14794B9, 0x7C4242F2,
+ 0xE116CB3D, 0x7C362904,
+ 0xE0E60684, 0x7C29FBEE,
+ 0xE0B54698, 0x7C1DBBB2,
+ 0xE0848B7F, 0x7C116853,
+ 0xE053D541, 0x7C0501D1,
+ 0xE02323E5, 0x7BF88830,
+ 0xDFF27773, 0x7BEBFB70,
+ 0xDFC1CFF2, 0x7BDF5B94,
+ 0xDF912D6A, 0x7BD2A89E,
+ 0xDF608FE3, 0x7BC5E28F,
+ 0xDF2FF764, 0x7BB9096A,
+ 0xDEFF63F4, 0x7BAC1D31,
+ 0xDECED59B, 0x7B9F1DE5,
+ 0xDE9E4C60, 0x7B920B89,
+ 0xDE6DC84B, 0x7B84E61E,
+ 0xDE3D4963, 0x7B77ADA8,
+ 0xDE0CCFB1, 0x7B6A6227,
+ 0xDDDC5B3A, 0x7B5D039D,
+ 0xDDABEC07, 0x7B4F920E,
+ 0xDD7B8220, 0x7B420D7A,
+ 0xDD4B1D8B, 0x7B3475E4,
+ 0xDD1ABE51, 0x7B26CB4F,
+ 0xDCEA6478, 0x7B190DBB,
+ 0xDCBA1008, 0x7B0B3D2C,
+ 0xDC89C108, 0x7AFD59A3,
+ 0xDC597781, 0x7AEF6323,
+ 0xDC293379, 0x7AE159AE,
+ 0xDBF8F4F8, 0x7AD33D45,
+ 0xDBC8BC05, 0x7AC50DEB,
+ 0xDB9888A8, 0x7AB6CBA3,
+ 0xDB685AE8, 0x7AA8766E,
+ 0xDB3832CD, 0x7A9A0E4F,
+ 0xDB08105E, 0x7A8B9348,
+ 0xDAD7F3A2, 0x7A7D055B,
+ 0xDAA7DCA1, 0x7A6E648A,
+ 0xDA77CB62, 0x7A5FB0D8,
+ 0xDA47BFED, 0x7A50EA46,
+ 0xDA17BA4A, 0x7A4210D8,
+ 0xD9E7BA7E, 0x7A33248F,
+ 0xD9B7C093, 0x7A24256E,
+ 0xD987CC8F, 0x7A151377,
+ 0xD957DE7A, 0x7A05EEAD,
+ 0xD927F65B, 0x79F6B711,
+ 0xD8F81439, 0x79E76CA6,
+ 0xD8C8381C, 0x79D80F6F,
+ 0xD898620C, 0x79C89F6D,
+ 0xD868920F, 0x79B91CA4,
+ 0xD838C82D, 0x79A98715,
+ 0xD809046D, 0x7999DEC3,
+ 0xD7D946D7, 0x798A23B1,
+ 0xD7A98F73, 0x797A55E0,
+ 0xD779DE46, 0x796A7554,
+ 0xD74A335A, 0x795A820E,
+ 0xD71A8EB5, 0x794A7C11,
+ 0xD6EAF05E, 0x793A6360,
+ 0xD6BB585D, 0x792A37FE,
+ 0xD68BC6BA, 0x7919F9EB,
+ 0xD65C3B7B, 0x7909A92C,
+ 0xD62CB6A7, 0x78F945C3,
+ 0xD5FD3847, 0x78E8CFB1,
+ 0xD5CDC062, 0x78D846FB,
+ 0xD59E4EFE, 0x78C7ABA1,
+ 0xD56EE424, 0x78B6FDA8,
+ 0xD53F7FDA, 0x78A63D10,
+ 0xD5102227, 0x789569DE,
+ 0xD4E0CB14, 0x78848413,
+ 0xD4B17AA7, 0x78738BB3,
+ 0xD48230E8, 0x786280BF,
+ 0xD452EDDE, 0x7851633B,
+ 0xD423B190, 0x78403328,
+ 0xD3F47C06, 0x782EF08B,
+ 0xD3C54D46, 0x781D9B64,
+ 0xD3962559, 0x780C33B8,
+ 0xD3670445, 0x77FAB988,
+ 0xD337EA12, 0x77E92CD8,
+ 0xD308D6C6, 0x77D78DAA,
+ 0xD2D9CA6A, 0x77C5DC01,
+ 0xD2AAC504, 0x77B417DF,
+ 0xD27BC69C, 0x77A24148,
+ 0xD24CCF38, 0x7790583D,
+ 0xD21DDEE1, 0x777E5CC3,
+ 0xD1EEF59E, 0x776C4EDB,
+ 0xD1C01374, 0x775A2E88,
+ 0xD191386D, 0x7747FBCE,
+ 0xD162648F, 0x7735B6AE,
+ 0xD13397E1, 0x77235F2D,
+ 0xD104D26B, 0x7710F54B,
+ 0xD0D61433, 0x76FE790E,
+ 0xD0A75D42, 0x76EBEA77,
+ 0xD078AD9D, 0x76D94988,
+ 0xD04A054D, 0x76C69646,
+ 0xD01B6459, 0x76B3D0B3,
+ 0xCFECCAC7, 0x76A0F8D2,
+ 0xCFBE389F, 0x768E0EA5,
+ 0xCF8FADE8, 0x767B1230,
+ 0xCF612AAA, 0x76680376,
+ 0xCF32AEEB, 0x7654E279,
+ 0xCF043AB2, 0x7641AF3C,
+ 0xCED5CE08, 0x762E69C3,
+ 0xCEA768F2, 0x761B1211,
+ 0xCE790B78, 0x7607A827,
+ 0xCE4AB5A2, 0x75F42C0A,
+ 0xCE1C6776, 0x75E09DBD,
+ 0xCDEE20FC, 0x75CCFD42,
+ 0xCDBFE23A, 0x75B94A9C,
+ 0xCD91AB38, 0x75A585CF,
+ 0xCD637BFD, 0x7591AEDD,
+ 0xCD355490, 0x757DC5CA,
+ 0xCD0734F8, 0x7569CA98,
+ 0xCCD91D3D, 0x7555BD4B,
+ 0xCCAB0D65, 0x75419DE6,
+ 0xCC7D0577, 0x752D6C6C,
+ 0xCC4F057B, 0x751928E0,
+ 0xCC210D78, 0x7504D345,
+ 0xCBF31D75, 0x74F06B9E,
+ 0xCBC53578, 0x74DBF1EF,
+ 0xCB975589, 0x74C7663A,
+ 0xCB697DB0, 0x74B2C883,
+ 0xCB3BADF2, 0x749E18CD,
+ 0xCB0DE658, 0x7489571B,
+ 0xCAE026E8, 0x74748371,
+ 0xCAB26FA9, 0x745F9DD1,
+ 0xCA84C0A2, 0x744AA63E,
+ 0xCA5719DB, 0x74359CBD,
+ 0xCA297B5A, 0x74208150,
+ 0xC9FBE527, 0x740B53FA,
+ 0xC9CE5748, 0x73F614C0,
+ 0xC9A0D1C4, 0x73E0C3A3,
+ 0xC97354A3, 0x73CB60A7,
+ 0xC945DFEC, 0x73B5EBD0,
+ 0xC91873A5, 0x73A06522,
+ 0xC8EB0FD6, 0x738ACC9E,
+ 0xC8BDB485, 0x73752249,
+ 0xC89061BA, 0x735F6626,
+ 0xC863177B, 0x73499838,
+ 0xC835D5D0, 0x7333B883,
+ 0xC8089CBF, 0x731DC709,
+ 0xC7DB6C50, 0x7307C3D0,
+ 0xC7AE4489, 0x72F1AED8,
+ 0xC7812571, 0x72DB8828,
+ 0xC7540F10, 0x72C54FC0,
+ 0xC727016C, 0x72AF05A6,
+ 0xC6F9FC8D, 0x7298A9DC,
+ 0xC6CD0079, 0x72823C66,
+ 0xC6A00D36, 0x726BBD48,
+ 0xC67322CD, 0x72552C84,
+ 0xC6464144, 0x723E8A1F,
+ 0xC61968A2, 0x7227D61C,
+ 0xC5EC98ED, 0x7211107D,
+ 0xC5BFD22E, 0x71FA3948,
+ 0xC593146A, 0x71E3507F,
+ 0xC5665FA8, 0x71CC5626,
+ 0xC539B3F0, 0x71B54A40,
+ 0xC50D1148, 0x719E2CD2,
+ 0xC4E077B8, 0x7186FDDE,
+ 0xC4B3E746, 0x716FBD68,
+ 0xC4875FF8, 0x71586B73,
+ 0xC45AE1D7, 0x71410804,
+ 0xC42E6CE8, 0x7129931E,
+ 0xC4020132, 0x71120CC5,
+ 0xC3D59EBD, 0x70FA74FB,
+ 0xC3A9458F, 0x70E2CBC6,
+ 0xC37CF5B0, 0x70CB1127,
+ 0xC350AF25, 0x70B34524,
+ 0xC32471F6, 0x709B67C0,
+ 0xC2F83E2A, 0x708378FE,
+ 0xC2CC13C7, 0x706B78E3,
+ 0xC29FF2D4, 0x70536771,
+ 0xC273DB58, 0x703B44AC,
+ 0xC247CD5A, 0x70231099,
+ 0xC21BC8E0, 0x700ACB3B,
+ 0xC1EFCDF2, 0x6FF27496,
+ 0xC1C3DC96, 0x6FDA0CAD,
+ 0xC197F4D3, 0x6FC19385,
+ 0xC16C16B0, 0x6FA90920,
+ 0xC1404233, 0x6F906D84,
+ 0xC1147763, 0x6F77C0B3,
+ 0xC0E8B648, 0x6F5F02B1,
+ 0xC0BCFEE7, 0x6F463383,
+ 0xC0915147, 0x6F2D532C,
+ 0xC065AD70, 0x6F1461AF,
+ 0xC03A1368, 0x6EFB5F12,
+ 0xC00E8335, 0x6EE24B57,
+ 0xBFE2FCDF, 0x6EC92682,
+ 0xBFB7806C, 0x6EAFF098,
+ 0xBF8C0DE2, 0x6E96A99C,
+ 0xBF60A54A, 0x6E7D5193,
+ 0xBF3546A8, 0x6E63E87F,
+ 0xBF09F204, 0x6E4A6E65,
+ 0xBEDEA765, 0x6E30E349,
+ 0xBEB366D1, 0x6E17472F,
+ 0xBE88304F, 0x6DFD9A1B,
+ 0xBE5D03E5, 0x6DE3DC11,
+ 0xBE31E19B, 0x6DCA0D14,
+ 0xBE06C977, 0x6DB02D29,
+ 0xBDDBBB7F, 0x6D963C54,
+ 0xBDB0B7BA, 0x6D7C3A98,
+ 0xBD85BE2F, 0x6D6227FA,
+ 0xBD5ACEE5, 0x6D48047E,
+ 0xBD2FE9E1, 0x6D2DD027,
+ 0xBD050F2C, 0x6D138AFA,
+ 0xBCDA3ECA, 0x6CF934FB,
+ 0xBCAF78C3, 0x6CDECE2E,
+ 0xBC84BD1E, 0x6CC45697,
+ 0xBC5A0BE1, 0x6CA9CE3A,
+ 0xBC2F6513, 0x6C8F351C,
+ 0xBC04C8BA, 0x6C748B3F,
+ 0xBBDA36DC, 0x6C59D0A9,
+ 0xBBAFAF81, 0x6C3F055D,
+ 0xBB8532AF, 0x6C242960,
+ 0xBB5AC06C, 0x6C093CB6,
+ 0xBB3058C0, 0x6BEE3F62,
+ 0xBB05FBB0, 0x6BD3316A,
+ 0xBADBA943, 0x6BB812D0,
+ 0xBAB1617F, 0x6B9CE39B,
+ 0xBA87246C, 0x6B81A3CD,
+ 0xBA5CF210, 0x6B66536A,
+ 0xBA32CA70, 0x6B4AF278,
+ 0xBA08AD94, 0x6B2F80FA,
+ 0xB9DE9B83, 0x6B13FEF5,
+ 0xB9B49442, 0x6AF86C6C,
+ 0xB98A97D8, 0x6ADCC964,
+ 0xB960A64B, 0x6AC115E1,
+ 0xB936BFA3, 0x6AA551E8,
+ 0xB90CE3E6, 0x6A897D7D,
+ 0xB8E31319, 0x6A6D98A4,
+ 0xB8B94D44, 0x6A51A361,
+ 0xB88F926C, 0x6A359DB9,
+ 0xB865E299, 0x6A1987B0,
+ 0xB83C3DD1, 0x69FD614A,
+ 0xB812A419, 0x69E12A8C,
+ 0xB7E9157A, 0x69C4E37A,
+ 0xB7BF91F8, 0x69A88C18,
+ 0xB796199B, 0x698C246C,
+ 0xB76CAC68, 0x696FAC78,
+ 0xB7434A67, 0x69532442,
+ 0xB719F39D, 0x69368BCE,
+ 0xB6F0A811, 0x6919E320,
+ 0xB6C767CA, 0x68FD2A3D,
+ 0xB69E32CD, 0x68E06129,
+ 0xB6750921, 0x68C387E9,
+ 0xB64BEACC, 0x68A69E81,
+ 0xB622D7D5, 0x6889A4F5,
+ 0xB5F9D042, 0x686C9B4B,
+ 0xB5D0D41A, 0x684F8186,
+ 0xB5A7E362, 0x683257AA,
+ 0xB57EFE21, 0x68151DBE,
+ 0xB556245E, 0x67F7D3C4,
+ 0xB52D561E, 0x67DA79C2,
+ 0xB5049368, 0x67BD0FBC,
+ 0xB4DBDC42, 0x679F95B7,
+ 0xB4B330B2, 0x67820BB6,
+ 0xB48A90C0, 0x676471C0,
+ 0xB461FC70, 0x6746C7D7,
+ 0xB43973C9, 0x67290E02,
+ 0xB410F6D2, 0x670B4443,
+ 0xB3E88591, 0x66ED6AA1,
+ 0xB3C0200C, 0x66CF811F,
+ 0xB397C649, 0x66B187C3,
+ 0xB36F784E, 0x66937E90,
+ 0xB3473622, 0x6675658C,
+ 0xB31EFFCB, 0x66573CBB,
+ 0xB2F6D54F, 0x66390422,
+ 0xB2CEB6B5, 0x661ABBC5,
+ 0xB2A6A401, 0x65FC63A9,
+ 0xB27E9D3B, 0x65DDFBD3,
+ 0xB256A26A, 0x65BF8447,
+ 0xB22EB392, 0x65A0FD0B,
+ 0xB206D0BA, 0x65826622,
+ 0xB1DEF9E8, 0x6563BF92,
+ 0xB1B72F23, 0x6545095F,
+ 0xB18F7070, 0x6526438E,
+ 0xB167BDD6, 0x65076E24,
+ 0xB140175B, 0x64E88926,
+ 0xB1187D05, 0x64C99498,
+ 0xB0F0EEDA, 0x64AA907F,
+ 0xB0C96CDF, 0x648B7CDF,
+ 0xB0A1F71C, 0x646C59BF,
+ 0xB07A8D97, 0x644D2722,
+ 0xB0533055, 0x642DE50D,
+ 0xB02BDF5C, 0x640E9385,
+ 0xB0049AB2, 0x63EF328F,
+ 0xAFDD625F, 0x63CFC230,
+ 0xAFB63667, 0x63B0426D,
+ 0xAF8F16D0, 0x6390B34A,
+ 0xAF6803A1, 0x637114CC,
+ 0xAF40FCE0, 0x635166F8,
+ 0xAF1A0293, 0x6331A9D4,
+ 0xAEF314BF, 0x6311DD63,
+ 0xAECC336B, 0x62F201AC,
+ 0xAEA55E9D, 0x62D216B2,
+ 0xAE7E965B, 0x62B21C7B,
+ 0xAE57DAAA, 0x6292130C,
+ 0xAE312B91, 0x6271FA69,
+ 0xAE0A8916, 0x6251D297,
+ 0xADE3F33E, 0x62319B9D,
+ 0xADBD6A10, 0x6211557D,
+ 0xAD96ED91, 0x61F1003E,
+ 0xAD707DC8, 0x61D09BE5,
+ 0xAD4A1ABA, 0x61B02876,
+ 0xAD23C46D, 0x618FA5F6,
+ 0xACFD7AE8, 0x616F146B,
+ 0xACD73E30, 0x614E73D9,
+ 0xACB10E4A, 0x612DC446,
+ 0xAC8AEB3E, 0x610D05B7,
+ 0xAC64D510, 0x60EC3830,
+ 0xAC3ECBC7, 0x60CB5BB6,
+ 0xAC18CF68, 0x60AA704F,
+ 0xABF2DFFA, 0x60897600,
+ 0xABCCFD82, 0x60686CCE,
+ 0xABA72806, 0x604754BE,
+ 0xAB815F8C, 0x60262DD5,
+ 0xAB5BA41A, 0x6004F818,
+ 0xAB35F5B5, 0x5FE3B38D,
+ 0xAB105464, 0x5FC26038,
+ 0xAAEAC02B, 0x5FA0FE1E,
+ 0xAAC53912, 0x5F7F8D46,
+ 0xAA9FBF1D, 0x5F5E0DB3,
+ 0xAA7A5253, 0x5F3C7F6B,
+ 0xAA54F2B9, 0x5F1AE273,
+ 0xAA2FA055, 0x5EF936D1,
+ 0xAA0A5B2D, 0x5ED77C89,
+ 0xA9E52347, 0x5EB5B3A1,
+ 0xA9BFF8A8, 0x5E93DC1F,
+ 0xA99ADB56, 0x5E71F606,
+ 0xA975CB56, 0x5E50015D,
+ 0xA950C8AF, 0x5E2DFE28,
+ 0xA92BD366, 0x5E0BEC6E,
+ 0xA906EB81, 0x5DE9CC32,
+ 0xA8E21106, 0x5DC79D7C,
+ 0xA8BD43FA, 0x5DA5604E,
+ 0xA8988463, 0x5D8314B0,
+ 0xA873D246, 0x5D60BAA6,
+ 0xA84F2DA9, 0x5D3E5236,
+ 0xA82A9693, 0x5D1BDB65,
+ 0xA8060D08, 0x5CF95638,
+ 0xA7E1910E, 0x5CD6C2B4,
+ 0xA7BD22AB, 0x5CB420DF,
+ 0xA798C1E4, 0x5C9170BF,
+ 0xA7746EC0, 0x5C6EB258,
+ 0xA7502943, 0x5C4BE5B0,
+ 0xA72BF173, 0x5C290ACC,
+ 0xA707C756, 0x5C0621B2,
+ 0xA6E3AAF2, 0x5BE32A67,
+ 0xA6BF9C4B, 0x5BC024F0,
+ 0xA69B9B68, 0x5B9D1153,
+ 0xA677A84E, 0x5B79EF96,
+ 0xA653C302, 0x5B56BFBD,
+ 0xA62FEB8B, 0x5B3381CE,
+ 0xA60C21ED, 0x5B1035CF,
+ 0xA5E8662F, 0x5AECDBC4,
+ 0xA5C4B855, 0x5AC973B4,
+ 0xA5A11865, 0x5AA5FDA4,
+ 0xA57D8666, 0x5A82799A,
+ 0xA55A025B, 0x5A5EE79A,
+ 0xA5368C4B, 0x5A3B47AA,
+ 0xA513243B, 0x5A1799D0,
+ 0xA4EFCA31, 0x59F3DE12,
+ 0xA4CC7E31, 0x59D01474,
+ 0xA4A94042, 0x59AC3CFD,
+ 0xA4861069, 0x598857B1,
+ 0xA462EEAC, 0x59646497,
+ 0xA43FDB0F, 0x594063B4,
+ 0xA41CD598, 0x591C550E,
+ 0xA3F9DE4D, 0x58F838A9,
+ 0xA3D6F533, 0x58D40E8C,
+ 0xA3B41A4F, 0x58AFD6BC,
+ 0xA3914DA7, 0x588B913F,
+ 0xA36E8F40, 0x58673E1B,
+ 0xA34BDF20, 0x5842DD54,
+ 0xA3293D4B, 0x581E6EF1,
+ 0xA306A9C7, 0x57F9F2F7,
+ 0xA2E4249A, 0x57D5696C,
+ 0xA2C1ADC9, 0x57B0D256,
+ 0xA29F4559, 0x578C2DB9,
+ 0xA27CEB4F, 0x57677B9D,
+ 0xA25A9FB1, 0x5742BC05,
+ 0xA2386283, 0x571DEEF9,
+ 0xA21633CD, 0x56F9147E,
+ 0xA1F41391, 0x56D42C99,
+ 0xA1D201D7, 0x56AF3750,
+ 0xA1AFFEA2, 0x568A34A9,
+ 0xA18E09F9, 0x566524AA,
+ 0xA16C23E1, 0x56400757,
+ 0xA14A4C5E, 0x561ADCB8,
+ 0xA1288376, 0x55F5A4D2,
+ 0xA106C92E, 0x55D05FAA,
+ 0xA0E51D8C, 0x55AB0D46,
+ 0xA0C38094, 0x5585ADAC,
+ 0xA0A1F24C, 0x556040E2,
+ 0xA08072BA, 0x553AC6ED,
+ 0xA05F01E1, 0x55153FD4,
+ 0xA03D9FC7, 0x54EFAB9C,
+ 0xA01C4C72, 0x54CA0A4A,
+ 0x9FFB07E7, 0x54A45BE5,
+ 0x9FD9D22A, 0x547EA073,
+ 0x9FB8AB41, 0x5458D7F9,
+ 0x9F979331, 0x5433027D,
+ 0x9F7689FF, 0x540D2005,
+ 0x9F558FB0, 0x53E73097,
+ 0x9F34A449, 0x53C13438,
+ 0x9F13C7D0, 0x539B2AEF,
+ 0x9EF2FA48, 0x537514C1,
+ 0x9ED23BB9, 0x534EF1B5,
+ 0x9EB18C26, 0x5328C1D0,
+ 0x9E90EB94, 0x53028517,
+ 0x9E705A09, 0x52DC3B92,
+ 0x9E4FD789, 0x52B5E545,
+ 0x9E2F641A, 0x528F8237,
+ 0x9E0EFFC1, 0x5269126E,
+ 0x9DEEAA82, 0x524295EF,
+ 0x9DCE6462, 0x521C0CC1,
+ 0x9DAE2D68, 0x51F576E9,
+ 0x9D8E0596, 0x51CED46E,
+ 0x9D6DECF4, 0x51A82555,
+ 0x9D4DE384, 0x518169A4,
+ 0x9D2DE94D, 0x515AA162,
+ 0x9D0DFE53, 0x5133CC94,
+ 0x9CEE229C, 0x510CEB40,
+ 0x9CCE562B, 0x50E5FD6C,
+ 0x9CAE9907, 0x50BF031F,
+ 0x9C8EEB33, 0x5097FC5E,
+ 0x9C6F4CB5, 0x5070E92F,
+ 0x9C4FBD92, 0x5049C999,
+ 0x9C303DCF, 0x50229DA0,
+ 0x9C10CD70, 0x4FFB654D,
+ 0x9BF16C7A, 0x4FD420A3,
+ 0x9BD21AF2, 0x4FACCFAB,
+ 0x9BB2D8DD, 0x4F857268,
+ 0x9B93A640, 0x4F5E08E3,
+ 0x9B748320, 0x4F369320,
+ 0x9B556F80, 0x4F0F1126,
+ 0x9B366B67, 0x4EE782FA,
+ 0x9B1776D9, 0x4EBFE8A4,
+ 0x9AF891DB, 0x4E984229,
+ 0x9AD9BC71, 0x4E708F8F,
+ 0x9ABAF6A0, 0x4E48D0DC,
+ 0x9A9C406D, 0x4E210617,
+ 0x9A7D99DD, 0x4DF92F45,
+ 0x9A5F02F5, 0x4DD14C6E,
+ 0x9A407BB8, 0x4DA95D96,
+ 0x9A22042C, 0x4D8162C4,
+ 0x9A039C56, 0x4D595BFE,
+ 0x99E5443A, 0x4D31494B,
+ 0x99C6FBDE, 0x4D092AB0,
+ 0x99A8C344, 0x4CE10034,
+ 0x998A9A73, 0x4CB8C9DD,
+ 0x996C816F, 0x4C9087B1,
+ 0x994E783C, 0x4C6839B6,
+ 0x99307EE0, 0x4C3FDFF3,
+ 0x9912955E, 0x4C177A6E,
+ 0x98F4BBBC, 0x4BEF092D,
+ 0x98D6F1FE, 0x4BC68C36,
+ 0x98B93828, 0x4B9E038F,
+ 0x989B8E3F, 0x4B756F3F,
+ 0x987DF449, 0x4B4CCF4D,
+ 0x98606A48, 0x4B2423BD,
+ 0x9842F043, 0x4AFB6C97,
+ 0x9825863D, 0x4AD2A9E1,
+ 0x98082C3B, 0x4AA9DBA1,
+ 0x97EAE241, 0x4A8101DE,
+ 0x97CDA855, 0x4A581C9D,
+ 0x97B07E7A, 0x4A2F2BE5,
+ 0x979364B5, 0x4A062FBD,
+ 0x97765B0A, 0x49DD282A,
+ 0x9759617E, 0x49B41533,
+ 0x973C7816, 0x498AF6DE,
+ 0x971F9ED6, 0x4961CD32,
+ 0x9702D5C2, 0x49389836,
+ 0x96E61CDF, 0x490F57EE,
+ 0x96C97431, 0x48E60C62,
+ 0x96ACDBBD, 0x48BCB598,
+ 0x96905387, 0x48935397,
+ 0x9673DB94, 0x4869E664,
+ 0x965773E7, 0x48406E07,
+ 0x963B1C85, 0x4816EA85,
+ 0x961ED573, 0x47ED5BE6,
+ 0x96029EB5, 0x47C3C22E,
+ 0x95E6784F, 0x479A1D66,
+ 0x95CA6246, 0x47706D93,
+ 0x95AE5C9E, 0x4746B2BC,
+ 0x9592675B, 0x471CECE6,
+ 0x95768282, 0x46F31C1A,
+ 0x955AAE17, 0x46C9405C,
+ 0x953EEA1E, 0x469F59B4,
+ 0x9523369B, 0x46756827,
+ 0x95079393, 0x464B6BBD,
+ 0x94EC010B, 0x4621647C,
+ 0x94D07F05, 0x45F7526B,
+ 0x94B50D87, 0x45CD358F,
+ 0x9499AC95, 0x45A30DF0,
+ 0x947E5C32, 0x4578DB93,
+ 0x94631C64, 0x454E9E80,
+ 0x9447ED2F, 0x452456BC,
+ 0x942CCE95, 0x44FA044F,
+ 0x9411C09D, 0x44CFA73F,
+ 0x93F6C34A, 0x44A53F93,
+ 0x93DBD69F, 0x447ACD50,
+ 0x93C0FAA2, 0x4450507E,
+ 0x93A62F56, 0x4425C923,
+ 0x938B74C0, 0x43FB3745,
+ 0x9370CAE4, 0x43D09AEC,
+ 0x935631C5, 0x43A5F41E,
+ 0x933BA968, 0x437B42E1,
+ 0x932131D1, 0x4350873C,
+ 0x9306CB04, 0x4325C135,
+ 0x92EC7505, 0x42FAF0D4,
+ 0x92D22FD8, 0x42D0161E,
+ 0x92B7FB82, 0x42A5311A,
+ 0x929DD805, 0x427A41D0,
+ 0x9283C567, 0x424F4845,
+ 0x9269C3AC, 0x42244480,
+ 0x924FD2D6, 0x41F93688,
+ 0x9235F2EB, 0x41CE1E64,
+ 0x921C23EE, 0x41A2FC1A,
+ 0x920265E4, 0x4177CFB0,
+ 0x91E8B8D0, 0x414C992E,
+ 0x91CF1CB6, 0x4121589A,
+ 0x91B5919A, 0x40F60DFB,
+ 0x919C1780, 0x40CAB957,
+ 0x9182AE6C, 0x409F5AB6,
+ 0x91695663, 0x4073F21D,
+ 0x91500F67, 0x40487F93,
+ 0x9136D97D, 0x401D0320,
+ 0x911DB4A8, 0x3FF17CCA,
+ 0x9104A0ED, 0x3FC5EC97,
+ 0x90EB9E50, 0x3F9A528F,
+ 0x90D2ACD3, 0x3F6EAEB8,
+ 0x90B9CC7C, 0x3F430118,
+ 0x90A0FD4E, 0x3F1749B7,
+ 0x90883F4C, 0x3EEB889C,
+ 0x906F927B, 0x3EBFBDCC,
+ 0x9056F6DF, 0x3E93E94F,
+ 0x903E6C7A, 0x3E680B2C,
+ 0x9025F352, 0x3E3C2369,
+ 0x900D8B69, 0x3E10320D,
+ 0x8FF534C4, 0x3DE4371F,
+ 0x8FDCEF66, 0x3DB832A5,
+ 0x8FC4BB53, 0x3D8C24A7,
+ 0x8FAC988E, 0x3D600D2B,
+ 0x8F94871D, 0x3D33EC39,
+ 0x8F7C8701, 0x3D07C1D5,
+ 0x8F64983F, 0x3CDB8E09,
+ 0x8F4CBADB, 0x3CAF50DA,
+ 0x8F34EED8, 0x3C830A4F,
+ 0x8F1D343A, 0x3C56BA70,
+ 0x8F058B04, 0x3C2A6142,
+ 0x8EEDF33B, 0x3BFDFECD,
+ 0x8ED66CE1, 0x3BD19317,
+ 0x8EBEF7FB, 0x3BA51E29,
+ 0x8EA7948C, 0x3B78A007,
+ 0x8E904298, 0x3B4C18BA,
+ 0x8E790222, 0x3B1F8847,
+ 0x8E61D32D, 0x3AF2EEB7,
+ 0x8E4AB5BF, 0x3AC64C0F,
+ 0x8E33A9D9, 0x3A99A057,
+ 0x8E1CAF80, 0x3A6CEB95,
+ 0x8E05C6B7, 0x3A402DD1,
+ 0x8DEEEF82, 0x3A136712,
+ 0x8DD829E4, 0x39E6975D,
+ 0x8DC175E0, 0x39B9BEBB,
+ 0x8DAAD37B, 0x398CDD32,
+ 0x8D9442B7, 0x395FF2C9,
+ 0x8D7DC399, 0x3932FF87,
+ 0x8D675623, 0x39060372,
+ 0x8D50FA59, 0x38D8FE93,
+ 0x8D3AB03F, 0x38ABF0EF,
+ 0x8D2477D8, 0x387EDA8E,
+ 0x8D0E5127, 0x3851BB76,
+ 0x8CF83C30, 0x382493B0,
+ 0x8CE238F6, 0x37F76340,
+ 0x8CCC477D, 0x37CA2A30,
+ 0x8CB667C7, 0x379CE884,
+ 0x8CA099D9, 0x376F9E46,
+ 0x8C8ADDB6, 0x37424B7A,
+ 0x8C753361, 0x3714F02A,
+ 0x8C5F9ADD, 0x36E78C5A,
+ 0x8C4A142F, 0x36BA2013,
+ 0x8C349F58, 0x368CAB5C,
+ 0x8C1F3C5C, 0x365F2E3B,
+ 0x8C09EB40, 0x3631A8B7,
+ 0x8BF4AC05, 0x36041AD9,
+ 0x8BDF7EAF, 0x35D684A5,
+ 0x8BCA6342, 0x35A8E624,
+ 0x8BB559C1, 0x357B3F5D,
+ 0x8BA0622F, 0x354D9056,
+ 0x8B8B7C8F, 0x351FD917,
+ 0x8B76A8E4, 0x34F219A7,
+ 0x8B61E732, 0x34C4520D,
+ 0x8B4D377C, 0x3496824F,
+ 0x8B3899C5, 0x3468AA76,
+ 0x8B240E10, 0x343ACA87,
+ 0x8B0F9461, 0x340CE28A,
+ 0x8AFB2CBA, 0x33DEF287,
+ 0x8AE6D71F, 0x33B0FA84,
+ 0x8AD29393, 0x3382FA88,
+ 0x8ABE6219, 0x3354F29A,
+ 0x8AAA42B4, 0x3326E2C2,
+ 0x8A963567, 0x32F8CB07,
+ 0x8A823A35, 0x32CAAB6F,
+ 0x8A6E5122, 0x329C8402,
+ 0x8A5A7A30, 0x326E54C7,
+ 0x8A46B563, 0x32401DC5,
+ 0x8A3302BD, 0x3211DF03,
+ 0x8A1F6242, 0x31E39889,
+ 0x8A0BD3F5, 0x31B54A5D,
+ 0x89F857D8, 0x3186F487,
+ 0x89E4EDEE, 0x3158970D,
+ 0x89D1963C, 0x312A31F8,
+ 0x89BE50C3, 0x30FBC54D,
+ 0x89AB1D86, 0x30CD5114,
+ 0x8997FC89, 0x309ED555,
+ 0x8984EDCF, 0x30705217,
+ 0x8971F15A, 0x3041C760,
+ 0x895F072D, 0x30133538,
+ 0x894C2F4C, 0x2FE49BA6,
+ 0x893969B9, 0x2FB5FAB2,
+ 0x8926B677, 0x2F875262,
+ 0x89141589, 0x2F58A2BD,
+ 0x890186F1, 0x2F29EBCC,
+ 0x88EF0AB4, 0x2EFB2D94,
+ 0x88DCA0D3, 0x2ECC681E,
+ 0x88CA4951, 0x2E9D9B70,
+ 0x88B80431, 0x2E6EC792,
+ 0x88A5D177, 0x2E3FEC8B,
+ 0x8893B124, 0x2E110A62,
+ 0x8881A33C, 0x2DE2211E,
+ 0x886FA7C2, 0x2DB330C7,
+ 0x885DBEB7, 0x2D843963,
+ 0x884BE820, 0x2D553AFB,
+ 0x883A23FE, 0x2D263595,
+ 0x88287255, 0x2CF72939,
+ 0x8816D327, 0x2CC815ED,
+ 0x88054677, 0x2C98FBBA,
+ 0x87F3CC47, 0x2C69DAA6,
+ 0x87E2649B, 0x2C3AB2B9,
+ 0x87D10F75, 0x2C0B83F9,
+ 0x87BFCCD7, 0x2BDC4E6F,
+ 0x87AE9CC5, 0x2BAD1221,
+ 0x879D7F40, 0x2B7DCF17,
+ 0x878C744C, 0x2B4E8558,
+ 0x877B7BEC, 0x2B1F34EB,
+ 0x876A9621, 0x2AEFDDD8,
+ 0x8759C2EF, 0x2AC08025,
+ 0x87490257, 0x2A911BDB,
+ 0x8738545E, 0x2A61B101,
+ 0x8727B904, 0x2A323F9D,
+ 0x8717304E, 0x2A02C7B8,
+ 0x8706BA3C, 0x29D34958,
+ 0x86F656D3, 0x29A3C484,
+ 0x86E60614, 0x29743945,
+ 0x86D5C802, 0x2944A7A2,
+ 0x86C59C9F, 0x29150FA1,
+ 0x86B583EE, 0x28E5714A,
+ 0x86A57DF1, 0x28B5CCA5,
+ 0x86958AAB, 0x288621B9,
+ 0x8685AA1F, 0x2856708C,
+ 0x8675DC4E, 0x2826B928,
+ 0x8666213C, 0x27F6FB92,
+ 0x865678EA, 0x27C737D2,
+ 0x8646E35B, 0x27976DF1,
+ 0x86376092, 0x27679DF4,
+ 0x8627F090, 0x2737C7E3,
+ 0x86189359, 0x2707EBC6,
+ 0x860948EE, 0x26D809A5,
+ 0x85FA1152, 0x26A82185,
+ 0x85EAEC88, 0x26783370,
+ 0x85DBDA91, 0x26483F6C,
+ 0x85CCDB70, 0x26184581,
+ 0x85BDEF27, 0x25E845B5,
+ 0x85AF15B9, 0x25B84012,
+ 0x85A04F28, 0x2588349D,
+ 0x85919B75, 0x2558235E,
+ 0x8582FAA4, 0x25280C5D,
+ 0x85746CB7, 0x24F7EFA1,
+ 0x8565F1B0, 0x24C7CD32,
+ 0x85578991, 0x2497A517,
+ 0x8549345C, 0x24677757,
+ 0x853AF214, 0x243743FA,
+ 0x852CC2BA, 0x24070B07,
+ 0x851EA652, 0x23D6CC86,
+ 0x85109CDC, 0x23A6887E,
+ 0x8502A65C, 0x23763EF7,
+ 0x84F4C2D3, 0x2345EFF7,
+ 0x84E6F244, 0x23159B87,
+ 0x84D934B0, 0x22E541AE,
+ 0x84CB8A1B, 0x22B4E274,
+ 0x84BDF285, 0x22847DDF,
+ 0x84B06DF1, 0x225413F8,
+ 0x84A2FC62, 0x2223A4C5,
+ 0x84959DD9, 0x21F3304E,
+ 0x84885257, 0x21C2B69C,
+ 0x847B19E1, 0x219237B4,
+ 0x846DF476, 0x2161B39F,
+ 0x8460E21A, 0x21312A65,
+ 0x8453E2CE, 0x21009C0B,
+ 0x8446F695, 0x20D0089B,
+ 0x843A1D70, 0x209F701C,
+ 0x842D5761, 0x206ED295,
+ 0x8420A46B, 0x203E300D,
+ 0x8414048F, 0x200D888C,
+ 0x840777CF, 0x1FDCDC1A,
+ 0x83FAFE2E, 0x1FAC2ABF,
+ 0x83EE97AC, 0x1F7B7480,
+ 0x83E2444D, 0x1F4AB967,
+ 0x83D60411, 0x1F19F97B,
+ 0x83C9D6FB, 0x1EE934C2,
+ 0x83BDBD0D, 0x1EB86B46,
+ 0x83B1B649, 0x1E879D0C,
+ 0x83A5C2B0, 0x1E56CA1E,
+ 0x8399E244, 0x1E25F281,
+ 0x838E1507, 0x1DF5163F,
+ 0x83825AFB, 0x1DC4355D,
+ 0x8376B422, 0x1D934FE5,
+ 0x836B207D, 0x1D6265DD,
+ 0x835FA00E, 0x1D31774D,
+ 0x835432D8, 0x1D00843C,
+ 0x8348D8DB, 0x1CCF8CB3,
+ 0x833D921A, 0x1C9E90B8,
+ 0x83325E97, 0x1C6D9053,
+ 0x83273E52, 0x1C3C8B8C,
+ 0x831C314E, 0x1C0B826A,
+ 0x8311378C, 0x1BDA74F5,
+ 0x8306510F, 0x1BA96334,
+ 0x82FB7DD8, 0x1B784D30,
+ 0x82F0BDE8, 0x1B4732EF,
+ 0x82E61141, 0x1B161479,
+ 0x82DB77E5, 0x1AE4F1D6,
+ 0x82D0F1D5, 0x1AB3CB0C,
+ 0x82C67F13, 0x1A82A025,
+ 0x82BC1FA1, 0x1A517127,
+ 0x82B1D381, 0x1A203E1B,
+ 0x82A79AB3, 0x19EF0706,
+ 0x829D753A, 0x19BDCBF2,
+ 0x82936316, 0x198C8CE6,
+ 0x8289644A, 0x195B49E9,
+ 0x827F78D8, 0x192A0303,
+ 0x8275A0C0, 0x18F8B83C,
+ 0x826BDC04, 0x18C7699B,
+ 0x82622AA5, 0x18961727,
+ 0x82588CA6, 0x1864C0E9,
+ 0x824F0208, 0x183366E8,
+ 0x82458ACB, 0x1802092C,
+ 0x823C26F2, 0x17D0A7BB,
+ 0x8232D67E, 0x179F429F,
+ 0x82299971, 0x176DD9DE,
+ 0x82206FCB, 0x173C6D80,
+ 0x8217598F, 0x170AFD8D,
+ 0x820E56BE, 0x16D98A0C,
+ 0x82056758, 0x16A81305,
+ 0x81FC8B60, 0x1676987F,
+ 0x81F3C2D7, 0x16451A83,
+ 0x81EB0DBD, 0x16139917,
+ 0x81E26C16, 0x15E21444,
+ 0x81D9DDE1, 0x15B08C11,
+ 0x81D16320, 0x157F0086,
+ 0x81C8FBD5, 0x154D71AA,
+ 0x81C0A801, 0x151BDF85,
+ 0x81B867A4, 0x14EA4A1F,
+ 0x81B03AC1, 0x14B8B17F,
+ 0x81A82159, 0x148715AD,
+ 0x81A01B6C, 0x145576B1,
+ 0x819828FD, 0x1423D492,
+ 0x81904A0C, 0x13F22F57,
+ 0x81887E9A, 0x13C0870A,
+ 0x8180C6A9, 0x138EDBB0,
+ 0x8179223A, 0x135D2D53,
+ 0x8171914E, 0x132B7BF9,
+ 0x816A13E6, 0x12F9C7AA,
+ 0x8162AA03, 0x12C8106E,
+ 0x815B53A8, 0x1296564D,
+ 0x815410D3, 0x1264994E,
+ 0x814CE188, 0x1232D978,
+ 0x8145C5C6, 0x120116D4,
+ 0x813EBD90, 0x11CF516A,
+ 0x8137C8E6, 0x119D8940,
+ 0x8130E7C8, 0x116BBE5F,
+ 0x812A1A39, 0x1139F0CE,
+ 0x81236039, 0x11082096,
+ 0x811CB9CA, 0x10D64DBC,
+ 0x811626EC, 0x10A4784A,
+ 0x810FA7A0, 0x1072A047,
+ 0x81093BE8, 0x1040C5BB,
+ 0x8102E3C3, 0x100EE8AD,
+ 0x80FC9F35, 0x0FDD0925,
+ 0x80F66E3C, 0x0FAB272B,
+ 0x80F050DB, 0x0F7942C6,
+ 0x80EA4712, 0x0F475BFE,
+ 0x80E450E2, 0x0F1572DC,
+ 0x80DE6E4C, 0x0EE38765,
+ 0x80D89F51, 0x0EB199A3,
+ 0x80D2E3F1, 0x0E7FA99D,
+ 0x80CD3C2F, 0x0E4DB75B,
+ 0x80C7A80A, 0x0E1BC2E3,
+ 0x80C22783, 0x0DE9CC3F,
+ 0x80BCBA9C, 0x0DB7D376,
+ 0x80B76155, 0x0D85D88F,
+ 0x80B21BAF, 0x0D53DB92,
+ 0x80ACE9AB, 0x0D21DC87,
+ 0x80A7CB49, 0x0CEFDB75,
+ 0x80A2C08B, 0x0CBDD865,
+ 0x809DC970, 0x0C8BD35E,
+ 0x8098E5FB, 0x0C59CC67,
+ 0x8094162B, 0x0C27C389,
+ 0x808F5A02, 0x0BF5B8CB,
+ 0x808AB180, 0x0BC3AC35,
+ 0x80861CA5, 0x0B919DCE,
+ 0x80819B74, 0x0B5F8D9F,
+ 0x807D2DEB, 0x0B2D7BAE,
+ 0x8078D40D, 0x0AFB6805,
+ 0x80748DD9, 0x0AC952AA,
+ 0x80705B50, 0x0A973BA5,
+ 0x806C3C73, 0x0A6522FE,
+ 0x80683143, 0x0A3308BC,
+ 0x806439C0, 0x0A00ECE8,
+ 0x806055EA, 0x09CECF89,
+ 0x805C85C3, 0x099CB0A7,
+ 0x8058C94C, 0x096A9049,
+ 0x80552083, 0x09386E77,
+ 0x80518B6B, 0x09064B3A,
+ 0x804E0A03, 0x08D42698,
+ 0x804A9C4D, 0x08A2009A,
+ 0x80474248, 0x086FD947,
+ 0x8043FBF6, 0x083DB0A7,
+ 0x8040C956, 0x080B86C1,
+ 0x803DAA69, 0x07D95B9E,
+ 0x803A9F31, 0x07A72F45,
+ 0x8037A7AC, 0x077501BE,
+ 0x8034C3DC, 0x0742D310,
+ 0x8031F3C1, 0x0710A344,
+ 0x802F375C, 0x06DE7261,
+ 0x802C8EAD, 0x06AC406F,
+ 0x8029F9B4, 0x067A0D75,
+ 0x80277872, 0x0647D97C,
+ 0x80250AE7, 0x0615A48A,
+ 0x8022B113, 0x05E36EA9,
+ 0x80206AF8, 0x05B137DF,
+ 0x801E3894, 0x057F0034,
+ 0x801C19E9, 0x054CC7B0,
+ 0x801A0EF7, 0x051A8E5C,
+ 0x801817BF, 0x04E8543D,
+ 0x80163440, 0x04B6195D,
+ 0x8014647A, 0x0483DDC3,
+ 0x8012A86F, 0x0451A176,
+ 0x8011001E, 0x041F647F,
+ 0x800F6B88, 0x03ED26E6,
+ 0x800DEAAC, 0x03BAE8B1,
+ 0x800C7D8C, 0x0388A9E9,
+ 0x800B2427, 0x03566A96,
+ 0x8009DE7D, 0x03242ABF,
+ 0x8008AC90, 0x02F1EA6B,
+ 0x80078E5E, 0x02BFA9A4,
+ 0x800683E8, 0x028D6870,
+ 0x80058D2E, 0x025B26D7,
+ 0x8004AA31, 0x0228E4E1,
+ 0x8003DAF0, 0x01F6A296,
+ 0x80031F6C, 0x01C45FFE,
+ 0x800277A5, 0x01921D1F,
+ 0x8001E39B, 0x015FDA03,
+ 0x8001634D, 0x012D96B0,
+ 0x8000F6BD, 0x00FB532F,
+ 0x80009DE9, 0x00C90F88,
+ 0x800058D3, 0x0096CBC1,
+ 0x8000277A, 0x006487E3,
+ 0x800009DE, 0x003243F5,
+ 0x80000000, 0x00000000,
+ 0x800009DE, 0xFFCDBC0A,
+ 0x8000277A, 0xFF9B781D,
+ 0x800058D3, 0xFF69343E,
+ 0x80009DE9, 0xFF36F078,
+ 0x8000F6BD, 0xFF04ACD0,
+ 0x8001634D, 0xFED2694F,
+ 0x8001E39B, 0xFEA025FC,
+ 0x800277A5, 0xFE6DE2E0,
+ 0x80031F6C, 0xFE3BA001,
+ 0x8003DAF0, 0xFE095D69,
+ 0x8004AA31, 0xFDD71B1E,
+ 0x80058D2E, 0xFDA4D928,
+ 0x800683E8, 0xFD72978F,
+ 0x80078E5E, 0xFD40565B,
+ 0x8008AC90, 0xFD0E1594,
+ 0x8009DE7D, 0xFCDBD541,
+ 0x800B2427, 0xFCA99569,
+ 0x800C7D8C, 0xFC775616,
+ 0x800DEAAC, 0xFC45174E,
+ 0x800F6B88, 0xFC12D919,
+ 0x8011001E, 0xFBE09B80,
+ 0x8012A86F, 0xFBAE5E89,
+ 0x8014647A, 0xFB7C223C,
+ 0x80163440, 0xFB49E6A2,
+ 0x801817BF, 0xFB17ABC2,
+ 0x801A0EF7, 0xFAE571A4,
+ 0x801C19E9, 0xFAB3384F,
+ 0x801E3894, 0xFA80FFCB,
+ 0x80206AF8, 0xFA4EC820,
+ 0x8022B113, 0xFA1C9156,
+ 0x80250AE7, 0xF9EA5B75,
+ 0x80277872, 0xF9B82683,
+ 0x8029F9B4, 0xF985F28A,
+ 0x802C8EAD, 0xF953BF90,
+ 0x802F375C, 0xF9218D9E,
+ 0x8031F3C1, 0xF8EF5CBB,
+ 0x8034C3DC, 0xF8BD2CEF,
+ 0x8037A7AC, 0xF88AFE41,
+ 0x803A9F31, 0xF858D0BA,
+ 0x803DAA69, 0xF826A461,
+ 0x8040C956, 0xF7F4793E,
+ 0x8043FBF6, 0xF7C24F58,
+ 0x80474248, 0xF79026B8,
+ 0x804A9C4D, 0xF75DFF65,
+ 0x804E0A03, 0xF72BD967,
+ 0x80518B6B, 0xF6F9B4C5,
+ 0x80552083, 0xF6C79188,
+ 0x8058C94C, 0xF6956FB6,
+ 0x805C85C3, 0xF6634F58,
+ 0x806055EA, 0xF6313076,
+ 0x806439C0, 0xF5FF1317,
+ 0x80683143, 0xF5CCF743,
+ 0x806C3C73, 0xF59ADD01,
+ 0x80705B50, 0xF568C45A,
+ 0x80748DD9, 0xF536AD55,
+ 0x8078D40D, 0xF50497FA,
+ 0x807D2DEB, 0xF4D28451,
+ 0x80819B74, 0xF4A07260,
+ 0x80861CA5, 0xF46E6231,
+ 0x808AB180, 0xF43C53CA,
+ 0x808F5A02, 0xF40A4734,
+ 0x8094162B, 0xF3D83C76,
+ 0x8098E5FB, 0xF3A63398,
+ 0x809DC970, 0xF3742CA1,
+ 0x80A2C08B, 0xF342279A,
+ 0x80A7CB49, 0xF310248A,
+ 0x80ACE9AB, 0xF2DE2378,
+ 0x80B21BAF, 0xF2AC246D,
+ 0x80B76155, 0xF27A2770,
+ 0x80BCBA9C, 0xF2482C89,
+ 0x80C22783, 0xF21633C0,
+ 0x80C7A80A, 0xF1E43D1C,
+ 0x80CD3C2F, 0xF1B248A5,
+ 0x80D2E3F1, 0xF1805662,
+ 0x80D89F51, 0xF14E665C,
+ 0x80DE6E4C, 0xF11C789A,
+ 0x80E450E2, 0xF0EA8D23,
+ 0x80EA4712, 0xF0B8A401,
+ 0x80F050DB, 0xF086BD39,
+ 0x80F66E3C, 0xF054D8D4,
+ 0x80FC9F35, 0xF022F6DA,
+ 0x8102E3C3, 0xEFF11752,
+ 0x81093BE8, 0xEFBF3A44,
+ 0x810FA7A0, 0xEF8D5FB8,
+ 0x811626EC, 0xEF5B87B5,
+ 0x811CB9CA, 0xEF29B243,
+ 0x81236039, 0xEEF7DF6A,
+ 0x812A1A39, 0xEEC60F31,
+ 0x8130E7C8, 0xEE9441A0,
+ 0x8137C8E6, 0xEE6276BF,
+ 0x813EBD90, 0xEE30AE95,
+ 0x8145C5C6, 0xEDFEE92B,
+ 0x814CE188, 0xEDCD2687,
+ 0x815410D3, 0xED9B66B2,
+ 0x815B53A8, 0xED69A9B2,
+ 0x8162AA03, 0xED37EF91,
+ 0x816A13E6, 0xED063855,
+ 0x8171914E, 0xECD48406,
+ 0x8179223A, 0xECA2D2AC,
+ 0x8180C6A9, 0xEC71244F,
+ 0x81887E9A, 0xEC3F78F5,
+ 0x81904A0C, 0xEC0DD0A8,
+ 0x819828FD, 0xEBDC2B6D,
+ 0x81A01B6C, 0xEBAA894E,
+ 0x81A82159, 0xEB78EA52,
+ 0x81B03AC1, 0xEB474E80,
+ 0x81B867A4, 0xEB15B5E0,
+ 0x81C0A801, 0xEAE4207A,
+ 0x81C8FBD5, 0xEAB28E55,
+ 0x81D16320, 0xEA80FF79,
+ 0x81D9DDE1, 0xEA4F73EE,
+ 0x81E26C16, 0xEA1DEBBB,
+ 0x81EB0DBD, 0xE9EC66E8,
+ 0x81F3C2D7, 0xE9BAE57C,
+ 0x81FC8B60, 0xE9896780,
+ 0x82056758, 0xE957ECFB,
+ 0x820E56BE, 0xE92675F4,
+ 0x8217598F, 0xE8F50273,
+ 0x82206FCB, 0xE8C3927F,
+ 0x82299971, 0xE8922621,
+ 0x8232D67E, 0xE860BD60,
+ 0x823C26F2, 0xE82F5844,
+ 0x82458ACB, 0xE7FDF6D3,
+ 0x824F0208, 0xE7CC9917,
+ 0x82588CA6, 0xE79B3F16,
+ 0x82622AA5, 0xE769E8D8,
+ 0x826BDC04, 0xE7389664,
+ 0x8275A0C0, 0xE70747C3,
+ 0x827F78D8, 0xE6D5FCFC,
+ 0x8289644A, 0xE6A4B616,
+ 0x82936316, 0xE6737319,
+ 0x829D753A, 0xE642340D,
+ 0x82A79AB3, 0xE610F8F9,
+ 0x82B1D381, 0xE5DFC1E4,
+ 0x82BC1FA1, 0xE5AE8ED8,
+ 0x82C67F13, 0xE57D5FDA,
+ 0x82D0F1D5, 0xE54C34F3,
+ 0x82DB77E5, 0xE51B0E2A,
+ 0x82E61141, 0xE4E9EB86,
+ 0x82F0BDE8, 0xE4B8CD10,
+ 0x82FB7DD8, 0xE487B2CF,
+ 0x8306510F, 0xE4569CCB,
+ 0x8311378C, 0xE4258B0A,
+ 0x831C314E, 0xE3F47D95,
+ 0x83273E52, 0xE3C37473,
+ 0x83325E97, 0xE3926FAC,
+ 0x833D921A, 0xE3616F47,
+ 0x8348D8DB, 0xE330734C,
+ 0x835432D8, 0xE2FF7BC3,
+ 0x835FA00E, 0xE2CE88B2,
+ 0x836B207D, 0xE29D9A22,
+ 0x8376B422, 0xE26CB01A,
+ 0x83825AFB, 0xE23BCAA2,
+ 0x838E1507, 0xE20AE9C1,
+ 0x8399E244, 0xE1DA0D7E,
+ 0x83A5C2B0, 0xE1A935E1,
+ 0x83B1B649, 0xE17862F3,
+ 0x83BDBD0D, 0xE14794B9,
+ 0x83C9D6FB, 0xE116CB3D,
+ 0x83D60411, 0xE0E60684,
+ 0x83E2444D, 0xE0B54698,
+ 0x83EE97AC, 0xE0848B7F,
+ 0x83FAFE2E, 0xE053D541,
+ 0x840777CF, 0xE02323E5,
+ 0x8414048F, 0xDFF27773,
+ 0x8420A46B, 0xDFC1CFF2,
+ 0x842D5761, 0xDF912D6A,
+ 0x843A1D70, 0xDF608FE3,
+ 0x8446F695, 0xDF2FF764,
+ 0x8453E2CE, 0xDEFF63F4,
+ 0x8460E21A, 0xDECED59B,
+ 0x846DF476, 0xDE9E4C60,
+ 0x847B19E1, 0xDE6DC84B,
+ 0x84885257, 0xDE3D4963,
+ 0x84959DD9, 0xDE0CCFB1,
+ 0x84A2FC62, 0xDDDC5B3A,
+ 0x84B06DF1, 0xDDABEC07,
+ 0x84BDF285, 0xDD7B8220,
+ 0x84CB8A1B, 0xDD4B1D8B,
+ 0x84D934B0, 0xDD1ABE51,
+ 0x84E6F244, 0xDCEA6478,
+ 0x84F4C2D3, 0xDCBA1008,
+ 0x8502A65C, 0xDC89C108,
+ 0x85109CDC, 0xDC597781,
+ 0x851EA652, 0xDC293379,
+ 0x852CC2BA, 0xDBF8F4F8,
+ 0x853AF214, 0xDBC8BC05,
+ 0x8549345C, 0xDB9888A8,
+ 0x85578991, 0xDB685AE8,
+ 0x8565F1B0, 0xDB3832CD,
+ 0x85746CB7, 0xDB08105E,
+ 0x8582FAA4, 0xDAD7F3A2,
+ 0x85919B75, 0xDAA7DCA1,
+ 0x85A04F28, 0xDA77CB62,
+ 0x85AF15B9, 0xDA47BFED,
+ 0x85BDEF27, 0xDA17BA4A,
+ 0x85CCDB70, 0xD9E7BA7E,
+ 0x85DBDA91, 0xD9B7C093,
+ 0x85EAEC88, 0xD987CC8F,
+ 0x85FA1152, 0xD957DE7A,
+ 0x860948EE, 0xD927F65B,
+ 0x86189359, 0xD8F81439,
+ 0x8627F090, 0xD8C8381C,
+ 0x86376092, 0xD898620C,
+ 0x8646E35B, 0xD868920F,
+ 0x865678EA, 0xD838C82D,
+ 0x8666213C, 0xD809046D,
+ 0x8675DC4E, 0xD7D946D7,
+ 0x8685AA1F, 0xD7A98F73,
+ 0x86958AAB, 0xD779DE46,
+ 0x86A57DF1, 0xD74A335A,
+ 0x86B583EE, 0xD71A8EB5,
+ 0x86C59C9F, 0xD6EAF05E,
+ 0x86D5C802, 0xD6BB585D,
+ 0x86E60614, 0xD68BC6BA,
+ 0x86F656D3, 0xD65C3B7B,
+ 0x8706BA3C, 0xD62CB6A7,
+ 0x8717304E, 0xD5FD3847,
+ 0x8727B904, 0xD5CDC062,
+ 0x8738545E, 0xD59E4EFE,
+ 0x87490257, 0xD56EE424,
+ 0x8759C2EF, 0xD53F7FDA,
+ 0x876A9621, 0xD5102227,
+ 0x877B7BEC, 0xD4E0CB14,
+ 0x878C744C, 0xD4B17AA7,
+ 0x879D7F40, 0xD48230E8,
+ 0x87AE9CC5, 0xD452EDDE,
+ 0x87BFCCD7, 0xD423B190,
+ 0x87D10F75, 0xD3F47C06,
+ 0x87E2649B, 0xD3C54D46,
+ 0x87F3CC47, 0xD3962559,
+ 0x88054677, 0xD3670445,
+ 0x8816D327, 0xD337EA12,
+ 0x88287255, 0xD308D6C6,
+ 0x883A23FE, 0xD2D9CA6A,
+ 0x884BE820, 0xD2AAC504,
+ 0x885DBEB7, 0xD27BC69C,
+ 0x886FA7C2, 0xD24CCF38,
+ 0x8881A33C, 0xD21DDEE1,
+ 0x8893B124, 0xD1EEF59E,
+ 0x88A5D177, 0xD1C01374,
+ 0x88B80431, 0xD191386D,
+ 0x88CA4951, 0xD162648F,
+ 0x88DCA0D3, 0xD13397E1,
+ 0x88EF0AB4, 0xD104D26B,
+ 0x890186F1, 0xD0D61433,
+ 0x89141589, 0xD0A75D42,
+ 0x8926B677, 0xD078AD9D,
+ 0x893969B9, 0xD04A054D,
+ 0x894C2F4C, 0xD01B6459,
+ 0x895F072D, 0xCFECCAC7,
+ 0x8971F15A, 0xCFBE389F,
+ 0x8984EDCF, 0xCF8FADE8,
+ 0x8997FC89, 0xCF612AAA,
+ 0x89AB1D86, 0xCF32AEEB,
+ 0x89BE50C3, 0xCF043AB2,
+ 0x89D1963C, 0xCED5CE08,
+ 0x89E4EDEE, 0xCEA768F2,
+ 0x89F857D8, 0xCE790B78,
+ 0x8A0BD3F5, 0xCE4AB5A2,
+ 0x8A1F6242, 0xCE1C6776,
+ 0x8A3302BD, 0xCDEE20FC,
+ 0x8A46B563, 0xCDBFE23A,
+ 0x8A5A7A30, 0xCD91AB38,
+ 0x8A6E5122, 0xCD637BFD,
+ 0x8A823A35, 0xCD355490,
+ 0x8A963567, 0xCD0734F8,
+ 0x8AAA42B4, 0xCCD91D3D,
+ 0x8ABE6219, 0xCCAB0D65,
+ 0x8AD29393, 0xCC7D0577,
+ 0x8AE6D71F, 0xCC4F057B,
+ 0x8AFB2CBA, 0xCC210D78,
+ 0x8B0F9461, 0xCBF31D75,
+ 0x8B240E10, 0xCBC53578,
+ 0x8B3899C5, 0xCB975589,
+ 0x8B4D377C, 0xCB697DB0,
+ 0x8B61E732, 0xCB3BADF2,
+ 0x8B76A8E4, 0xCB0DE658,
+ 0x8B8B7C8F, 0xCAE026E8,
+ 0x8BA0622F, 0xCAB26FA9,
+ 0x8BB559C1, 0xCA84C0A2,
+ 0x8BCA6342, 0xCA5719DB,
+ 0x8BDF7EAF, 0xCA297B5A,
+ 0x8BF4AC05, 0xC9FBE527,
+ 0x8C09EB40, 0xC9CE5748,
+ 0x8C1F3C5C, 0xC9A0D1C4,
+ 0x8C349F58, 0xC97354A3,
+ 0x8C4A142F, 0xC945DFEC,
+ 0x8C5F9ADD, 0xC91873A5,
+ 0x8C753361, 0xC8EB0FD6,
+ 0x8C8ADDB6, 0xC8BDB485,
+ 0x8CA099D9, 0xC89061BA,
+ 0x8CB667C7, 0xC863177B,
+ 0x8CCC477D, 0xC835D5D0,
+ 0x8CE238F6, 0xC8089CBF,
+ 0x8CF83C30, 0xC7DB6C50,
+ 0x8D0E5127, 0xC7AE4489,
+ 0x8D2477D8, 0xC7812571,
+ 0x8D3AB03F, 0xC7540F10,
+ 0x8D50FA59, 0xC727016C,
+ 0x8D675623, 0xC6F9FC8D,
+ 0x8D7DC399, 0xC6CD0079,
+ 0x8D9442B7, 0xC6A00D36,
+ 0x8DAAD37B, 0xC67322CD,
+ 0x8DC175E0, 0xC6464144,
+ 0x8DD829E4, 0xC61968A2,
+ 0x8DEEEF82, 0xC5EC98ED,
+ 0x8E05C6B7, 0xC5BFD22E,
+ 0x8E1CAF80, 0xC593146A,
+ 0x8E33A9D9, 0xC5665FA8,
+ 0x8E4AB5BF, 0xC539B3F0,
+ 0x8E61D32D, 0xC50D1148,
+ 0x8E790222, 0xC4E077B8,
+ 0x8E904298, 0xC4B3E746,
+ 0x8EA7948C, 0xC4875FF8,
+ 0x8EBEF7FB, 0xC45AE1D7,
+ 0x8ED66CE1, 0xC42E6CE8,
+ 0x8EEDF33B, 0xC4020132,
+ 0x8F058B04, 0xC3D59EBD,
+ 0x8F1D343A, 0xC3A9458F,
+ 0x8F34EED8, 0xC37CF5B0,
+ 0x8F4CBADB, 0xC350AF25,
+ 0x8F64983F, 0xC32471F6,
+ 0x8F7C8701, 0xC2F83E2A,
+ 0x8F94871D, 0xC2CC13C7,
+ 0x8FAC988E, 0xC29FF2D4,
+ 0x8FC4BB53, 0xC273DB58,
+ 0x8FDCEF66, 0xC247CD5A,
+ 0x8FF534C4, 0xC21BC8E0,
+ 0x900D8B69, 0xC1EFCDF2,
+ 0x9025F352, 0xC1C3DC96,
+ 0x903E6C7A, 0xC197F4D3,
+ 0x9056F6DF, 0xC16C16B0,
+ 0x906F927B, 0xC1404233,
+ 0x90883F4C, 0xC1147763,
+ 0x90A0FD4E, 0xC0E8B648,
+ 0x90B9CC7C, 0xC0BCFEE7,
+ 0x90D2ACD3, 0xC0915147,
+ 0x90EB9E50, 0xC065AD70,
+ 0x9104A0ED, 0xC03A1368,
+ 0x911DB4A8, 0xC00E8335,
+ 0x9136D97D, 0xBFE2FCDF,
+ 0x91500F67, 0xBFB7806C,
+ 0x91695663, 0xBF8C0DE2,
+ 0x9182AE6C, 0xBF60A54A,
+ 0x919C1780, 0xBF3546A8,
+ 0x91B5919A, 0xBF09F204,
+ 0x91CF1CB6, 0xBEDEA765,
+ 0x91E8B8D0, 0xBEB366D1,
+ 0x920265E4, 0xBE88304F,
+ 0x921C23EE, 0xBE5D03E5,
+ 0x9235F2EB, 0xBE31E19B,
+ 0x924FD2D6, 0xBE06C977,
+ 0x9269C3AC, 0xBDDBBB7F,
+ 0x9283C567, 0xBDB0B7BA,
+ 0x929DD805, 0xBD85BE2F,
+ 0x92B7FB82, 0xBD5ACEE5,
+ 0x92D22FD8, 0xBD2FE9E1,
+ 0x92EC7505, 0xBD050F2C,
+ 0x9306CB04, 0xBCDA3ECA,
+ 0x932131D1, 0xBCAF78C3,
+ 0x933BA968, 0xBC84BD1E,
+ 0x935631C5, 0xBC5A0BE1,
+ 0x9370CAE4, 0xBC2F6513,
+ 0x938B74C0, 0xBC04C8BA,
+ 0x93A62F56, 0xBBDA36DC,
+ 0x93C0FAA2, 0xBBAFAF81,
+ 0x93DBD69F, 0xBB8532AF,
+ 0x93F6C34A, 0xBB5AC06C,
+ 0x9411C09D, 0xBB3058C0,
+ 0x942CCE95, 0xBB05FBB0,
+ 0x9447ED2F, 0xBADBA943,
+ 0x94631C64, 0xBAB1617F,
+ 0x947E5C32, 0xBA87246C,
+ 0x9499AC95, 0xBA5CF210,
+ 0x94B50D87, 0xBA32CA70,
+ 0x94D07F05, 0xBA08AD94,
+ 0x94EC010B, 0xB9DE9B83,
+ 0x95079393, 0xB9B49442,
+ 0x9523369B, 0xB98A97D8,
+ 0x953EEA1E, 0xB960A64B,
+ 0x955AAE17, 0xB936BFA3,
+ 0x95768282, 0xB90CE3E6,
+ 0x9592675B, 0xB8E31319,
+ 0x95AE5C9E, 0xB8B94D44,
+ 0x95CA6246, 0xB88F926C,
+ 0x95E6784F, 0xB865E299,
+ 0x96029EB5, 0xB83C3DD1,
+ 0x961ED573, 0xB812A419,
+ 0x963B1C85, 0xB7E9157A,
+ 0x965773E7, 0xB7BF91F8,
+ 0x9673DB94, 0xB796199B,
+ 0x96905387, 0xB76CAC68,
+ 0x96ACDBBD, 0xB7434A67,
+ 0x96C97431, 0xB719F39D,
+ 0x96E61CDF, 0xB6F0A811,
+ 0x9702D5C2, 0xB6C767CA,
+ 0x971F9ED6, 0xB69E32CD,
+ 0x973C7816, 0xB6750921,
+ 0x9759617E, 0xB64BEACC,
+ 0x97765B0A, 0xB622D7D5,
+ 0x979364B5, 0xB5F9D042,
+ 0x97B07E7A, 0xB5D0D41A,
+ 0x97CDA855, 0xB5A7E362,
+ 0x97EAE241, 0xB57EFE21,
+ 0x98082C3B, 0xB556245E,
+ 0x9825863D, 0xB52D561E,
+ 0x9842F043, 0xB5049368,
+ 0x98606A48, 0xB4DBDC42,
+ 0x987DF449, 0xB4B330B2,
+ 0x989B8E3F, 0xB48A90C0,
+ 0x98B93828, 0xB461FC70,
+ 0x98D6F1FE, 0xB43973C9,
+ 0x98F4BBBC, 0xB410F6D2,
+ 0x9912955E, 0xB3E88591,
+ 0x99307EE0, 0xB3C0200C,
+ 0x994E783C, 0xB397C649,
+ 0x996C816F, 0xB36F784E,
+ 0x998A9A73, 0xB3473622,
+ 0x99A8C344, 0xB31EFFCB,
+ 0x99C6FBDE, 0xB2F6D54F,
+ 0x99E5443A, 0xB2CEB6B5,
+ 0x9A039C56, 0xB2A6A401,
+ 0x9A22042C, 0xB27E9D3B,
+ 0x9A407BB8, 0xB256A26A,
+ 0x9A5F02F5, 0xB22EB392,
+ 0x9A7D99DD, 0xB206D0BA,
+ 0x9A9C406D, 0xB1DEF9E8,
+ 0x9ABAF6A0, 0xB1B72F23,
+ 0x9AD9BC71, 0xB18F7070,
+ 0x9AF891DB, 0xB167BDD6,
+ 0x9B1776D9, 0xB140175B,
+ 0x9B366B67, 0xB1187D05,
+ 0x9B556F80, 0xB0F0EEDA,
+ 0x9B748320, 0xB0C96CDF,
+ 0x9B93A640, 0xB0A1F71C,
+ 0x9BB2D8DD, 0xB07A8D97,
+ 0x9BD21AF2, 0xB0533055,
+ 0x9BF16C7A, 0xB02BDF5C,
+ 0x9C10CD70, 0xB0049AB2,
+ 0x9C303DCF, 0xAFDD625F,
+ 0x9C4FBD92, 0xAFB63667,
+ 0x9C6F4CB5, 0xAF8F16D0,
+ 0x9C8EEB33, 0xAF6803A1,
+ 0x9CAE9907, 0xAF40FCE0,
+ 0x9CCE562B, 0xAF1A0293,
+ 0x9CEE229C, 0xAEF314BF,
+ 0x9D0DFE53, 0xAECC336B,
+ 0x9D2DE94D, 0xAEA55E9D,
+ 0x9D4DE384, 0xAE7E965B,
+ 0x9D6DECF4, 0xAE57DAAA,
+ 0x9D8E0596, 0xAE312B91,
+ 0x9DAE2D68, 0xAE0A8916,
+ 0x9DCE6462, 0xADE3F33E,
+ 0x9DEEAA82, 0xADBD6A10,
+ 0x9E0EFFC1, 0xAD96ED91,
+ 0x9E2F641A, 0xAD707DC8,
+ 0x9E4FD789, 0xAD4A1ABA,
+ 0x9E705A09, 0xAD23C46D,
+ 0x9E90EB94, 0xACFD7AE8,
+ 0x9EB18C26, 0xACD73E30,
+ 0x9ED23BB9, 0xACB10E4A,
+ 0x9EF2FA48, 0xAC8AEB3E,
+ 0x9F13C7D0, 0xAC64D510,
+ 0x9F34A449, 0xAC3ECBC7,
+ 0x9F558FB0, 0xAC18CF68,
+ 0x9F7689FF, 0xABF2DFFA,
+ 0x9F979331, 0xABCCFD82,
+ 0x9FB8AB41, 0xABA72806,
+ 0x9FD9D22A, 0xAB815F8C,
+ 0x9FFB07E7, 0xAB5BA41A,
+ 0xA01C4C72, 0xAB35F5B5,
+ 0xA03D9FC7, 0xAB105464,
+ 0xA05F01E1, 0xAAEAC02B,
+ 0xA08072BA, 0xAAC53912,
+ 0xA0A1F24C, 0xAA9FBF1D,
+ 0xA0C38094, 0xAA7A5253,
+ 0xA0E51D8C, 0xAA54F2B9,
+ 0xA106C92E, 0xAA2FA055,
+ 0xA1288376, 0xAA0A5B2D,
+ 0xA14A4C5E, 0xA9E52347,
+ 0xA16C23E1, 0xA9BFF8A8,
+ 0xA18E09F9, 0xA99ADB56,
+ 0xA1AFFEA2, 0xA975CB56,
+ 0xA1D201D7, 0xA950C8AF,
+ 0xA1F41391, 0xA92BD366,
+ 0xA21633CD, 0xA906EB81,
+ 0xA2386283, 0xA8E21106,
+ 0xA25A9FB1, 0xA8BD43FA,
+ 0xA27CEB4F, 0xA8988463,
+ 0xA29F4559, 0xA873D246,
+ 0xA2C1ADC9, 0xA84F2DA9,
+ 0xA2E4249A, 0xA82A9693,
+ 0xA306A9C7, 0xA8060D08,
+ 0xA3293D4B, 0xA7E1910E,
+ 0xA34BDF20, 0xA7BD22AB,
+ 0xA36E8F40, 0xA798C1E4,
+ 0xA3914DA7, 0xA7746EC0,
+ 0xA3B41A4F, 0xA7502943,
+ 0xA3D6F533, 0xA72BF173,
+ 0xA3F9DE4D, 0xA707C756,
+ 0xA41CD598, 0xA6E3AAF2,
+ 0xA43FDB0F, 0xA6BF9C4B,
+ 0xA462EEAC, 0xA69B9B68,
+ 0xA4861069, 0xA677A84E,
+ 0xA4A94042, 0xA653C302,
+ 0xA4CC7E31, 0xA62FEB8B,
+ 0xA4EFCA31, 0xA60C21ED,
+ 0xA513243B, 0xA5E8662F,
+ 0xA5368C4B, 0xA5C4B855,
+ 0xA55A025B, 0xA5A11865,
+ 0xA57D8666, 0xA57D8666,
+ 0xA5A11865, 0xA55A025B,
+ 0xA5C4B855, 0xA5368C4B,
+ 0xA5E8662F, 0xA513243B,
+ 0xA60C21ED, 0xA4EFCA31,
+ 0xA62FEB8B, 0xA4CC7E31,
+ 0xA653C302, 0xA4A94042,
+ 0xA677A84E, 0xA4861069,
+ 0xA69B9B68, 0xA462EEAC,
+ 0xA6BF9C4B, 0xA43FDB0F,
+ 0xA6E3AAF2, 0xA41CD598,
+ 0xA707C756, 0xA3F9DE4D,
+ 0xA72BF173, 0xA3D6F533,
+ 0xA7502943, 0xA3B41A4F,
+ 0xA7746EC0, 0xA3914DA7,
+ 0xA798C1E4, 0xA36E8F40,
+ 0xA7BD22AB, 0xA34BDF20,
+ 0xA7E1910E, 0xA3293D4B,
+ 0xA8060D08, 0xA306A9C7,
+ 0xA82A9693, 0xA2E4249A,
+ 0xA84F2DA9, 0xA2C1ADC9,
+ 0xA873D246, 0xA29F4559,
+ 0xA8988463, 0xA27CEB4F,
+ 0xA8BD43FA, 0xA25A9FB1,
+ 0xA8E21106, 0xA2386283,
+ 0xA906EB81, 0xA21633CD,
+ 0xA92BD366, 0xA1F41391,
+ 0xA950C8AF, 0xA1D201D7,
+ 0xA975CB56, 0xA1AFFEA2,
+ 0xA99ADB56, 0xA18E09F9,
+ 0xA9BFF8A8, 0xA16C23E1,
+ 0xA9E52347, 0xA14A4C5E,
+ 0xAA0A5B2D, 0xA1288376,
+ 0xAA2FA055, 0xA106C92E,
+ 0xAA54F2B9, 0xA0E51D8C,
+ 0xAA7A5253, 0xA0C38094,
+ 0xAA9FBF1D, 0xA0A1F24C,
+ 0xAAC53912, 0xA08072BA,
+ 0xAAEAC02B, 0xA05F01E1,
+ 0xAB105464, 0xA03D9FC7,
+ 0xAB35F5B5, 0xA01C4C72,
+ 0xAB5BA41A, 0x9FFB07E7,
+ 0xAB815F8C, 0x9FD9D22A,
+ 0xABA72806, 0x9FB8AB41,
+ 0xABCCFD82, 0x9F979331,
+ 0xABF2DFFA, 0x9F7689FF,
+ 0xAC18CF68, 0x9F558FB0,
+ 0xAC3ECBC7, 0x9F34A449,
+ 0xAC64D510, 0x9F13C7D0,
+ 0xAC8AEB3E, 0x9EF2FA48,
+ 0xACB10E4A, 0x9ED23BB9,
+ 0xACD73E30, 0x9EB18C26,
+ 0xACFD7AE8, 0x9E90EB94,
+ 0xAD23C46D, 0x9E705A09,
+ 0xAD4A1ABA, 0x9E4FD789,
+ 0xAD707DC8, 0x9E2F641A,
+ 0xAD96ED91, 0x9E0EFFC1,
+ 0xADBD6A10, 0x9DEEAA82,
+ 0xADE3F33E, 0x9DCE6462,
+ 0xAE0A8916, 0x9DAE2D68,
+ 0xAE312B91, 0x9D8E0596,
+ 0xAE57DAAA, 0x9D6DECF4,
+ 0xAE7E965B, 0x9D4DE384,
+ 0xAEA55E9D, 0x9D2DE94D,
+ 0xAECC336B, 0x9D0DFE53,
+ 0xAEF314BF, 0x9CEE229C,
+ 0xAF1A0293, 0x9CCE562B,
+ 0xAF40FCE0, 0x9CAE9907,
+ 0xAF6803A1, 0x9C8EEB33,
+ 0xAF8F16D0, 0x9C6F4CB5,
+ 0xAFB63667, 0x9C4FBD92,
+ 0xAFDD625F, 0x9C303DCF,
+ 0xB0049AB2, 0x9C10CD70,
+ 0xB02BDF5C, 0x9BF16C7A,
+ 0xB0533055, 0x9BD21AF2,
+ 0xB07A8D97, 0x9BB2D8DD,
+ 0xB0A1F71C, 0x9B93A640,
+ 0xB0C96CDF, 0x9B748320,
+ 0xB0F0EEDA, 0x9B556F80,
+ 0xB1187D05, 0x9B366B67,
+ 0xB140175B, 0x9B1776D9,
+ 0xB167BDD6, 0x9AF891DB,
+ 0xB18F7070, 0x9AD9BC71,
+ 0xB1B72F23, 0x9ABAF6A0,
+ 0xB1DEF9E8, 0x9A9C406D,
+ 0xB206D0BA, 0x9A7D99DD,
+ 0xB22EB392, 0x9A5F02F5,
+ 0xB256A26A, 0x9A407BB8,
+ 0xB27E9D3B, 0x9A22042C,
+ 0xB2A6A401, 0x9A039C56,
+ 0xB2CEB6B5, 0x99E5443A,
+ 0xB2F6D54F, 0x99C6FBDE,
+ 0xB31EFFCB, 0x99A8C344,
+ 0xB3473622, 0x998A9A73,
+ 0xB36F784E, 0x996C816F,
+ 0xB397C649, 0x994E783C,
+ 0xB3C0200C, 0x99307EE0,
+ 0xB3E88591, 0x9912955E,
+ 0xB410F6D2, 0x98F4BBBC,
+ 0xB43973C9, 0x98D6F1FE,
+ 0xB461FC70, 0x98B93828,
+ 0xB48A90C0, 0x989B8E3F,
+ 0xB4B330B2, 0x987DF449,
+ 0xB4DBDC42, 0x98606A48,
+ 0xB5049368, 0x9842F043,
+ 0xB52D561E, 0x9825863D,
+ 0xB556245E, 0x98082C3B,
+ 0xB57EFE21, 0x97EAE241,
+ 0xB5A7E362, 0x97CDA855,
+ 0xB5D0D41A, 0x97B07E7A,
+ 0xB5F9D042, 0x979364B5,
+ 0xB622D7D5, 0x97765B0A,
+ 0xB64BEACC, 0x9759617E,
+ 0xB6750921, 0x973C7816,
+ 0xB69E32CD, 0x971F9ED6,
+ 0xB6C767CA, 0x9702D5C2,
+ 0xB6F0A811, 0x96E61CDF,
+ 0xB719F39D, 0x96C97431,
+ 0xB7434A67, 0x96ACDBBD,
+ 0xB76CAC68, 0x96905387,
+ 0xB796199B, 0x9673DB94,
+ 0xB7BF91F8, 0x965773E7,
+ 0xB7E9157A, 0x963B1C85,
+ 0xB812A419, 0x961ED573,
+ 0xB83C3DD1, 0x96029EB5,
+ 0xB865E299, 0x95E6784F,
+ 0xB88F926C, 0x95CA6246,
+ 0xB8B94D44, 0x95AE5C9E,
+ 0xB8E31319, 0x9592675B,
+ 0xB90CE3E6, 0x95768282,
+ 0xB936BFA3, 0x955AAE17,
+ 0xB960A64B, 0x953EEA1E,
+ 0xB98A97D8, 0x9523369B,
+ 0xB9B49442, 0x95079393,
+ 0xB9DE9B83, 0x94EC010B,
+ 0xBA08AD94, 0x94D07F05,
+ 0xBA32CA70, 0x94B50D87,
+ 0xBA5CF210, 0x9499AC95,
+ 0xBA87246C, 0x947E5C32,
+ 0xBAB1617F, 0x94631C64,
+ 0xBADBA943, 0x9447ED2F,
+ 0xBB05FBB0, 0x942CCE95,
+ 0xBB3058C0, 0x9411C09D,
+ 0xBB5AC06C, 0x93F6C34A,
+ 0xBB8532AF, 0x93DBD69F,
+ 0xBBAFAF81, 0x93C0FAA2,
+ 0xBBDA36DC, 0x93A62F56,
+ 0xBC04C8BA, 0x938B74C0,
+ 0xBC2F6513, 0x9370CAE4,
+ 0xBC5A0BE1, 0x935631C5,
+ 0xBC84BD1E, 0x933BA968,
+ 0xBCAF78C3, 0x932131D1,
+ 0xBCDA3ECA, 0x9306CB04,
+ 0xBD050F2C, 0x92EC7505,
+ 0xBD2FE9E1, 0x92D22FD8,
+ 0xBD5ACEE5, 0x92B7FB82,
+ 0xBD85BE2F, 0x929DD805,
+ 0xBDB0B7BA, 0x9283C567,
+ 0xBDDBBB7F, 0x9269C3AC,
+ 0xBE06C977, 0x924FD2D6,
+ 0xBE31E19B, 0x9235F2EB,
+ 0xBE5D03E5, 0x921C23EE,
+ 0xBE88304F, 0x920265E4,
+ 0xBEB366D1, 0x91E8B8D0,
+ 0xBEDEA765, 0x91CF1CB6,
+ 0xBF09F204, 0x91B5919A,
+ 0xBF3546A8, 0x919C1780,
+ 0xBF60A54A, 0x9182AE6C,
+ 0xBF8C0DE2, 0x91695663,
+ 0xBFB7806C, 0x91500F67,
+ 0xBFE2FCDF, 0x9136D97D,
+ 0xC00E8335, 0x911DB4A8,
+ 0xC03A1368, 0x9104A0ED,
+ 0xC065AD70, 0x90EB9E50,
+ 0xC0915147, 0x90D2ACD3,
+ 0xC0BCFEE7, 0x90B9CC7C,
+ 0xC0E8B648, 0x90A0FD4E,
+ 0xC1147763, 0x90883F4C,
+ 0xC1404233, 0x906F927B,
+ 0xC16C16B0, 0x9056F6DF,
+ 0xC197F4D3, 0x903E6C7A,
+ 0xC1C3DC96, 0x9025F352,
+ 0xC1EFCDF2, 0x900D8B69,
+ 0xC21BC8E0, 0x8FF534C4,
+ 0xC247CD5A, 0x8FDCEF66,
+ 0xC273DB58, 0x8FC4BB53,
+ 0xC29FF2D4, 0x8FAC988E,
+ 0xC2CC13C7, 0x8F94871D,
+ 0xC2F83E2A, 0x8F7C8701,
+ 0xC32471F6, 0x8F64983F,
+ 0xC350AF25, 0x8F4CBADB,
+ 0xC37CF5B0, 0x8F34EED8,
+ 0xC3A9458F, 0x8F1D343A,
+ 0xC3D59EBD, 0x8F058B04,
+ 0xC4020132, 0x8EEDF33B,
+ 0xC42E6CE8, 0x8ED66CE1,
+ 0xC45AE1D7, 0x8EBEF7FB,
+ 0xC4875FF8, 0x8EA7948C,
+ 0xC4B3E746, 0x8E904298,
+ 0xC4E077B8, 0x8E790222,
+ 0xC50D1148, 0x8E61D32D,
+ 0xC539B3F0, 0x8E4AB5BF,
+ 0xC5665FA8, 0x8E33A9D9,
+ 0xC593146A, 0x8E1CAF80,
+ 0xC5BFD22E, 0x8E05C6B7,
+ 0xC5EC98ED, 0x8DEEEF82,
+ 0xC61968A2, 0x8DD829E4,
+ 0xC6464144, 0x8DC175E0,
+ 0xC67322CD, 0x8DAAD37B,
+ 0xC6A00D36, 0x8D9442B7,
+ 0xC6CD0079, 0x8D7DC399,
+ 0xC6F9FC8D, 0x8D675623,
+ 0xC727016C, 0x8D50FA59,
+ 0xC7540F10, 0x8D3AB03F,
+ 0xC7812571, 0x8D2477D8,
+ 0xC7AE4489, 0x8D0E5127,
+ 0xC7DB6C50, 0x8CF83C30,
+ 0xC8089CBF, 0x8CE238F6,
+ 0xC835D5D0, 0x8CCC477D,
+ 0xC863177B, 0x8CB667C7,
+ 0xC89061BA, 0x8CA099D9,
+ 0xC8BDB485, 0x8C8ADDB6,
+ 0xC8EB0FD6, 0x8C753361,
+ 0xC91873A5, 0x8C5F9ADD,
+ 0xC945DFEC, 0x8C4A142F,
+ 0xC97354A3, 0x8C349F58,
+ 0xC9A0D1C4, 0x8C1F3C5C,
+ 0xC9CE5748, 0x8C09EB40,
+ 0xC9FBE527, 0x8BF4AC05,
+ 0xCA297B5A, 0x8BDF7EAF,
+ 0xCA5719DB, 0x8BCA6342,
+ 0xCA84C0A2, 0x8BB559C1,
+ 0xCAB26FA9, 0x8BA0622F,
+ 0xCAE026E8, 0x8B8B7C8F,
+ 0xCB0DE658, 0x8B76A8E4,
+ 0xCB3BADF2, 0x8B61E732,
+ 0xCB697DB0, 0x8B4D377C,
+ 0xCB975589, 0x8B3899C5,
+ 0xCBC53578, 0x8B240E10,
+ 0xCBF31D75, 0x8B0F9461,
+ 0xCC210D78, 0x8AFB2CBA,
+ 0xCC4F057B, 0x8AE6D71F,
+ 0xCC7D0577, 0x8AD29393,
+ 0xCCAB0D65, 0x8ABE6219,
+ 0xCCD91D3D, 0x8AAA42B4,
+ 0xCD0734F8, 0x8A963567,
+ 0xCD355490, 0x8A823A35,
+ 0xCD637BFD, 0x8A6E5122,
+ 0xCD91AB38, 0x8A5A7A30,
+ 0xCDBFE23A, 0x8A46B563,
+ 0xCDEE20FC, 0x8A3302BD,
+ 0xCE1C6776, 0x8A1F6242,
+ 0xCE4AB5A2, 0x8A0BD3F5,
+ 0xCE790B78, 0x89F857D8,
+ 0xCEA768F2, 0x89E4EDEE,
+ 0xCED5CE08, 0x89D1963C,
+ 0xCF043AB2, 0x89BE50C3,
+ 0xCF32AEEB, 0x89AB1D86,
+ 0xCF612AAA, 0x8997FC89,
+ 0xCF8FADE8, 0x8984EDCF,
+ 0xCFBE389F, 0x8971F15A,
+ 0xCFECCAC7, 0x895F072D,
+ 0xD01B6459, 0x894C2F4C,
+ 0xD04A054D, 0x893969B9,
+ 0xD078AD9D, 0x8926B677,
+ 0xD0A75D42, 0x89141589,
+ 0xD0D61433, 0x890186F1,
+ 0xD104D26B, 0x88EF0AB4,
+ 0xD13397E1, 0x88DCA0D3,
+ 0xD162648F, 0x88CA4951,
+ 0xD191386D, 0x88B80431,
+ 0xD1C01374, 0x88A5D177,
+ 0xD1EEF59E, 0x8893B124,
+ 0xD21DDEE1, 0x8881A33C,
+ 0xD24CCF38, 0x886FA7C2,
+ 0xD27BC69C, 0x885DBEB7,
+ 0xD2AAC504, 0x884BE820,
+ 0xD2D9CA6A, 0x883A23FE,
+ 0xD308D6C6, 0x88287255,
+ 0xD337EA12, 0x8816D327,
+ 0xD3670445, 0x88054677,
+ 0xD3962559, 0x87F3CC47,
+ 0xD3C54D46, 0x87E2649B,
+ 0xD3F47C06, 0x87D10F75,
+ 0xD423B190, 0x87BFCCD7,
+ 0xD452EDDE, 0x87AE9CC5,
+ 0xD48230E8, 0x879D7F40,
+ 0xD4B17AA7, 0x878C744C,
+ 0xD4E0CB14, 0x877B7BEC,
+ 0xD5102227, 0x876A9621,
+ 0xD53F7FDA, 0x8759C2EF,
+ 0xD56EE424, 0x87490257,
+ 0xD59E4EFE, 0x8738545E,
+ 0xD5CDC062, 0x8727B904,
+ 0xD5FD3847, 0x8717304E,
+ 0xD62CB6A7, 0x8706BA3C,
+ 0xD65C3B7B, 0x86F656D3,
+ 0xD68BC6BA, 0x86E60614,
+ 0xD6BB585D, 0x86D5C802,
+ 0xD6EAF05E, 0x86C59C9F,
+ 0xD71A8EB5, 0x86B583EE,
+ 0xD74A335A, 0x86A57DF1,
+ 0xD779DE46, 0x86958AAB,
+ 0xD7A98F73, 0x8685AA1F,
+ 0xD7D946D7, 0x8675DC4E,
+ 0xD809046D, 0x8666213C,
+ 0xD838C82D, 0x865678EA,
+ 0xD868920F, 0x8646E35B,
+ 0xD898620C, 0x86376092,
+ 0xD8C8381C, 0x8627F090,
+ 0xD8F81439, 0x86189359,
+ 0xD927F65B, 0x860948EE,
+ 0xD957DE7A, 0x85FA1152,
+ 0xD987CC8F, 0x85EAEC88,
+ 0xD9B7C093, 0x85DBDA91,
+ 0xD9E7BA7E, 0x85CCDB70,
+ 0xDA17BA4A, 0x85BDEF27,
+ 0xDA47BFED, 0x85AF15B9,
+ 0xDA77CB62, 0x85A04F28,
+ 0xDAA7DCA1, 0x85919B75,
+ 0xDAD7F3A2, 0x8582FAA4,
+ 0xDB08105E, 0x85746CB7,
+ 0xDB3832CD, 0x8565F1B0,
+ 0xDB685AE8, 0x85578991,
+ 0xDB9888A8, 0x8549345C,
+ 0xDBC8BC05, 0x853AF214,
+ 0xDBF8F4F8, 0x852CC2BA,
+ 0xDC293379, 0x851EA652,
+ 0xDC597781, 0x85109CDC,
+ 0xDC89C108, 0x8502A65C,
+ 0xDCBA1008, 0x84F4C2D3,
+ 0xDCEA6478, 0x84E6F244,
+ 0xDD1ABE51, 0x84D934B0,
+ 0xDD4B1D8B, 0x84CB8A1B,
+ 0xDD7B8220, 0x84BDF285,
+ 0xDDABEC07, 0x84B06DF1,
+ 0xDDDC5B3A, 0x84A2FC62,
+ 0xDE0CCFB1, 0x84959DD9,
+ 0xDE3D4963, 0x84885257,
+ 0xDE6DC84B, 0x847B19E1,
+ 0xDE9E4C60, 0x846DF476,
+ 0xDECED59B, 0x8460E21A,
+ 0xDEFF63F4, 0x8453E2CE,
+ 0xDF2FF764, 0x8446F695,
+ 0xDF608FE3, 0x843A1D70,
+ 0xDF912D6A, 0x842D5761,
+ 0xDFC1CFF2, 0x8420A46B,
+ 0xDFF27773, 0x8414048F,
+ 0xE02323E5, 0x840777CF,
+ 0xE053D541, 0x83FAFE2E,
+ 0xE0848B7F, 0x83EE97AC,
+ 0xE0B54698, 0x83E2444D,
+ 0xE0E60684, 0x83D60411,
+ 0xE116CB3D, 0x83C9D6FB,
+ 0xE14794B9, 0x83BDBD0D,
+ 0xE17862F3, 0x83B1B649,
+ 0xE1A935E1, 0x83A5C2B0,
+ 0xE1DA0D7E, 0x8399E244,
+ 0xE20AE9C1, 0x838E1507,
+ 0xE23BCAA2, 0x83825AFB,
+ 0xE26CB01A, 0x8376B422,
+ 0xE29D9A22, 0x836B207D,
+ 0xE2CE88B2, 0x835FA00E,
+ 0xE2FF7BC3, 0x835432D8,
+ 0xE330734C, 0x8348D8DB,
+ 0xE3616F47, 0x833D921A,
+ 0xE3926FAC, 0x83325E97,
+ 0xE3C37473, 0x83273E52,
+ 0xE3F47D95, 0x831C314E,
+ 0xE4258B0A, 0x8311378C,
+ 0xE4569CCB, 0x8306510F,
+ 0xE487B2CF, 0x82FB7DD8,
+ 0xE4B8CD10, 0x82F0BDE8,
+ 0xE4E9EB86, 0x82E61141,
+ 0xE51B0E2A, 0x82DB77E5,
+ 0xE54C34F3, 0x82D0F1D5,
+ 0xE57D5FDA, 0x82C67F13,
+ 0xE5AE8ED8, 0x82BC1FA1,
+ 0xE5DFC1E4, 0x82B1D381,
+ 0xE610F8F9, 0x82A79AB3,
+ 0xE642340D, 0x829D753A,
+ 0xE6737319, 0x82936316,
+ 0xE6A4B616, 0x8289644A,
+ 0xE6D5FCFC, 0x827F78D8,
+ 0xE70747C3, 0x8275A0C0,
+ 0xE7389664, 0x826BDC04,
+ 0xE769E8D8, 0x82622AA5,
+ 0xE79B3F16, 0x82588CA6,
+ 0xE7CC9917, 0x824F0208,
+ 0xE7FDF6D3, 0x82458ACB,
+ 0xE82F5844, 0x823C26F2,
+ 0xE860BD60, 0x8232D67E,
+ 0xE8922621, 0x82299971,
+ 0xE8C3927F, 0x82206FCB,
+ 0xE8F50273, 0x8217598F,
+ 0xE92675F4, 0x820E56BE,
+ 0xE957ECFB, 0x82056758,
+ 0xE9896780, 0x81FC8B60,
+ 0xE9BAE57C, 0x81F3C2D7,
+ 0xE9EC66E8, 0x81EB0DBD,
+ 0xEA1DEBBB, 0x81E26C16,
+ 0xEA4F73EE, 0x81D9DDE1,
+ 0xEA80FF79, 0x81D16320,
+ 0xEAB28E55, 0x81C8FBD5,
+ 0xEAE4207A, 0x81C0A801,
+ 0xEB15B5E0, 0x81B867A4,
+ 0xEB474E80, 0x81B03AC1,
+ 0xEB78EA52, 0x81A82159,
+ 0xEBAA894E, 0x81A01B6C,
+ 0xEBDC2B6D, 0x819828FD,
+ 0xEC0DD0A8, 0x81904A0C,
+ 0xEC3F78F5, 0x81887E9A,
+ 0xEC71244F, 0x8180C6A9,
+ 0xECA2D2AC, 0x8179223A,
+ 0xECD48406, 0x8171914E,
+ 0xED063855, 0x816A13E6,
+ 0xED37EF91, 0x8162AA03,
+ 0xED69A9B2, 0x815B53A8,
+ 0xED9B66B2, 0x815410D3,
+ 0xEDCD2687, 0x814CE188,
+ 0xEDFEE92B, 0x8145C5C6,
+ 0xEE30AE95, 0x813EBD90,
+ 0xEE6276BF, 0x8137C8E6,
+ 0xEE9441A0, 0x8130E7C8,
+ 0xEEC60F31, 0x812A1A39,
+ 0xEEF7DF6A, 0x81236039,
+ 0xEF29B243, 0x811CB9CA,
+ 0xEF5B87B5, 0x811626EC,
+ 0xEF8D5FB8, 0x810FA7A0,
+ 0xEFBF3A44, 0x81093BE8,
+ 0xEFF11752, 0x8102E3C3,
+ 0xF022F6DA, 0x80FC9F35,
+ 0xF054D8D4, 0x80F66E3C,
+ 0xF086BD39, 0x80F050DB,
+ 0xF0B8A401, 0x80EA4712,
+ 0xF0EA8D23, 0x80E450E2,
+ 0xF11C789A, 0x80DE6E4C,
+ 0xF14E665C, 0x80D89F51,
+ 0xF1805662, 0x80D2E3F1,
+ 0xF1B248A5, 0x80CD3C2F,
+ 0xF1E43D1C, 0x80C7A80A,
+ 0xF21633C0, 0x80C22783,
+ 0xF2482C89, 0x80BCBA9C,
+ 0xF27A2770, 0x80B76155,
+ 0xF2AC246D, 0x80B21BAF,
+ 0xF2DE2378, 0x80ACE9AB,
+ 0xF310248A, 0x80A7CB49,
+ 0xF342279A, 0x80A2C08B,
+ 0xF3742CA1, 0x809DC970,
+ 0xF3A63398, 0x8098E5FB,
+ 0xF3D83C76, 0x8094162B,
+ 0xF40A4734, 0x808F5A02,
+ 0xF43C53CA, 0x808AB180,
+ 0xF46E6231, 0x80861CA5,
+ 0xF4A07260, 0x80819B74,
+ 0xF4D28451, 0x807D2DEB,
+ 0xF50497FA, 0x8078D40D,
+ 0xF536AD55, 0x80748DD9,
+ 0xF568C45A, 0x80705B50,
+ 0xF59ADD01, 0x806C3C73,
+ 0xF5CCF743, 0x80683143,
+ 0xF5FF1317, 0x806439C0,
+ 0xF6313076, 0x806055EA,
+ 0xF6634F58, 0x805C85C3,
+ 0xF6956FB6, 0x8058C94C,
+ 0xF6C79188, 0x80552083,
+ 0xF6F9B4C5, 0x80518B6B,
+ 0xF72BD967, 0x804E0A03,
+ 0xF75DFF65, 0x804A9C4D,
+ 0xF79026B8, 0x80474248,
+ 0xF7C24F58, 0x8043FBF6,
+ 0xF7F4793E, 0x8040C956,
+ 0xF826A461, 0x803DAA69,
+ 0xF858D0BA, 0x803A9F31,
+ 0xF88AFE41, 0x8037A7AC,
+ 0xF8BD2CEF, 0x8034C3DC,
+ 0xF8EF5CBB, 0x8031F3C1,
+ 0xF9218D9E, 0x802F375C,
+ 0xF953BF90, 0x802C8EAD,
+ 0xF985F28A, 0x8029F9B4,
+ 0xF9B82683, 0x80277872,
+ 0xF9EA5B75, 0x80250AE7,
+ 0xFA1C9156, 0x8022B113,
+ 0xFA4EC820, 0x80206AF8,
+ 0xFA80FFCB, 0x801E3894,
+ 0xFAB3384F, 0x801C19E9,
+ 0xFAE571A4, 0x801A0EF7,
+ 0xFB17ABC2, 0x801817BF,
+ 0xFB49E6A2, 0x80163440,
+ 0xFB7C223C, 0x8014647A,
+ 0xFBAE5E89, 0x8012A86F,
+ 0xFBE09B80, 0x8011001E,
+ 0xFC12D919, 0x800F6B88,
+ 0xFC45174E, 0x800DEAAC,
+ 0xFC775616, 0x800C7D8C,
+ 0xFCA99569, 0x800B2427,
+ 0xFCDBD541, 0x8009DE7D,
+ 0xFD0E1594, 0x8008AC90,
+ 0xFD40565B, 0x80078E5E,
+ 0xFD72978F, 0x800683E8,
+ 0xFDA4D928, 0x80058D2E,
+ 0xFDD71B1E, 0x8004AA31,
+ 0xFE095D69, 0x8003DAF0,
+ 0xFE3BA001, 0x80031F6C,
+ 0xFE6DE2E0, 0x800277A5,
+ 0xFEA025FC, 0x8001E39B,
+ 0xFED2694F, 0x8001634D,
+ 0xFF04ACD0, 0x8000F6BD,
+ 0xFF36F078, 0x80009DE9,
+ 0xFF69343E, 0x800058D3,
+ 0xFF9B781D, 0x8000277A,
+ 0xFFCDBC0A, 0x800009DE
+};
+
+
+
+/*
+* @brief q15 Twiddle factors Table
+*/
+
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 16 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_16_q15[24] = {
+ 0x7FFF, 0x0000,
+ 0x7641, 0x30FB,
+ 0x5A82, 0x5A82,
+ 0x30FB, 0x7641,
+ 0x0000, 0x7FFF,
+ 0xCF04, 0x7641,
+ 0xA57D, 0x5A82,
+ 0x89BE, 0x30FB,
+ 0x8000, 0x0000,
+ 0x89BE, 0xCF04,
+ 0xA57D, 0xA57D,
+ 0xCF04, 0x89BE
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 32 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_32_q15[48] = {
+ 0x7FFF, 0x0000,
+ 0x7D8A, 0x18F8,
+ 0x7641, 0x30FB,
+ 0x6A6D, 0x471C,
+ 0x5A82, 0x5A82,
+ 0x471C, 0x6A6D,
+ 0x30FB, 0x7641,
+ 0x18F8, 0x7D8A,
+ 0x0000, 0x7FFF,
+ 0xE707, 0x7D8A,
+ 0xCF04, 0x7641,
+ 0xB8E3, 0x6A6D,
+ 0xA57D, 0x5A82,
+ 0x9592, 0x471C,
+ 0x89BE, 0x30FB,
+ 0x8275, 0x18F8,
+ 0x8000, 0x0000,
+ 0x8275, 0xE707,
+ 0x89BE, 0xCF04,
+ 0x9592, 0xB8E3,
+ 0xA57D, 0xA57D,
+ 0xB8E3, 0x9592,
+ 0xCF04, 0x89BE,
+ 0xE707, 0x8275
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 64 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_64_q15[96] = {
+ 0x7FFF, 0x0000,
+ 0x7F62, 0x0C8B,
+ 0x7D8A, 0x18F8,
+ 0x7A7D, 0x2528,
+ 0x7641, 0x30FB,
+ 0x70E2, 0x3C56,
+ 0x6A6D, 0x471C,
+ 0x62F2, 0x5133,
+ 0x5A82, 0x5A82,
+ 0x5133, 0x62F2,
+ 0x471C, 0x6A6D,
+ 0x3C56, 0x70E2,
+ 0x30FB, 0x7641,
+ 0x2528, 0x7A7D,
+ 0x18F8, 0x7D8A,
+ 0x0C8B, 0x7F62,
+ 0x0000, 0x7FFF,
+ 0xF374, 0x7F62,
+ 0xE707, 0x7D8A,
+ 0xDAD7, 0x7A7D,
+ 0xCF04, 0x7641,
+ 0xC3A9, 0x70E2,
+ 0xB8E3, 0x6A6D,
+ 0xAECC, 0x62F2,
+ 0xA57D, 0x5A82,
+ 0x9D0D, 0x5133,
+ 0x9592, 0x471C,
+ 0x8F1D, 0x3C56,
+ 0x89BE, 0x30FB,
+ 0x8582, 0x2528,
+ 0x8275, 0x18F8,
+ 0x809D, 0x0C8B,
+ 0x8000, 0x0000,
+ 0x809D, 0xF374,
+ 0x8275, 0xE707,
+ 0x8582, 0xDAD7,
+ 0x89BE, 0xCF04,
+ 0x8F1D, 0xC3A9,
+ 0x9592, 0xB8E3,
+ 0x9D0D, 0xAECC,
+ 0xA57D, 0xA57D,
+ 0xAECC, 0x9D0D,
+ 0xB8E3, 0x9592,
+ 0xC3A9, 0x8F1D,
+ 0xCF04, 0x89BE,
+ 0xDAD7, 0x8582,
+ 0xE707, 0x8275,
+ 0xF374, 0x809D
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 128 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_128_q15[192] = {
+ 0x7FFF, 0x0000,
+ 0x7FD8, 0x0647,
+ 0x7F62, 0x0C8B,
+ 0x7E9D, 0x12C8,
+ 0x7D8A, 0x18F8,
+ 0x7C29, 0x1F19,
+ 0x7A7D, 0x2528,
+ 0x7884, 0x2B1F,
+ 0x7641, 0x30FB,
+ 0x73B5, 0x36BA,
+ 0x70E2, 0x3C56,
+ 0x6DCA, 0x41CE,
+ 0x6A6D, 0x471C,
+ 0x66CF, 0x4C3F,
+ 0x62F2, 0x5133,
+ 0x5ED7, 0x55F5,
+ 0x5A82, 0x5A82,
+ 0x55F5, 0x5ED7,
+ 0x5133, 0x62F2,
+ 0x4C3F, 0x66CF,
+ 0x471C, 0x6A6D,
+ 0x41CE, 0x6DCA,
+ 0x3C56, 0x70E2,
+ 0x36BA, 0x73B5,
+ 0x30FB, 0x7641,
+ 0x2B1F, 0x7884,
+ 0x2528, 0x7A7D,
+ 0x1F19, 0x7C29,
+ 0x18F8, 0x7D8A,
+ 0x12C8, 0x7E9D,
+ 0x0C8B, 0x7F62,
+ 0x0647, 0x7FD8,
+ 0x0000, 0x7FFF,
+ 0xF9B8, 0x7FD8,
+ 0xF374, 0x7F62,
+ 0xED37, 0x7E9D,
+ 0xE707, 0x7D8A,
+ 0xE0E6, 0x7C29,
+ 0xDAD7, 0x7A7D,
+ 0xD4E0, 0x7884,
+ 0xCF04, 0x7641,
+ 0xC945, 0x73B5,
+ 0xC3A9, 0x70E2,
+ 0xBE31, 0x6DCA,
+ 0xB8E3, 0x6A6D,
+ 0xB3C0, 0x66CF,
+ 0xAECC, 0x62F2,
+ 0xAA0A, 0x5ED7,
+ 0xA57D, 0x5A82,
+ 0xA128, 0x55F5,
+ 0x9D0D, 0x5133,
+ 0x9930, 0x4C3F,
+ 0x9592, 0x471C,
+ 0x9235, 0x41CE,
+ 0x8F1D, 0x3C56,
+ 0x8C4A, 0x36BA,
+ 0x89BE, 0x30FB,
+ 0x877B, 0x2B1F,
+ 0x8582, 0x2528,
+ 0x83D6, 0x1F19,
+ 0x8275, 0x18F8,
+ 0x8162, 0x12C8,
+ 0x809D, 0x0C8B,
+ 0x8027, 0x0647,
+ 0x8000, 0x0000,
+ 0x8027, 0xF9B8,
+ 0x809D, 0xF374,
+ 0x8162, 0xED37,
+ 0x8275, 0xE707,
+ 0x83D6, 0xE0E6,
+ 0x8582, 0xDAD7,
+ 0x877B, 0xD4E0,
+ 0x89BE, 0xCF04,
+ 0x8C4A, 0xC945,
+ 0x8F1D, 0xC3A9,
+ 0x9235, 0xBE31,
+ 0x9592, 0xB8E3,
+ 0x9930, 0xB3C0,
+ 0x9D0D, 0xAECC,
+ 0xA128, 0xAA0A,
+ 0xA57D, 0xA57D,
+ 0xAA0A, 0xA128,
+ 0xAECC, 0x9D0D,
+ 0xB3C0, 0x9930,
+ 0xB8E3, 0x9592,
+ 0xBE31, 0x9235,
+ 0xC3A9, 0x8F1D,
+ 0xC945, 0x8C4A,
+ 0xCF04, 0x89BE,
+ 0xD4E0, 0x877B,
+ 0xDAD7, 0x8582,
+ 0xE0E6, 0x83D6,
+ 0xE707, 0x8275,
+ 0xED37, 0x8162,
+ 0xF374, 0x809D,
+ 0xF9B8, 0x8027
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 256 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_256_q15[384] = {
+ 0x7FFF, 0x0000,
+ 0x7FF6, 0x0324,
+ 0x7FD8, 0x0647,
+ 0x7FA7, 0x096A,
+ 0x7F62, 0x0C8B,
+ 0x7F09, 0x0FAB,
+ 0x7E9D, 0x12C8,
+ 0x7E1D, 0x15E2,
+ 0x7D8A, 0x18F8,
+ 0x7CE3, 0x1C0B,
+ 0x7C29, 0x1F19,
+ 0x7B5D, 0x2223,
+ 0x7A7D, 0x2528,
+ 0x798A, 0x2826,
+ 0x7884, 0x2B1F,
+ 0x776C, 0x2E11,
+ 0x7641, 0x30FB,
+ 0x7504, 0x33DE,
+ 0x73B5, 0x36BA,
+ 0x7255, 0x398C,
+ 0x70E2, 0x3C56,
+ 0x6F5F, 0x3F17,
+ 0x6DCA, 0x41CE,
+ 0x6C24, 0x447A,
+ 0x6A6D, 0x471C,
+ 0x68A6, 0x49B4,
+ 0x66CF, 0x4C3F,
+ 0x64E8, 0x4EBF,
+ 0x62F2, 0x5133,
+ 0x60EC, 0x539B,
+ 0x5ED7, 0x55F5,
+ 0x5CB4, 0x5842,
+ 0x5A82, 0x5A82,
+ 0x5842, 0x5CB4,
+ 0x55F5, 0x5ED7,
+ 0x539B, 0x60EC,
+ 0x5133, 0x62F2,
+ 0x4EBF, 0x64E8,
+ 0x4C3F, 0x66CF,
+ 0x49B4, 0x68A6,
+ 0x471C, 0x6A6D,
+ 0x447A, 0x6C24,
+ 0x41CE, 0x6DCA,
+ 0x3F17, 0x6F5F,
+ 0x3C56, 0x70E2,
+ 0x398C, 0x7255,
+ 0x36BA, 0x73B5,
+ 0x33DE, 0x7504,
+ 0x30FB, 0x7641,
+ 0x2E11, 0x776C,
+ 0x2B1F, 0x7884,
+ 0x2826, 0x798A,
+ 0x2528, 0x7A7D,
+ 0x2223, 0x7B5D,
+ 0x1F19, 0x7C29,
+ 0x1C0B, 0x7CE3,
+ 0x18F8, 0x7D8A,
+ 0x15E2, 0x7E1D,
+ 0x12C8, 0x7E9D,
+ 0x0FAB, 0x7F09,
+ 0x0C8B, 0x7F62,
+ 0x096A, 0x7FA7,
+ 0x0647, 0x7FD8,
+ 0x0324, 0x7FF6,
+ 0x0000, 0x7FFF,
+ 0xFCDB, 0x7FF6,
+ 0xF9B8, 0x7FD8,
+ 0xF695, 0x7FA7,
+ 0xF374, 0x7F62,
+ 0xF054, 0x7F09,
+ 0xED37, 0x7E9D,
+ 0xEA1D, 0x7E1D,
+ 0xE707, 0x7D8A,
+ 0xE3F4, 0x7CE3,
+ 0xE0E6, 0x7C29,
+ 0xDDDC, 0x7B5D,
+ 0xDAD7, 0x7A7D,
+ 0xD7D9, 0x798A,
+ 0xD4E0, 0x7884,
+ 0xD1EE, 0x776C,
+ 0xCF04, 0x7641,
+ 0xCC21, 0x7504,
+ 0xC945, 0x73B5,
+ 0xC673, 0x7255,
+ 0xC3A9, 0x70E2,
+ 0xC0E8, 0x6F5F,
+ 0xBE31, 0x6DCA,
+ 0xBB85, 0x6C24,
+ 0xB8E3, 0x6A6D,
+ 0xB64B, 0x68A6,
+ 0xB3C0, 0x66CF,
+ 0xB140, 0x64E8,
+ 0xAECC, 0x62F2,
+ 0xAC64, 0x60EC,
+ 0xAA0A, 0x5ED7,
+ 0xA7BD, 0x5CB4,
+ 0xA57D, 0x5A82,
+ 0xA34B, 0x5842,
+ 0xA128, 0x55F5,
+ 0x9F13, 0x539B,
+ 0x9D0D, 0x5133,
+ 0x9B17, 0x4EBF,
+ 0x9930, 0x4C3F,
+ 0x9759, 0x49B4,
+ 0x9592, 0x471C,
+ 0x93DB, 0x447A,
+ 0x9235, 0x41CE,
+ 0x90A0, 0x3F17,
+ 0x8F1D, 0x3C56,
+ 0x8DAA, 0x398C,
+ 0x8C4A, 0x36BA,
+ 0x8AFB, 0x33DE,
+ 0x89BE, 0x30FB,
+ 0x8893, 0x2E11,
+ 0x877B, 0x2B1F,
+ 0x8675, 0x2826,
+ 0x8582, 0x2528,
+ 0x84A2, 0x2223,
+ 0x83D6, 0x1F19,
+ 0x831C, 0x1C0B,
+ 0x8275, 0x18F8,
+ 0x81E2, 0x15E2,
+ 0x8162, 0x12C8,
+ 0x80F6, 0x0FAB,
+ 0x809D, 0x0C8B,
+ 0x8058, 0x096A,
+ 0x8027, 0x0647,
+ 0x8009, 0x0324,
+ 0x8000, 0x0000,
+ 0x8009, 0xFCDB,
+ 0x8027, 0xF9B8,
+ 0x8058, 0xF695,
+ 0x809D, 0xF374,
+ 0x80F6, 0xF054,
+ 0x8162, 0xED37,
+ 0x81E2, 0xEA1D,
+ 0x8275, 0xE707,
+ 0x831C, 0xE3F4,
+ 0x83D6, 0xE0E6,
+ 0x84A2, 0xDDDC,
+ 0x8582, 0xDAD7,
+ 0x8675, 0xD7D9,
+ 0x877B, 0xD4E0,
+ 0x8893, 0xD1EE,
+ 0x89BE, 0xCF04,
+ 0x8AFB, 0xCC21,
+ 0x8C4A, 0xC945,
+ 0x8DAA, 0xC673,
+ 0x8F1D, 0xC3A9,
+ 0x90A0, 0xC0E8,
+ 0x9235, 0xBE31,
+ 0x93DB, 0xBB85,
+ 0x9592, 0xB8E3,
+ 0x9759, 0xB64B,
+ 0x9930, 0xB3C0,
+ 0x9B17, 0xB140,
+ 0x9D0D, 0xAECC,
+ 0x9F13, 0xAC64,
+ 0xA128, 0xAA0A,
+ 0xA34B, 0xA7BD,
+ 0xA57D, 0xA57D,
+ 0xA7BD, 0xA34B,
+ 0xAA0A, 0xA128,
+ 0xAC64, 0x9F13,
+ 0xAECC, 0x9D0D,
+ 0xB140, 0x9B17,
+ 0xB3C0, 0x9930,
+ 0xB64B, 0x9759,
+ 0xB8E3, 0x9592,
+ 0xBB85, 0x93DB,
+ 0xBE31, 0x9235,
+ 0xC0E8, 0x90A0,
+ 0xC3A9, 0x8F1D,
+ 0xC673, 0x8DAA,
+ 0xC945, 0x8C4A,
+ 0xCC21, 0x8AFB,
+ 0xCF04, 0x89BE,
+ 0xD1EE, 0x8893,
+ 0xD4E0, 0x877B,
+ 0xD7D9, 0x8675,
+ 0xDAD7, 0x8582,
+ 0xDDDC, 0x84A2,
+ 0xE0E6, 0x83D6,
+ 0xE3F4, 0x831C,
+ 0xE707, 0x8275,
+ 0xEA1D, 0x81E2,
+ 0xED37, 0x8162,
+ 0xF054, 0x80F6,
+ 0xF374, 0x809D,
+ 0xF695, 0x8058,
+ 0xF9B8, 0x8027,
+ 0xFCDB, 0x8009
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 512 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_512_q15[768] = {
+ 0x7FFF, 0x0000,
+ 0x7FFD, 0x0192,
+ 0x7FF6, 0x0324,
+ 0x7FE9, 0x04B6,
+ 0x7FD8, 0x0647,
+ 0x7FC2, 0x07D9,
+ 0x7FA7, 0x096A,
+ 0x7F87, 0x0AFB,
+ 0x7F62, 0x0C8B,
+ 0x7F38, 0x0E1B,
+ 0x7F09, 0x0FAB,
+ 0x7ED5, 0x1139,
+ 0x7E9D, 0x12C8,
+ 0x7E5F, 0x1455,
+ 0x7E1D, 0x15E2,
+ 0x7DD6, 0x176D,
+ 0x7D8A, 0x18F8,
+ 0x7D39, 0x1A82,
+ 0x7CE3, 0x1C0B,
+ 0x7C89, 0x1D93,
+ 0x7C29, 0x1F19,
+ 0x7BC5, 0x209F,
+ 0x7B5D, 0x2223,
+ 0x7AEF, 0x23A6,
+ 0x7A7D, 0x2528,
+ 0x7A05, 0x26A8,
+ 0x798A, 0x2826,
+ 0x7909, 0x29A3,
+ 0x7884, 0x2B1F,
+ 0x77FA, 0x2C98,
+ 0x776C, 0x2E11,
+ 0x76D9, 0x2F87,
+ 0x7641, 0x30FB,
+ 0x75A5, 0x326E,
+ 0x7504, 0x33DE,
+ 0x745F, 0x354D,
+ 0x73B5, 0x36BA,
+ 0x7307, 0x3824,
+ 0x7255, 0x398C,
+ 0x719E, 0x3AF2,
+ 0x70E2, 0x3C56,
+ 0x7023, 0x3DB8,
+ 0x6F5F, 0x3F17,
+ 0x6E96, 0x4073,
+ 0x6DCA, 0x41CE,
+ 0x6CF9, 0x4325,
+ 0x6C24, 0x447A,
+ 0x6B4A, 0x45CD,
+ 0x6A6D, 0x471C,
+ 0x698C, 0x4869,
+ 0x68A6, 0x49B4,
+ 0x67BD, 0x4AFB,
+ 0x66CF, 0x4C3F,
+ 0x65DD, 0x4D81,
+ 0x64E8, 0x4EBF,
+ 0x63EF, 0x4FFB,
+ 0x62F2, 0x5133,
+ 0x61F1, 0x5269,
+ 0x60EC, 0x539B,
+ 0x5FE3, 0x54CA,
+ 0x5ED7, 0x55F5,
+ 0x5DC7, 0x571D,
+ 0x5CB4, 0x5842,
+ 0x5B9D, 0x5964,
+ 0x5A82, 0x5A82,
+ 0x5964, 0x5B9D,
+ 0x5842, 0x5CB4,
+ 0x571D, 0x5DC7,
+ 0x55F5, 0x5ED7,
+ 0x54CA, 0x5FE3,
+ 0x539B, 0x60EC,
+ 0x5269, 0x61F1,
+ 0x5133, 0x62F2,
+ 0x4FFB, 0x63EF,
+ 0x4EBF, 0x64E8,
+ 0x4D81, 0x65DD,
+ 0x4C3F, 0x66CF,
+ 0x4AFB, 0x67BD,
+ 0x49B4, 0x68A6,
+ 0x4869, 0x698C,
+ 0x471C, 0x6A6D,
+ 0x45CD, 0x6B4A,
+ 0x447A, 0x6C24,
+ 0x4325, 0x6CF9,
+ 0x41CE, 0x6DCA,
+ 0x4073, 0x6E96,
+ 0x3F17, 0x6F5F,
+ 0x3DB8, 0x7023,
+ 0x3C56, 0x70E2,
+ 0x3AF2, 0x719E,
+ 0x398C, 0x7255,
+ 0x3824, 0x7307,
+ 0x36BA, 0x73B5,
+ 0x354D, 0x745F,
+ 0x33DE, 0x7504,
+ 0x326E, 0x75A5,
+ 0x30FB, 0x7641,
+ 0x2F87, 0x76D9,
+ 0x2E11, 0x776C,
+ 0x2C98, 0x77FA,
+ 0x2B1F, 0x7884,
+ 0x29A3, 0x7909,
+ 0x2826, 0x798A,
+ 0x26A8, 0x7A05,
+ 0x2528, 0x7A7D,
+ 0x23A6, 0x7AEF,
+ 0x2223, 0x7B5D,
+ 0x209F, 0x7BC5,
+ 0x1F19, 0x7C29,
+ 0x1D93, 0x7C89,
+ 0x1C0B, 0x7CE3,
+ 0x1A82, 0x7D39,
+ 0x18F8, 0x7D8A,
+ 0x176D, 0x7DD6,
+ 0x15E2, 0x7E1D,
+ 0x1455, 0x7E5F,
+ 0x12C8, 0x7E9D,
+ 0x1139, 0x7ED5,
+ 0x0FAB, 0x7F09,
+ 0x0E1B, 0x7F38,
+ 0x0C8B, 0x7F62,
+ 0x0AFB, 0x7F87,
+ 0x096A, 0x7FA7,
+ 0x07D9, 0x7FC2,
+ 0x0647, 0x7FD8,
+ 0x04B6, 0x7FE9,
+ 0x0324, 0x7FF6,
+ 0x0192, 0x7FFD,
+ 0x0000, 0x7FFF,
+ 0xFE6D, 0x7FFD,
+ 0xFCDB, 0x7FF6,
+ 0xFB49, 0x7FE9,
+ 0xF9B8, 0x7FD8,
+ 0xF826, 0x7FC2,
+ 0xF695, 0x7FA7,
+ 0xF504, 0x7F87,
+ 0xF374, 0x7F62,
+ 0xF1E4, 0x7F38,
+ 0xF054, 0x7F09,
+ 0xEEC6, 0x7ED5,
+ 0xED37, 0x7E9D,
+ 0xEBAA, 0x7E5F,
+ 0xEA1D, 0x7E1D,
+ 0xE892, 0x7DD6,
+ 0xE707, 0x7D8A,
+ 0xE57D, 0x7D39,
+ 0xE3F4, 0x7CE3,
+ 0xE26C, 0x7C89,
+ 0xE0E6, 0x7C29,
+ 0xDF60, 0x7BC5,
+ 0xDDDC, 0x7B5D,
+ 0xDC59, 0x7AEF,
+ 0xDAD7, 0x7A7D,
+ 0xD957, 0x7A05,
+ 0xD7D9, 0x798A,
+ 0xD65C, 0x7909,
+ 0xD4E0, 0x7884,
+ 0xD367, 0x77FA,
+ 0xD1EE, 0x776C,
+ 0xD078, 0x76D9,
+ 0xCF04, 0x7641,
+ 0xCD91, 0x75A5,
+ 0xCC21, 0x7504,
+ 0xCAB2, 0x745F,
+ 0xC945, 0x73B5,
+ 0xC7DB, 0x7307,
+ 0xC673, 0x7255,
+ 0xC50D, 0x719E,
+ 0xC3A9, 0x70E2,
+ 0xC247, 0x7023,
+ 0xC0E8, 0x6F5F,
+ 0xBF8C, 0x6E96,
+ 0xBE31, 0x6DCA,
+ 0xBCDA, 0x6CF9,
+ 0xBB85, 0x6C24,
+ 0xBA32, 0x6B4A,
+ 0xB8E3, 0x6A6D,
+ 0xB796, 0x698C,
+ 0xB64B, 0x68A6,
+ 0xB504, 0x67BD,
+ 0xB3C0, 0x66CF,
+ 0xB27E, 0x65DD,
+ 0xB140, 0x64E8,
+ 0xB004, 0x63EF,
+ 0xAECC, 0x62F2,
+ 0xAD96, 0x61F1,
+ 0xAC64, 0x60EC,
+ 0xAB35, 0x5FE3,
+ 0xAA0A, 0x5ED7,
+ 0xA8E2, 0x5DC7,
+ 0xA7BD, 0x5CB4,
+ 0xA69B, 0x5B9D,
+ 0xA57D, 0x5A82,
+ 0xA462, 0x5964,
+ 0xA34B, 0x5842,
+ 0xA238, 0x571D,
+ 0xA128, 0x55F5,
+ 0xA01C, 0x54CA,
+ 0x9F13, 0x539B,
+ 0x9E0E, 0x5269,
+ 0x9D0D, 0x5133,
+ 0x9C10, 0x4FFB,
+ 0x9B17, 0x4EBF,
+ 0x9A22, 0x4D81,
+ 0x9930, 0x4C3F,
+ 0x9842, 0x4AFB,
+ 0x9759, 0x49B4,
+ 0x9673, 0x4869,
+ 0x9592, 0x471C,
+ 0x94B5, 0x45CD,
+ 0x93DB, 0x447A,
+ 0x9306, 0x4325,
+ 0x9235, 0x41CE,
+ 0x9169, 0x4073,
+ 0x90A0, 0x3F17,
+ 0x8FDC, 0x3DB8,
+ 0x8F1D, 0x3C56,
+ 0x8E61, 0x3AF2,
+ 0x8DAA, 0x398C,
+ 0x8CF8, 0x3824,
+ 0x8C4A, 0x36BA,
+ 0x8BA0, 0x354D,
+ 0x8AFB, 0x33DE,
+ 0x8A5A, 0x326E,
+ 0x89BE, 0x30FB,
+ 0x8926, 0x2F87,
+ 0x8893, 0x2E11,
+ 0x8805, 0x2C98,
+ 0x877B, 0x2B1F,
+ 0x86F6, 0x29A3,
+ 0x8675, 0x2826,
+ 0x85FA, 0x26A8,
+ 0x8582, 0x2528,
+ 0x8510, 0x23A6,
+ 0x84A2, 0x2223,
+ 0x843A, 0x209F,
+ 0x83D6, 0x1F19,
+ 0x8376, 0x1D93,
+ 0x831C, 0x1C0B,
+ 0x82C6, 0x1A82,
+ 0x8275, 0x18F8,
+ 0x8229, 0x176D,
+ 0x81E2, 0x15E2,
+ 0x81A0, 0x1455,
+ 0x8162, 0x12C8,
+ 0x812A, 0x1139,
+ 0x80F6, 0x0FAB,
+ 0x80C7, 0x0E1B,
+ 0x809D, 0x0C8B,
+ 0x8078, 0x0AFB,
+ 0x8058, 0x096A,
+ 0x803D, 0x07D9,
+ 0x8027, 0x0647,
+ 0x8016, 0x04B6,
+ 0x8009, 0x0324,
+ 0x8002, 0x0192,
+ 0x8000, 0x0000,
+ 0x8002, 0xFE6D,
+ 0x8009, 0xFCDB,
+ 0x8016, 0xFB49,
+ 0x8027, 0xF9B8,
+ 0x803D, 0xF826,
+ 0x8058, 0xF695,
+ 0x8078, 0xF504,
+ 0x809D, 0xF374,
+ 0x80C7, 0xF1E4,
+ 0x80F6, 0xF054,
+ 0x812A, 0xEEC6,
+ 0x8162, 0xED37,
+ 0x81A0, 0xEBAA,
+ 0x81E2, 0xEA1D,
+ 0x8229, 0xE892,
+ 0x8275, 0xE707,
+ 0x82C6, 0xE57D,
+ 0x831C, 0xE3F4,
+ 0x8376, 0xE26C,
+ 0x83D6, 0xE0E6,
+ 0x843A, 0xDF60,
+ 0x84A2, 0xDDDC,
+ 0x8510, 0xDC59,
+ 0x8582, 0xDAD7,
+ 0x85FA, 0xD957,
+ 0x8675, 0xD7D9,
+ 0x86F6, 0xD65C,
+ 0x877B, 0xD4E0,
+ 0x8805, 0xD367,
+ 0x8893, 0xD1EE,
+ 0x8926, 0xD078,
+ 0x89BE, 0xCF04,
+ 0x8A5A, 0xCD91,
+ 0x8AFB, 0xCC21,
+ 0x8BA0, 0xCAB2,
+ 0x8C4A, 0xC945,
+ 0x8CF8, 0xC7DB,
+ 0x8DAA, 0xC673,
+ 0x8E61, 0xC50D,
+ 0x8F1D, 0xC3A9,
+ 0x8FDC, 0xC247,
+ 0x90A0, 0xC0E8,
+ 0x9169, 0xBF8C,
+ 0x9235, 0xBE31,
+ 0x9306, 0xBCDA,
+ 0x93DB, 0xBB85,
+ 0x94B5, 0xBA32,
+ 0x9592, 0xB8E3,
+ 0x9673, 0xB796,
+ 0x9759, 0xB64B,
+ 0x9842, 0xB504,
+ 0x9930, 0xB3C0,
+ 0x9A22, 0xB27E,
+ 0x9B17, 0xB140,
+ 0x9C10, 0xB004,
+ 0x9D0D, 0xAECC,
+ 0x9E0E, 0xAD96,
+ 0x9F13, 0xAC64,
+ 0xA01C, 0xAB35,
+ 0xA128, 0xAA0A,
+ 0xA238, 0xA8E2,
+ 0xA34B, 0xA7BD,
+ 0xA462, 0xA69B,
+ 0xA57D, 0xA57D,
+ 0xA69B, 0xA462,
+ 0xA7BD, 0xA34B,
+ 0xA8E2, 0xA238,
+ 0xAA0A, 0xA128,
+ 0xAB35, 0xA01C,
+ 0xAC64, 0x9F13,
+ 0xAD96, 0x9E0E,
+ 0xAECC, 0x9D0D,
+ 0xB004, 0x9C10,
+ 0xB140, 0x9B17,
+ 0xB27E, 0x9A22,
+ 0xB3C0, 0x9930,
+ 0xB504, 0x9842,
+ 0xB64B, 0x9759,
+ 0xB796, 0x9673,
+ 0xB8E3, 0x9592,
+ 0xBA32, 0x94B5,
+ 0xBB85, 0x93DB,
+ 0xBCDA, 0x9306,
+ 0xBE31, 0x9235,
+ 0xBF8C, 0x9169,
+ 0xC0E8, 0x90A0,
+ 0xC247, 0x8FDC,
+ 0xC3A9, 0x8F1D,
+ 0xC50D, 0x8E61,
+ 0xC673, 0x8DAA,
+ 0xC7DB, 0x8CF8,
+ 0xC945, 0x8C4A,
+ 0xCAB2, 0x8BA0,
+ 0xCC21, 0x8AFB,
+ 0xCD91, 0x8A5A,
+ 0xCF04, 0x89BE,
+ 0xD078, 0x8926,
+ 0xD1EE, 0x8893,
+ 0xD367, 0x8805,
+ 0xD4E0, 0x877B,
+ 0xD65C, 0x86F6,
+ 0xD7D9, 0x8675,
+ 0xD957, 0x85FA,
+ 0xDAD7, 0x8582,
+ 0xDC59, 0x8510,
+ 0xDDDC, 0x84A2,
+ 0xDF60, 0x843A,
+ 0xE0E6, 0x83D6,
+ 0xE26C, 0x8376,
+ 0xE3F4, 0x831C,
+ 0xE57D, 0x82C6,
+ 0xE707, 0x8275,
+ 0xE892, 0x8229,
+ 0xEA1D, 0x81E2,
+ 0xEBAA, 0x81A0,
+ 0xED37, 0x8162,
+ 0xEEC6, 0x812A,
+ 0xF054, 0x80F6,
+ 0xF1E4, 0x80C7,
+ 0xF374, 0x809D,
+ 0xF504, 0x8078,
+ 0xF695, 0x8058,
+ 0xF826, 0x803D,
+ 0xF9B8, 0x8027,
+ 0xFB49, 0x8016,
+ 0xFCDB, 0x8009,
+ 0xFE6D, 0x8002
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 1024 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_1024_q15[1536] = {
+ 0x7FFF, 0x0000,
+ 0x7FFF, 0x00C9,
+ 0x7FFD, 0x0192,
+ 0x7FFA, 0x025B,
+ 0x7FF6, 0x0324,
+ 0x7FF0, 0x03ED,
+ 0x7FE9, 0x04B6,
+ 0x7FE1, 0x057F,
+ 0x7FD8, 0x0647,
+ 0x7FCE, 0x0710,
+ 0x7FC2, 0x07D9,
+ 0x7FB5, 0x08A2,
+ 0x7FA7, 0x096A,
+ 0x7F97, 0x0A33,
+ 0x7F87, 0x0AFB,
+ 0x7F75, 0x0BC3,
+ 0x7F62, 0x0C8B,
+ 0x7F4D, 0x0D53,
+ 0x7F38, 0x0E1B,
+ 0x7F21, 0x0EE3,
+ 0x7F09, 0x0FAB,
+ 0x7EF0, 0x1072,
+ 0x7ED5, 0x1139,
+ 0x7EBA, 0x1201,
+ 0x7E9D, 0x12C8,
+ 0x7E7F, 0x138E,
+ 0x7E5F, 0x1455,
+ 0x7E3F, 0x151B,
+ 0x7E1D, 0x15E2,
+ 0x7DFA, 0x16A8,
+ 0x7DD6, 0x176D,
+ 0x7DB0, 0x1833,
+ 0x7D8A, 0x18F8,
+ 0x7D62, 0x19BD,
+ 0x7D39, 0x1A82,
+ 0x7D0F, 0x1B47,
+ 0x7CE3, 0x1C0B,
+ 0x7CB7, 0x1CCF,
+ 0x7C89, 0x1D93,
+ 0x7C5A, 0x1E56,
+ 0x7C29, 0x1F19,
+ 0x7BF8, 0x1FDC,
+ 0x7BC5, 0x209F,
+ 0x7B92, 0x2161,
+ 0x7B5D, 0x2223,
+ 0x7B26, 0x22E5,
+ 0x7AEF, 0x23A6,
+ 0x7AB6, 0x2467,
+ 0x7A7D, 0x2528,
+ 0x7A42, 0x25E8,
+ 0x7A05, 0x26A8,
+ 0x79C8, 0x2767,
+ 0x798A, 0x2826,
+ 0x794A, 0x28E5,
+ 0x7909, 0x29A3,
+ 0x78C7, 0x2A61,
+ 0x7884, 0x2B1F,
+ 0x7840, 0x2BDC,
+ 0x77FA, 0x2C98,
+ 0x77B4, 0x2D55,
+ 0x776C, 0x2E11,
+ 0x7723, 0x2ECC,
+ 0x76D9, 0x2F87,
+ 0x768E, 0x3041,
+ 0x7641, 0x30FB,
+ 0x75F4, 0x31B5,
+ 0x75A5, 0x326E,
+ 0x7555, 0x3326,
+ 0x7504, 0x33DE,
+ 0x74B2, 0x3496,
+ 0x745F, 0x354D,
+ 0x740B, 0x3604,
+ 0x73B5, 0x36BA,
+ 0x735F, 0x376F,
+ 0x7307, 0x3824,
+ 0x72AF, 0x38D8,
+ 0x7255, 0x398C,
+ 0x71FA, 0x3A40,
+ 0x719E, 0x3AF2,
+ 0x7141, 0x3BA5,
+ 0x70E2, 0x3C56,
+ 0x7083, 0x3D07,
+ 0x7023, 0x3DB8,
+ 0x6FC1, 0x3E68,
+ 0x6F5F, 0x3F17,
+ 0x6EFB, 0x3FC5,
+ 0x6E96, 0x4073,
+ 0x6E30, 0x4121,
+ 0x6DCA, 0x41CE,
+ 0x6D62, 0x427A,
+ 0x6CF9, 0x4325,
+ 0x6C8F, 0x43D0,
+ 0x6C24, 0x447A,
+ 0x6BB8, 0x4524,
+ 0x6B4A, 0x45CD,
+ 0x6ADC, 0x4675,
+ 0x6A6D, 0x471C,
+ 0x69FD, 0x47C3,
+ 0x698C, 0x4869,
+ 0x6919, 0x490F,
+ 0x68A6, 0x49B4,
+ 0x6832, 0x4A58,
+ 0x67BD, 0x4AFB,
+ 0x6746, 0x4B9E,
+ 0x66CF, 0x4C3F,
+ 0x6657, 0x4CE1,
+ 0x65DD, 0x4D81,
+ 0x6563, 0x4E21,
+ 0x64E8, 0x4EBF,
+ 0x646C, 0x4F5E,
+ 0x63EF, 0x4FFB,
+ 0x6371, 0x5097,
+ 0x62F2, 0x5133,
+ 0x6271, 0x51CE,
+ 0x61F1, 0x5269,
+ 0x616F, 0x5302,
+ 0x60EC, 0x539B,
+ 0x6068, 0x5433,
+ 0x5FE3, 0x54CA,
+ 0x5F5E, 0x5560,
+ 0x5ED7, 0x55F5,
+ 0x5E50, 0x568A,
+ 0x5DC7, 0x571D,
+ 0x5D3E, 0x57B0,
+ 0x5CB4, 0x5842,
+ 0x5C29, 0x58D4,
+ 0x5B9D, 0x5964,
+ 0x5B10, 0x59F3,
+ 0x5A82, 0x5A82,
+ 0x59F3, 0x5B10,
+ 0x5964, 0x5B9D,
+ 0x58D4, 0x5C29,
+ 0x5842, 0x5CB4,
+ 0x57B0, 0x5D3E,
+ 0x571D, 0x5DC7,
+ 0x568A, 0x5E50,
+ 0x55F5, 0x5ED7,
+ 0x5560, 0x5F5E,
+ 0x54CA, 0x5FE3,
+ 0x5433, 0x6068,
+ 0x539B, 0x60EC,
+ 0x5302, 0x616F,
+ 0x5269, 0x61F1,
+ 0x51CE, 0x6271,
+ 0x5133, 0x62F2,
+ 0x5097, 0x6371,
+ 0x4FFB, 0x63EF,
+ 0x4F5E, 0x646C,
+ 0x4EBF, 0x64E8,
+ 0x4E21, 0x6563,
+ 0x4D81, 0x65DD,
+ 0x4CE1, 0x6657,
+ 0x4C3F, 0x66CF,
+ 0x4B9E, 0x6746,
+ 0x4AFB, 0x67BD,
+ 0x4A58, 0x6832,
+ 0x49B4, 0x68A6,
+ 0x490F, 0x6919,
+ 0x4869, 0x698C,
+ 0x47C3, 0x69FD,
+ 0x471C, 0x6A6D,
+ 0x4675, 0x6ADC,
+ 0x45CD, 0x6B4A,
+ 0x4524, 0x6BB8,
+ 0x447A, 0x6C24,
+ 0x43D0, 0x6C8F,
+ 0x4325, 0x6CF9,
+ 0x427A, 0x6D62,
+ 0x41CE, 0x6DCA,
+ 0x4121, 0x6E30,
+ 0x4073, 0x6E96,
+ 0x3FC5, 0x6EFB,
+ 0x3F17, 0x6F5F,
+ 0x3E68, 0x6FC1,
+ 0x3DB8, 0x7023,
+ 0x3D07, 0x7083,
+ 0x3C56, 0x70E2,
+ 0x3BA5, 0x7141,
+ 0x3AF2, 0x719E,
+ 0x3A40, 0x71FA,
+ 0x398C, 0x7255,
+ 0x38D8, 0x72AF,
+ 0x3824, 0x7307,
+ 0x376F, 0x735F,
+ 0x36BA, 0x73B5,
+ 0x3604, 0x740B,
+ 0x354D, 0x745F,
+ 0x3496, 0x74B2,
+ 0x33DE, 0x7504,
+ 0x3326, 0x7555,
+ 0x326E, 0x75A5,
+ 0x31B5, 0x75F4,
+ 0x30FB, 0x7641,
+ 0x3041, 0x768E,
+ 0x2F87, 0x76D9,
+ 0x2ECC, 0x7723,
+ 0x2E11, 0x776C,
+ 0x2D55, 0x77B4,
+ 0x2C98, 0x77FA,
+ 0x2BDC, 0x7840,
+ 0x2B1F, 0x7884,
+ 0x2A61, 0x78C7,
+ 0x29A3, 0x7909,
+ 0x28E5, 0x794A,
+ 0x2826, 0x798A,
+ 0x2767, 0x79C8,
+ 0x26A8, 0x7A05,
+ 0x25E8, 0x7A42,
+ 0x2528, 0x7A7D,
+ 0x2467, 0x7AB6,
+ 0x23A6, 0x7AEF,
+ 0x22E5, 0x7B26,
+ 0x2223, 0x7B5D,
+ 0x2161, 0x7B92,
+ 0x209F, 0x7BC5,
+ 0x1FDC, 0x7BF8,
+ 0x1F19, 0x7C29,
+ 0x1E56, 0x7C5A,
+ 0x1D93, 0x7C89,
+ 0x1CCF, 0x7CB7,
+ 0x1C0B, 0x7CE3,
+ 0x1B47, 0x7D0F,
+ 0x1A82, 0x7D39,
+ 0x19BD, 0x7D62,
+ 0x18F8, 0x7D8A,
+ 0x1833, 0x7DB0,
+ 0x176D, 0x7DD6,
+ 0x16A8, 0x7DFA,
+ 0x15E2, 0x7E1D,
+ 0x151B, 0x7E3F,
+ 0x1455, 0x7E5F,
+ 0x138E, 0x7E7F,
+ 0x12C8, 0x7E9D,
+ 0x1201, 0x7EBA,
+ 0x1139, 0x7ED5,
+ 0x1072, 0x7EF0,
+ 0x0FAB, 0x7F09,
+ 0x0EE3, 0x7F21,
+ 0x0E1B, 0x7F38,
+ 0x0D53, 0x7F4D,
+ 0x0C8B, 0x7F62,
+ 0x0BC3, 0x7F75,
+ 0x0AFB, 0x7F87,
+ 0x0A33, 0x7F97,
+ 0x096A, 0x7FA7,
+ 0x08A2, 0x7FB5,
+ 0x07D9, 0x7FC2,
+ 0x0710, 0x7FCE,
+ 0x0647, 0x7FD8,
+ 0x057F, 0x7FE1,
+ 0x04B6, 0x7FE9,
+ 0x03ED, 0x7FF0,
+ 0x0324, 0x7FF6,
+ 0x025B, 0x7FFA,
+ 0x0192, 0x7FFD,
+ 0x00C9, 0x7FFF,
+ 0x0000, 0x7FFF,
+ 0xFF36, 0x7FFF,
+ 0xFE6D, 0x7FFD,
+ 0xFDA4, 0x7FFA,
+ 0xFCDB, 0x7FF6,
+ 0xFC12, 0x7FF0,
+ 0xFB49, 0x7FE9,
+ 0xFA80, 0x7FE1,
+ 0xF9B8, 0x7FD8,
+ 0xF8EF, 0x7FCE,
+ 0xF826, 0x7FC2,
+ 0xF75D, 0x7FB5,
+ 0xF695, 0x7FA7,
+ 0xF5CC, 0x7F97,
+ 0xF504, 0x7F87,
+ 0xF43C, 0x7F75,
+ 0xF374, 0x7F62,
+ 0xF2AC, 0x7F4D,
+ 0xF1E4, 0x7F38,
+ 0xF11C, 0x7F21,
+ 0xF054, 0x7F09,
+ 0xEF8D, 0x7EF0,
+ 0xEEC6, 0x7ED5,
+ 0xEDFE, 0x7EBA,
+ 0xED37, 0x7E9D,
+ 0xEC71, 0x7E7F,
+ 0xEBAA, 0x7E5F,
+ 0xEAE4, 0x7E3F,
+ 0xEA1D, 0x7E1D,
+ 0xE957, 0x7DFA,
+ 0xE892, 0x7DD6,
+ 0xE7CC, 0x7DB0,
+ 0xE707, 0x7D8A,
+ 0xE642, 0x7D62,
+ 0xE57D, 0x7D39,
+ 0xE4B8, 0x7D0F,
+ 0xE3F4, 0x7CE3,
+ 0xE330, 0x7CB7,
+ 0xE26C, 0x7C89,
+ 0xE1A9, 0x7C5A,
+ 0xE0E6, 0x7C29,
+ 0xE023, 0x7BF8,
+ 0xDF60, 0x7BC5,
+ 0xDE9E, 0x7B92,
+ 0xDDDC, 0x7B5D,
+ 0xDD1A, 0x7B26,
+ 0xDC59, 0x7AEF,
+ 0xDB98, 0x7AB6,
+ 0xDAD7, 0x7A7D,
+ 0xDA17, 0x7A42,
+ 0xD957, 0x7A05,
+ 0xD898, 0x79C8,
+ 0xD7D9, 0x798A,
+ 0xD71A, 0x794A,
+ 0xD65C, 0x7909,
+ 0xD59E, 0x78C7,
+ 0xD4E0, 0x7884,
+ 0xD423, 0x7840,
+ 0xD367, 0x77FA,
+ 0xD2AA, 0x77B4,
+ 0xD1EE, 0x776C,
+ 0xD133, 0x7723,
+ 0xD078, 0x76D9,
+ 0xCFBE, 0x768E,
+ 0xCF04, 0x7641,
+ 0xCE4A, 0x75F4,
+ 0xCD91, 0x75A5,
+ 0xCCD9, 0x7555,
+ 0xCC21, 0x7504,
+ 0xCB69, 0x74B2,
+ 0xCAB2, 0x745F,
+ 0xC9FB, 0x740B,
+ 0xC945, 0x73B5,
+ 0xC890, 0x735F,
+ 0xC7DB, 0x7307,
+ 0xC727, 0x72AF,
+ 0xC673, 0x7255,
+ 0xC5BF, 0x71FA,
+ 0xC50D, 0x719E,
+ 0xC45A, 0x7141,
+ 0xC3A9, 0x70E2,
+ 0xC2F8, 0x7083,
+ 0xC247, 0x7023,
+ 0xC197, 0x6FC1,
+ 0xC0E8, 0x6F5F,
+ 0xC03A, 0x6EFB,
+ 0xBF8C, 0x6E96,
+ 0xBEDE, 0x6E30,
+ 0xBE31, 0x6DCA,
+ 0xBD85, 0x6D62,
+ 0xBCDA, 0x6CF9,
+ 0xBC2F, 0x6C8F,
+ 0xBB85, 0x6C24,
+ 0xBADB, 0x6BB8,
+ 0xBA32, 0x6B4A,
+ 0xB98A, 0x6ADC,
+ 0xB8E3, 0x6A6D,
+ 0xB83C, 0x69FD,
+ 0xB796, 0x698C,
+ 0xB6F0, 0x6919,
+ 0xB64B, 0x68A6,
+ 0xB5A7, 0x6832,
+ 0xB504, 0x67BD,
+ 0xB461, 0x6746,
+ 0xB3C0, 0x66CF,
+ 0xB31E, 0x6657,
+ 0xB27E, 0x65DD,
+ 0xB1DE, 0x6563,
+ 0xB140, 0x64E8,
+ 0xB0A1, 0x646C,
+ 0xB004, 0x63EF,
+ 0xAF68, 0x6371,
+ 0xAECC, 0x62F2,
+ 0xAE31, 0x6271,
+ 0xAD96, 0x61F1,
+ 0xACFD, 0x616F,
+ 0xAC64, 0x60EC,
+ 0xABCC, 0x6068,
+ 0xAB35, 0x5FE3,
+ 0xAA9F, 0x5F5E,
+ 0xAA0A, 0x5ED7,
+ 0xA975, 0x5E50,
+ 0xA8E2, 0x5DC7,
+ 0xA84F, 0x5D3E,
+ 0xA7BD, 0x5CB4,
+ 0xA72B, 0x5C29,
+ 0xA69B, 0x5B9D,
+ 0xA60C, 0x5B10,
+ 0xA57D, 0x5A82,
+ 0xA4EF, 0x59F3,
+ 0xA462, 0x5964,
+ 0xA3D6, 0x58D4,
+ 0xA34B, 0x5842,
+ 0xA2C1, 0x57B0,
+ 0xA238, 0x571D,
+ 0xA1AF, 0x568A,
+ 0xA128, 0x55F5,
+ 0xA0A1, 0x5560,
+ 0xA01C, 0x54CA,
+ 0x9F97, 0x5433,
+ 0x9F13, 0x539B,
+ 0x9E90, 0x5302,
+ 0x9E0E, 0x5269,
+ 0x9D8E, 0x51CE,
+ 0x9D0D, 0x5133,
+ 0x9C8E, 0x5097,
+ 0x9C10, 0x4FFB,
+ 0x9B93, 0x4F5E,
+ 0x9B17, 0x4EBF,
+ 0x9A9C, 0x4E21,
+ 0x9A22, 0x4D81,
+ 0x99A8, 0x4CE1,
+ 0x9930, 0x4C3F,
+ 0x98B9, 0x4B9E,
+ 0x9842, 0x4AFB,
+ 0x97CD, 0x4A58,
+ 0x9759, 0x49B4,
+ 0x96E6, 0x490F,
+ 0x9673, 0x4869,
+ 0x9602, 0x47C3,
+ 0x9592, 0x471C,
+ 0x9523, 0x4675,
+ 0x94B5, 0x45CD,
+ 0x9447, 0x4524,
+ 0x93DB, 0x447A,
+ 0x9370, 0x43D0,
+ 0x9306, 0x4325,
+ 0x929D, 0x427A,
+ 0x9235, 0x41CE,
+ 0x91CF, 0x4121,
+ 0x9169, 0x4073,
+ 0x9104, 0x3FC5,
+ 0x90A0, 0x3F17,
+ 0x903E, 0x3E68,
+ 0x8FDC, 0x3DB8,
+ 0x8F7C, 0x3D07,
+ 0x8F1D, 0x3C56,
+ 0x8EBE, 0x3BA5,
+ 0x8E61, 0x3AF2,
+ 0x8E05, 0x3A40,
+ 0x8DAA, 0x398C,
+ 0x8D50, 0x38D8,
+ 0x8CF8, 0x3824,
+ 0x8CA0, 0x376F,
+ 0x8C4A, 0x36BA,
+ 0x8BF4, 0x3604,
+ 0x8BA0, 0x354D,
+ 0x8B4D, 0x3496,
+ 0x8AFB, 0x33DE,
+ 0x8AAA, 0x3326,
+ 0x8A5A, 0x326E,
+ 0x8A0B, 0x31B5,
+ 0x89BE, 0x30FB,
+ 0x8971, 0x3041,
+ 0x8926, 0x2F87,
+ 0x88DC, 0x2ECC,
+ 0x8893, 0x2E11,
+ 0x884B, 0x2D55,
+ 0x8805, 0x2C98,
+ 0x87BF, 0x2BDC,
+ 0x877B, 0x2B1F,
+ 0x8738, 0x2A61,
+ 0x86F6, 0x29A3,
+ 0x86B5, 0x28E5,
+ 0x8675, 0x2826,
+ 0x8637, 0x2767,
+ 0x85FA, 0x26A8,
+ 0x85BD, 0x25E8,
+ 0x8582, 0x2528,
+ 0x8549, 0x2467,
+ 0x8510, 0x23A6,
+ 0x84D9, 0x22E5,
+ 0x84A2, 0x2223,
+ 0x846D, 0x2161,
+ 0x843A, 0x209F,
+ 0x8407, 0x1FDC,
+ 0x83D6, 0x1F19,
+ 0x83A5, 0x1E56,
+ 0x8376, 0x1D93,
+ 0x8348, 0x1CCF,
+ 0x831C, 0x1C0B,
+ 0x82F0, 0x1B47,
+ 0x82C6, 0x1A82,
+ 0x829D, 0x19BD,
+ 0x8275, 0x18F8,
+ 0x824F, 0x1833,
+ 0x8229, 0x176D,
+ 0x8205, 0x16A8,
+ 0x81E2, 0x15E2,
+ 0x81C0, 0x151B,
+ 0x81A0, 0x1455,
+ 0x8180, 0x138E,
+ 0x8162, 0x12C8,
+ 0x8145, 0x1201,
+ 0x812A, 0x1139,
+ 0x810F, 0x1072,
+ 0x80F6, 0x0FAB,
+ 0x80DE, 0x0EE3,
+ 0x80C7, 0x0E1B,
+ 0x80B2, 0x0D53,
+ 0x809D, 0x0C8B,
+ 0x808A, 0x0BC3,
+ 0x8078, 0x0AFB,
+ 0x8068, 0x0A33,
+ 0x8058, 0x096A,
+ 0x804A, 0x08A2,
+ 0x803D, 0x07D9,
+ 0x8031, 0x0710,
+ 0x8027, 0x0647,
+ 0x801E, 0x057F,
+ 0x8016, 0x04B6,
+ 0x800F, 0x03ED,
+ 0x8009, 0x0324,
+ 0x8005, 0x025B,
+ 0x8002, 0x0192,
+ 0x8000, 0x00C9,
+ 0x8000, 0x0000,
+ 0x8000, 0xFF36,
+ 0x8002, 0xFE6D,
+ 0x8005, 0xFDA4,
+ 0x8009, 0xFCDB,
+ 0x800F, 0xFC12,
+ 0x8016, 0xFB49,
+ 0x801E, 0xFA80,
+ 0x8027, 0xF9B8,
+ 0x8031, 0xF8EF,
+ 0x803D, 0xF826,
+ 0x804A, 0xF75D,
+ 0x8058, 0xF695,
+ 0x8068, 0xF5CC,
+ 0x8078, 0xF504,
+ 0x808A, 0xF43C,
+ 0x809D, 0xF374,
+ 0x80B2, 0xF2AC,
+ 0x80C7, 0xF1E4,
+ 0x80DE, 0xF11C,
+ 0x80F6, 0xF054,
+ 0x810F, 0xEF8D,
+ 0x812A, 0xEEC6,
+ 0x8145, 0xEDFE,
+ 0x8162, 0xED37,
+ 0x8180, 0xEC71,
+ 0x81A0, 0xEBAA,
+ 0x81C0, 0xEAE4,
+ 0x81E2, 0xEA1D,
+ 0x8205, 0xE957,
+ 0x8229, 0xE892,
+ 0x824F, 0xE7CC,
+ 0x8275, 0xE707,
+ 0x829D, 0xE642,
+ 0x82C6, 0xE57D,
+ 0x82F0, 0xE4B8,
+ 0x831C, 0xE3F4,
+ 0x8348, 0xE330,
+ 0x8376, 0xE26C,
+ 0x83A5, 0xE1A9,
+ 0x83D6, 0xE0E6,
+ 0x8407, 0xE023,
+ 0x843A, 0xDF60,
+ 0x846D, 0xDE9E,
+ 0x84A2, 0xDDDC,
+ 0x84D9, 0xDD1A,
+ 0x8510, 0xDC59,
+ 0x8549, 0xDB98,
+ 0x8582, 0xDAD7,
+ 0x85BD, 0xDA17,
+ 0x85FA, 0xD957,
+ 0x8637, 0xD898,
+ 0x8675, 0xD7D9,
+ 0x86B5, 0xD71A,
+ 0x86F6, 0xD65C,
+ 0x8738, 0xD59E,
+ 0x877B, 0xD4E0,
+ 0x87BF, 0xD423,
+ 0x8805, 0xD367,
+ 0x884B, 0xD2AA,
+ 0x8893, 0xD1EE,
+ 0x88DC, 0xD133,
+ 0x8926, 0xD078,
+ 0x8971, 0xCFBE,
+ 0x89BE, 0xCF04,
+ 0x8A0B, 0xCE4A,
+ 0x8A5A, 0xCD91,
+ 0x8AAA, 0xCCD9,
+ 0x8AFB, 0xCC21,
+ 0x8B4D, 0xCB69,
+ 0x8BA0, 0xCAB2,
+ 0x8BF4, 0xC9FB,
+ 0x8C4A, 0xC945,
+ 0x8CA0, 0xC890,
+ 0x8CF8, 0xC7DB,
+ 0x8D50, 0xC727,
+ 0x8DAA, 0xC673,
+ 0x8E05, 0xC5BF,
+ 0x8E61, 0xC50D,
+ 0x8EBE, 0xC45A,
+ 0x8F1D, 0xC3A9,
+ 0x8F7C, 0xC2F8,
+ 0x8FDC, 0xC247,
+ 0x903E, 0xC197,
+ 0x90A0, 0xC0E8,
+ 0x9104, 0xC03A,
+ 0x9169, 0xBF8C,
+ 0x91CF, 0xBEDE,
+ 0x9235, 0xBE31,
+ 0x929D, 0xBD85,
+ 0x9306, 0xBCDA,
+ 0x9370, 0xBC2F,
+ 0x93DB, 0xBB85,
+ 0x9447, 0xBADB,
+ 0x94B5, 0xBA32,
+ 0x9523, 0xB98A,
+ 0x9592, 0xB8E3,
+ 0x9602, 0xB83C,
+ 0x9673, 0xB796,
+ 0x96E6, 0xB6F0,
+ 0x9759, 0xB64B,
+ 0x97CD, 0xB5A7,
+ 0x9842, 0xB504,
+ 0x98B9, 0xB461,
+ 0x9930, 0xB3C0,
+ 0x99A8, 0xB31E,
+ 0x9A22, 0xB27E,
+ 0x9A9C, 0xB1DE,
+ 0x9B17, 0xB140,
+ 0x9B93, 0xB0A1,
+ 0x9C10, 0xB004,
+ 0x9C8E, 0xAF68,
+ 0x9D0D, 0xAECC,
+ 0x9D8E, 0xAE31,
+ 0x9E0E, 0xAD96,
+ 0x9E90, 0xACFD,
+ 0x9F13, 0xAC64,
+ 0x9F97, 0xABCC,
+ 0xA01C, 0xAB35,
+ 0xA0A1, 0xAA9F,
+ 0xA128, 0xAA0A,
+ 0xA1AF, 0xA975,
+ 0xA238, 0xA8E2,
+ 0xA2C1, 0xA84F,
+ 0xA34B, 0xA7BD,
+ 0xA3D6, 0xA72B,
+ 0xA462, 0xA69B,
+ 0xA4EF, 0xA60C,
+ 0xA57D, 0xA57D,
+ 0xA60C, 0xA4EF,
+ 0xA69B, 0xA462,
+ 0xA72B, 0xA3D6,
+ 0xA7BD, 0xA34B,
+ 0xA84F, 0xA2C1,
+ 0xA8E2, 0xA238,
+ 0xA975, 0xA1AF,
+ 0xAA0A, 0xA128,
+ 0xAA9F, 0xA0A1,
+ 0xAB35, 0xA01C,
+ 0xABCC, 0x9F97,
+ 0xAC64, 0x9F13,
+ 0xACFD, 0x9E90,
+ 0xAD96, 0x9E0E,
+ 0xAE31, 0x9D8E,
+ 0xAECC, 0x9D0D,
+ 0xAF68, 0x9C8E,
+ 0xB004, 0x9C10,
+ 0xB0A1, 0x9B93,
+ 0xB140, 0x9B17,
+ 0xB1DE, 0x9A9C,
+ 0xB27E, 0x9A22,
+ 0xB31E, 0x99A8,
+ 0xB3C0, 0x9930,
+ 0xB461, 0x98B9,
+ 0xB504, 0x9842,
+ 0xB5A7, 0x97CD,
+ 0xB64B, 0x9759,
+ 0xB6F0, 0x96E6,
+ 0xB796, 0x9673,
+ 0xB83C, 0x9602,
+ 0xB8E3, 0x9592,
+ 0xB98A, 0x9523,
+ 0xBA32, 0x94B5,
+ 0xBADB, 0x9447,
+ 0xBB85, 0x93DB,
+ 0xBC2F, 0x9370,
+ 0xBCDA, 0x9306,
+ 0xBD85, 0x929D,
+ 0xBE31, 0x9235,
+ 0xBEDE, 0x91CF,
+ 0xBF8C, 0x9169,
+ 0xC03A, 0x9104,
+ 0xC0E8, 0x90A0,
+ 0xC197, 0x903E,
+ 0xC247, 0x8FDC,
+ 0xC2F8, 0x8F7C,
+ 0xC3A9, 0x8F1D,
+ 0xC45A, 0x8EBE,
+ 0xC50D, 0x8E61,
+ 0xC5BF, 0x8E05,
+ 0xC673, 0x8DAA,
+ 0xC727, 0x8D50,
+ 0xC7DB, 0x8CF8,
+ 0xC890, 0x8CA0,
+ 0xC945, 0x8C4A,
+ 0xC9FB, 0x8BF4,
+ 0xCAB2, 0x8BA0,
+ 0xCB69, 0x8B4D,
+ 0xCC21, 0x8AFB,
+ 0xCCD9, 0x8AAA,
+ 0xCD91, 0x8A5A,
+ 0xCE4A, 0x8A0B,
+ 0xCF04, 0x89BE,
+ 0xCFBE, 0x8971,
+ 0xD078, 0x8926,
+ 0xD133, 0x88DC,
+ 0xD1EE, 0x8893,
+ 0xD2AA, 0x884B,
+ 0xD367, 0x8805,
+ 0xD423, 0x87BF,
+ 0xD4E0, 0x877B,
+ 0xD59E, 0x8738,
+ 0xD65C, 0x86F6,
+ 0xD71A, 0x86B5,
+ 0xD7D9, 0x8675,
+ 0xD898, 0x8637,
+ 0xD957, 0x85FA,
+ 0xDA17, 0x85BD,
+ 0xDAD7, 0x8582,
+ 0xDB98, 0x8549,
+ 0xDC59, 0x8510,
+ 0xDD1A, 0x84D9,
+ 0xDDDC, 0x84A2,
+ 0xDE9E, 0x846D,
+ 0xDF60, 0x843A,
+ 0xE023, 0x8407,
+ 0xE0E6, 0x83D6,
+ 0xE1A9, 0x83A5,
+ 0xE26C, 0x8376,
+ 0xE330, 0x8348,
+ 0xE3F4, 0x831C,
+ 0xE4B8, 0x82F0,
+ 0xE57D, 0x82C6,
+ 0xE642, 0x829D,
+ 0xE707, 0x8275,
+ 0xE7CC, 0x824F,
+ 0xE892, 0x8229,
+ 0xE957, 0x8205,
+ 0xEA1D, 0x81E2,
+ 0xEAE4, 0x81C0,
+ 0xEBAA, 0x81A0,
+ 0xEC71, 0x8180,
+ 0xED37, 0x8162,
+ 0xEDFE, 0x8145,
+ 0xEEC6, 0x812A,
+ 0xEF8D, 0x810F,
+ 0xF054, 0x80F6,
+ 0xF11C, 0x80DE,
+ 0xF1E4, 0x80C7,
+ 0xF2AC, 0x80B2,
+ 0xF374, 0x809D,
+ 0xF43C, 0x808A,
+ 0xF504, 0x8078,
+ 0xF5CC, 0x8068,
+ 0xF695, 0x8058,
+ 0xF75D, 0x804A,
+ 0xF826, 0x803D,
+ 0xF8EF, 0x8031,
+ 0xF9B8, 0x8027,
+ 0xFA80, 0x801E,
+ 0xFB49, 0x8016,
+ 0xFC12, 0x800F,
+ 0xFCDB, 0x8009,
+ 0xFDA4, 0x8005,
+ 0xFE6D, 0x8002,
+ 0xFF36, 0x8000
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 2048 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_2048_q15[3072] = {
+ 0x7FFF, 0x0000,
+ 0x7FFF, 0x0064,
+ 0x7FFF, 0x00C9,
+ 0x7FFE, 0x012D,
+ 0x7FFD, 0x0192,
+ 0x7FFC, 0x01F6,
+ 0x7FFA, 0x025B,
+ 0x7FF8, 0x02BF,
+ 0x7FF6, 0x0324,
+ 0x7FF3, 0x0388,
+ 0x7FF0, 0x03ED,
+ 0x7FED, 0x0451,
+ 0x7FE9, 0x04B6,
+ 0x7FE5, 0x051A,
+ 0x7FE1, 0x057F,
+ 0x7FDD, 0x05E3,
+ 0x7FD8, 0x0647,
+ 0x7FD3, 0x06AC,
+ 0x7FCE, 0x0710,
+ 0x7FC8, 0x0775,
+ 0x7FC2, 0x07D9,
+ 0x7FBC, 0x083D,
+ 0x7FB5, 0x08A2,
+ 0x7FAE, 0x0906,
+ 0x7FA7, 0x096A,
+ 0x7F9F, 0x09CE,
+ 0x7F97, 0x0A33,
+ 0x7F8F, 0x0A97,
+ 0x7F87, 0x0AFB,
+ 0x7F7E, 0x0B5F,
+ 0x7F75, 0x0BC3,
+ 0x7F6B, 0x0C27,
+ 0x7F62, 0x0C8B,
+ 0x7F58, 0x0CEF,
+ 0x7F4D, 0x0D53,
+ 0x7F43, 0x0DB7,
+ 0x7F38, 0x0E1B,
+ 0x7F2D, 0x0E7F,
+ 0x7F21, 0x0EE3,
+ 0x7F15, 0x0F47,
+ 0x7F09, 0x0FAB,
+ 0x7EFD, 0x100E,
+ 0x7EF0, 0x1072,
+ 0x7EE3, 0x10D6,
+ 0x7ED5, 0x1139,
+ 0x7EC8, 0x119D,
+ 0x7EBA, 0x1201,
+ 0x7EAB, 0x1264,
+ 0x7E9D, 0x12C8,
+ 0x7E8E, 0x132B,
+ 0x7E7F, 0x138E,
+ 0x7E6F, 0x13F2,
+ 0x7E5F, 0x1455,
+ 0x7E4F, 0x14B8,
+ 0x7E3F, 0x151B,
+ 0x7E2E, 0x157F,
+ 0x7E1D, 0x15E2,
+ 0x7E0C, 0x1645,
+ 0x7DFA, 0x16A8,
+ 0x7DE8, 0x170A,
+ 0x7DD6, 0x176D,
+ 0x7DC3, 0x17D0,
+ 0x7DB0, 0x1833,
+ 0x7D9D, 0x1896,
+ 0x7D8A, 0x18F8,
+ 0x7D76, 0x195B,
+ 0x7D62, 0x19BD,
+ 0x7D4E, 0x1A20,
+ 0x7D39, 0x1A82,
+ 0x7D24, 0x1AE4,
+ 0x7D0F, 0x1B47,
+ 0x7CF9, 0x1BA9,
+ 0x7CE3, 0x1C0B,
+ 0x7CCD, 0x1C6D,
+ 0x7CB7, 0x1CCF,
+ 0x7CA0, 0x1D31,
+ 0x7C89, 0x1D93,
+ 0x7C71, 0x1DF5,
+ 0x7C5A, 0x1E56,
+ 0x7C42, 0x1EB8,
+ 0x7C29, 0x1F19,
+ 0x7C11, 0x1F7B,
+ 0x7BF8, 0x1FDC,
+ 0x7BDF, 0x203E,
+ 0x7BC5, 0x209F,
+ 0x7BAC, 0x2100,
+ 0x7B92, 0x2161,
+ 0x7B77, 0x21C2,
+ 0x7B5D, 0x2223,
+ 0x7B42, 0x2284,
+ 0x7B26, 0x22E5,
+ 0x7B0B, 0x2345,
+ 0x7AEF, 0x23A6,
+ 0x7AD3, 0x2407,
+ 0x7AB6, 0x2467,
+ 0x7A9A, 0x24C7,
+ 0x7A7D, 0x2528,
+ 0x7A5F, 0x2588,
+ 0x7A42, 0x25E8,
+ 0x7A24, 0x2648,
+ 0x7A05, 0x26A8,
+ 0x79E7, 0x2707,
+ 0x79C8, 0x2767,
+ 0x79A9, 0x27C7,
+ 0x798A, 0x2826,
+ 0x796A, 0x2886,
+ 0x794A, 0x28E5,
+ 0x792A, 0x2944,
+ 0x7909, 0x29A3,
+ 0x78E8, 0x2A02,
+ 0x78C7, 0x2A61,
+ 0x78A6, 0x2AC0,
+ 0x7884, 0x2B1F,
+ 0x7862, 0x2B7D,
+ 0x7840, 0x2BDC,
+ 0x781D, 0x2C3A,
+ 0x77FA, 0x2C98,
+ 0x77D7, 0x2CF7,
+ 0x77B4, 0x2D55,
+ 0x7790, 0x2DB3,
+ 0x776C, 0x2E11,
+ 0x7747, 0x2E6E,
+ 0x7723, 0x2ECC,
+ 0x76FE, 0x2F29,
+ 0x76D9, 0x2F87,
+ 0x76B3, 0x2FE4,
+ 0x768E, 0x3041,
+ 0x7668, 0x309E,
+ 0x7641, 0x30FB,
+ 0x761B, 0x3158,
+ 0x75F4, 0x31B5,
+ 0x75CC, 0x3211,
+ 0x75A5, 0x326E,
+ 0x757D, 0x32CA,
+ 0x7555, 0x3326,
+ 0x752D, 0x3382,
+ 0x7504, 0x33DE,
+ 0x74DB, 0x343A,
+ 0x74B2, 0x3496,
+ 0x7489, 0x34F2,
+ 0x745F, 0x354D,
+ 0x7435, 0x35A8,
+ 0x740B, 0x3604,
+ 0x73E0, 0x365F,
+ 0x73B5, 0x36BA,
+ 0x738A, 0x3714,
+ 0x735F, 0x376F,
+ 0x7333, 0x37CA,
+ 0x7307, 0x3824,
+ 0x72DB, 0x387E,
+ 0x72AF, 0x38D8,
+ 0x7282, 0x3932,
+ 0x7255, 0x398C,
+ 0x7227, 0x39E6,
+ 0x71FA, 0x3A40,
+ 0x71CC, 0x3A99,
+ 0x719E, 0x3AF2,
+ 0x716F, 0x3B4C,
+ 0x7141, 0x3BA5,
+ 0x7112, 0x3BFD,
+ 0x70E2, 0x3C56,
+ 0x70B3, 0x3CAF,
+ 0x7083, 0x3D07,
+ 0x7053, 0x3D60,
+ 0x7023, 0x3DB8,
+ 0x6FF2, 0x3E10,
+ 0x6FC1, 0x3E68,
+ 0x6F90, 0x3EBF,
+ 0x6F5F, 0x3F17,
+ 0x6F2D, 0x3F6E,
+ 0x6EFB, 0x3FC5,
+ 0x6EC9, 0x401D,
+ 0x6E96, 0x4073,
+ 0x6E63, 0x40CA,
+ 0x6E30, 0x4121,
+ 0x6DFD, 0x4177,
+ 0x6DCA, 0x41CE,
+ 0x6D96, 0x4224,
+ 0x6D62, 0x427A,
+ 0x6D2D, 0x42D0,
+ 0x6CF9, 0x4325,
+ 0x6CC4, 0x437B,
+ 0x6C8F, 0x43D0,
+ 0x6C59, 0x4425,
+ 0x6C24, 0x447A,
+ 0x6BEE, 0x44CF,
+ 0x6BB8, 0x4524,
+ 0x6B81, 0x4578,
+ 0x6B4A, 0x45CD,
+ 0x6B13, 0x4621,
+ 0x6ADC, 0x4675,
+ 0x6AA5, 0x46C9,
+ 0x6A6D, 0x471C,
+ 0x6A35, 0x4770,
+ 0x69FD, 0x47C3,
+ 0x69C4, 0x4816,
+ 0x698C, 0x4869,
+ 0x6953, 0x48BC,
+ 0x6919, 0x490F,
+ 0x68E0, 0x4961,
+ 0x68A6, 0x49B4,
+ 0x686C, 0x4A06,
+ 0x6832, 0x4A58,
+ 0x67F7, 0x4AA9,
+ 0x67BD, 0x4AFB,
+ 0x6782, 0x4B4C,
+ 0x6746, 0x4B9E,
+ 0x670B, 0x4BEF,
+ 0x66CF, 0x4C3F,
+ 0x6693, 0x4C90,
+ 0x6657, 0x4CE1,
+ 0x661A, 0x4D31,
+ 0x65DD, 0x4D81,
+ 0x65A0, 0x4DD1,
+ 0x6563, 0x4E21,
+ 0x6526, 0x4E70,
+ 0x64E8, 0x4EBF,
+ 0x64AA, 0x4F0F,
+ 0x646C, 0x4F5E,
+ 0x642D, 0x4FAC,
+ 0x63EF, 0x4FFB,
+ 0x63B0, 0x5049,
+ 0x6371, 0x5097,
+ 0x6331, 0x50E5,
+ 0x62F2, 0x5133,
+ 0x62B2, 0x5181,
+ 0x6271, 0x51CE,
+ 0x6231, 0x521C,
+ 0x61F1, 0x5269,
+ 0x61B0, 0x52B5,
+ 0x616F, 0x5302,
+ 0x612D, 0x534E,
+ 0x60EC, 0x539B,
+ 0x60AA, 0x53E7,
+ 0x6068, 0x5433,
+ 0x6026, 0x547E,
+ 0x5FE3, 0x54CA,
+ 0x5FA0, 0x5515,
+ 0x5F5E, 0x5560,
+ 0x5F1A, 0x55AB,
+ 0x5ED7, 0x55F5,
+ 0x5E93, 0x5640,
+ 0x5E50, 0x568A,
+ 0x5E0B, 0x56D4,
+ 0x5DC7, 0x571D,
+ 0x5D83, 0x5767,
+ 0x5D3E, 0x57B0,
+ 0x5CF9, 0x57F9,
+ 0x5CB4, 0x5842,
+ 0x5C6E, 0x588B,
+ 0x5C29, 0x58D4,
+ 0x5BE3, 0x591C,
+ 0x5B9D, 0x5964,
+ 0x5B56, 0x59AC,
+ 0x5B10, 0x59F3,
+ 0x5AC9, 0x5A3B,
+ 0x5A82, 0x5A82,
+ 0x5A3B, 0x5AC9,
+ 0x59F3, 0x5B10,
+ 0x59AC, 0x5B56,
+ 0x5964, 0x5B9D,
+ 0x591C, 0x5BE3,
+ 0x58D4, 0x5C29,
+ 0x588B, 0x5C6E,
+ 0x5842, 0x5CB4,
+ 0x57F9, 0x5CF9,
+ 0x57B0, 0x5D3E,
+ 0x5767, 0x5D83,
+ 0x571D, 0x5DC7,
+ 0x56D4, 0x5E0B,
+ 0x568A, 0x5E50,
+ 0x5640, 0x5E93,
+ 0x55F5, 0x5ED7,
+ 0x55AB, 0x5F1A,
+ 0x5560, 0x5F5E,
+ 0x5515, 0x5FA0,
+ 0x54CA, 0x5FE3,
+ 0x547E, 0x6026,
+ 0x5433, 0x6068,
+ 0x53E7, 0x60AA,
+ 0x539B, 0x60EC,
+ 0x534E, 0x612D,
+ 0x5302, 0x616F,
+ 0x52B5, 0x61B0,
+ 0x5269, 0x61F1,
+ 0x521C, 0x6231,
+ 0x51CE, 0x6271,
+ 0x5181, 0x62B2,
+ 0x5133, 0x62F2,
+ 0x50E5, 0x6331,
+ 0x5097, 0x6371,
+ 0x5049, 0x63B0,
+ 0x4FFB, 0x63EF,
+ 0x4FAC, 0x642D,
+ 0x4F5E, 0x646C,
+ 0x4F0F, 0x64AA,
+ 0x4EBF, 0x64E8,
+ 0x4E70, 0x6526,
+ 0x4E21, 0x6563,
+ 0x4DD1, 0x65A0,
+ 0x4D81, 0x65DD,
+ 0x4D31, 0x661A,
+ 0x4CE1, 0x6657,
+ 0x4C90, 0x6693,
+ 0x4C3F, 0x66CF,
+ 0x4BEF, 0x670B,
+ 0x4B9E, 0x6746,
+ 0x4B4C, 0x6782,
+ 0x4AFB, 0x67BD,
+ 0x4AA9, 0x67F7,
+ 0x4A58, 0x6832,
+ 0x4A06, 0x686C,
+ 0x49B4, 0x68A6,
+ 0x4961, 0x68E0,
+ 0x490F, 0x6919,
+ 0x48BC, 0x6953,
+ 0x4869, 0x698C,
+ 0x4816, 0x69C4,
+ 0x47C3, 0x69FD,
+ 0x4770, 0x6A35,
+ 0x471C, 0x6A6D,
+ 0x46C9, 0x6AA5,
+ 0x4675, 0x6ADC,
+ 0x4621, 0x6B13,
+ 0x45CD, 0x6B4A,
+ 0x4578, 0x6B81,
+ 0x4524, 0x6BB8,
+ 0x44CF, 0x6BEE,
+ 0x447A, 0x6C24,
+ 0x4425, 0x6C59,
+ 0x43D0, 0x6C8F,
+ 0x437B, 0x6CC4,
+ 0x4325, 0x6CF9,
+ 0x42D0, 0x6D2D,
+ 0x427A, 0x6D62,
+ 0x4224, 0x6D96,
+ 0x41CE, 0x6DCA,
+ 0x4177, 0x6DFD,
+ 0x4121, 0x6E30,
+ 0x40CA, 0x6E63,
+ 0x4073, 0x6E96,
+ 0x401D, 0x6EC9,
+ 0x3FC5, 0x6EFB,
+ 0x3F6E, 0x6F2D,
+ 0x3F17, 0x6F5F,
+ 0x3EBF, 0x6F90,
+ 0x3E68, 0x6FC1,
+ 0x3E10, 0x6FF2,
+ 0x3DB8, 0x7023,
+ 0x3D60, 0x7053,
+ 0x3D07, 0x7083,
+ 0x3CAF, 0x70B3,
+ 0x3C56, 0x70E2,
+ 0x3BFD, 0x7112,
+ 0x3BA5, 0x7141,
+ 0x3B4C, 0x716F,
+ 0x3AF2, 0x719E,
+ 0x3A99, 0x71CC,
+ 0x3A40, 0x71FA,
+ 0x39E6, 0x7227,
+ 0x398C, 0x7255,
+ 0x3932, 0x7282,
+ 0x38D8, 0x72AF,
+ 0x387E, 0x72DB,
+ 0x3824, 0x7307,
+ 0x37CA, 0x7333,
+ 0x376F, 0x735F,
+ 0x3714, 0x738A,
+ 0x36BA, 0x73B5,
+ 0x365F, 0x73E0,
+ 0x3604, 0x740B,
+ 0x35A8, 0x7435,
+ 0x354D, 0x745F,
+ 0x34F2, 0x7489,
+ 0x3496, 0x74B2,
+ 0x343A, 0x74DB,
+ 0x33DE, 0x7504,
+ 0x3382, 0x752D,
+ 0x3326, 0x7555,
+ 0x32CA, 0x757D,
+ 0x326E, 0x75A5,
+ 0x3211, 0x75CC,
+ 0x31B5, 0x75F4,
+ 0x3158, 0x761B,
+ 0x30FB, 0x7641,
+ 0x309E, 0x7668,
+ 0x3041, 0x768E,
+ 0x2FE4, 0x76B3,
+ 0x2F87, 0x76D9,
+ 0x2F29, 0x76FE,
+ 0x2ECC, 0x7723,
+ 0x2E6E, 0x7747,
+ 0x2E11, 0x776C,
+ 0x2DB3, 0x7790,
+ 0x2D55, 0x77B4,
+ 0x2CF7, 0x77D7,
+ 0x2C98, 0x77FA,
+ 0x2C3A, 0x781D,
+ 0x2BDC, 0x7840,
+ 0x2B7D, 0x7862,
+ 0x2B1F, 0x7884,
+ 0x2AC0, 0x78A6,
+ 0x2A61, 0x78C7,
+ 0x2A02, 0x78E8,
+ 0x29A3, 0x7909,
+ 0x2944, 0x792A,
+ 0x28E5, 0x794A,
+ 0x2886, 0x796A,
+ 0x2826, 0x798A,
+ 0x27C7, 0x79A9,
+ 0x2767, 0x79C8,
+ 0x2707, 0x79E7,
+ 0x26A8, 0x7A05,
+ 0x2648, 0x7A24,
+ 0x25E8, 0x7A42,
+ 0x2588, 0x7A5F,
+ 0x2528, 0x7A7D,
+ 0x24C7, 0x7A9A,
+ 0x2467, 0x7AB6,
+ 0x2407, 0x7AD3,
+ 0x23A6, 0x7AEF,
+ 0x2345, 0x7B0B,
+ 0x22E5, 0x7B26,
+ 0x2284, 0x7B42,
+ 0x2223, 0x7B5D,
+ 0x21C2, 0x7B77,
+ 0x2161, 0x7B92,
+ 0x2100, 0x7BAC,
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+ 0x203E, 0x7BDF,
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+ 0xE51B, 0x7D24,
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+ 0xE20A, 0x7C71,
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+ 0xE084, 0x7C11,
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+ 0xDEFF, 0x7BAC,
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+ 0xDE3D, 0x7B77,
+ 0xDDDC, 0x7B5D,
+ 0xDD7B, 0x7B42,
+ 0xDD1A, 0x7B26,
+ 0xDCBA, 0x7B0B,
+ 0xDC59, 0x7AEF,
+ 0xDBF8, 0x7AD3,
+ 0xDB98, 0x7AB6,
+ 0xDB38, 0x7A9A,
+ 0xDAD7, 0x7A7D,
+ 0xDA77, 0x7A5F,
+ 0xDA17, 0x7A42,
+ 0xD9B7, 0x7A24,
+ 0xD957, 0x7A05,
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+ 0xD779, 0x796A,
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+ 0xD6BB, 0x792A,
+ 0xD65C, 0x7909,
+ 0xD5FD, 0x78E8,
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+ 0xD4E0, 0x7884,
+ 0xD482, 0x7862,
+ 0xD423, 0x7840,
+ 0xD3C5, 0x781D,
+ 0xD367, 0x77FA,
+ 0xD308, 0x77D7,
+ 0xD2AA, 0x77B4,
+ 0xD24C, 0x7790,
+ 0xD1EE, 0x776C,
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+ 0xD133, 0x7723,
+ 0xD0D6, 0x76FE,
+ 0xD078, 0x76D9,
+ 0xD01B, 0x76B3,
+ 0xCFBE, 0x768E,
+ 0xCF61, 0x7668,
+ 0xCF04, 0x7641,
+ 0xCEA7, 0x761B,
+ 0xCE4A, 0x75F4,
+ 0xCDEE, 0x75CC,
+ 0xCD91, 0x75A5,
+ 0xCD35, 0x757D,
+ 0xCCD9, 0x7555,
+ 0xCC7D, 0x752D,
+ 0xCC21, 0x7504,
+ 0xCBC5, 0x74DB,
+ 0xCB69, 0x74B2,
+ 0xCB0D, 0x7489,
+ 0xCAB2, 0x745F,
+ 0xCA57, 0x7435,
+ 0xC9FB, 0x740B,
+ 0xC9A0, 0x73E0,
+ 0xC945, 0x73B5,
+ 0xC8EB, 0x738A,
+ 0xC890, 0x735F,
+ 0xC835, 0x7333,
+ 0xC7DB, 0x7307,
+ 0xC781, 0x72DB,
+ 0xC727, 0x72AF,
+ 0xC6CD, 0x7282,
+ 0xC673, 0x7255,
+ 0xC619, 0x7227,
+ 0xC5BF, 0x71FA,
+ 0xC566, 0x71CC,
+ 0xC50D, 0x719E,
+ 0xC4B3, 0x716F,
+ 0xC45A, 0x7141,
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+ 0xC3A9, 0x70E2,
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+ 0xC2F8, 0x7083,
+ 0xC29F, 0x7053,
+ 0xC247, 0x7023,
+ 0xC1EF, 0x6FF2,
+ 0xC197, 0x6FC1,
+ 0xC140, 0x6F90,
+ 0xC0E8, 0x6F5F,
+ 0xC091, 0x6F2D,
+ 0xC03A, 0x6EFB,
+ 0xBFE2, 0x6EC9,
+ 0xBF8C, 0x6E96,
+ 0xBF35, 0x6E63,
+ 0xBEDE, 0x6E30,
+ 0xBE88, 0x6DFD,
+ 0xBE31, 0x6DCA,
+ 0xBDDB, 0x6D96,
+ 0xBD85, 0x6D62,
+ 0xBD2F, 0x6D2D,
+ 0xBCDA, 0x6CF9,
+ 0xBC84, 0x6CC4,
+ 0xBC2F, 0x6C8F,
+ 0xBBDA, 0x6C59,
+ 0xBB85, 0x6C24,
+ 0xBB30, 0x6BEE,
+ 0xBADB, 0x6BB8,
+ 0xBA87, 0x6B81,
+ 0xBA32, 0x6B4A,
+ 0xB9DE, 0x6B13,
+ 0xB98A, 0x6ADC,
+ 0xB936, 0x6AA5,
+ 0xB8E3, 0x6A6D,
+ 0xB88F, 0x6A35,
+ 0xB83C, 0x69FD,
+ 0xB7E9, 0x69C4,
+ 0xB796, 0x698C,
+ 0xB743, 0x6953,
+ 0xB6F0, 0x6919,
+ 0xB69E, 0x68E0,
+ 0xB64B, 0x68A6,
+ 0xB5F9, 0x686C,
+ 0xB5A7, 0x6832,
+ 0xB556, 0x67F7,
+ 0xB504, 0x67BD,
+ 0xB4B3, 0x6782,
+ 0xB461, 0x6746,
+ 0xB410, 0x670B,
+ 0xB3C0, 0x66CF,
+ 0xB36F, 0x6693,
+ 0xB31E, 0x6657,
+ 0xB2CE, 0x661A,
+ 0xB27E, 0x65DD,
+ 0xB22E, 0x65A0,
+ 0xB1DE, 0x6563,
+ 0xB18F, 0x6526,
+ 0xB140, 0x64E8,
+ 0xB0F0, 0x64AA,
+ 0xB0A1, 0x646C,
+ 0xB053, 0x642D,
+ 0xB004, 0x63EF,
+ 0xAFB6, 0x63B0,
+ 0xAF68, 0x6371,
+ 0xAF1A, 0x6331,
+ 0xAECC, 0x62F2,
+ 0xAE7E, 0x62B2,
+ 0xAE31, 0x6271,
+ 0xADE3, 0x6231,
+ 0xAD96, 0x61F1,
+ 0xAD4A, 0x61B0,
+ 0xACFD, 0x616F,
+ 0xACB1, 0x612D,
+ 0xAC64, 0x60EC,
+ 0xAC18, 0x60AA,
+ 0xABCC, 0x6068,
+ 0xAB81, 0x6026,
+ 0xAB35, 0x5FE3,
+ 0xAAEA, 0x5FA0,
+ 0xAA9F, 0x5F5E,
+ 0xAA54, 0x5F1A,
+ 0xAA0A, 0x5ED7,
+ 0xA9BF, 0x5E93,
+ 0xA975, 0x5E50,
+ 0xA92B, 0x5E0B,
+ 0xA8E2, 0x5DC7,
+ 0xA898, 0x5D83,
+ 0xA84F, 0x5D3E,
+ 0xA806, 0x5CF9,
+ 0xA7BD, 0x5CB4,
+ 0xA774, 0x5C6E,
+ 0xA72B, 0x5C29,
+ 0xA6E3, 0x5BE3,
+ 0xA69B, 0x5B9D,
+ 0xA653, 0x5B56,
+ 0xA60C, 0x5B10,
+ 0xA5C4, 0x5AC9,
+ 0xA57D, 0x5A82,
+ 0xA536, 0x5A3B,
+ 0xA4EF, 0x59F3,
+ 0xA4A9, 0x59AC,
+ 0xA462, 0x5964,
+ 0xA41C, 0x591C,
+ 0xA3D6, 0x58D4,
+ 0xA391, 0x588B,
+ 0xA34B, 0x5842,
+ 0xA306, 0x57F9,
+ 0xA2C1, 0x57B0,
+ 0xA27C, 0x5767,
+ 0xA238, 0x571D,
+ 0xA1F4, 0x56D4,
+ 0xA1AF, 0x568A,
+ 0xA16C, 0x5640,
+ 0xA128, 0x55F5,
+ 0xA0E5, 0x55AB,
+ 0xA0A1, 0x5560,
+ 0xA05F, 0x5515,
+ 0xA01C, 0x54CA,
+ 0x9FD9, 0x547E,
+ 0x9F97, 0x5433,
+ 0x9F55, 0x53E7,
+ 0x9F13, 0x539B,
+ 0x9ED2, 0x534E,
+ 0x9E90, 0x5302,
+ 0x9E4F, 0x52B5,
+ 0x9E0E, 0x5269,
+ 0x9DCE, 0x521C,
+ 0x9D8E, 0x51CE,
+ 0x9D4D, 0x5181,
+ 0x9D0D, 0x5133,
+ 0x9CCE, 0x50E5,
+ 0x9C8E, 0x5097,
+ 0x9C4F, 0x5049,
+ 0x9C10, 0x4FFB,
+ 0x9BD2, 0x4FAC,
+ 0x9B93, 0x4F5E,
+ 0x9B55, 0x4F0F,
+ 0x9B17, 0x4EBF,
+ 0x9AD9, 0x4E70,
+ 0x9A9C, 0x4E21,
+ 0x9A5F, 0x4DD1,
+ 0x9A22, 0x4D81,
+ 0x99E5, 0x4D31,
+ 0x99A8, 0x4CE1,
+ 0x996C, 0x4C90,
+ 0x9930, 0x4C3F,
+ 0x98F4, 0x4BEF,
+ 0x98B9, 0x4B9E,
+ 0x987D, 0x4B4C,
+ 0x9842, 0x4AFB,
+ 0x9808, 0x4AA9,
+ 0x97CD, 0x4A58,
+ 0x9793, 0x4A06,
+ 0x9759, 0x49B4,
+ 0x971F, 0x4961,
+ 0x96E6, 0x490F,
+ 0x96AC, 0x48BC,
+ 0x9673, 0x4869,
+ 0x963B, 0x4816,
+ 0x9602, 0x47C3,
+ 0x95CA, 0x4770,
+ 0x9592, 0x471C,
+ 0x955A, 0x46C9,
+ 0x9523, 0x4675,
+ 0x94EC, 0x4621,
+ 0x94B5, 0x45CD,
+ 0x947E, 0x4578,
+ 0x9447, 0x4524,
+ 0x9411, 0x44CF,
+ 0x93DB, 0x447A,
+ 0x93A6, 0x4425,
+ 0x9370, 0x43D0,
+ 0x933B, 0x437B,
+ 0x9306, 0x4325,
+ 0x92D2, 0x42D0,
+ 0x929D, 0x427A,
+ 0x9269, 0x4224,
+ 0x9235, 0x41CE,
+ 0x9202, 0x4177,
+ 0x91CF, 0x4121,
+ 0x919C, 0x40CA,
+ 0x9169, 0x4073,
+ 0x9136, 0x401D,
+ 0x9104, 0x3FC5,
+ 0x90D2, 0x3F6E,
+ 0x90A0, 0x3F17,
+ 0x906F, 0x3EBF,
+ 0x903E, 0x3E68,
+ 0x900D, 0x3E10,
+ 0x8FDC, 0x3DB8,
+ 0x8FAC, 0x3D60,
+ 0x8F7C, 0x3D07,
+ 0x8F4C, 0x3CAF,
+ 0x8F1D, 0x3C56,
+ 0x8EED, 0x3BFD,
+ 0x8EBE, 0x3BA5,
+ 0x8E90, 0x3B4C,
+ 0x8E61, 0x3AF2,
+ 0x8E33, 0x3A99,
+ 0x8E05, 0x3A40,
+ 0x8DD8, 0x39E6,
+ 0x8DAA, 0x398C,
+ 0x8D7D, 0x3932,
+ 0x8D50, 0x38D8,
+ 0x8D24, 0x387E,
+ 0x8CF8, 0x3824,
+ 0x8CCC, 0x37CA,
+ 0x8CA0, 0x376F,
+ 0x8C75, 0x3714,
+ 0x8C4A, 0x36BA,
+ 0x8C1F, 0x365F,
+ 0x8BF4, 0x3604,
+ 0x8BCA, 0x35A8,
+ 0x8BA0, 0x354D,
+ 0x8B76, 0x34F2,
+ 0x8B4D, 0x3496,
+ 0x8B24, 0x343A,
+ 0x8AFB, 0x33DE,
+ 0x8AD2, 0x3382,
+ 0x8AAA, 0x3326,
+ 0x8A82, 0x32CA,
+ 0x8A5A, 0x326E,
+ 0x8A33, 0x3211,
+ 0x8A0B, 0x31B5,
+ 0x89E4, 0x3158,
+ 0x89BE, 0x30FB,
+ 0x8997, 0x309E,
+ 0x8971, 0x3041,
+ 0x894C, 0x2FE4,
+ 0x8926, 0x2F87,
+ 0x8901, 0x2F29,
+ 0x88DC, 0x2ECC,
+ 0x88B8, 0x2E6E,
+ 0x8893, 0x2E11,
+ 0x886F, 0x2DB3,
+ 0x884B, 0x2D55,
+ 0x8828, 0x2CF7,
+ 0x8805, 0x2C98,
+ 0x87E2, 0x2C3A,
+ 0x87BF, 0x2BDC,
+ 0x879D, 0x2B7D,
+ 0x877B, 0x2B1F,
+ 0x8759, 0x2AC0,
+ 0x8738, 0x2A61,
+ 0x8717, 0x2A02,
+ 0x86F6, 0x29A3,
+ 0x86D5, 0x2944,
+ 0x86B5, 0x28E5,
+ 0x8695, 0x2886,
+ 0x8675, 0x2826,
+ 0x8656, 0x27C7,
+ 0x8637, 0x2767,
+ 0x8618, 0x2707,
+ 0x85FA, 0x26A8,
+ 0x85DB, 0x2648,
+ 0x85BD, 0x25E8,
+ 0x85A0, 0x2588,
+ 0x8582, 0x2528,
+ 0x8565, 0x24C7,
+ 0x8549, 0x2467,
+ 0x852C, 0x2407,
+ 0x8510, 0x23A6,
+ 0x84F4, 0x2345,
+ 0x84D9, 0x22E5,
+ 0x84BD, 0x2284,
+ 0x84A2, 0x2223,
+ 0x8488, 0x21C2,
+ 0x846D, 0x2161,
+ 0x8453, 0x2100,
+ 0x843A, 0x209F,
+ 0x8420, 0x203E,
+ 0x8407, 0x1FDC,
+ 0x83EE, 0x1F7B,
+ 0x83D6, 0x1F19,
+ 0x83BD, 0x1EB8,
+ 0x83A5, 0x1E56,
+ 0x838E, 0x1DF5,
+ 0x8376, 0x1D93,
+ 0x835F, 0x1D31,
+ 0x8348, 0x1CCF,
+ 0x8332, 0x1C6D,
+ 0x831C, 0x1C0B,
+ 0x8306, 0x1BA9,
+ 0x82F0, 0x1B47,
+ 0x82DB, 0x1AE4,
+ 0x82C6, 0x1A82,
+ 0x82B1, 0x1A20,
+ 0x829D, 0x19BD,
+ 0x8289, 0x195B,
+ 0x8275, 0x18F8,
+ 0x8262, 0x1896,
+ 0x824F, 0x1833,
+ 0x823C, 0x17D0,
+ 0x8229, 0x176D,
+ 0x8217, 0x170A,
+ 0x8205, 0x16A8,
+ 0x81F3, 0x1645,
+ 0x81E2, 0x15E2,
+ 0x81D1, 0x157F,
+ 0x81C0, 0x151B,
+ 0x81B0, 0x14B8,
+ 0x81A0, 0x1455,
+ 0x8190, 0x13F2,
+ 0x8180, 0x138E,
+ 0x8171, 0x132B,
+ 0x8162, 0x12C8,
+ 0x8154, 0x1264,
+ 0x8145, 0x1201,
+ 0x8137, 0x119D,
+ 0x812A, 0x1139,
+ 0x811C, 0x10D6,
+ 0x810F, 0x1072,
+ 0x8102, 0x100E,
+ 0x80F6, 0x0FAB,
+ 0x80EA, 0x0F47,
+ 0x80DE, 0x0EE3,
+ 0x80D2, 0x0E7F,
+ 0x80C7, 0x0E1B,
+ 0x80BC, 0x0DB7,
+ 0x80B2, 0x0D53,
+ 0x80A7, 0x0CEF,
+ 0x809D, 0x0C8B,
+ 0x8094, 0x0C27,
+ 0x808A, 0x0BC3,
+ 0x8081, 0x0B5F,
+ 0x8078, 0x0AFB,
+ 0x8070, 0x0A97,
+ 0x8068, 0x0A33,
+ 0x8060, 0x09CE,
+ 0x8058, 0x096A,
+ 0x8051, 0x0906,
+ 0x804A, 0x08A2,
+ 0x8043, 0x083D,
+ 0x803D, 0x07D9,
+ 0x8037, 0x0775,
+ 0x8031, 0x0710,
+ 0x802C, 0x06AC,
+ 0x8027, 0x0647,
+ 0x8022, 0x05E3,
+ 0x801E, 0x057F,
+ 0x801A, 0x051A,
+ 0x8016, 0x04B6,
+ 0x8012, 0x0451,
+ 0x800F, 0x03ED,
+ 0x800C, 0x0388,
+ 0x8009, 0x0324,
+ 0x8007, 0x02BF,
+ 0x8005, 0x025B,
+ 0x8003, 0x01F6,
+ 0x8002, 0x0192,
+ 0x8001, 0x012D,
+ 0x8000, 0x00C9,
+ 0x8000, 0x0064,
+ 0x8000, 0x0000,
+ 0x8000, 0xFF9B,
+ 0x8000, 0xFF36,
+ 0x8001, 0xFED2,
+ 0x8002, 0xFE6D,
+ 0x8003, 0xFE09,
+ 0x8005, 0xFDA4,
+ 0x8007, 0xFD40,
+ 0x8009, 0xFCDB,
+ 0x800C, 0xFC77,
+ 0x800F, 0xFC12,
+ 0x8012, 0xFBAE,
+ 0x8016, 0xFB49,
+ 0x801A, 0xFAE5,
+ 0x801E, 0xFA80,
+ 0x8022, 0xFA1C,
+ 0x8027, 0xF9B8,
+ 0x802C, 0xF953,
+ 0x8031, 0xF8EF,
+ 0x8037, 0xF88A,
+ 0x803D, 0xF826,
+ 0x8043, 0xF7C2,
+ 0x804A, 0xF75D,
+ 0x8051, 0xF6F9,
+ 0x8058, 0xF695,
+ 0x8060, 0xF631,
+ 0x8068, 0xF5CC,
+ 0x8070, 0xF568,
+ 0x8078, 0xF504,
+ 0x8081, 0xF4A0,
+ 0x808A, 0xF43C,
+ 0x8094, 0xF3D8,
+ 0x809D, 0xF374,
+ 0x80A7, 0xF310,
+ 0x80B2, 0xF2AC,
+ 0x80BC, 0xF248,
+ 0x80C7, 0xF1E4,
+ 0x80D2, 0xF180,
+ 0x80DE, 0xF11C,
+ 0x80EA, 0xF0B8,
+ 0x80F6, 0xF054,
+ 0x8102, 0xEFF1,
+ 0x810F, 0xEF8D,
+ 0x811C, 0xEF29,
+ 0x812A, 0xEEC6,
+ 0x8137, 0xEE62,
+ 0x8145, 0xEDFE,
+ 0x8154, 0xED9B,
+ 0x8162, 0xED37,
+ 0x8171, 0xECD4,
+ 0x8180, 0xEC71,
+ 0x8190, 0xEC0D,
+ 0x81A0, 0xEBAA,
+ 0x81B0, 0xEB47,
+ 0x81C0, 0xEAE4,
+ 0x81D1, 0xEA80,
+ 0x81E2, 0xEA1D,
+ 0x81F3, 0xE9BA,
+ 0x8205, 0xE957,
+ 0x8217, 0xE8F5,
+ 0x8229, 0xE892,
+ 0x823C, 0xE82F,
+ 0x824F, 0xE7CC,
+ 0x8262, 0xE769,
+ 0x8275, 0xE707,
+ 0x8289, 0xE6A4,
+ 0x829D, 0xE642,
+ 0x82B1, 0xE5DF,
+ 0x82C6, 0xE57D,
+ 0x82DB, 0xE51B,
+ 0x82F0, 0xE4B8,
+ 0x8306, 0xE456,
+ 0x831C, 0xE3F4,
+ 0x8332, 0xE392,
+ 0x8348, 0xE330,
+ 0x835F, 0xE2CE,
+ 0x8376, 0xE26C,
+ 0x838E, 0xE20A,
+ 0x83A5, 0xE1A9,
+ 0x83BD, 0xE147,
+ 0x83D6, 0xE0E6,
+ 0x83EE, 0xE084,
+ 0x8407, 0xE023,
+ 0x8420, 0xDFC1,
+ 0x843A, 0xDF60,
+ 0x8453, 0xDEFF,
+ 0x846D, 0xDE9E,
+ 0x8488, 0xDE3D,
+ 0x84A2, 0xDDDC,
+ 0x84BD, 0xDD7B,
+ 0x84D9, 0xDD1A,
+ 0x84F4, 0xDCBA,
+ 0x8510, 0xDC59,
+ 0x852C, 0xDBF8,
+ 0x8549, 0xDB98,
+ 0x8565, 0xDB38,
+ 0x8582, 0xDAD7,
+ 0x85A0, 0xDA77,
+ 0x85BD, 0xDA17,
+ 0x85DB, 0xD9B7,
+ 0x85FA, 0xD957,
+ 0x8618, 0xD8F8,
+ 0x8637, 0xD898,
+ 0x8656, 0xD838,
+ 0x8675, 0xD7D9,
+ 0x8695, 0xD779,
+ 0x86B5, 0xD71A,
+ 0x86D5, 0xD6BB,
+ 0x86F6, 0xD65C,
+ 0x8717, 0xD5FD,
+ 0x8738, 0xD59E,
+ 0x8759, 0xD53F,
+ 0x877B, 0xD4E0,
+ 0x879D, 0xD482,
+ 0x87BF, 0xD423,
+ 0x87E2, 0xD3C5,
+ 0x8805, 0xD367,
+ 0x8828, 0xD308,
+ 0x884B, 0xD2AA,
+ 0x886F, 0xD24C,
+ 0x8893, 0xD1EE,
+ 0x88B8, 0xD191,
+ 0x88DC, 0xD133,
+ 0x8901, 0xD0D6,
+ 0x8926, 0xD078,
+ 0x894C, 0xD01B,
+ 0x8971, 0xCFBE,
+ 0x8997, 0xCF61,
+ 0x89BE, 0xCF04,
+ 0x89E4, 0xCEA7,
+ 0x8A0B, 0xCE4A,
+ 0x8A33, 0xCDEE,
+ 0x8A5A, 0xCD91,
+ 0x8A82, 0xCD35,
+ 0x8AAA, 0xCCD9,
+ 0x8AD2, 0xCC7D,
+ 0x8AFB, 0xCC21,
+ 0x8B24, 0xCBC5,
+ 0x8B4D, 0xCB69,
+ 0x8B76, 0xCB0D,
+ 0x8BA0, 0xCAB2,
+ 0x8BCA, 0xCA57,
+ 0x8BF4, 0xC9FB,
+ 0x8C1F, 0xC9A0,
+ 0x8C4A, 0xC945,
+ 0x8C75, 0xC8EB,
+ 0x8CA0, 0xC890,
+ 0x8CCC, 0xC835,
+ 0x8CF8, 0xC7DB,
+ 0x8D24, 0xC781,
+ 0x8D50, 0xC727,
+ 0x8D7D, 0xC6CD,
+ 0x8DAA, 0xC673,
+ 0x8DD8, 0xC619,
+ 0x8E05, 0xC5BF,
+ 0x8E33, 0xC566,
+ 0x8E61, 0xC50D,
+ 0x8E90, 0xC4B3,
+ 0x8EBE, 0xC45A,
+ 0x8EED, 0xC402,
+ 0x8F1D, 0xC3A9,
+ 0x8F4C, 0xC350,
+ 0x8F7C, 0xC2F8,
+ 0x8FAC, 0xC29F,
+ 0x8FDC, 0xC247,
+ 0x900D, 0xC1EF,
+ 0x903E, 0xC197,
+ 0x906F, 0xC140,
+ 0x90A0, 0xC0E8,
+ 0x90D2, 0xC091,
+ 0x9104, 0xC03A,
+ 0x9136, 0xBFE2,
+ 0x9169, 0xBF8C,
+ 0x919C, 0xBF35,
+ 0x91CF, 0xBEDE,
+ 0x9202, 0xBE88,
+ 0x9235, 0xBE31,
+ 0x9269, 0xBDDB,
+ 0x929D, 0xBD85,
+ 0x92D2, 0xBD2F,
+ 0x9306, 0xBCDA,
+ 0x933B, 0xBC84,
+ 0x9370, 0xBC2F,
+ 0x93A6, 0xBBDA,
+ 0x93DB, 0xBB85,
+ 0x9411, 0xBB30,
+ 0x9447, 0xBADB,
+ 0x947E, 0xBA87,
+ 0x94B5, 0xBA32,
+ 0x94EC, 0xB9DE,
+ 0x9523, 0xB98A,
+ 0x955A, 0xB936,
+ 0x9592, 0xB8E3,
+ 0x95CA, 0xB88F,
+ 0x9602, 0xB83C,
+ 0x963B, 0xB7E9,
+ 0x9673, 0xB796,
+ 0x96AC, 0xB743,
+ 0x96E6, 0xB6F0,
+ 0x971F, 0xB69E,
+ 0x9759, 0xB64B,
+ 0x9793, 0xB5F9,
+ 0x97CD, 0xB5A7,
+ 0x9808, 0xB556,
+ 0x9842, 0xB504,
+ 0x987D, 0xB4B3,
+ 0x98B9, 0xB461,
+ 0x98F4, 0xB410,
+ 0x9930, 0xB3C0,
+ 0x996C, 0xB36F,
+ 0x99A8, 0xB31E,
+ 0x99E5, 0xB2CE,
+ 0x9A22, 0xB27E,
+ 0x9A5F, 0xB22E,
+ 0x9A9C, 0xB1DE,
+ 0x9AD9, 0xB18F,
+ 0x9B17, 0xB140,
+ 0x9B55, 0xB0F0,
+ 0x9B93, 0xB0A1,
+ 0x9BD2, 0xB053,
+ 0x9C10, 0xB004,
+ 0x9C4F, 0xAFB6,
+ 0x9C8E, 0xAF68,
+ 0x9CCE, 0xAF1A,
+ 0x9D0D, 0xAECC,
+ 0x9D4D, 0xAE7E,
+ 0x9D8E, 0xAE31,
+ 0x9DCE, 0xADE3,
+ 0x9E0E, 0xAD96,
+ 0x9E4F, 0xAD4A,
+ 0x9E90, 0xACFD,
+ 0x9ED2, 0xACB1,
+ 0x9F13, 0xAC64,
+ 0x9F55, 0xAC18,
+ 0x9F97, 0xABCC,
+ 0x9FD9, 0xAB81,
+ 0xA01C, 0xAB35,
+ 0xA05F, 0xAAEA,
+ 0xA0A1, 0xAA9F,
+ 0xA0E5, 0xAA54,
+ 0xA128, 0xAA0A,
+ 0xA16C, 0xA9BF,
+ 0xA1AF, 0xA975,
+ 0xA1F4, 0xA92B,
+ 0xA238, 0xA8E2,
+ 0xA27C, 0xA898,
+ 0xA2C1, 0xA84F,
+ 0xA306, 0xA806,
+ 0xA34B, 0xA7BD,
+ 0xA391, 0xA774,
+ 0xA3D6, 0xA72B,
+ 0xA41C, 0xA6E3,
+ 0xA462, 0xA69B,
+ 0xA4A9, 0xA653,
+ 0xA4EF, 0xA60C,
+ 0xA536, 0xA5C4,
+ 0xA57D, 0xA57D,
+ 0xA5C4, 0xA536,
+ 0xA60C, 0xA4EF,
+ 0xA653, 0xA4A9,
+ 0xA69B, 0xA462,
+ 0xA6E3, 0xA41C,
+ 0xA72B, 0xA3D6,
+ 0xA774, 0xA391,
+ 0xA7BD, 0xA34B,
+ 0xA806, 0xA306,
+ 0xA84F, 0xA2C1,
+ 0xA898, 0xA27C,
+ 0xA8E2, 0xA238,
+ 0xA92B, 0xA1F4,
+ 0xA975, 0xA1AF,
+ 0xA9BF, 0xA16C,
+ 0xAA0A, 0xA128,
+ 0xAA54, 0xA0E5,
+ 0xAA9F, 0xA0A1,
+ 0xAAEA, 0xA05F,
+ 0xAB35, 0xA01C,
+ 0xAB81, 0x9FD9,
+ 0xABCC, 0x9F97,
+ 0xAC18, 0x9F55,
+ 0xAC64, 0x9F13,
+ 0xACB1, 0x9ED2,
+ 0xACFD, 0x9E90,
+ 0xAD4A, 0x9E4F,
+ 0xAD96, 0x9E0E,
+ 0xADE3, 0x9DCE,
+ 0xAE31, 0x9D8E,
+ 0xAE7E, 0x9D4D,
+ 0xAECC, 0x9D0D,
+ 0xAF1A, 0x9CCE,
+ 0xAF68, 0x9C8E,
+ 0xAFB6, 0x9C4F,
+ 0xB004, 0x9C10,
+ 0xB053, 0x9BD2,
+ 0xB0A1, 0x9B93,
+ 0xB0F0, 0x9B55,
+ 0xB140, 0x9B17,
+ 0xB18F, 0x9AD9,
+ 0xB1DE, 0x9A9C,
+ 0xB22E, 0x9A5F,
+ 0xB27E, 0x9A22,
+ 0xB2CE, 0x99E5,
+ 0xB31E, 0x99A8,
+ 0xB36F, 0x996C,
+ 0xB3C0, 0x9930,
+ 0xB410, 0x98F4,
+ 0xB461, 0x98B9,
+ 0xB4B3, 0x987D,
+ 0xB504, 0x9842,
+ 0xB556, 0x9808,
+ 0xB5A7, 0x97CD,
+ 0xB5F9, 0x9793,
+ 0xB64B, 0x9759,
+ 0xB69E, 0x971F,
+ 0xB6F0, 0x96E6,
+ 0xB743, 0x96AC,
+ 0xB796, 0x9673,
+ 0xB7E9, 0x963B,
+ 0xB83C, 0x9602,
+ 0xB88F, 0x95CA,
+ 0xB8E3, 0x9592,
+ 0xB936, 0x955A,
+ 0xB98A, 0x9523,
+ 0xB9DE, 0x94EC,
+ 0xBA32, 0x94B5,
+ 0xBA87, 0x947E,
+ 0xBADB, 0x9447,
+ 0xBB30, 0x9411,
+ 0xBB85, 0x93DB,
+ 0xBBDA, 0x93A6,
+ 0xBC2F, 0x9370,
+ 0xBC84, 0x933B,
+ 0xBCDA, 0x9306,
+ 0xBD2F, 0x92D2,
+ 0xBD85, 0x929D,
+ 0xBDDB, 0x9269,
+ 0xBE31, 0x9235,
+ 0xBE88, 0x9202,
+ 0xBEDE, 0x91CF,
+ 0xBF35, 0x919C,
+ 0xBF8C, 0x9169,
+ 0xBFE2, 0x9136,
+ 0xC03A, 0x9104,
+ 0xC091, 0x90D2,
+ 0xC0E8, 0x90A0,
+ 0xC140, 0x906F,
+ 0xC197, 0x903E,
+ 0xC1EF, 0x900D,
+ 0xC247, 0x8FDC,
+ 0xC29F, 0x8FAC,
+ 0xC2F8, 0x8F7C,
+ 0xC350, 0x8F4C,
+ 0xC3A9, 0x8F1D,
+ 0xC402, 0x8EED,
+ 0xC45A, 0x8EBE,
+ 0xC4B3, 0x8E90,
+ 0xC50D, 0x8E61,
+ 0xC566, 0x8E33,
+ 0xC5BF, 0x8E05,
+ 0xC619, 0x8DD8,
+ 0xC673, 0x8DAA,
+ 0xC6CD, 0x8D7D,
+ 0xC727, 0x8D50,
+ 0xC781, 0x8D24,
+ 0xC7DB, 0x8CF8,
+ 0xC835, 0x8CCC,
+ 0xC890, 0x8CA0,
+ 0xC8EB, 0x8C75,
+ 0xC945, 0x8C4A,
+ 0xC9A0, 0x8C1F,
+ 0xC9FB, 0x8BF4,
+ 0xCA57, 0x8BCA,
+ 0xCAB2, 0x8BA0,
+ 0xCB0D, 0x8B76,
+ 0xCB69, 0x8B4D,
+ 0xCBC5, 0x8B24,
+ 0xCC21, 0x8AFB,
+ 0xCC7D, 0x8AD2,
+ 0xCCD9, 0x8AAA,
+ 0xCD35, 0x8A82,
+ 0xCD91, 0x8A5A,
+ 0xCDEE, 0x8A33,
+ 0xCE4A, 0x8A0B,
+ 0xCEA7, 0x89E4,
+ 0xCF04, 0x89BE,
+ 0xCF61, 0x8997,
+ 0xCFBE, 0x8971,
+ 0xD01B, 0x894C,
+ 0xD078, 0x8926,
+ 0xD0D6, 0x8901,
+ 0xD133, 0x88DC,
+ 0xD191, 0x88B8,
+ 0xD1EE, 0x8893,
+ 0xD24C, 0x886F,
+ 0xD2AA, 0x884B,
+ 0xD308, 0x8828,
+ 0xD367, 0x8805,
+ 0xD3C5, 0x87E2,
+ 0xD423, 0x87BF,
+ 0xD482, 0x879D,
+ 0xD4E0, 0x877B,
+ 0xD53F, 0x8759,
+ 0xD59E, 0x8738,
+ 0xD5FD, 0x8717,
+ 0xD65C, 0x86F6,
+ 0xD6BB, 0x86D5,
+ 0xD71A, 0x86B5,
+ 0xD779, 0x8695,
+ 0xD7D9, 0x8675,
+ 0xD838, 0x8656,
+ 0xD898, 0x8637,
+ 0xD8F8, 0x8618,
+ 0xD957, 0x85FA,
+ 0xD9B7, 0x85DB,
+ 0xDA17, 0x85BD,
+ 0xDA77, 0x85A0,
+ 0xDAD7, 0x8582,
+ 0xDB38, 0x8565,
+ 0xDB98, 0x8549,
+ 0xDBF8, 0x852C,
+ 0xDC59, 0x8510,
+ 0xDCBA, 0x84F4,
+ 0xDD1A, 0x84D9,
+ 0xDD7B, 0x84BD,
+ 0xDDDC, 0x84A2,
+ 0xDE3D, 0x8488,
+ 0xDE9E, 0x846D,
+ 0xDEFF, 0x8453,
+ 0xDF60, 0x843A,
+ 0xDFC1, 0x8420,
+ 0xE023, 0x8407,
+ 0xE084, 0x83EE,
+ 0xE0E6, 0x83D6,
+ 0xE147, 0x83BD,
+ 0xE1A9, 0x83A5,
+ 0xE20A, 0x838E,
+ 0xE26C, 0x8376,
+ 0xE2CE, 0x835F,
+ 0xE330, 0x8348,
+ 0xE392, 0x8332,
+ 0xE3F4, 0x831C,
+ 0xE456, 0x8306,
+ 0xE4B8, 0x82F0,
+ 0xE51B, 0x82DB,
+ 0xE57D, 0x82C6,
+ 0xE5DF, 0x82B1,
+ 0xE642, 0x829D,
+ 0xE6A4, 0x8289,
+ 0xE707, 0x8275,
+ 0xE769, 0x8262,
+ 0xE7CC, 0x824F,
+ 0xE82F, 0x823C,
+ 0xE892, 0x8229,
+ 0xE8F5, 0x8217,
+ 0xE957, 0x8205,
+ 0xE9BA, 0x81F3,
+ 0xEA1D, 0x81E2,
+ 0xEA80, 0x81D1,
+ 0xEAE4, 0x81C0,
+ 0xEB47, 0x81B0,
+ 0xEBAA, 0x81A0,
+ 0xEC0D, 0x8190,
+ 0xEC71, 0x8180,
+ 0xECD4, 0x8171,
+ 0xED37, 0x8162,
+ 0xED9B, 0x8154,
+ 0xEDFE, 0x8145,
+ 0xEE62, 0x8137,
+ 0xEEC6, 0x812A,
+ 0xEF29, 0x811C,
+ 0xEF8D, 0x810F,
+ 0xEFF1, 0x8102,
+ 0xF054, 0x80F6,
+ 0xF0B8, 0x80EA,
+ 0xF11C, 0x80DE,
+ 0xF180, 0x80D2,
+ 0xF1E4, 0x80C7,
+ 0xF248, 0x80BC,
+ 0xF2AC, 0x80B2,
+ 0xF310, 0x80A7,
+ 0xF374, 0x809D,
+ 0xF3D8, 0x8094,
+ 0xF43C, 0x808A,
+ 0xF4A0, 0x8081,
+ 0xF504, 0x8078,
+ 0xF568, 0x8070,
+ 0xF5CC, 0x8068,
+ 0xF631, 0x8060,
+ 0xF695, 0x8058,
+ 0xF6F9, 0x8051,
+ 0xF75D, 0x804A,
+ 0xF7C2, 0x8043,
+ 0xF826, 0x803D,
+ 0xF88A, 0x8037,
+ 0xF8EF, 0x8031,
+ 0xF953, 0x802C,
+ 0xF9B8, 0x8027,
+ 0xFA1C, 0x8022,
+ 0xFA80, 0x801E,
+ 0xFAE5, 0x801A,
+ 0xFB49, 0x8016,
+ 0xFBAE, 0x8012,
+ 0xFC12, 0x800F,
+ 0xFC77, 0x800C,
+ 0xFCDB, 0x8009,
+ 0xFD40, 0x8007,
+ 0xFDA4, 0x8005,
+ 0xFE09, 0x8003,
+ 0xFE6D, 0x8002,
+ 0xFED2, 0x8001,
+ 0xFF36, 0x8000,
+ 0xFF9B, 0x8000
+};
+
+/**
+* \par
+* Example code for q15 Twiddle factors Generation::
+* \par
+* for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to q15(Fixed point 1.15):
+* round(twiddleCoefq15(i) * pow(2, 15))
+*
+*/
+const q15_t twiddleCoef_4096_q15[6144] =
+{
+ 0x7FFF, 0x0000,
+ 0x7FFF, 0x0032,
+ 0x7FFF, 0x0064,
+ 0x7FFF, 0x0096,
+ 0x7FFF, 0x00C9,
+ 0x7FFF, 0x00FB,
+ 0x7FFE, 0x012D,
+ 0x7FFE, 0x015F,
+ 0x7FFD, 0x0192,
+ 0x7FFC, 0x01C4,
+ 0x7FFC, 0x01F6,
+ 0x7FFB, 0x0228,
+ 0x7FFA, 0x025B,
+ 0x7FF9, 0x028D,
+ 0x7FF8, 0x02BF,
+ 0x7FF7, 0x02F1,
+ 0x7FF6, 0x0324,
+ 0x7FF4, 0x0356,
+ 0x7FF3, 0x0388,
+ 0x7FF2, 0x03BA,
+ 0x7FF0, 0x03ED,
+ 0x7FEE, 0x041F,
+ 0x7FED, 0x0451,
+ 0x7FEB, 0x0483,
+ 0x7FE9, 0x04B6,
+ 0x7FE7, 0x04E8,
+ 0x7FE5, 0x051A,
+ 0x7FE3, 0x054C,
+ 0x7FE1, 0x057F,
+ 0x7FDF, 0x05B1,
+ 0x7FDD, 0x05E3,
+ 0x7FDA, 0x0615,
+ 0x7FD8, 0x0647,
+ 0x7FD6, 0x067A,
+ 0x7FD3, 0x06AC,
+ 0x7FD0, 0x06DE,
+ 0x7FCE, 0x0710,
+ 0x7FCB, 0x0742,
+ 0x7FC8, 0x0775,
+ 0x7FC5, 0x07A7,
+ 0x7FC2, 0x07D9,
+ 0x7FBF, 0x080B,
+ 0x7FBC, 0x083D,
+ 0x7FB8, 0x086F,
+ 0x7FB5, 0x08A2,
+ 0x7FB1, 0x08D4,
+ 0x7FAE, 0x0906,
+ 0x7FAA, 0x0938,
+ 0x7FA7, 0x096A,
+ 0x7FA3, 0x099C,
+ 0x7F9F, 0x09CE,
+ 0x7F9B, 0x0A00,
+ 0x7F97, 0x0A33,
+ 0x7F93, 0x0A65,
+ 0x7F8F, 0x0A97,
+ 0x7F8B, 0x0AC9,
+ 0x7F87, 0x0AFB,
+ 0x7F82, 0x0B2D,
+ 0x7F7E, 0x0B5F,
+ 0x7F79, 0x0B91,
+ 0x7F75, 0x0BC3,
+ 0x7F70, 0x0BF5,
+ 0x7F6B, 0x0C27,
+ 0x7F67, 0x0C59,
+ 0x7F62, 0x0C8B,
+ 0x7F5D, 0x0CBD,
+ 0x7F58, 0x0CEF,
+ 0x7F53, 0x0D21,
+ 0x7F4D, 0x0D53,
+ 0x7F48, 0x0D85,
+ 0x7F43, 0x0DB7,
+ 0x7F3D, 0x0DE9,
+ 0x7F38, 0x0E1B,
+ 0x7F32, 0x0E4D,
+ 0x7F2D, 0x0E7F,
+ 0x7F27, 0x0EB1,
+ 0x7F21, 0x0EE3,
+ 0x7F1B, 0x0F15,
+ 0x7F15, 0x0F47,
+ 0x7F0F, 0x0F79,
+ 0x7F09, 0x0FAB,
+ 0x7F03, 0x0FDD,
+ 0x7EFD, 0x100E,
+ 0x7EF6, 0x1040,
+ 0x7EF0, 0x1072,
+ 0x7EE9, 0x10A4,
+ 0x7EE3, 0x10D6,
+ 0x7EDC, 0x1108,
+ 0x7ED5, 0x1139,
+ 0x7ECF, 0x116B,
+ 0x7EC8, 0x119D,
+ 0x7EC1, 0x11CF,
+ 0x7EBA, 0x1201,
+ 0x7EB3, 0x1232,
+ 0x7EAB, 0x1264,
+ 0x7EA4, 0x1296,
+ 0x7E9D, 0x12C8,
+ 0x7E95, 0x12F9,
+ 0x7E8E, 0x132B,
+ 0x7E86, 0x135D,
+ 0x7E7F, 0x138E,
+ 0x7E77, 0x13C0,
+ 0x7E6F, 0x13F2,
+ 0x7E67, 0x1423,
+ 0x7E5F, 0x1455,
+ 0x7E57, 0x1487,
+ 0x7E4F, 0x14B8,
+ 0x7E47, 0x14EA,
+ 0x7E3F, 0x151B,
+ 0x7E37, 0x154D,
+ 0x7E2E, 0x157F,
+ 0x7E26, 0x15B0,
+ 0x7E1D, 0x15E2,
+ 0x7E14, 0x1613,
+ 0x7E0C, 0x1645,
+ 0x7E03, 0x1676,
+ 0x7DFA, 0x16A8,
+ 0x7DF1, 0x16D9,
+ 0x7DE8, 0x170A,
+ 0x7DDF, 0x173C,
+ 0x7DD6, 0x176D,
+ 0x7DCD, 0x179F,
+ 0x7DC3, 0x17D0,
+ 0x7DBA, 0x1802,
+ 0x7DB0, 0x1833,
+ 0x7DA7, 0x1864,
+ 0x7D9D, 0x1896,
+ 0x7D94, 0x18C7,
+ 0x7D8A, 0x18F8,
+ 0x7D80, 0x192A,
+ 0x7D76, 0x195B,
+ 0x7D6C, 0x198C,
+ 0x7D62, 0x19BD,
+ 0x7D58, 0x19EF,
+ 0x7D4E, 0x1A20,
+ 0x7D43, 0x1A51,
+ 0x7D39, 0x1A82,
+ 0x7D2F, 0x1AB3,
+ 0x7D24, 0x1AE4,
+ 0x7D19, 0x1B16,
+ 0x7D0F, 0x1B47,
+ 0x7D04, 0x1B78,
+ 0x7CF9, 0x1BA9,
+ 0x7CEE, 0x1BDA,
+ 0x7CE3, 0x1C0B,
+ 0x7CD8, 0x1C3C,
+ 0x7CCD, 0x1C6D,
+ 0x7CC2, 0x1C9E,
+ 0x7CB7, 0x1CCF,
+ 0x7CAB, 0x1D00,
+ 0x7CA0, 0x1D31,
+ 0x7C94, 0x1D62,
+ 0x7C89, 0x1D93,
+ 0x7C7D, 0x1DC4,
+ 0x7C71, 0x1DF5,
+ 0x7C66, 0x1E25,
+ 0x7C5A, 0x1E56,
+ 0x7C4E, 0x1E87,
+ 0x7C42, 0x1EB8,
+ 0x7C36, 0x1EE9,
+ 0x7C29, 0x1F19,
+ 0x7C1D, 0x1F4A,
+ 0x7C11, 0x1F7B,
+ 0x7C05, 0x1FAC,
+ 0x7BF8, 0x1FDC,
+ 0x7BEB, 0x200D,
+ 0x7BDF, 0x203E,
+ 0x7BD2, 0x206E,
+ 0x7BC5, 0x209F,
+ 0x7BB9, 0x20D0,
+ 0x7BAC, 0x2100,
+ 0x7B9F, 0x2131,
+ 0x7B92, 0x2161,
+ 0x7B84, 0x2192,
+ 0x7B77, 0x21C2,
+ 0x7B6A, 0x21F3,
+ 0x7B5D, 0x2223,
+ 0x7B4F, 0x2254,
+ 0x7B42, 0x2284,
+ 0x7B34, 0x22B4,
+ 0x7B26, 0x22E5,
+ 0x7B19, 0x2315,
+ 0x7B0B, 0x2345,
+ 0x7AFD, 0x2376,
+ 0x7AEF, 0x23A6,
+ 0x7AE1, 0x23D6,
+ 0x7AD3, 0x2407,
+ 0x7AC5, 0x2437,
+ 0x7AB6, 0x2467,
+ 0x7AA8, 0x2497,
+ 0x7A9A, 0x24C7,
+ 0x7A8B, 0x24F7,
+ 0x7A7D, 0x2528,
+ 0x7A6E, 0x2558,
+ 0x7A5F, 0x2588,
+ 0x7A50, 0x25B8,
+ 0x7A42, 0x25E8,
+ 0x7A33, 0x2618,
+ 0x7A24, 0x2648,
+ 0x7A15, 0x2678,
+ 0x7A05, 0x26A8,
+ 0x79F6, 0x26D8,
+ 0x79E7, 0x2707,
+ 0x79D8, 0x2737,
+ 0x79C8, 0x2767,
+ 0x79B9, 0x2797,
+ 0x79A9, 0x27C7,
+ 0x7999, 0x27F6,
+ 0x798A, 0x2826,
+ 0x797A, 0x2856,
+ 0x796A, 0x2886,
+ 0x795A, 0x28B5,
+ 0x794A, 0x28E5,
+ 0x793A, 0x2915,
+ 0x792A, 0x2944,
+ 0x7919, 0x2974,
+ 0x7909, 0x29A3,
+ 0x78F9, 0x29D3,
+ 0x78E8, 0x2A02,
+ 0x78D8, 0x2A32,
+ 0x78C7, 0x2A61,
+ 0x78B6, 0x2A91,
+ 0x78A6, 0x2AC0,
+ 0x7895, 0x2AEF,
+ 0x7884, 0x2B1F,
+ 0x7873, 0x2B4E,
+ 0x7862, 0x2B7D,
+ 0x7851, 0x2BAD,
+ 0x7840, 0x2BDC,
+ 0x782E, 0x2C0B,
+ 0x781D, 0x2C3A,
+ 0x780C, 0x2C69,
+ 0x77FA, 0x2C98,
+ 0x77E9, 0x2CC8,
+ 0x77D7, 0x2CF7,
+ 0x77C5, 0x2D26,
+ 0x77B4, 0x2D55,
+ 0x77A2, 0x2D84,
+ 0x7790, 0x2DB3,
+ 0x777E, 0x2DE2,
+ 0x776C, 0x2E11,
+ 0x775A, 0x2E3F,
+ 0x7747, 0x2E6E,
+ 0x7735, 0x2E9D,
+ 0x7723, 0x2ECC,
+ 0x7710, 0x2EFB,
+ 0x76FE, 0x2F29,
+ 0x76EB, 0x2F58,
+ 0x76D9, 0x2F87,
+ 0x76C6, 0x2FB5,
+ 0x76B3, 0x2FE4,
+ 0x76A0, 0x3013,
+ 0x768E, 0x3041,
+ 0x767B, 0x3070,
+ 0x7668, 0x309E,
+ 0x7654, 0x30CD,
+ 0x7641, 0x30FB,
+ 0x762E, 0x312A,
+ 0x761B, 0x3158,
+ 0x7607, 0x3186,
+ 0x75F4, 0x31B5,
+ 0x75E0, 0x31E3,
+ 0x75CC, 0x3211,
+ 0x75B9, 0x3240,
+ 0x75A5, 0x326E,
+ 0x7591, 0x329C,
+ 0x757D, 0x32CA,
+ 0x7569, 0x32F8,
+ 0x7555, 0x3326,
+ 0x7541, 0x3354,
+ 0x752D, 0x3382,
+ 0x7519, 0x33B0,
+ 0x7504, 0x33DE,
+ 0x74F0, 0x340C,
+ 0x74DB, 0x343A,
+ 0x74C7, 0x3468,
+ 0x74B2, 0x3496,
+ 0x749E, 0x34C4,
+ 0x7489, 0x34F2,
+ 0x7474, 0x351F,
+ 0x745F, 0x354D,
+ 0x744A, 0x357B,
+ 0x7435, 0x35A8,
+ 0x7420, 0x35D6,
+ 0x740B, 0x3604,
+ 0x73F6, 0x3631,
+ 0x73E0, 0x365F,
+ 0x73CB, 0x368C,
+ 0x73B5, 0x36BA,
+ 0x73A0, 0x36E7,
+ 0x738A, 0x3714,
+ 0x7375, 0x3742,
+ 0x735F, 0x376F,
+ 0x7349, 0x379C,
+ 0x7333, 0x37CA,
+ 0x731D, 0x37F7,
+ 0x7307, 0x3824,
+ 0x72F1, 0x3851,
+ 0x72DB, 0x387E,
+ 0x72C5, 0x38AB,
+ 0x72AF, 0x38D8,
+ 0x7298, 0x3906,
+ 0x7282, 0x3932,
+ 0x726B, 0x395F,
+ 0x7255, 0x398C,
+ 0x723E, 0x39B9,
+ 0x7227, 0x39E6,
+ 0x7211, 0x3A13,
+ 0x71FA, 0x3A40,
+ 0x71E3, 0x3A6C,
+ 0x71CC, 0x3A99,
+ 0x71B5, 0x3AC6,
+ 0x719E, 0x3AF2,
+ 0x7186, 0x3B1F,
+ 0x716F, 0x3B4C,
+ 0x7158, 0x3B78,
+ 0x7141, 0x3BA5,
+ 0x7129, 0x3BD1,
+ 0x7112, 0x3BFD,
+ 0x70FA, 0x3C2A,
+ 0x70E2, 0x3C56,
+ 0x70CB, 0x3C83,
+ 0x70B3, 0x3CAF,
+ 0x709B, 0x3CDB,
+ 0x7083, 0x3D07,
+ 0x706B, 0x3D33,
+ 0x7053, 0x3D60,
+ 0x703B, 0x3D8C,
+ 0x7023, 0x3DB8,
+ 0x700A, 0x3DE4,
+ 0x6FF2, 0x3E10,
+ 0x6FDA, 0x3E3C,
+ 0x6FC1, 0x3E68,
+ 0x6FA9, 0x3E93,
+ 0x6F90, 0x3EBF,
+ 0x6F77, 0x3EEB,
+ 0x6F5F, 0x3F17,
+ 0x6F46, 0x3F43,
+ 0x6F2D, 0x3F6E,
+ 0x6F14, 0x3F9A,
+ 0x6EFB, 0x3FC5,
+ 0x6EE2, 0x3FF1,
+ 0x6EC9, 0x401D,
+ 0x6EAF, 0x4048,
+ 0x6E96, 0x4073,
+ 0x6E7D, 0x409F,
+ 0x6E63, 0x40CA,
+ 0x6E4A, 0x40F6,
+ 0x6E30, 0x4121,
+ 0x6E17, 0x414C,
+ 0x6DFD, 0x4177,
+ 0x6DE3, 0x41A2,
+ 0x6DCA, 0x41CE,
+ 0x6DB0, 0x41F9,
+ 0x6D96, 0x4224,
+ 0x6D7C, 0x424F,
+ 0x6D62, 0x427A,
+ 0x6D48, 0x42A5,
+ 0x6D2D, 0x42D0,
+ 0x6D13, 0x42FA,
+ 0x6CF9, 0x4325,
+ 0x6CDE, 0x4350,
+ 0x6CC4, 0x437B,
+ 0x6CA9, 0x43A5,
+ 0x6C8F, 0x43D0,
+ 0x6C74, 0x43FB,
+ 0x6C59, 0x4425,
+ 0x6C3F, 0x4450,
+ 0x6C24, 0x447A,
+ 0x6C09, 0x44A5,
+ 0x6BEE, 0x44CF,
+ 0x6BD3, 0x44FA,
+ 0x6BB8, 0x4524,
+ 0x6B9C, 0x454E,
+ 0x6B81, 0x4578,
+ 0x6B66, 0x45A3,
+ 0x6B4A, 0x45CD,
+ 0x6B2F, 0x45F7,
+ 0x6B13, 0x4621,
+ 0x6AF8, 0x464B,
+ 0x6ADC, 0x4675,
+ 0x6AC1, 0x469F,
+ 0x6AA5, 0x46C9,
+ 0x6A89, 0x46F3,
+ 0x6A6D, 0x471C,
+ 0x6A51, 0x4746,
+ 0x6A35, 0x4770,
+ 0x6A19, 0x479A,
+ 0x69FD, 0x47C3,
+ 0x69E1, 0x47ED,
+ 0x69C4, 0x4816,
+ 0x69A8, 0x4840,
+ 0x698C, 0x4869,
+ 0x696F, 0x4893,
+ 0x6953, 0x48BC,
+ 0x6936, 0x48E6,
+ 0x6919, 0x490F,
+ 0x68FD, 0x4938,
+ 0x68E0, 0x4961,
+ 0x68C3, 0x498A,
+ 0x68A6, 0x49B4,
+ 0x6889, 0x49DD,
+ 0x686C, 0x4A06,
+ 0x684F, 0x4A2F,
+ 0x6832, 0x4A58,
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+ 0x099C, 0x7FA3,
+ 0x096A, 0x7FA7,
+ 0x0938, 0x7FAA,
+ 0x0906, 0x7FAE,
+ 0x08D4, 0x7FB1,
+ 0x08A2, 0x7FB5,
+ 0x086F, 0x7FB8,
+ 0x083D, 0x7FBC,
+ 0x080B, 0x7FBF,
+ 0x07D9, 0x7FC2,
+ 0x07A7, 0x7FC5,
+ 0x0775, 0x7FC8,
+ 0x0742, 0x7FCB,
+ 0x0710, 0x7FCE,
+ 0x06DE, 0x7FD0,
+ 0x06AC, 0x7FD3,
+ 0x067A, 0x7FD6,
+ 0x0647, 0x7FD8,
+ 0x0615, 0x7FDA,
+ 0x05E3, 0x7FDD,
+ 0x05B1, 0x7FDF,
+ 0x057F, 0x7FE1,
+ 0x054C, 0x7FE3,
+ 0x051A, 0x7FE5,
+ 0x04E8, 0x7FE7,
+ 0x04B6, 0x7FE9,
+ 0x0483, 0x7FEB,
+ 0x0451, 0x7FED,
+ 0x041F, 0x7FEE,
+ 0x03ED, 0x7FF0,
+ 0x03BA, 0x7FF2,
+ 0x0388, 0x7FF3,
+ 0x0356, 0x7FF4,
+ 0x0324, 0x7FF6,
+ 0x02F1, 0x7FF7,
+ 0x02BF, 0x7FF8,
+ 0x028D, 0x7FF9,
+ 0x025B, 0x7FFA,
+ 0x0228, 0x7FFB,
+ 0x01F6, 0x7FFC,
+ 0x01C4, 0x7FFC,
+ 0x0192, 0x7FFD,
+ 0x015F, 0x7FFE,
+ 0x012D, 0x7FFE,
+ 0x00FB, 0x7FFF,
+ 0x00C9, 0x7FFF,
+ 0x0096, 0x7FFF,
+ 0x0064, 0x7FFF,
+ 0x0032, 0x7FFF,
+ 0x0000, 0x7FFF,
+ 0xFFCD, 0x7FFF,
+ 0xFF9B, 0x7FFF,
+ 0xFF69, 0x7FFF,
+ 0xFF36, 0x7FFF,
+ 0xFF04, 0x7FFF,
+ 0xFED2, 0x7FFE,
+ 0xFEA0, 0x7FFE,
+ 0xFE6D, 0x7FFD,
+ 0xFE3B, 0x7FFC,
+ 0xFE09, 0x7FFC,
+ 0xFDD7, 0x7FFB,
+ 0xFDA4, 0x7FFA,
+ 0xFD72, 0x7FF9,
+ 0xFD40, 0x7FF8,
+ 0xFD0E, 0x7FF7,
+ 0xFCDB, 0x7FF6,
+ 0xFCA9, 0x7FF4,
+ 0xFC77, 0x7FF3,
+ 0xFC45, 0x7FF2,
+ 0xFC12, 0x7FF0,
+ 0xFBE0, 0x7FEE,
+ 0xFBAE, 0x7FED,
+ 0xFB7C, 0x7FEB,
+ 0xFB49, 0x7FE9,
+ 0xFB17, 0x7FE7,
+ 0xFAE5, 0x7FE5,
+ 0xFAB3, 0x7FE3,
+ 0xFA80, 0x7FE1,
+ 0xFA4E, 0x7FDF,
+ 0xFA1C, 0x7FDD,
+ 0xF9EA, 0x7FDA,
+ 0xF9B8, 0x7FD8,
+ 0xF985, 0x7FD6,
+ 0xF953, 0x7FD3,
+ 0xF921, 0x7FD0,
+ 0xF8EF, 0x7FCE,
+ 0xF8BD, 0x7FCB,
+ 0xF88A, 0x7FC8,
+ 0xF858, 0x7FC5,
+ 0xF826, 0x7FC2,
+ 0xF7F4, 0x7FBF,
+ 0xF7C2, 0x7FBC,
+ 0xF790, 0x7FB8,
+ 0xF75D, 0x7FB5,
+ 0xF72B, 0x7FB1,
+ 0xF6F9, 0x7FAE,
+ 0xF6C7, 0x7FAA,
+ 0xF695, 0x7FA7,
+ 0xF663, 0x7FA3,
+ 0xF631, 0x7F9F,
+ 0xF5FF, 0x7F9B,
+ 0xF5CC, 0x7F97,
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+ 0xF568, 0x7F8F,
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+ 0xF4D2, 0x7F82,
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+ 0xF46E, 0x7F79,
+ 0xF43C, 0x7F75,
+ 0xF40A, 0x7F70,
+ 0xF3D8, 0x7F6B,
+ 0xF3A6, 0x7F67,
+ 0xF374, 0x7F62,
+ 0xF342, 0x7F5D,
+ 0xF310, 0x7F58,
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+ 0xF2AC, 0x7F4D,
+ 0xF27A, 0x7F48,
+ 0xF248, 0x7F43,
+ 0xF216, 0x7F3D,
+ 0xF1E4, 0x7F38,
+ 0xF1B2, 0x7F32,
+ 0xF180, 0x7F2D,
+ 0xF14E, 0x7F27,
+ 0xF11C, 0x7F21,
+ 0xF0EA, 0x7F1B,
+ 0xF0B8, 0x7F15,
+ 0xF086, 0x7F0F,
+ 0xF054, 0x7F09,
+ 0xF022, 0x7F03,
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+ 0xEFBF, 0x7EF6,
+ 0xEF8D, 0x7EF0,
+ 0xEF5B, 0x7EE9,
+ 0xEF29, 0x7EE3,
+ 0xEEF7, 0x7EDC,
+ 0xEEC6, 0x7ED5,
+ 0xEE94, 0x7ECF,
+ 0xEE62, 0x7EC8,
+ 0xEE30, 0x7EC1,
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+ 0xEDCD, 0x7EB3,
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+ 0xED06, 0x7E95,
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+ 0xEC3F, 0x7E77,
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+ 0xEAB2, 0x7E37,
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+ 0xEA4F, 0x7E26,
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+ 0xACFD, 0x616F,
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+ 0xA41C, 0x591C,
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+ 0xA3B4, 0x58AF,
+ 0xA391, 0x588B,
+ 0xA36E, 0x5867,
+ 0xA34B, 0x5842,
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+ 0xA306, 0x57F9,
+ 0xA2E4, 0x57D5,
+ 0xA2C1, 0x57B0,
+ 0xA29F, 0x578C,
+ 0xA27C, 0x5767,
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+ 0x8000, 0x00FB,
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+ 0x8000, 0x0032,
+ 0x8000, 0x0000,
+ 0x8000, 0xFFCD,
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+ 0x8000, 0xFF69,
+ 0x8000, 0xFF36,
+ 0x8000, 0xFF04,
+ 0x8001, 0xFED2,
+ 0x8001, 0xFEA0,
+ 0x8002, 0xFE6D,
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+ 0x8003, 0xFE09,
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+ 0x8007, 0xFD40,
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+ 0x800C, 0xFC77,
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+ 0x800F, 0xFC12,
+ 0x8011, 0xFBE0,
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+ 0x8014, 0xFB7C,
+ 0x8016, 0xFB49,
+ 0x8018, 0xFB17,
+ 0x801A, 0xFAE5,
+ 0x801C, 0xFAB3,
+ 0x801E, 0xFA80,
+ 0x8020, 0xFA4E,
+ 0x8022, 0xFA1C,
+ 0x8025, 0xF9EA,
+ 0x8027, 0xF9B8,
+ 0x8029, 0xF985,
+ 0x802C, 0xF953,
+ 0x802F, 0xF921,
+ 0x8031, 0xF8EF,
+ 0x8034, 0xF8BD,
+ 0x8037, 0xF88A,
+ 0x803A, 0xF858,
+ 0x803D, 0xF826,
+ 0x8040, 0xF7F4,
+ 0x8043, 0xF7C2,
+ 0x8047, 0xF790,
+ 0x804A, 0xF75D,
+ 0x804E, 0xF72B,
+ 0x8051, 0xF6F9,
+ 0x8055, 0xF6C7,
+ 0x8058, 0xF695,
+ 0x805C, 0xF663,
+ 0x8060, 0xF631,
+ 0x8064, 0xF5FF,
+ 0x8068, 0xF5CC,
+ 0x806C, 0xF59A,
+ 0x8070, 0xF568,
+ 0x8074, 0xF536,
+ 0x8078, 0xF504,
+ 0x807D, 0xF4D2,
+ 0x8081, 0xF4A0,
+ 0x8086, 0xF46E,
+ 0x808A, 0xF43C,
+ 0x808F, 0xF40A,
+ 0x8094, 0xF3D8,
+ 0x8098, 0xF3A6,
+ 0x809D, 0xF374,
+ 0x80A2, 0xF342,
+ 0x80A7, 0xF310,
+ 0x80AC, 0xF2DE,
+ 0x80B2, 0xF2AC,
+ 0x80B7, 0xF27A,
+ 0x80BC, 0xF248,
+ 0x80C2, 0xF216,
+ 0x80C7, 0xF1E4,
+ 0x80CD, 0xF1B2,
+ 0x80D2, 0xF180,
+ 0x80D8, 0xF14E,
+ 0x80DE, 0xF11C,
+ 0x80E4, 0xF0EA,
+ 0x80EA, 0xF0B8,
+ 0x80F0, 0xF086,
+ 0x80F6, 0xF054,
+ 0x80FC, 0xF022,
+ 0x8102, 0xEFF1,
+ 0x8109, 0xEFBF,
+ 0x810F, 0xEF8D,
+ 0x8116, 0xEF5B,
+ 0x811C, 0xEF29,
+ 0x8123, 0xEEF7,
+ 0x812A, 0xEEC6,
+ 0x8130, 0xEE94,
+ 0x8137, 0xEE62,
+ 0x813E, 0xEE30,
+ 0x8145, 0xEDFE,
+ 0x814C, 0xEDCD,
+ 0x8154, 0xED9B,
+ 0x815B, 0xED69,
+ 0x8162, 0xED37,
+ 0x816A, 0xED06,
+ 0x8171, 0xECD4,
+ 0x8179, 0xECA2,
+ 0x8180, 0xEC71,
+ 0x8188, 0xEC3F,
+ 0x8190, 0xEC0D,
+ 0x8198, 0xEBDC,
+ 0x81A0, 0xEBAA,
+ 0x81A8, 0xEB78,
+ 0x81B0, 0xEB47,
+ 0x81B8, 0xEB15,
+ 0x81C0, 0xEAE4,
+ 0x81C8, 0xEAB2,
+ 0x81D1, 0xEA80,
+ 0x81D9, 0xEA4F,
+ 0x81E2, 0xEA1D,
+ 0x81EB, 0xE9EC,
+ 0x81F3, 0xE9BA,
+ 0x81FC, 0xE989,
+ 0x8205, 0xE957,
+ 0x820E, 0xE926,
+ 0x8217, 0xE8F5,
+ 0x8220, 0xE8C3,
+ 0x8229, 0xE892,
+ 0x8232, 0xE860,
+ 0x823C, 0xE82F,
+ 0x8245, 0xE7FD,
+ 0x824F, 0xE7CC,
+ 0x8258, 0xE79B,
+ 0x8262, 0xE769,
+ 0x826B, 0xE738,
+ 0x8275, 0xE707,
+ 0x827F, 0xE6D5,
+ 0x8289, 0xE6A4,
+ 0x8293, 0xE673,
+ 0x829D, 0xE642,
+ 0x82A7, 0xE610,
+ 0x82B1, 0xE5DF,
+ 0x82BC, 0xE5AE,
+ 0x82C6, 0xE57D,
+ 0x82D0, 0xE54C,
+ 0x82DB, 0xE51B,
+ 0x82E6, 0xE4E9,
+ 0x82F0, 0xE4B8,
+ 0x82FB, 0xE487,
+ 0x8306, 0xE456,
+ 0x8311, 0xE425,
+ 0x831C, 0xE3F4,
+ 0x8327, 0xE3C3,
+ 0x8332, 0xE392,
+ 0x833D, 0xE361,
+ 0x8348, 0xE330,
+ 0x8354, 0xE2FF,
+ 0x835F, 0xE2CE,
+ 0x836B, 0xE29D,
+ 0x8376, 0xE26C,
+ 0x8382, 0xE23B,
+ 0x838E, 0xE20A,
+ 0x8399, 0xE1DA,
+ 0x83A5, 0xE1A9,
+ 0x83B1, 0xE178,
+ 0x83BD, 0xE147,
+ 0x83C9, 0xE116,
+ 0x83D6, 0xE0E6,
+ 0x83E2, 0xE0B5,
+ 0x83EE, 0xE084,
+ 0x83FA, 0xE053,
+ 0x8407, 0xE023,
+ 0x8414, 0xDFF2,
+ 0x8420, 0xDFC1,
+ 0x842D, 0xDF91,
+ 0x843A, 0xDF60,
+ 0x8446, 0xDF2F,
+ 0x8453, 0xDEFF,
+ 0x8460, 0xDECE,
+ 0x846D, 0xDE9E,
+ 0x847B, 0xDE6D,
+ 0x8488, 0xDE3D,
+ 0x8495, 0xDE0C,
+ 0x84A2, 0xDDDC,
+ 0x84B0, 0xDDAB,
+ 0x84BD, 0xDD7B,
+ 0x84CB, 0xDD4B,
+ 0x84D9, 0xDD1A,
+ 0x84E6, 0xDCEA,
+ 0x84F4, 0xDCBA,
+ 0x8502, 0xDC89,
+ 0x8510, 0xDC59,
+ 0x851E, 0xDC29,
+ 0x852C, 0xDBF8,
+ 0x853A, 0xDBC8,
+ 0x8549, 0xDB98,
+ 0x8557, 0xDB68,
+ 0x8565, 0xDB38,
+ 0x8574, 0xDB08,
+ 0x8582, 0xDAD7,
+ 0x8591, 0xDAA7,
+ 0x85A0, 0xDA77,
+ 0x85AF, 0xDA47,
+ 0x85BD, 0xDA17,
+ 0x85CC, 0xD9E7,
+ 0x85DB, 0xD9B7,
+ 0x85EA, 0xD987,
+ 0x85FA, 0xD957,
+ 0x8609, 0xD927,
+ 0x8618, 0xD8F8,
+ 0x8627, 0xD8C8,
+ 0x8637, 0xD898,
+ 0x8646, 0xD868,
+ 0x8656, 0xD838,
+ 0x8666, 0xD809,
+ 0x8675, 0xD7D9,
+ 0x8685, 0xD7A9,
+ 0x8695, 0xD779,
+ 0x86A5, 0xD74A,
+ 0x86B5, 0xD71A,
+ 0x86C5, 0xD6EA,
+ 0x86D5, 0xD6BB,
+ 0x86E6, 0xD68B,
+ 0x86F6, 0xD65C,
+ 0x8706, 0xD62C,
+ 0x8717, 0xD5FD,
+ 0x8727, 0xD5CD,
+ 0x8738, 0xD59E,
+ 0x8749, 0xD56E,
+ 0x8759, 0xD53F,
+ 0x876A, 0xD510,
+ 0x877B, 0xD4E0,
+ 0x878C, 0xD4B1,
+ 0x879D, 0xD482,
+ 0x87AE, 0xD452,
+ 0x87BF, 0xD423,
+ 0x87D1, 0xD3F4,
+ 0x87E2, 0xD3C5,
+ 0x87F3, 0xD396,
+ 0x8805, 0xD367,
+ 0x8816, 0xD337,
+ 0x8828, 0xD308,
+ 0x883A, 0xD2D9,
+ 0x884B, 0xD2AA,
+ 0x885D, 0xD27B,
+ 0x886F, 0xD24C,
+ 0x8881, 0xD21D,
+ 0x8893, 0xD1EE,
+ 0x88A5, 0xD1C0,
+ 0x88B8, 0xD191,
+ 0x88CA, 0xD162,
+ 0x88DC, 0xD133,
+ 0x88EF, 0xD104,
+ 0x8901, 0xD0D6,
+ 0x8914, 0xD0A7,
+ 0x8926, 0xD078,
+ 0x8939, 0xD04A,
+ 0x894C, 0xD01B,
+ 0x895F, 0xCFEC,
+ 0x8971, 0xCFBE,
+ 0x8984, 0xCF8F,
+ 0x8997, 0xCF61,
+ 0x89AB, 0xCF32,
+ 0x89BE, 0xCF04,
+ 0x89D1, 0xCED5,
+ 0x89E4, 0xCEA7,
+ 0x89F8, 0xCE79,
+ 0x8A0B, 0xCE4A,
+ 0x8A1F, 0xCE1C,
+ 0x8A33, 0xCDEE,
+ 0x8A46, 0xCDBF,
+ 0x8A5A, 0xCD91,
+ 0x8A6E, 0xCD63,
+ 0x8A82, 0xCD35,
+ 0x8A96, 0xCD07,
+ 0x8AAA, 0xCCD9,
+ 0x8ABE, 0xCCAB,
+ 0x8AD2, 0xCC7D,
+ 0x8AE6, 0xCC4F,
+ 0x8AFB, 0xCC21,
+ 0x8B0F, 0xCBF3,
+ 0x8B24, 0xCBC5,
+ 0x8B38, 0xCB97,
+ 0x8B4D, 0xCB69,
+ 0x8B61, 0xCB3B,
+ 0x8B76, 0xCB0D,
+ 0x8B8B, 0xCAE0,
+ 0x8BA0, 0xCAB2,
+ 0x8BB5, 0xCA84,
+ 0x8BCA, 0xCA57,
+ 0x8BDF, 0xCA29,
+ 0x8BF4, 0xC9FB,
+ 0x8C09, 0xC9CE,
+ 0x8C1F, 0xC9A0,
+ 0x8C34, 0xC973,
+ 0x8C4A, 0xC945,
+ 0x8C5F, 0xC918,
+ 0x8C75, 0xC8EB,
+ 0x8C8A, 0xC8BD,
+ 0x8CA0, 0xC890,
+ 0x8CB6, 0xC863,
+ 0x8CCC, 0xC835,
+ 0x8CE2, 0xC808,
+ 0x8CF8, 0xC7DB,
+ 0x8D0E, 0xC7AE,
+ 0x8D24, 0xC781,
+ 0x8D3A, 0xC754,
+ 0x8D50, 0xC727,
+ 0x8D67, 0xC6F9,
+ 0x8D7D, 0xC6CD,
+ 0x8D94, 0xC6A0,
+ 0x8DAA, 0xC673,
+ 0x8DC1, 0xC646,
+ 0x8DD8, 0xC619,
+ 0x8DEE, 0xC5EC,
+ 0x8E05, 0xC5BF,
+ 0x8E1C, 0xC593,
+ 0x8E33, 0xC566,
+ 0x8E4A, 0xC539,
+ 0x8E61, 0xC50D,
+ 0x8E79, 0xC4E0,
+ 0x8E90, 0xC4B3,
+ 0x8EA7, 0xC487,
+ 0x8EBE, 0xC45A,
+ 0x8ED6, 0xC42E,
+ 0x8EED, 0xC402,
+ 0x8F05, 0xC3D5,
+ 0x8F1D, 0xC3A9,
+ 0x8F34, 0xC37C,
+ 0x8F4C, 0xC350,
+ 0x8F64, 0xC324,
+ 0x8F7C, 0xC2F8,
+ 0x8F94, 0xC2CC,
+ 0x8FAC, 0xC29F,
+ 0x8FC4, 0xC273,
+ 0x8FDC, 0xC247,
+ 0x8FF5, 0xC21B,
+ 0x900D, 0xC1EF,
+ 0x9025, 0xC1C3,
+ 0x903E, 0xC197,
+ 0x9056, 0xC16C,
+ 0x906F, 0xC140,
+ 0x9088, 0xC114,
+ 0x90A0, 0xC0E8,
+ 0x90B9, 0xC0BC,
+ 0x90D2, 0xC091,
+ 0x90EB, 0xC065,
+ 0x9104, 0xC03A,
+ 0x911D, 0xC00E,
+ 0x9136, 0xBFE2,
+ 0x9150, 0xBFB7,
+ 0x9169, 0xBF8C,
+ 0x9182, 0xBF60,
+ 0x919C, 0xBF35,
+ 0x91B5, 0xBF09,
+ 0x91CF, 0xBEDE,
+ 0x91E8, 0xBEB3,
+ 0x9202, 0xBE88,
+ 0x921C, 0xBE5D,
+ 0x9235, 0xBE31,
+ 0x924F, 0xBE06,
+ 0x9269, 0xBDDB,
+ 0x9283, 0xBDB0,
+ 0x929D, 0xBD85,
+ 0x92B7, 0xBD5A,
+ 0x92D2, 0xBD2F,
+ 0x92EC, 0xBD05,
+ 0x9306, 0xBCDA,
+ 0x9321, 0xBCAF,
+ 0x933B, 0xBC84,
+ 0x9356, 0xBC5A,
+ 0x9370, 0xBC2F,
+ 0x938B, 0xBC04,
+ 0x93A6, 0xBBDA,
+ 0x93C0, 0xBBAF,
+ 0x93DB, 0xBB85,
+ 0x93F6, 0xBB5A,
+ 0x9411, 0xBB30,
+ 0x942C, 0xBB05,
+ 0x9447, 0xBADB,
+ 0x9463, 0xBAB1,
+ 0x947E, 0xBA87,
+ 0x9499, 0xBA5C,
+ 0x94B5, 0xBA32,
+ 0x94D0, 0xBA08,
+ 0x94EC, 0xB9DE,
+ 0x9507, 0xB9B4,
+ 0x9523, 0xB98A,
+ 0x953E, 0xB960,
+ 0x955A, 0xB936,
+ 0x9576, 0xB90C,
+ 0x9592, 0xB8E3,
+ 0x95AE, 0xB8B9,
+ 0x95CA, 0xB88F,
+ 0x95E6, 0xB865,
+ 0x9602, 0xB83C,
+ 0x961E, 0xB812,
+ 0x963B, 0xB7E9,
+ 0x9657, 0xB7BF,
+ 0x9673, 0xB796,
+ 0x9690, 0xB76C,
+ 0x96AC, 0xB743,
+ 0x96C9, 0xB719,
+ 0x96E6, 0xB6F0,
+ 0x9702, 0xB6C7,
+ 0x971F, 0xB69E,
+ 0x973C, 0xB675,
+ 0x9759, 0xB64B,
+ 0x9776, 0xB622,
+ 0x9793, 0xB5F9,
+ 0x97B0, 0xB5D0,
+ 0x97CD, 0xB5A7,
+ 0x97EA, 0xB57E,
+ 0x9808, 0xB556,
+ 0x9825, 0xB52D,
+ 0x9842, 0xB504,
+ 0x9860, 0xB4DB,
+ 0x987D, 0xB4B3,
+ 0x989B, 0xB48A,
+ 0x98B9, 0xB461,
+ 0x98D6, 0xB439,
+ 0x98F4, 0xB410,
+ 0x9912, 0xB3E8,
+ 0x9930, 0xB3C0,
+ 0x994E, 0xB397,
+ 0x996C, 0xB36F,
+ 0x998A, 0xB347,
+ 0x99A8, 0xB31E,
+ 0x99C6, 0xB2F6,
+ 0x99E5, 0xB2CE,
+ 0x9A03, 0xB2A6,
+ 0x9A22, 0xB27E,
+ 0x9A40, 0xB256,
+ 0x9A5F, 0xB22E,
+ 0x9A7D, 0xB206,
+ 0x9A9C, 0xB1DE,
+ 0x9ABA, 0xB1B7,
+ 0x9AD9, 0xB18F,
+ 0x9AF8, 0xB167,
+ 0x9B17, 0xB140,
+ 0x9B36, 0xB118,
+ 0x9B55, 0xB0F0,
+ 0x9B74, 0xB0C9,
+ 0x9B93, 0xB0A1,
+ 0x9BB2, 0xB07A,
+ 0x9BD2, 0xB053,
+ 0x9BF1, 0xB02B,
+ 0x9C10, 0xB004,
+ 0x9C30, 0xAFDD,
+ 0x9C4F, 0xAFB6,
+ 0x9C6F, 0xAF8F,
+ 0x9C8E, 0xAF68,
+ 0x9CAE, 0xAF40,
+ 0x9CCE, 0xAF1A,
+ 0x9CEE, 0xAEF3,
+ 0x9D0D, 0xAECC,
+ 0x9D2D, 0xAEA5,
+ 0x9D4D, 0xAE7E,
+ 0x9D6D, 0xAE57,
+ 0x9D8E, 0xAE31,
+ 0x9DAE, 0xAE0A,
+ 0x9DCE, 0xADE3,
+ 0x9DEE, 0xADBD,
+ 0x9E0E, 0xAD96,
+ 0x9E2F, 0xAD70,
+ 0x9E4F, 0xAD4A,
+ 0x9E70, 0xAD23,
+ 0x9E90, 0xACFD,
+ 0x9EB1, 0xACD7,
+ 0x9ED2, 0xACB1,
+ 0x9EF2, 0xAC8A,
+ 0x9F13, 0xAC64,
+ 0x9F34, 0xAC3E,
+ 0x9F55, 0xAC18,
+ 0x9F76, 0xABF2,
+ 0x9F97, 0xABCC,
+ 0x9FB8, 0xABA7,
+ 0x9FD9, 0xAB81,
+ 0x9FFB, 0xAB5B,
+ 0xA01C, 0xAB35,
+ 0xA03D, 0xAB10,
+ 0xA05F, 0xAAEA,
+ 0xA080, 0xAAC5,
+ 0xA0A1, 0xAA9F,
+ 0xA0C3, 0xAA7A,
+ 0xA0E5, 0xAA54,
+ 0xA106, 0xAA2F,
+ 0xA128, 0xAA0A,
+ 0xA14A, 0xA9E5,
+ 0xA16C, 0xA9BF,
+ 0xA18E, 0xA99A,
+ 0xA1AF, 0xA975,
+ 0xA1D2, 0xA950,
+ 0xA1F4, 0xA92B,
+ 0xA216, 0xA906,
+ 0xA238, 0xA8E2,
+ 0xA25A, 0xA8BD,
+ 0xA27C, 0xA898,
+ 0xA29F, 0xA873,
+ 0xA2C1, 0xA84F,
+ 0xA2E4, 0xA82A,
+ 0xA306, 0xA806,
+ 0xA329, 0xA7E1,
+ 0xA34B, 0xA7BD,
+ 0xA36E, 0xA798,
+ 0xA391, 0xA774,
+ 0xA3B4, 0xA750,
+ 0xA3D6, 0xA72B,
+ 0xA3F9, 0xA707,
+ 0xA41C, 0xA6E3,
+ 0xA43F, 0xA6BF,
+ 0xA462, 0xA69B,
+ 0xA486, 0xA677,
+ 0xA4A9, 0xA653,
+ 0xA4CC, 0xA62F,
+ 0xA4EF, 0xA60C,
+ 0xA513, 0xA5E8,
+ 0xA536, 0xA5C4,
+ 0xA55A, 0xA5A1,
+ 0xA57D, 0xA57D,
+ 0xA5A1, 0xA55A,
+ 0xA5C4, 0xA536,
+ 0xA5E8, 0xA513,
+ 0xA60C, 0xA4EF,
+ 0xA62F, 0xA4CC,
+ 0xA653, 0xA4A9,
+ 0xA677, 0xA486,
+ 0xA69B, 0xA462,
+ 0xA6BF, 0xA43F,
+ 0xA6E3, 0xA41C,
+ 0xA707, 0xA3F9,
+ 0xA72B, 0xA3D6,
+ 0xA750, 0xA3B4,
+ 0xA774, 0xA391,
+ 0xA798, 0xA36E,
+ 0xA7BD, 0xA34B,
+ 0xA7E1, 0xA329,
+ 0xA806, 0xA306,
+ 0xA82A, 0xA2E4,
+ 0xA84F, 0xA2C1,
+ 0xA873, 0xA29F,
+ 0xA898, 0xA27C,
+ 0xA8BD, 0xA25A,
+ 0xA8E2, 0xA238,
+ 0xA906, 0xA216,
+ 0xA92B, 0xA1F4,
+ 0xA950, 0xA1D2,
+ 0xA975, 0xA1AF,
+ 0xA99A, 0xA18E,
+ 0xA9BF, 0xA16C,
+ 0xA9E5, 0xA14A,
+ 0xAA0A, 0xA128,
+ 0xAA2F, 0xA106,
+ 0xAA54, 0xA0E5,
+ 0xAA7A, 0xA0C3,
+ 0xAA9F, 0xA0A1,
+ 0xAAC5, 0xA080,
+ 0xAAEA, 0xA05F,
+ 0xAB10, 0xA03D,
+ 0xAB35, 0xA01C,
+ 0xAB5B, 0x9FFB,
+ 0xAB81, 0x9FD9,
+ 0xABA7, 0x9FB8,
+ 0xABCC, 0x9F97,
+ 0xABF2, 0x9F76,
+ 0xAC18, 0x9F55,
+ 0xAC3E, 0x9F34,
+ 0xAC64, 0x9F13,
+ 0xAC8A, 0x9EF2,
+ 0xACB1, 0x9ED2,
+ 0xACD7, 0x9EB1,
+ 0xACFD, 0x9E90,
+ 0xAD23, 0x9E70,
+ 0xAD4A, 0x9E4F,
+ 0xAD70, 0x9E2F,
+ 0xAD96, 0x9E0E,
+ 0xADBD, 0x9DEE,
+ 0xADE3, 0x9DCE,
+ 0xAE0A, 0x9DAE,
+ 0xAE31, 0x9D8E,
+ 0xAE57, 0x9D6D,
+ 0xAE7E, 0x9D4D,
+ 0xAEA5, 0x9D2D,
+ 0xAECC, 0x9D0D,
+ 0xAEF3, 0x9CEE,
+ 0xAF1A, 0x9CCE,
+ 0xAF40, 0x9CAE,
+ 0xAF68, 0x9C8E,
+ 0xAF8F, 0x9C6F,
+ 0xAFB6, 0x9C4F,
+ 0xAFDD, 0x9C30,
+ 0xB004, 0x9C10,
+ 0xB02B, 0x9BF1,
+ 0xB053, 0x9BD2,
+ 0xB07A, 0x9BB2,
+ 0xB0A1, 0x9B93,
+ 0xB0C9, 0x9B74,
+ 0xB0F0, 0x9B55,
+ 0xB118, 0x9B36,
+ 0xB140, 0x9B17,
+ 0xB167, 0x9AF8,
+ 0xB18F, 0x9AD9,
+ 0xB1B7, 0x9ABA,
+ 0xB1DE, 0x9A9C,
+ 0xB206, 0x9A7D,
+ 0xB22E, 0x9A5F,
+ 0xB256, 0x9A40,
+ 0xB27E, 0x9A22,
+ 0xB2A6, 0x9A03,
+ 0xB2CE, 0x99E5,
+ 0xB2F6, 0x99C6,
+ 0xB31E, 0x99A8,
+ 0xB347, 0x998A,
+ 0xB36F, 0x996C,
+ 0xB397, 0x994E,
+ 0xB3C0, 0x9930,
+ 0xB3E8, 0x9912,
+ 0xB410, 0x98F4,
+ 0xB439, 0x98D6,
+ 0xB461, 0x98B9,
+ 0xB48A, 0x989B,
+ 0xB4B3, 0x987D,
+ 0xB4DB, 0x9860,
+ 0xB504, 0x9842,
+ 0xB52D, 0x9825,
+ 0xB556, 0x9808,
+ 0xB57E, 0x97EA,
+ 0xB5A7, 0x97CD,
+ 0xB5D0, 0x97B0,
+ 0xB5F9, 0x9793,
+ 0xB622, 0x9776,
+ 0xB64B, 0x9759,
+ 0xB675, 0x973C,
+ 0xB69E, 0x971F,
+ 0xB6C7, 0x9702,
+ 0xB6F0, 0x96E6,
+ 0xB719, 0x96C9,
+ 0xB743, 0x96AC,
+ 0xB76C, 0x9690,
+ 0xB796, 0x9673,
+ 0xB7BF, 0x9657,
+ 0xB7E9, 0x963B,
+ 0xB812, 0x961E,
+ 0xB83C, 0x9602,
+ 0xB865, 0x95E6,
+ 0xB88F, 0x95CA,
+ 0xB8B9, 0x95AE,
+ 0xB8E3, 0x9592,
+ 0xB90C, 0x9576,
+ 0xB936, 0x955A,
+ 0xB960, 0x953E,
+ 0xB98A, 0x9523,
+ 0xB9B4, 0x9507,
+ 0xB9DE, 0x94EC,
+ 0xBA08, 0x94D0,
+ 0xBA32, 0x94B5,
+ 0xBA5C, 0x9499,
+ 0xBA87, 0x947E,
+ 0xBAB1, 0x9463,
+ 0xBADB, 0x9447,
+ 0xBB05, 0x942C,
+ 0xBB30, 0x9411,
+ 0xBB5A, 0x93F6,
+ 0xBB85, 0x93DB,
+ 0xBBAF, 0x93C0,
+ 0xBBDA, 0x93A6,
+ 0xBC04, 0x938B,
+ 0xBC2F, 0x9370,
+ 0xBC5A, 0x9356,
+ 0xBC84, 0x933B,
+ 0xBCAF, 0x9321,
+ 0xBCDA, 0x9306,
+ 0xBD05, 0x92EC,
+ 0xBD2F, 0x92D2,
+ 0xBD5A, 0x92B7,
+ 0xBD85, 0x929D,
+ 0xBDB0, 0x9283,
+ 0xBDDB, 0x9269,
+ 0xBE06, 0x924F,
+ 0xBE31, 0x9235,
+ 0xBE5D, 0x921C,
+ 0xBE88, 0x9202,
+ 0xBEB3, 0x91E8,
+ 0xBEDE, 0x91CF,
+ 0xBF09, 0x91B5,
+ 0xBF35, 0x919C,
+ 0xBF60, 0x9182,
+ 0xBF8C, 0x9169,
+ 0xBFB7, 0x9150,
+ 0xBFE2, 0x9136,
+ 0xC00E, 0x911D,
+ 0xC03A, 0x9104,
+ 0xC065, 0x90EB,
+ 0xC091, 0x90D2,
+ 0xC0BC, 0x90B9,
+ 0xC0E8, 0x90A0,
+ 0xC114, 0x9088,
+ 0xC140, 0x906F,
+ 0xC16C, 0x9056,
+ 0xC197, 0x903E,
+ 0xC1C3, 0x9025,
+ 0xC1EF, 0x900D,
+ 0xC21B, 0x8FF5,
+ 0xC247, 0x8FDC,
+ 0xC273, 0x8FC4,
+ 0xC29F, 0x8FAC,
+ 0xC2CC, 0x8F94,
+ 0xC2F8, 0x8F7C,
+ 0xC324, 0x8F64,
+ 0xC350, 0x8F4C,
+ 0xC37C, 0x8F34,
+ 0xC3A9, 0x8F1D,
+ 0xC3D5, 0x8F05,
+ 0xC402, 0x8EED,
+ 0xC42E, 0x8ED6,
+ 0xC45A, 0x8EBE,
+ 0xC487, 0x8EA7,
+ 0xC4B3, 0x8E90,
+ 0xC4E0, 0x8E79,
+ 0xC50D, 0x8E61,
+ 0xC539, 0x8E4A,
+ 0xC566, 0x8E33,
+ 0xC593, 0x8E1C,
+ 0xC5BF, 0x8E05,
+ 0xC5EC, 0x8DEE,
+ 0xC619, 0x8DD8,
+ 0xC646, 0x8DC1,
+ 0xC673, 0x8DAA,
+ 0xC6A0, 0x8D94,
+ 0xC6CD, 0x8D7D,
+ 0xC6F9, 0x8D67,
+ 0xC727, 0x8D50,
+ 0xC754, 0x8D3A,
+ 0xC781, 0x8D24,
+ 0xC7AE, 0x8D0E,
+ 0xC7DB, 0x8CF8,
+ 0xC808, 0x8CE2,
+ 0xC835, 0x8CCC,
+ 0xC863, 0x8CB6,
+ 0xC890, 0x8CA0,
+ 0xC8BD, 0x8C8A,
+ 0xC8EB, 0x8C75,
+ 0xC918, 0x8C5F,
+ 0xC945, 0x8C4A,
+ 0xC973, 0x8C34,
+ 0xC9A0, 0x8C1F,
+ 0xC9CE, 0x8C09,
+ 0xC9FB, 0x8BF4,
+ 0xCA29, 0x8BDF,
+ 0xCA57, 0x8BCA,
+ 0xCA84, 0x8BB5,
+ 0xCAB2, 0x8BA0,
+ 0xCAE0, 0x8B8B,
+ 0xCB0D, 0x8B76,
+ 0xCB3B, 0x8B61,
+ 0xCB69, 0x8B4D,
+ 0xCB97, 0x8B38,
+ 0xCBC5, 0x8B24,
+ 0xCBF3, 0x8B0F,
+ 0xCC21, 0x8AFB,
+ 0xCC4F, 0x8AE6,
+ 0xCC7D, 0x8AD2,
+ 0xCCAB, 0x8ABE,
+ 0xCCD9, 0x8AAA,
+ 0xCD07, 0x8A96,
+ 0xCD35, 0x8A82,
+ 0xCD63, 0x8A6E,
+ 0xCD91, 0x8A5A,
+ 0xCDBF, 0x8A46,
+ 0xCDEE, 0x8A33,
+ 0xCE1C, 0x8A1F,
+ 0xCE4A, 0x8A0B,
+ 0xCE79, 0x89F8,
+ 0xCEA7, 0x89E4,
+ 0xCED5, 0x89D1,
+ 0xCF04, 0x89BE,
+ 0xCF32, 0x89AB,
+ 0xCF61, 0x8997,
+ 0xCF8F, 0x8984,
+ 0xCFBE, 0x8971,
+ 0xCFEC, 0x895F,
+ 0xD01B, 0x894C,
+ 0xD04A, 0x8939,
+ 0xD078, 0x8926,
+ 0xD0A7, 0x8914,
+ 0xD0D6, 0x8901,
+ 0xD104, 0x88EF,
+ 0xD133, 0x88DC,
+ 0xD162, 0x88CA,
+ 0xD191, 0x88B8,
+ 0xD1C0, 0x88A5,
+ 0xD1EE, 0x8893,
+ 0xD21D, 0x8881,
+ 0xD24C, 0x886F,
+ 0xD27B, 0x885D,
+ 0xD2AA, 0x884B,
+ 0xD2D9, 0x883A,
+ 0xD308, 0x8828,
+ 0xD337, 0x8816,
+ 0xD367, 0x8805,
+ 0xD396, 0x87F3,
+ 0xD3C5, 0x87E2,
+ 0xD3F4, 0x87D1,
+ 0xD423, 0x87BF,
+ 0xD452, 0x87AE,
+ 0xD482, 0x879D,
+ 0xD4B1, 0x878C,
+ 0xD4E0, 0x877B,
+ 0xD510, 0x876A,
+ 0xD53F, 0x8759,
+ 0xD56E, 0x8749,
+ 0xD59E, 0x8738,
+ 0xD5CD, 0x8727,
+ 0xD5FD, 0x8717,
+ 0xD62C, 0x8706,
+ 0xD65C, 0x86F6,
+ 0xD68B, 0x86E6,
+ 0xD6BB, 0x86D5,
+ 0xD6EA, 0x86C5,
+ 0xD71A, 0x86B5,
+ 0xD74A, 0x86A5,
+ 0xD779, 0x8695,
+ 0xD7A9, 0x8685,
+ 0xD7D9, 0x8675,
+ 0xD809, 0x8666,
+ 0xD838, 0x8656,
+ 0xD868, 0x8646,
+ 0xD898, 0x8637,
+ 0xD8C8, 0x8627,
+ 0xD8F8, 0x8618,
+ 0xD927, 0x8609,
+ 0xD957, 0x85FA,
+ 0xD987, 0x85EA,
+ 0xD9B7, 0x85DB,
+ 0xD9E7, 0x85CC,
+ 0xDA17, 0x85BD,
+ 0xDA47, 0x85AF,
+ 0xDA77, 0x85A0,
+ 0xDAA7, 0x8591,
+ 0xDAD7, 0x8582,
+ 0xDB08, 0x8574,
+ 0xDB38, 0x8565,
+ 0xDB68, 0x8557,
+ 0xDB98, 0x8549,
+ 0xDBC8, 0x853A,
+ 0xDBF8, 0x852C,
+ 0xDC29, 0x851E,
+ 0xDC59, 0x8510,
+ 0xDC89, 0x8502,
+ 0xDCBA, 0x84F4,
+ 0xDCEA, 0x84E6,
+ 0xDD1A, 0x84D9,
+ 0xDD4B, 0x84CB,
+ 0xDD7B, 0x84BD,
+ 0xDDAB, 0x84B0,
+ 0xDDDC, 0x84A2,
+ 0xDE0C, 0x8495,
+ 0xDE3D, 0x8488,
+ 0xDE6D, 0x847B,
+ 0xDE9E, 0x846D,
+ 0xDECE, 0x8460,
+ 0xDEFF, 0x8453,
+ 0xDF2F, 0x8446,
+ 0xDF60, 0x843A,
+ 0xDF91, 0x842D,
+ 0xDFC1, 0x8420,
+ 0xDFF2, 0x8414,
+ 0xE023, 0x8407,
+ 0xE053, 0x83FA,
+ 0xE084, 0x83EE,
+ 0xE0B5, 0x83E2,
+ 0xE0E6, 0x83D6,
+ 0xE116, 0x83C9,
+ 0xE147, 0x83BD,
+ 0xE178, 0x83B1,
+ 0xE1A9, 0x83A5,
+ 0xE1DA, 0x8399,
+ 0xE20A, 0x838E,
+ 0xE23B, 0x8382,
+ 0xE26C, 0x8376,
+ 0xE29D, 0x836B,
+ 0xE2CE, 0x835F,
+ 0xE2FF, 0x8354,
+ 0xE330, 0x8348,
+ 0xE361, 0x833D,
+ 0xE392, 0x8332,
+ 0xE3C3, 0x8327,
+ 0xE3F4, 0x831C,
+ 0xE425, 0x8311,
+ 0xE456, 0x8306,
+ 0xE487, 0x82FB,
+ 0xE4B8, 0x82F0,
+ 0xE4E9, 0x82E6,
+ 0xE51B, 0x82DB,
+ 0xE54C, 0x82D0,
+ 0xE57D, 0x82C6,
+ 0xE5AE, 0x82BC,
+ 0xE5DF, 0x82B1,
+ 0xE610, 0x82A7,
+ 0xE642, 0x829D,
+ 0xE673, 0x8293,
+ 0xE6A4, 0x8289,
+ 0xE6D5, 0x827F,
+ 0xE707, 0x8275,
+ 0xE738, 0x826B,
+ 0xE769, 0x8262,
+ 0xE79B, 0x8258,
+ 0xE7CC, 0x824F,
+ 0xE7FD, 0x8245,
+ 0xE82F, 0x823C,
+ 0xE860, 0x8232,
+ 0xE892, 0x8229,
+ 0xE8C3, 0x8220,
+ 0xE8F5, 0x8217,
+ 0xE926, 0x820E,
+ 0xE957, 0x8205,
+ 0xE989, 0x81FC,
+ 0xE9BA, 0x81F3,
+ 0xE9EC, 0x81EB,
+ 0xEA1D, 0x81E2,
+ 0xEA4F, 0x81D9,
+ 0xEA80, 0x81D1,
+ 0xEAB2, 0x81C8,
+ 0xEAE4, 0x81C0,
+ 0xEB15, 0x81B8,
+ 0xEB47, 0x81B0,
+ 0xEB78, 0x81A8,
+ 0xEBAA, 0x81A0,
+ 0xEBDC, 0x8198,
+ 0xEC0D, 0x8190,
+ 0xEC3F, 0x8188,
+ 0xEC71, 0x8180,
+ 0xECA2, 0x8179,
+ 0xECD4, 0x8171,
+ 0xED06, 0x816A,
+ 0xED37, 0x8162,
+ 0xED69, 0x815B,
+ 0xED9B, 0x8154,
+ 0xEDCD, 0x814C,
+ 0xEDFE, 0x8145,
+ 0xEE30, 0x813E,
+ 0xEE62, 0x8137,
+ 0xEE94, 0x8130,
+ 0xEEC6, 0x812A,
+ 0xEEF7, 0x8123,
+ 0xEF29, 0x811C,
+ 0xEF5B, 0x8116,
+ 0xEF8D, 0x810F,
+ 0xEFBF, 0x8109,
+ 0xEFF1, 0x8102,
+ 0xF022, 0x80FC,
+ 0xF054, 0x80F6,
+ 0xF086, 0x80F0,
+ 0xF0B8, 0x80EA,
+ 0xF0EA, 0x80E4,
+ 0xF11C, 0x80DE,
+ 0xF14E, 0x80D8,
+ 0xF180, 0x80D2,
+ 0xF1B2, 0x80CD,
+ 0xF1E4, 0x80C7,
+ 0xF216, 0x80C2,
+ 0xF248, 0x80BC,
+ 0xF27A, 0x80B7,
+ 0xF2AC, 0x80B2,
+ 0xF2DE, 0x80AC,
+ 0xF310, 0x80A7,
+ 0xF342, 0x80A2,
+ 0xF374, 0x809D,
+ 0xF3A6, 0x8098,
+ 0xF3D8, 0x8094,
+ 0xF40A, 0x808F,
+ 0xF43C, 0x808A,
+ 0xF46E, 0x8086,
+ 0xF4A0, 0x8081,
+ 0xF4D2, 0x807D,
+ 0xF504, 0x8078,
+ 0xF536, 0x8074,
+ 0xF568, 0x8070,
+ 0xF59A, 0x806C,
+ 0xF5CC, 0x8068,
+ 0xF5FF, 0x8064,
+ 0xF631, 0x8060,
+ 0xF663, 0x805C,
+ 0xF695, 0x8058,
+ 0xF6C7, 0x8055,
+ 0xF6F9, 0x8051,
+ 0xF72B, 0x804E,
+ 0xF75D, 0x804A,
+ 0xF790, 0x8047,
+ 0xF7C2, 0x8043,
+ 0xF7F4, 0x8040,
+ 0xF826, 0x803D,
+ 0xF858, 0x803A,
+ 0xF88A, 0x8037,
+ 0xF8BD, 0x8034,
+ 0xF8EF, 0x8031,
+ 0xF921, 0x802F,
+ 0xF953, 0x802C,
+ 0xF985, 0x8029,
+ 0xF9B8, 0x8027,
+ 0xF9EA, 0x8025,
+ 0xFA1C, 0x8022,
+ 0xFA4E, 0x8020,
+ 0xFA80, 0x801E,
+ 0xFAB3, 0x801C,
+ 0xFAE5, 0x801A,
+ 0xFB17, 0x8018,
+ 0xFB49, 0x8016,
+ 0xFB7C, 0x8014,
+ 0xFBAE, 0x8012,
+ 0xFBE0, 0x8011,
+ 0xFC12, 0x800F,
+ 0xFC45, 0x800D,
+ 0xFC77, 0x800C,
+ 0xFCA9, 0x800B,
+ 0xFCDB, 0x8009,
+ 0xFD0E, 0x8008,
+ 0xFD40, 0x8007,
+ 0xFD72, 0x8006,
+ 0xFDA4, 0x8005,
+ 0xFDD7, 0x8004,
+ 0xFE09, 0x8003,
+ 0xFE3B, 0x8003,
+ 0xFE6D, 0x8002,
+ 0xFEA0, 0x8001,
+ 0xFED2, 0x8001,
+ 0xFF04, 0x8000,
+ 0xFF36, 0x8000,
+ 0xFF69, 0x8000,
+ 0xFF9B, 0x8000,
+ 0xFFCD, 0x8000
+};
+
+
+/**
+* @} end of CFFT_CIFFT group
+*/
+
+/*
+* @brief Q15 table for reciprocal
+*/
+const q15_t ALIGN4 armRecipTableQ15[64] = {
+ 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+ 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+ 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+ 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+ 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+ 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+ 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+ 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+ 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+ 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+ 0x41CC, 0x4146, 0x40C2, 0x4040
+};
+
+/*
+* @brief Q31 table for reciprocal
+*/
+const q31_t armRecipTableQ31[64] = {
+ 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+ 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+ 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+ 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+ 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+ 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+ 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+ 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+ 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+ 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+ 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+};
+
+const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH] =
+{
+ //8x2, size 20
+ 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112
+};
+
+const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH] =
+{
+ //8x4, size 48
+ 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208,
+ 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208,
+ 152,224, 176,208, 184,232, 216,240, 200,224, 232,240
+};
+
+const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH] =
+{
+ //radix 8, size 56
+ 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200,
+ 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400,
+ 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480,
+ 368,424, 376,488, 440,496
+};
+
+const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] =
+{
+ //8x2, size 208
+ 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768,
+ 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520,
+ 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776,
+ 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320,
+ 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400,
+ 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584,
+ 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600,
+ 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608,
+ 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864,
+ 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808,
+ 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832,
+ 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008,
+ 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008
+};
+
+const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] =
+{
+ //8x4, size 440
+ 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640,
+ 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768,
+ 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384,
+ 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984,
+ 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608,
+ 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736,
+ 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864,
+ 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992,
+ 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104,
+ 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720,
+ 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160,
+ 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936,
+ 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048,
+ 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808,
+ 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544,
+ 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880,
+ 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496,
+ 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120,
+ 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552,
+ 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824,
+ 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672,
+ 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016,
+ 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640,
+ 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432,
+ 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936,
+ 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960,
+ 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648,
+ 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936,
+ 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928,
+ 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840,
+ 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888,
+ 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032,
+ 1960,1968, 2008,2032, 1992,2016, 2024,2032
+};
+
+const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] =
+{
+ //radix 8, size 448
+ 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576,
+ 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152,
+ 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216,
+ 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280,
+ 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344,
+ 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408,
+ 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472,
+ 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544,
+ 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120,
+ 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696,
+ 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272,
+ 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848,
+ 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416,
+ 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992,
+ 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576,
+ 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152,
+ 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728,
+ 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808,
+ 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384,
+ 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960,
+ 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536,
+ 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136,
+ 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224,
+ 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328,
+ 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416,
+ 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520,
+ 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616,
+ 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744,
+ 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872,
+ 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000,
+ 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176,
+ 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368,
+ 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560,
+ 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888,
+ 3448,3952, 3512,4016, 3576,4080
+};
+
+const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH] =
+{
+ //8x2, size 1800
+ 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048,
+ 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048,
+ 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696,
+ 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648,
+ 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248,
+ 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200,
+ 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800,
+ 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752,
+ 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352,
+ 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304,
+ 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936,
+ 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856,
+ 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488,
+ 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408,
+ 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040,
+ 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960,
+ 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592,
+ 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096,
+ 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544,
+ 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080,
+ 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400,
+ 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120,
+ 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656,
+ 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168,
+ 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696,
+ 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208,
+ 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736,
+ 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272,
+ 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480,
+ 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312,
+ 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848,
+ 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280,
+ 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888,
+ 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288,
+ 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928,
+ 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464,
+ 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592,
+ 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504,
+ 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040,
+ 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136,
+ 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088,
+ 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816,
+ 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576,
+ 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664,
+ 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264,
+ 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800,
+ 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304,
+ 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840,
+ 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376,
+ 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392,
+ 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344,
+ 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944,
+ 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480,
+ 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016,
+ 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032,
+ 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984,
+ 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584,
+ 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632,
+ 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632,
+ 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168,
+ 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704,
+ 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208,
+ 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744,
+ 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248,
+ 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784,
+ 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320,
+ 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824,
+ 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360,
+ 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896,
+ 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400,
+ 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936,
+ 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440,
+ 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976,
+ 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512,
+ 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016,
+ 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552,
+ 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088,
+ 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592,
+ 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128,
+ 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160,
+ 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176,
+ 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712,
+ 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216,
+ 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752,
+ 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416,
+ 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304,
+ 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624,
+ 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296,
+ 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680,
+ 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208,
+ 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400,
+ 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808,
+ 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688,
+ 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976,
+ 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160,
+ 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344,
+ 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728,
+ 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736,
+ 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928,
+ 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872,
+ 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672,
+ 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208,
+ 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456,
+ 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248,
+ 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784,
+ 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448,
+ 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824,
+ 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240,
+ 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504,
+ 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168,
+ 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264,
+ 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456,
+ 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552,
+ 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312,
+ 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576,
+ 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248,
+ 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504,
+ 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360,
+ 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624,
+ 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384,
+ 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264,
+ 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664,
+ 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520,
+ 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280,
+ 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536,
+ 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048,
+ 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752,
+ 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992,
+ 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280,
+ 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856,
+ 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024,
+ 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624,
+ 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104,
+ 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664,
+ 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280,
+ 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688,
+ 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952,
+ 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456,
+ 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864,
+ 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784,
+ 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048,
+ 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728,
+ 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096,
+ 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112,
+ 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984,
+ 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160,
+ 8112,8136, 8120,8168, 8136,8160, 8152,8176
+};
+
+const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH] =
+{
+ //8x2, size 3808
+ 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024,
+ 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824,
+ 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752,
+ 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680,
+ 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576,
+ 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376,
+ 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304,
+ 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232,
+ 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048,
+ 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928,
+ 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856,
+ 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784,
+ 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712,
+ 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480,
+ 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408,
+ 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336,
+ 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264,
+ 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064,
+ 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960,
+ 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792,
+ 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496,
+ 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328,
+ 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032,
+ 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928,
+ 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856,
+ 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560,
+ 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392,
+ 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096,
+ 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240,
+ 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600,
+ 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432,
+ 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136,
+ 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968,
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+ 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608,
+ 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512,
+ 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760,
+ 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296,
+ 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664,
+ 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712,
+ 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816,
+ 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824,
+ 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696,
+ 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832,
+ 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544,
+ 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584,
+ 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496,
+ 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688,
+ 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920,
+ 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344,
+ 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576,
+ 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400,
+ 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448,
+ 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696,
+ 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816,
+ 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344,
+ 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976,
+ 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416,
+ 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496,
+ 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488,
+ 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536,
+ 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592,
+ 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736,
+ 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664,
+ 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064,
+ 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464,
+ 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816,
+ 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768,
+ 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576,
+ 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592,
+ 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536,
+ 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664,
+ 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616,
+ 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704,
+ 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728,
+ 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488,
+ 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384,
+ 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560,
+ 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392,
+ 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528,
+ 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464,
+ 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304,
+ 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632,
+ 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808,
+ 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704,
+ 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832,
+ 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712,
+ 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848,
+ 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600,
+ 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640,
+ 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728,
+ 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928,
+ 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384,
+ 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616,
+ 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656,
+ 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504,
+ 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528,
+ 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776,
+ 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880,
+ 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024,
+ 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232,
+ 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024,
+ 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544,
+ 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872,
+ 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016,
+ 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160,
+ 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304,
+ 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008,
+ 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152,
+ 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296,
+ 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632,
+ 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768,
+ 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760,
+ 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184,
+ 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856,
+ 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000,
+ 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160,
+ 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264,
+ 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048,
+ 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184,
+ 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264,
+ 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208,
+ 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352,
+ 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368,
+ 16328,16352, 16360,16368
+};
+
+const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH] =
+{
+ //radix 8, size 4032
+ 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512,
+ 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184,
+ 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600,
+ 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016,
+ 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432,
+ 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848,
+ 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264,
+ 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680,
+ 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160,
+ 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672,
+ 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088,
+ 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760,
+ 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176,
+ 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592,
+ 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008,
+ 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424,
+ 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840,
+ 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224,
+ 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800,
+ 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216,
+ 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632,
+ 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952,
+ 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272,
+ 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848,
+ 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168,
+ 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488,
+ 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808,
+ 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384,
+ 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768,
+ 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184,
+ 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600,
+ 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016,
+ 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336,
+ 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912,
+ 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232,
+ 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552,
+ 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872,
+ 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448,
+ 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832,
+ 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248,
+ 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664,
+ 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080,
+ 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496,
+ 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816,
+ 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392,
+ 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712,
+ 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032,
+ 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416,
+ 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992,
+ 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408,
+ 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824,
+ 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240,
+ 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656,
+ 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072,
+ 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392,
+ 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968,
+ 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288,
+ 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672,
+ 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088,
+ 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504,
+ 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080,
+ 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496,
+ 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912,
+ 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328,
+ 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744,
+ 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064,
+ 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640,
+ 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024,
+ 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440,
+ 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856,
+ 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272,
+ 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688,
+ 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104,
+ 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680,
+ 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096,
+ 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512,
+ 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488,
+ 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904,
+ 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320,
+ 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736,
+ 4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152,
+ 4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728,
+ 4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144,
+ 4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560,
+ 4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976,
+ 4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456,
+ 4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968,
+ 4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384,
+ 4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800,
+ 4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216,
+ 4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792,
+ 4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208,
+ 4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624,
+ 5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040,
+ 5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520,
+ 5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032,
+ 5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544,
+ 5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960,
+ 5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 5392,10376,
+ 5400,14472, 5408,18568, 5416,22664, 5424,26760, 5432,30856, 5448,6792,
+ 5456,10888, 5464,14984, 5472,19080, 5480,23176, 5488,27272, 5496,31368,
+ 5512,7304, 5520,11400, 5528,15496, 5536,19592, 5544,23688, 5552,27784,
+ 5560,31880, 5576,7816, 5584,11912, 5592,16008, 5600,20104, 5608,24200,
+ 5616,28296, 5624,32392, 5648,8392, 5656,12488, 5664,16584, 5672,20680,
+ 5680,24776, 5688,28872, 5712,8904, 5720,13000, 5728,17096, 5736,21192,
+ 5744,25288, 5752,29384, 5776,9416, 5784,13512, 5792,17608, 5800,21704,
+ 5808,25800, 5816,29896, 5840,9928, 5848,14024, 5856,18120, 5864,22216,
+ 5872,26312, 5880,30408, 5896,6344, 5904,10440, 5912,14536, 5920,18632,
+ 5928,22728, 5936,26824, 5944,30920, 5960,6856, 5968,10952, 5976,15048,
+ 5984,19144, 5992,23240, 6000,27336, 6008,31432, 6024,7368, 6032,11464,
+ 6040,15560, 6048,19656, 6056,23752, 6064,27848, 6072,31944, 6088,7880,
+ 6096,11976, 6104,16072, 6112,20168, 6120,24264, 6128,28360, 6136,32456,
+ 6160,8456, 6168,12552, 6176,16648, 6184,20744, 6192,24840, 6200,28936,
+ 6224,8968, 6232,13064, 6240,17160, 6248,21256, 6256,25352, 6264,29448,
+ 6288,9480, 6296,13576, 6304,17672, 6312,21768, 6320,25864, 6328,29960,
+ 6352,9992, 6360,14088, 6368,18184, 6376,22280, 6384,26376, 6392,30472,
+ 6416,10504, 6424,14600, 6432,18696, 6440,22792, 6448,26888, 6456,30984,
+ 6472,6920, 6480,11016, 6488,15112, 6496,19208, 6504,23304, 6512,27400,
+ 6520,31496, 6536,7432, 6544,11528, 6552,15624, 6560,19720, 6568,23816,
+ 6576,27912, 6584,32008, 6600,7944, 6608,12040, 6616,16136, 6624,20232,
+ 6632,24328, 6640,28424, 6648,32520, 6672,8520, 6680,12616, 6688,16712,
+ 6696,20808, 6704,24904, 6712,29000, 6736,9032, 6744,13128, 6752,17224,
+ 6760,21320, 6768,25416, 6776,29512, 6800,9544, 6808,13640, 6816,17736,
+ 6824,21832, 6832,25928, 6840,30024, 6864,10056, 6872,14152, 6880,18248,
+ 6888,22344, 6896,26440, 6904,30536, 6928,10568, 6936,14664, 6944,18760,
+ 6952,22856, 6960,26952, 6968,31048, 6992,11080, 7000,15176, 7008,19272,
+ 7016,23368, 7024,27464, 7032,31560, 7048,7496, 7056,11592, 7064,15688,
+ 7072,19784, 7080,23880, 7088,27976, 7096,32072, 7112,8008, 7120,12104,
+ 7128,16200, 7136,20296, 7144,24392, 7152,28488, 7160,32584, 7184,8584,
+ 7192,12680, 7200,16776, 7208,20872, 7216,24968, 7224,29064, 7248,9096,
+ 7256,13192, 7264,17288, 7272,21384, 7280,25480, 7288,29576, 7312,9608,
+ 7320,13704, 7328,17800, 7336,21896, 7344,25992, 7352,30088, 7376,10120,
+ 7384,14216, 7392,18312, 7400,22408, 7408,26504, 7416,30600, 7440,10632,
+ 7448,14728, 7456,18824, 7464,22920, 7472,27016, 7480,31112, 7504,11144,
+ 7512,15240, 7520,19336, 7528,23432, 7536,27528, 7544,31624, 7568,11656,
+ 7576,15752, 7584,19848, 7592,23944, 7600,28040, 7608,32136, 7624,8072,
+ 7632,12168, 7640,16264, 7648,20360, 7656,24456, 7664,28552, 7672,32648,
+ 7696,8648, 7704,12744, 7712,16840, 7720,20936, 7728,25032, 7736,29128,
+ 7760,9160, 7768,13256, 7776,17352, 7784,21448, 7792,25544, 7800,29640,
+ 7824,9672, 7832,13768, 7840,17864, 7848,21960, 7856,26056, 7864,30152,
+ 7888,10184, 7896,14280, 7904,18376, 7912,22472, 7920,26568, 7928,30664,
+ 7952,10696, 7960,14792, 7968,18888, 7976,22984, 7984,27080, 7992,31176,
+ 8016,11208, 8024,15304, 8032,19400, 8040,23496, 8048,27592, 8056,31688,
+ 8080,11720, 8088,15816, 8096,19912, 8104,24008, 8112,28104, 8120,32200,
+ 8144,12232, 8152,16328, 8160,20424, 8168,24520, 8176,28616, 8184,32712,
+ 8216,12304, 8224,16400, 8232,20496, 8240,24592, 8248,28688, 8272,8720,
+ 8280,12816, 8288,16912, 8296,21008, 8304,25104, 8312,29200, 8336,9232,
+ 8344,13328, 8352,17424, 8360,21520, 8368,25616, 8376,29712, 8400,9744,
+ 8408,13840, 8416,17936, 8424,22032, 8432,26128, 8440,30224, 8464,10256,
+ 8472,14352, 8480,18448, 8488,22544, 8496,26640, 8504,30736, 8528,10768,
+ 8536,14864, 8544,18960, 8552,23056, 8560,27152, 8568,31248, 8592,11280,
+ 8600,15376, 8608,19472, 8616,23568, 8624,27664, 8632,31760, 8656,11792,
+ 8664,15888, 8672,19984, 8680,24080, 8688,28176, 8696,32272, 8728,12368,
+ 8736,16464, 8744,20560, 8752,24656, 8760,28752, 8792,12880, 8800,16976,
+ 8808,21072, 8816,25168, 8824,29264, 8848,9296, 8856,13392, 8864,17488,
+ 8872,21584, 8880,25680, 8888,29776, 8912,9808, 8920,13904, 8928,18000,
+ 8936,22096, 8944,26192, 8952,30288, 8976,10320, 8984,14416, 8992,18512,
+ 9000,22608, 9008,26704, 9016,30800, 9040,10832, 9048,14928, 9056,19024,
+ 9064,23120, 9072,27216, 9080,31312, 9104,11344, 9112,15440, 9120,19536,
+ 9128,23632, 9136,27728, 9144,31824, 9168,11856, 9176,15952, 9184,20048,
+ 9192,24144, 9200,28240, 9208,32336, 9240,12432, 9248,16528, 9256,20624,
+ 9264,24720, 9272,28816, 9304,12944, 9312,17040, 9320,21136, 9328,25232,
+ 9336,29328, 9368,13456, 9376,17552, 9384,21648, 9392,25744, 9400,29840,
+ 9424,9872, 9432,13968, 9440,18064, 9448,22160, 9456,26256, 9464,30352,
+ 9488,10384, 9496,14480, 9504,18576, 9512,22672, 9520,26768, 9528,30864,
+ 9552,10896, 9560,14992, 9568,19088, 9576,23184, 9584,27280, 9592,31376,
+ 9616,11408, 9624,15504, 9632,19600, 9640,23696, 9648,27792, 9656,31888,
+ 9680,11920, 9688,16016, 9696,20112, 9704,24208, 9712,28304, 9720,32400,
+ 9752,12496, 9760,16592, 9768,20688, 9776,24784, 9784,28880, 9816,13008,
+ 9824,17104, 9832,21200, 9840,25296, 9848,29392, 9880,13520, 9888,17616,
+ 9896,21712, 9904,25808, 9912,29904, 9944,14032, 9952,18128, 9960,22224,
+ 9968,26320, 9976,30416, 10000,10448, 10008,14544, 10016,18640, 10024,22736,
+ 10032,26832, 10040,30928, 10064,10960, 10072,15056, 10080,19152,
+ 10088,23248, 10096,27344, 10104,31440, 10128,11472, 10136,15568,
+ 10144,19664, 10152,23760, 10160,27856, 10168,31952, 10192,11984,
+ 10200,16080, 10208,20176, 10216,24272, 10224,28368, 10232,32464,
+ 10264,12560, 10272,16656, 10280,20752, 10288,24848, 10296,28944,
+ 10328,13072, 10336,17168, 10344,21264, 10352,25360, 10360,29456,
+ 10392,13584, 10400,17680, 10408,21776, 10416,25872, 10424,29968,
+ 10456,14096, 10464,18192, 10472,22288, 10480,26384, 10488,30480,
+ 10520,14608, 10528,18704, 10536,22800, 10544,26896, 10552,30992,
+ 10576,11024, 10584,15120, 10592,19216, 10600,23312, 10608,27408,
+ 10616,31504, 10640,11536, 10648,15632, 10656,19728, 10664,23824,
+ 10672,27920, 10680,32016, 10704,12048, 10712,16144, 10720,20240,
+ 10728,24336, 10736,28432, 10744,32528, 10776,12624, 10784,16720,
+ 10792,20816, 10800,24912, 10808,29008, 10840,13136, 10848,17232,
+ 10856,21328, 10864,25424, 10872,29520, 10904,13648, 10912,17744,
+ 10920,21840, 10928,25936, 10936,30032, 10968,14160, 10976,18256,
+ 10984,22352, 10992,26448, 11000,30544, 11032,14672, 11040,18768,
+ 11048,22864, 11056,26960, 11064,31056, 11096,15184, 11104,19280,
+ 11112,23376, 11120,27472, 11128,31568, 11152,11600, 11160,15696,
+ 11168,19792, 11176,23888, 11184,27984, 11192,32080, 11216,12112,
+ 11224,16208, 11232,20304, 11240,24400, 11248,28496, 11256,32592,
+ 11288,12688, 11296,16784, 11304,20880, 11312,24976, 11320,29072,
+ 11352,13200, 11360,17296, 11368,21392, 11376,25488, 11384,29584,
+ 11416,13712, 11424,17808, 11432,21904, 11440,26000, 11448,30096,
+ 11480,14224, 11488,18320, 11496,22416, 11504,26512, 11512,30608,
+ 11544,14736, 11552,18832, 11560,22928, 11568,27024, 11576,31120,
+ 11608,15248, 11616,19344, 11624,23440, 11632,27536, 11640,31632,
+ 11672,15760, 11680,19856, 11688,23952, 11696,28048, 11704,32144,
+ 11728,12176, 11736,16272, 11744,20368, 11752,24464, 11760,28560,
+ 11768,32656, 11800,12752, 11808,16848, 11816,20944, 11824,25040,
+ 11832,29136, 11864,13264, 11872,17360, 11880,21456, 11888,25552,
+ 11896,29648, 11928,13776, 11936,17872, 11944,21968, 11952,26064,
+ 11960,30160, 11992,14288, 12000,18384, 12008,22480, 12016,26576,
+ 12024,30672, 12056,14800, 12064,18896, 12072,22992, 12080,27088,
+ 12088,31184, 12120,15312, 12128,19408, 12136,23504, 12144,27600,
+ 12152,31696, 12184,15824, 12192,19920, 12200,24016, 12208,28112,
+ 12216,32208, 12248,16336, 12256,20432, 12264,24528, 12272,28624,
+ 12280,32720, 12320,16408, 12328,20504, 12336,24600, 12344,28696,
+ 12376,12824, 12384,16920, 12392,21016, 12400,25112, 12408,29208,
+ 12440,13336, 12448,17432, 12456,21528, 12464,25624, 12472,29720,
+ 12504,13848, 12512,17944, 12520,22040, 12528,26136, 12536,30232,
+ 12568,14360, 12576,18456, 12584,22552, 12592,26648, 12600,30744,
+ 12632,14872, 12640,18968, 12648,23064, 12656,27160, 12664,31256,
+ 12696,15384, 12704,19480, 12712,23576, 12720,27672, 12728,31768,
+ 12760,15896, 12768,19992, 12776,24088, 12784,28184, 12792,32280,
+ 12832,16472, 12840,20568, 12848,24664, 12856,28760, 12896,16984,
+ 12904,21080, 12912,25176, 12920,29272, 12952,13400, 12960,17496,
+ 12968,21592, 12976,25688, 12984,29784, 13016,13912, 13024,18008,
+ 13032,22104, 13040,26200, 13048,30296, 13080,14424, 13088,18520,
+ 13096,22616, 13104,26712, 13112,30808, 13144,14936, 13152,19032,
+ 13160,23128, 13168,27224, 13176,31320, 13208,15448, 13216,19544,
+ 13224,23640, 13232,27736, 13240,31832, 13272,15960, 13280,20056,
+ 13288,24152, 13296,28248, 13304,32344, 13344,16536, 13352,20632,
+ 13360,24728, 13368,28824, 13408,17048, 13416,21144, 13424,25240,
+ 13432,29336, 13472,17560, 13480,21656, 13488,25752, 13496,29848,
+ 13528,13976, 13536,18072, 13544,22168, 13552,26264, 13560,30360,
+ 13592,14488, 13600,18584, 13608,22680, 13616,26776, 13624,30872,
+ 13656,15000, 13664,19096, 13672,23192, 13680,27288, 13688,31384,
+ 13720,15512, 13728,19608, 13736,23704, 13744,27800, 13752,31896,
+ 13784,16024, 13792,20120, 13800,24216, 13808,28312, 13816,32408,
+ 13856,16600, 13864,20696, 13872,24792, 13880,28888, 13920,17112,
+ 13928,21208, 13936,25304, 13944,29400, 13984,17624, 13992,21720,
+ 14000,25816, 14008,29912, 14048,18136, 14056,22232, 14064,26328,
+ 14072,30424, 14104,14552, 14112,18648, 14120,22744, 14128,26840,
+ 14136,30936, 14168,15064, 14176,19160, 14184,23256, 14192,27352,
+ 14200,31448, 14232,15576, 14240,19672, 14248,23768, 14256,27864,
+ 14264,31960, 14296,16088, 14304,20184, 14312,24280, 14320,28376,
+ 14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952,
+ 14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688,
+ 14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296,
+ 14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904,
+ 14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416,
+ 14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928,
+ 14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440,
+ 14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016,
+ 14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752,
+ 15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360,
+ 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968,
+ 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576,
+ 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088,
+ 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600,
+ 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304,
+ 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912,
+ 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520,
+ 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128,
+ 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864,
+ 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376,
+ 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952,
+ 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560,
+ 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168,
+ 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904,
+ 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512,
+ 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120,
+ 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728,
+ 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024,
+ 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632,
+ 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240,
+ 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976,
+ 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584,
+ 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192,
+ 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088,
+ 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696,
+ 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304,
+ 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040,
+ 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648,
+ 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256,
+ 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152,
+ 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856,
+ 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592,
+ 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200,
+ 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808,
+ 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416,
+ 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312,
+ 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240,
+ 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848,
+ 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456,
+ 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192,
+ 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864,
+ 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792,
+ 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496,
+ 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328,
+ 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936,
+ 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544,
+ 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440,
+ 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368,
+ 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072,
+ 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904,
+ 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512,
+ 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408,
+ 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112,
+ 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040,
+ 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968,
+ 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576,
+ 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472,
+ 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176,
+ 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104,
+ 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032,
+ 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736,
+ 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224,
+ 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152,
+ 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080,
+ 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784,
+ 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776,
+ 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800,
+ 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728,
+ 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656,
+ 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360,
+ 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768,
+ 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696,
+ 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400,
+ 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328,
+ 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416,
+ 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760,
+ 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464,
+ 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392,
+ 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480,
+ 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920,
+ 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848,
+ 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552,
+ 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960,
+ 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080,
+ 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104,
+ 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096,
+ 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536,
+ 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656,
+ 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680,
+ 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088,
+ 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208,
+ 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648,
+ 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648,
+ 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768,
+ 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208,
+ 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808,
+ 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248,
+ 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368,
+ 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384,
+ 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824,
+ 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424,
+ 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376,
+ 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496,
+ 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024,
+ 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464,
+ 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576,
+ 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528,
+ 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640,
+ 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688,
+ 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216,
+ 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752,
+ 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312,
+ 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864,
+ 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928,
+ 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504,
+ 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632,
+ 32248,32696
+};
+
+
+const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH] =
+{
+ //radix 4, size 12
+ 8,64, 16,32, 24,96, 40,80, 56,112, 88,104
+};
+
+const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH] =
+{
+ //4x2, size 24
+ 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144,
+ 88,208, 104,176, 120,240, 152,200, 184,232
+};
+
+const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH] =
+{
+ //radix 4, size 56
+ 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352,
+ 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432,
+ 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472
+};
+
+const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH] =
+{
+ //4x2, size 112
+ 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192,
+ 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608,
+ 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912,
+ 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624,
+ 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968,
+ 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984
+};
+
+const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH] =
+{
+ //radix 4, size 240
+ 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640,
+ 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320,
+ 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960,
+ 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672,
+ 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376,
+ 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040,
+ 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912,
+ 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488,
+ 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456,
+ 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520,
+ 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928,
+ 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832,
+ 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816,
+ 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976
+};
+
+const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH] =
+{
+ //4x2, size 480
+ 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280,
+ 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640,
+ 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944,
+ 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648,
+ 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216,
+ 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960,
+ 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616,
+ 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184,
+ 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976,
+ 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400,
+ 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784,
+ 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064,
+ 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344,
+ 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728,
+ 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152,
+ 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920,
+ 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024,
+ 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376,
+ 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480,
+ 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696,
+ 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824,
+ 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312,
+ 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464,
+ 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912,
+ 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624,
+ 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008,
+ 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072,
+ 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928,
+ 3512,3800, 3576,4056, 3704,3896, 3832,4024
+};
+
+const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] =
+{
+ //radix 4, size 992
+ 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608,
+ 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352,
+ 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864,
+ 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176,
+ 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688,
+ 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528,
+ 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040,
+ 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088,
+ 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696,
+ 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392,
+ 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904,
+ 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360,
+ 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544,
+ 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008,
+ 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080,
+ 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688,
+ 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432,
+ 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944,
+ 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304,
+ 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696,
+ 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536,
+ 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048,
+ 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168,
+ 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776,
+ 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960,
+ 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320,
+ 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784,
+ 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624,
+ 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112,
+ 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184,
+ 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368,
+ 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832,
+ 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264,
+ 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728,
+ 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008,
+ 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224,
+ 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664,
+ 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944,
+ 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352,
+ 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792,
+ 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072,
+ 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168,
+ 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400,
+ 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936,
+ 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784,
+ 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552,
+ 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208,
+ 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792,
+ 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000,
+ 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848,
+ 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664,
+ 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176,
+ 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384,
+ 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256,
+ 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512,
+ 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192,
+ 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496,
+ 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368,
+ 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112,
+ 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720,
+ 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312,
+ 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080,
+ 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504,
+ 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888,
+ 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680,
+ 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808,
+ 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512,
+ 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736,
+ 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056
+};
+
+const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] =
+{
+ //4x2, size 1984
+ 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024,
+ 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512,
+ 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848,
+ 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680,
+ 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400,
+ 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520,
+ 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816,
+ 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080,
+ 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416,
+ 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248,
+ 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736,
+ 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856,
+ 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576,
+ 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408,
+ 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744,
+ 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232,
+ 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064,
+ 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208,
+ 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232,
+ 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720,
+ 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840,
+ 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560,
+ 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584,
+ 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072,
+ 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904,
+ 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240,
+ 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264,
+ 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752,
+ 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776,
+ 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496,
+ 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520,
+ 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008,
+ 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032,
+ 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272,
+ 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296,
+ 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784,
+ 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808,
+ 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432,
+ 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456,
+ 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944,
+ 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968,
+ 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496,
+ 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520,
+ 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888,
+ 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608,
+ 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536,
+ 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024,
+ 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048,
+ 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192,
+ 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408,
+ 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848,
+ 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872,
+ 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496,
+ 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712,
+ 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080,
+ 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416,
+ 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344,
+ 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024,
+ 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000,
+ 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624,
+ 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840,
+ 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208,
+ 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304,
+ 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280,
+ 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672,
+ 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888,
+ 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392,
+ 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072,
+ 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096,
+ 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288,
+ 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504,
+ 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776,
+ 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688,
+ 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664,
+ 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248,
+ 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272,
+ 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392,
+ 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736,
+ 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952,
+ 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648,
+ 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992,
+ 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016,
+ 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424,
+ 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008,
+ 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888,
+ 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680,
+ 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264,
+ 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240,
+ 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264,
+ 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848,
+ 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728,
+ 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520,
+ 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104,
+ 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080,
+ 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392,
+ 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976,
+ 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856,
+ 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648,
+ 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232,
+ 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112,
+ 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328,
+ 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864,
+ 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560,
+ 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632,
+ 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096,
+ 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528,
+ 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600,
+ 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064,
+ 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832,
+ 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296,
+ 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368,
+ 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272,
+ 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736,
+ 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600,
+ 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064,
+ 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136,
+ 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400,
+ 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960,
+ 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608,
+ 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240,
+ 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312,
+ 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824,
+ 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616,
+ 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128,
+ 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200,
+ 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560,
+ 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072,
+ 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816,
+ 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328,
+ 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840,
+ 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584,
+ 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048,
+ 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504,
+ 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992,
+ 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688,
+ 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296,
+ 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952,
+ 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672,
+ 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232,
+ 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080,
+ 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848,
+ 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336,
+ 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616,
+ 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152,
+ 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024,
+ 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280,
+ 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680,
+ 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576,
+ 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344,
+ 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184,
+ 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248
+};
+
+const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] =
+{
+ //radix 4, size 4032
+ 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048,
+ 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720,
+ 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312,
+ 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552,
+ 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608,
+ 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136,
+ 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728,
+ 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968,
+ 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640,
+ 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304,
+ 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976,
+ 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568,
+ 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808,
+ 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248,
+ 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912,
+ 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368,
+ 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032,
+ 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320,
+ 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176,
+ 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464,
+ 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632,
+ 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776,
+ 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832,
+ 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688,
+ 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976,
+ 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144,
+ 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288,
+ 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576,
+ 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432,
+ 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720,
+ 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888,
+ 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032,
+ 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088,
+ 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944,
+ 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232,
+ 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400,
+ 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544,
+ 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256,
+ 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496,
+ 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784,
+ 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376,
+ 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232,
+ 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152,
+ 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008,
+ 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296,
+ 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888,
+ 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744,
+ 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896,
+ 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560,
+ 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728,
+ 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392,
+ 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680,
+ 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312,
+ 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976,
+ 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432,
+ 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288,
+ 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576,
+ 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480,
+ 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720,
+ 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312,
+ 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840,
+ 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896,
+ 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136,
+ 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424,
+ 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016,
+ 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872,
+ 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024,
+ 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688,
+ 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856,
+ 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144,
+ 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808,
+ 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440,
+ 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104,
+ 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560,
+ 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224,
+ 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416,
+ 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464,
+ 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752,
+ 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344,
+ 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584,
+ 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640,
+ 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168,
+ 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760,
+ 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000,
+ 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288,
+ 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960,
+ 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624,
+ 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792,
+ 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456,
+ 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376,
+ 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424,
+ 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016,
+ 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256,
+ 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544,
+ 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832,
+ 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496,
+ 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472,
+ 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712,
+ 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152,
+ 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816,
+ 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272,
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+ 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928,
+ 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464,
+ 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064,
+ 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136,
+ 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600,
+ 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744,
+ 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208,
+ 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280,
+ 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928,
+ 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488,
+ 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848,
+ 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264,
+ 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128,
+ 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640,
+ 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784,
+ 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296,
+ 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992,
+ 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600,
+ 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448,
+ 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168,
+ 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776,
+ 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312,
+ 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568,
+ 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160,
+ 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376,
+ 31480,32120, 31736,32632, 32248,32504
+};
+
+/**
+* \par
+* Example code for Floating-point RFFT Twiddle factors Generation:
+* \par
+* TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).'
+* \par
+* Real and Imag values are in interleaved fashion
+*/
+const float32_t twiddleCoef_rfft_32[32] = {
+0.0f , 1.0f ,
+0.195090322f , 0.98078528f ,
+0.382683432f , 0.923879533f ,
+0.555570233f , 0.831469612f ,
+0.707106781f , 0.707106781f ,
+0.831469612f , 0.555570233f ,
+0.923879533f , 0.382683432f ,
+0.98078528f , 0.195090322f ,
+1.0f , 0.0f ,
+0.98078528f , -0.195090322f ,
+0.923879533f , -0.382683432f ,
+0.831469612f , -0.555570233f ,
+0.707106781f , -0.707106781f ,
+0.555570233f , -0.831469612f ,
+0.382683432f , -0.923879533f ,
+0.195090322f , -0.98078528f
+};
+
+const float32_t twiddleCoef_rfft_64[64] = {
+0.0f, 1.0f,
+0.098017140329561f, 0.995184726672197f,
+0.195090322016128f, 0.98078528040323f,
+0.290284677254462f, 0.956940335732209f,
+0.38268343236509f, 0.923879532511287f,
+0.471396736825998f, 0.881921264348355f,
+0.555570233019602f, 0.831469612302545f,
+0.634393284163645f, 0.773010453362737f,
+0.707106781186547f, 0.707106781186548f,
+0.773010453362737f, 0.634393284163645f,
+0.831469612302545f, 0.555570233019602f,
+0.881921264348355f, 0.471396736825998f,
+0.923879532511287f, 0.38268343236509f,
+0.956940335732209f, 0.290284677254462f,
+0.98078528040323f, 0.195090322016128f,
+0.995184726672197f, 0.098017140329561f,
+1.0f, 0.0f,
+0.995184726672197f, -0.098017140329561f,
+0.98078528040323f, -0.195090322016128f,
+0.956940335732209f, -0.290284677254462f,
+0.923879532511287f, -0.38268343236509f,
+0.881921264348355f, -0.471396736825998f,
+0.831469612302545f, -0.555570233019602f,
+0.773010453362737f, -0.634393284163645f,
+0.707106781186548f, -0.707106781186547f,
+0.634393284163645f, -0.773010453362737f,
+0.555570233019602f, -0.831469612302545f,
+0.471396736825998f, -0.881921264348355f,
+0.38268343236509f, -0.923879532511287f,
+0.290284677254462f, -0.956940335732209f,
+0.195090322016129f, -0.98078528040323f,
+0.098017140329561f, -0.995184726672197f
+};
+
+const float32_t twiddleCoef_rfft_128[128] = {
+ 0.000000000f, 1.000000000f,
+ 0.049067674f, 0.998795456f,
+ 0.098017140f, 0.995184727f,
+ 0.146730474f, 0.989176510f,
+ 0.195090322f, 0.980785280f,
+ 0.242980180f, 0.970031253f,
+ 0.290284677f, 0.956940336f,
+ 0.336889853f, 0.941544065f,
+ 0.382683432f, 0.923879533f,
+ 0.427555093f, 0.903989293f,
+ 0.471396737f, 0.881921264f,
+ 0.514102744f, 0.857728610f,
+ 0.555570233f, 0.831469612f,
+ 0.595699304f, 0.803207531f,
+ 0.634393284f, 0.773010453f,
+ 0.671558955f, 0.740951125f,
+ 0.707106781f, 0.707106781f,
+ 0.740951125f, 0.671558955f,
+ 0.773010453f, 0.634393284f,
+ 0.803207531f, 0.595699304f,
+ 0.831469612f, 0.555570233f,
+ 0.857728610f, 0.514102744f,
+ 0.881921264f, 0.471396737f,
+ 0.903989293f, 0.427555093f,
+ 0.923879533f, 0.382683432f,
+ 0.941544065f, 0.336889853f,
+ 0.956940336f, 0.290284677f,
+ 0.970031253f, 0.242980180f,
+ 0.980785280f, 0.195090322f,
+ 0.989176510f, 0.146730474f,
+ 0.995184727f, 0.098017140f,
+ 0.998795456f, 0.049067674f,
+ 1.000000000f, 0.000000000f,
+ 0.998795456f, -0.049067674f,
+ 0.995184727f, -0.098017140f,
+ 0.989176510f, -0.146730474f,
+ 0.980785280f, -0.195090322f,
+ 0.970031253f, -0.242980180f,
+ 0.956940336f, -0.290284677f,
+ 0.941544065f, -0.336889853f,
+ 0.923879533f, -0.382683432f,
+ 0.903989293f, -0.427555093f,
+ 0.881921264f, -0.471396737f,
+ 0.857728610f, -0.514102744f,
+ 0.831469612f, -0.555570233f,
+ 0.803207531f, -0.595699304f,
+ 0.773010453f, -0.634393284f,
+ 0.740951125f, -0.671558955f,
+ 0.707106781f, -0.707106781f,
+ 0.671558955f, -0.740951125f,
+ 0.634393284f, -0.773010453f,
+ 0.595699304f, -0.803207531f,
+ 0.555570233f, -0.831469612f,
+ 0.514102744f, -0.857728610f,
+ 0.471396737f, -0.881921264f,
+ 0.427555093f, -0.903989293f,
+ 0.382683432f, -0.923879533f,
+ 0.336889853f, -0.941544065f,
+ 0.290284677f, -0.956940336f,
+ 0.242980180f, -0.970031253f,
+ 0.195090322f, -0.980785280f,
+ 0.146730474f, -0.989176510f,
+ 0.098017140f, -0.995184727f,
+ 0.049067674f, -0.998795456f
+};
+
+const float32_t twiddleCoef_rfft_256[256] = {
+ 0.000000000f, 1.000000000f,
+ 0.024541229f, 0.999698819f,
+ 0.049067674f, 0.998795456f,
+ 0.073564564f, 0.997290457f,
+ 0.098017140f, 0.995184727f,
+ 0.122410675f, 0.992479535f,
+ 0.146730474f, 0.989176510f,
+ 0.170961889f, 0.985277642f,
+ 0.195090322f, 0.980785280f,
+ 0.219101240f, 0.975702130f,
+ 0.242980180f, 0.970031253f,
+ 0.266712757f, 0.963776066f,
+ 0.290284677f, 0.956940336f,
+ 0.313681740f, 0.949528181f,
+ 0.336889853f, 0.941544065f,
+ 0.359895037f, 0.932992799f,
+ 0.382683432f, 0.923879533f,
+ 0.405241314f, 0.914209756f,
+ 0.427555093f, 0.903989293f,
+ 0.449611330f, 0.893224301f,
+ 0.471396737f, 0.881921264f,
+ 0.492898192f, 0.870086991f,
+ 0.514102744f, 0.857728610f,
+ 0.534997620f, 0.844853565f,
+ 0.555570233f, 0.831469612f,
+ 0.575808191f, 0.817584813f,
+ 0.595699304f, 0.803207531f,
+ 0.615231591f, 0.788346428f,
+ 0.634393284f, 0.773010453f,
+ 0.653172843f, 0.757208847f,
+ 0.671558955f, 0.740951125f,
+ 0.689540545f, 0.724247083f,
+ 0.707106781f, 0.707106781f,
+ 0.724247083f, 0.689540545f,
+ 0.740951125f, 0.671558955f,
+ 0.757208847f, 0.653172843f,
+ 0.773010453f, 0.634393284f,
+ 0.788346428f, 0.615231591f,
+ 0.803207531f, 0.595699304f,
+ 0.817584813f, 0.575808191f,
+ 0.831469612f, 0.555570233f,
+ 0.844853565f, 0.534997620f,
+ 0.857728610f, 0.514102744f,
+ 0.870086991f, 0.492898192f,
+ 0.881921264f, 0.471396737f,
+ 0.893224301f, 0.449611330f,
+ 0.903989293f, 0.427555093f,
+ 0.914209756f, 0.405241314f,
+ 0.923879533f, 0.382683432f,
+ 0.932992799f, 0.359895037f,
+ 0.941544065f, 0.336889853f,
+ 0.949528181f, 0.313681740f,
+ 0.956940336f, 0.290284677f,
+ 0.963776066f, 0.266712757f,
+ 0.970031253f, 0.242980180f,
+ 0.975702130f, 0.219101240f,
+ 0.980785280f, 0.195090322f,
+ 0.985277642f, 0.170961889f,
+ 0.989176510f, 0.146730474f,
+ 0.992479535f, 0.122410675f,
+ 0.995184727f, 0.098017140f,
+ 0.997290457f, 0.073564564f,
+ 0.998795456f, 0.049067674f,
+ 0.999698819f, 0.024541229f,
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, -0.024541229f,
+ 0.998795456f, -0.049067674f,
+ 0.997290457f, -0.073564564f,
+ 0.995184727f, -0.098017140f,
+ 0.992479535f, -0.122410675f,
+ 0.989176510f, -0.146730474f,
+ 0.985277642f, -0.170961889f,
+ 0.980785280f, -0.195090322f,
+ 0.975702130f, -0.219101240f,
+ 0.970031253f, -0.242980180f,
+ 0.963776066f, -0.266712757f,
+ 0.956940336f, -0.290284677f,
+ 0.949528181f, -0.313681740f,
+ 0.941544065f, -0.336889853f,
+ 0.932992799f, -0.359895037f,
+ 0.923879533f, -0.382683432f,
+ 0.914209756f, -0.405241314f,
+ 0.903989293f, -0.427555093f,
+ 0.893224301f, -0.449611330f,
+ 0.881921264f, -0.471396737f,
+ 0.870086991f, -0.492898192f,
+ 0.857728610f, -0.514102744f,
+ 0.844853565f, -0.534997620f,
+ 0.831469612f, -0.555570233f,
+ 0.817584813f, -0.575808191f,
+ 0.803207531f, -0.595699304f,
+ 0.788346428f, -0.615231591f,
+ 0.773010453f, -0.634393284f,
+ 0.757208847f, -0.653172843f,
+ 0.740951125f, -0.671558955f,
+ 0.724247083f, -0.689540545f,
+ 0.707106781f, -0.707106781f,
+ 0.689540545f, -0.724247083f,
+ 0.671558955f, -0.740951125f,
+ 0.653172843f, -0.757208847f,
+ 0.634393284f, -0.773010453f,
+ 0.615231591f, -0.788346428f,
+ 0.595699304f, -0.803207531f,
+ 0.575808191f, -0.817584813f,
+ 0.555570233f, -0.831469612f,
+ 0.534997620f, -0.844853565f,
+ 0.514102744f, -0.857728610f,
+ 0.492898192f, -0.870086991f,
+ 0.471396737f, -0.881921264f,
+ 0.449611330f, -0.893224301f,
+ 0.427555093f, -0.903989293f,
+ 0.405241314f, -0.914209756f,
+ 0.382683432f, -0.923879533f,
+ 0.359895037f, -0.932992799f,
+ 0.336889853f, -0.941544065f,
+ 0.313681740f, -0.949528181f,
+ 0.290284677f, -0.956940336f,
+ 0.266712757f, -0.963776066f,
+ 0.242980180f, -0.970031253f,
+ 0.219101240f, -0.975702130f,
+ 0.195090322f, -0.980785280f,
+ 0.170961889f, -0.985277642f,
+ 0.146730474f, -0.989176510f,
+ 0.122410675f, -0.992479535f,
+ 0.098017140f, -0.995184727f,
+ 0.073564564f, -0.997290457f,
+ 0.049067674f, -0.998795456f,
+ 0.024541229f, -0.999698819f
+};
+
+const float32_t twiddleCoef_rfft_512[512] = {
+ 0.000000000f, 1.000000000f,
+ 0.012271538f, 0.999924702f,
+ 0.024541229f, 0.999698819f,
+ 0.036807223f, 0.999322385f,
+ 0.049067674f, 0.998795456f,
+ 0.061320736f, 0.998118113f,
+ 0.073564564f, 0.997290457f,
+ 0.085797312f, 0.996312612f,
+ 0.098017140f, 0.995184727f,
+ 0.110222207f, 0.993906970f,
+ 0.122410675f, 0.992479535f,
+ 0.134580709f, 0.990902635f,
+ 0.146730474f, 0.989176510f,
+ 0.158858143f, 0.987301418f,
+ 0.170961889f, 0.985277642f,
+ 0.183039888f, 0.983105487f,
+ 0.195090322f, 0.980785280f,
+ 0.207111376f, 0.978317371f,
+ 0.219101240f, 0.975702130f,
+ 0.231058108f, 0.972939952f,
+ 0.242980180f, 0.970031253f,
+ 0.254865660f, 0.966976471f,
+ 0.266712757f, 0.963776066f,
+ 0.278519689f, 0.960430519f,
+ 0.290284677f, 0.956940336f,
+ 0.302005949f, 0.953306040f,
+ 0.313681740f, 0.949528181f,
+ 0.325310292f, 0.945607325f,
+ 0.336889853f, 0.941544065f,
+ 0.348418680f, 0.937339012f,
+ 0.359895037f, 0.932992799f,
+ 0.371317194f, 0.928506080f,
+ 0.382683432f, 0.923879533f,
+ 0.393992040f, 0.919113852f,
+ 0.405241314f, 0.914209756f,
+ 0.416429560f, 0.909167983f,
+ 0.427555093f, 0.903989293f,
+ 0.438616239f, 0.898674466f,
+ 0.449611330f, 0.893224301f,
+ 0.460538711f, 0.887639620f,
+ 0.471396737f, 0.881921264f,
+ 0.482183772f, 0.876070094f,
+ 0.492898192f, 0.870086991f,
+ 0.503538384f, 0.863972856f,
+ 0.514102744f, 0.857728610f,
+ 0.524589683f, 0.851355193f,
+ 0.534997620f, 0.844853565f,
+ 0.545324988f, 0.838224706f,
+ 0.555570233f, 0.831469612f,
+ 0.565731811f, 0.824589303f,
+ 0.575808191f, 0.817584813f,
+ 0.585797857f, 0.810457198f,
+ 0.595699304f, 0.803207531f,
+ 0.605511041f, 0.795836905f,
+ 0.615231591f, 0.788346428f,
+ 0.624859488f, 0.780737229f,
+ 0.634393284f, 0.773010453f,
+ 0.643831543f, 0.765167266f,
+ 0.653172843f, 0.757208847f,
+ 0.662415778f, 0.749136395f,
+ 0.671558955f, 0.740951125f,
+ 0.680600998f, 0.732654272f,
+ 0.689540545f, 0.724247083f,
+ 0.698376249f, 0.715730825f,
+ 0.707106781f, 0.707106781f,
+ 0.715730825f, 0.698376249f,
+ 0.724247083f, 0.689540545f,
+ 0.732654272f, 0.680600998f,
+ 0.740951125f, 0.671558955f,
+ 0.749136395f, 0.662415778f,
+ 0.757208847f, 0.653172843f,
+ 0.765167266f, 0.643831543f,
+ 0.773010453f, 0.634393284f,
+ 0.780737229f, 0.624859488f,
+ 0.788346428f, 0.615231591f,
+ 0.795836905f, 0.605511041f,
+ 0.803207531f, 0.595699304f,
+ 0.810457198f, 0.585797857f,
+ 0.817584813f, 0.575808191f,
+ 0.824589303f, 0.565731811f,
+ 0.831469612f, 0.555570233f,
+ 0.838224706f, 0.545324988f,
+ 0.844853565f, 0.534997620f,
+ 0.851355193f, 0.524589683f,
+ 0.857728610f, 0.514102744f,
+ 0.863972856f, 0.503538384f,
+ 0.870086991f, 0.492898192f,
+ 0.876070094f, 0.482183772f,
+ 0.881921264f, 0.471396737f,
+ 0.887639620f, 0.460538711f,
+ 0.893224301f, 0.449611330f,
+ 0.898674466f, 0.438616239f,
+ 0.903989293f, 0.427555093f,
+ 0.909167983f, 0.416429560f,
+ 0.914209756f, 0.405241314f,
+ 0.919113852f, 0.393992040f,
+ 0.923879533f, 0.382683432f,
+ 0.928506080f, 0.371317194f,
+ 0.932992799f, 0.359895037f,
+ 0.937339012f, 0.348418680f,
+ 0.941544065f, 0.336889853f,
+ 0.945607325f, 0.325310292f,
+ 0.949528181f, 0.313681740f,
+ 0.953306040f, 0.302005949f,
+ 0.956940336f, 0.290284677f,
+ 0.960430519f, 0.278519689f,
+ 0.963776066f, 0.266712757f,
+ 0.966976471f, 0.254865660f,
+ 0.970031253f, 0.242980180f,
+ 0.972939952f, 0.231058108f,
+ 0.975702130f, 0.219101240f,
+ 0.978317371f, 0.207111376f,
+ 0.980785280f, 0.195090322f,
+ 0.983105487f, 0.183039888f,
+ 0.985277642f, 0.170961889f,
+ 0.987301418f, 0.158858143f,
+ 0.989176510f, 0.146730474f,
+ 0.990902635f, 0.134580709f,
+ 0.992479535f, 0.122410675f,
+ 0.993906970f, 0.110222207f,
+ 0.995184727f, 0.098017140f,
+ 0.996312612f, 0.085797312f,
+ 0.997290457f, 0.073564564f,
+ 0.998118113f, 0.061320736f,
+ 0.998795456f, 0.049067674f,
+ 0.999322385f, 0.036807223f,
+ 0.999698819f, 0.024541229f,
+ 0.999924702f, 0.012271538f,
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, -0.012271538f,
+ 0.999698819f, -0.024541229f,
+ 0.999322385f, -0.036807223f,
+ 0.998795456f, -0.049067674f,
+ 0.998118113f, -0.061320736f,
+ 0.997290457f, -0.073564564f,
+ 0.996312612f, -0.085797312f,
+ 0.995184727f, -0.098017140f,
+ 0.993906970f, -0.110222207f,
+ 0.992479535f, -0.122410675f,
+ 0.990902635f, -0.134580709f,
+ 0.989176510f, -0.146730474f,
+ 0.987301418f, -0.158858143f,
+ 0.985277642f, -0.170961889f,
+ 0.983105487f, -0.183039888f,
+ 0.980785280f, -0.195090322f,
+ 0.978317371f, -0.207111376f,
+ 0.975702130f, -0.219101240f,
+ 0.972939952f, -0.231058108f,
+ 0.970031253f, -0.242980180f,
+ 0.966976471f, -0.254865660f,
+ 0.963776066f, -0.266712757f,
+ 0.960430519f, -0.278519689f,
+ 0.956940336f, -0.290284677f,
+ 0.953306040f, -0.302005949f,
+ 0.949528181f, -0.313681740f,
+ 0.945607325f, -0.325310292f,
+ 0.941544065f, -0.336889853f,
+ 0.937339012f, -0.348418680f,
+ 0.932992799f, -0.359895037f,
+ 0.928506080f, -0.371317194f,
+ 0.923879533f, -0.382683432f,
+ 0.919113852f, -0.393992040f,
+ 0.914209756f, -0.405241314f,
+ 0.909167983f, -0.416429560f,
+ 0.903989293f, -0.427555093f,
+ 0.898674466f, -0.438616239f,
+ 0.893224301f, -0.449611330f,
+ 0.887639620f, -0.460538711f,
+ 0.881921264f, -0.471396737f,
+ 0.876070094f, -0.482183772f,
+ 0.870086991f, -0.492898192f,
+ 0.863972856f, -0.503538384f,
+ 0.857728610f, -0.514102744f,
+ 0.851355193f, -0.524589683f,
+ 0.844853565f, -0.534997620f,
+ 0.838224706f, -0.545324988f,
+ 0.831469612f, -0.555570233f,
+ 0.824589303f, -0.565731811f,
+ 0.817584813f, -0.575808191f,
+ 0.810457198f, -0.585797857f,
+ 0.803207531f, -0.595699304f,
+ 0.795836905f, -0.605511041f,
+ 0.788346428f, -0.615231591f,
+ 0.780737229f, -0.624859488f,
+ 0.773010453f, -0.634393284f,
+ 0.765167266f, -0.643831543f,
+ 0.757208847f, -0.653172843f,
+ 0.749136395f, -0.662415778f,
+ 0.740951125f, -0.671558955f,
+ 0.732654272f, -0.680600998f,
+ 0.724247083f, -0.689540545f,
+ 0.715730825f, -0.698376249f,
+ 0.707106781f, -0.707106781f,
+ 0.698376249f, -0.715730825f,
+ 0.689540545f, -0.724247083f,
+ 0.680600998f, -0.732654272f,
+ 0.671558955f, -0.740951125f,
+ 0.662415778f, -0.749136395f,
+ 0.653172843f, -0.757208847f,
+ 0.643831543f, -0.765167266f,
+ 0.634393284f, -0.773010453f,
+ 0.624859488f, -0.780737229f,
+ 0.615231591f, -0.788346428f,
+ 0.605511041f, -0.795836905f,
+ 0.595699304f, -0.803207531f,
+ 0.585797857f, -0.810457198f,
+ 0.575808191f, -0.817584813f,
+ 0.565731811f, -0.824589303f,
+ 0.555570233f, -0.831469612f,
+ 0.545324988f, -0.838224706f,
+ 0.534997620f, -0.844853565f,
+ 0.524589683f, -0.851355193f,
+ 0.514102744f, -0.857728610f,
+ 0.503538384f, -0.863972856f,
+ 0.492898192f, -0.870086991f,
+ 0.482183772f, -0.876070094f,
+ 0.471396737f, -0.881921264f,
+ 0.460538711f, -0.887639620f,
+ 0.449611330f, -0.893224301f,
+ 0.438616239f, -0.898674466f,
+ 0.427555093f, -0.903989293f,
+ 0.416429560f, -0.909167983f,
+ 0.405241314f, -0.914209756f,
+ 0.393992040f, -0.919113852f,
+ 0.382683432f, -0.923879533f,
+ 0.371317194f, -0.928506080f,
+ 0.359895037f, -0.932992799f,
+ 0.348418680f, -0.937339012f,
+ 0.336889853f, -0.941544065f,
+ 0.325310292f, -0.945607325f,
+ 0.313681740f, -0.949528181f,
+ 0.302005949f, -0.953306040f,
+ 0.290284677f, -0.956940336f,
+ 0.278519689f, -0.960430519f,
+ 0.266712757f, -0.963776066f,
+ 0.254865660f, -0.966976471f,
+ 0.242980180f, -0.970031253f,
+ 0.231058108f, -0.972939952f,
+ 0.219101240f, -0.975702130f,
+ 0.207111376f, -0.978317371f,
+ 0.195090322f, -0.980785280f,
+ 0.183039888f, -0.983105487f,
+ 0.170961889f, -0.985277642f,
+ 0.158858143f, -0.987301418f,
+ 0.146730474f, -0.989176510f,
+ 0.134580709f, -0.990902635f,
+ 0.122410675f, -0.992479535f,
+ 0.110222207f, -0.993906970f,
+ 0.098017140f, -0.995184727f,
+ 0.085797312f, -0.996312612f,
+ 0.073564564f, -0.997290457f,
+ 0.061320736f, -0.998118113f,
+ 0.049067674f, -0.998795456f,
+ 0.036807223f, -0.999322385f,
+ 0.024541229f, -0.999698819f,
+ 0.012271538f, -0.999924702f
+};
+
+const float32_t twiddleCoef_rfft_1024[1024] = {
+ 0.000000000f, 1.000000000f,
+ 0.006135885f, 0.999981175f,
+ 0.012271538f, 0.999924702f,
+ 0.018406730f, 0.999830582f,
+ 0.024541229f, 0.999698819f,
+ 0.030674803f, 0.999529418f,
+ 0.036807223f, 0.999322385f,
+ 0.042938257f, 0.999077728f,
+ 0.049067674f, 0.998795456f,
+ 0.055195244f, 0.998475581f,
+ 0.061320736f, 0.998118113f,
+ 0.067443920f, 0.997723067f,
+ 0.073564564f, 0.997290457f,
+ 0.079682438f, 0.996820299f,
+ 0.085797312f, 0.996312612f,
+ 0.091908956f, 0.995767414f,
+ 0.098017140f, 0.995184727f,
+ 0.104121634f, 0.994564571f,
+ 0.110222207f, 0.993906970f,
+ 0.116318631f, 0.993211949f,
+ 0.122410675f, 0.992479535f,
+ 0.128498111f, 0.991709754f,
+ 0.134580709f, 0.990902635f,
+ 0.140658239f, 0.990058210f,
+ 0.146730474f, 0.989176510f,
+ 0.152797185f, 0.988257568f,
+ 0.158858143f, 0.987301418f,
+ 0.164913120f, 0.986308097f,
+ 0.170961889f, 0.985277642f,
+ 0.177004220f, 0.984210092f,
+ 0.183039888f, 0.983105487f,
+ 0.189068664f, 0.981963869f,
+ 0.195090322f, 0.980785280f,
+ 0.201104635f, 0.979569766f,
+ 0.207111376f, 0.978317371f,
+ 0.213110320f, 0.977028143f,
+ 0.219101240f, 0.975702130f,
+ 0.225083911f, 0.974339383f,
+ 0.231058108f, 0.972939952f,
+ 0.237023606f, 0.971503891f,
+ 0.242980180f, 0.970031253f,
+ 0.248927606f, 0.968522094f,
+ 0.254865660f, 0.966976471f,
+ 0.260794118f, 0.965394442f,
+ 0.266712757f, 0.963776066f,
+ 0.272621355f, 0.962121404f,
+ 0.278519689f, 0.960430519f,
+ 0.284407537f, 0.958703475f,
+ 0.290284677f, 0.956940336f,
+ 0.296150888f, 0.955141168f,
+ 0.302005949f, 0.953306040f,
+ 0.307849640f, 0.951435021f,
+ 0.313681740f, 0.949528181f,
+ 0.319502031f, 0.947585591f,
+ 0.325310292f, 0.945607325f,
+ 0.331106306f, 0.943593458f,
+ 0.336889853f, 0.941544065f,
+ 0.342660717f, 0.939459224f,
+ 0.348418680f, 0.937339012f,
+ 0.354163525f, 0.935183510f,
+ 0.359895037f, 0.932992799f,
+ 0.365612998f, 0.930766961f,
+ 0.371317194f, 0.928506080f,
+ 0.377007410f, 0.926210242f,
+ 0.382683432f, 0.923879533f,
+ 0.388345047f, 0.921514039f,
+ 0.393992040f, 0.919113852f,
+ 0.399624200f, 0.916679060f,
+ 0.405241314f, 0.914209756f,
+ 0.410843171f, 0.911706032f,
+ 0.416429560f, 0.909167983f,
+ 0.422000271f, 0.906595705f,
+ 0.427555093f, 0.903989293f,
+ 0.433093819f, 0.901348847f,
+ 0.438616239f, 0.898674466f,
+ 0.444122145f, 0.895966250f,
+ 0.449611330f, 0.893224301f,
+ 0.455083587f, 0.890448723f,
+ 0.460538711f, 0.887639620f,
+ 0.465976496f, 0.884797098f,
+ 0.471396737f, 0.881921264f,
+ 0.476799230f, 0.879012226f,
+ 0.482183772f, 0.876070094f,
+ 0.487550160f, 0.873094978f,
+ 0.492898192f, 0.870086991f,
+ 0.498227667f, 0.867046246f,
+ 0.503538384f, 0.863972856f,
+ 0.508830143f, 0.860866939f,
+ 0.514102744f, 0.857728610f,
+ 0.519355990f, 0.854557988f,
+ 0.524589683f, 0.851355193f,
+ 0.529803625f, 0.848120345f,
+ 0.534997620f, 0.844853565f,
+ 0.540171473f, 0.841554977f,
+ 0.545324988f, 0.838224706f,
+ 0.550457973f, 0.834862875f,
+ 0.555570233f, 0.831469612f,
+ 0.560661576f, 0.828045045f,
+ 0.565731811f, 0.824589303f,
+ 0.570780746f, 0.821102515f,
+ 0.575808191f, 0.817584813f,
+ 0.580813958f, 0.814036330f,
+ 0.585797857f, 0.810457198f,
+ 0.590759702f, 0.806847554f,
+ 0.595699304f, 0.803207531f,
+ 0.600616479f, 0.799537269f,
+ 0.605511041f, 0.795836905f,
+ 0.610382806f, 0.792106577f,
+ 0.615231591f, 0.788346428f,
+ 0.620057212f, 0.784556597f,
+ 0.624859488f, 0.780737229f,
+ 0.629638239f, 0.776888466f,
+ 0.634393284f, 0.773010453f,
+ 0.639124445f, 0.769103338f,
+ 0.643831543f, 0.765167266f,
+ 0.648514401f, 0.761202385f,
+ 0.653172843f, 0.757208847f,
+ 0.657806693f, 0.753186799f,
+ 0.662415778f, 0.749136395f,
+ 0.666999922f, 0.745057785f,
+ 0.671558955f, 0.740951125f,
+ 0.676092704f, 0.736816569f,
+ 0.680600998f, 0.732654272f,
+ 0.685083668f, 0.728464390f,
+ 0.689540545f, 0.724247083f,
+ 0.693971461f, 0.720002508f,
+ 0.698376249f, 0.715730825f,
+ 0.702754744f, 0.711432196f,
+ 0.707106781f, 0.707106781f,
+ 0.711432196f, 0.702754744f,
+ 0.715730825f, 0.698376249f,
+ 0.720002508f, 0.693971461f,
+ 0.724247083f, 0.689540545f,
+ 0.728464390f, 0.685083668f,
+ 0.732654272f, 0.680600998f,
+ 0.736816569f, 0.676092704f,
+ 0.740951125f, 0.671558955f,
+ 0.745057785f, 0.666999922f,
+ 0.749136395f, 0.662415778f,
+ 0.753186799f, 0.657806693f,
+ 0.757208847f, 0.653172843f,
+ 0.761202385f, 0.648514401f,
+ 0.765167266f, 0.643831543f,
+ 0.769103338f, 0.639124445f,
+ 0.773010453f, 0.634393284f,
+ 0.776888466f, 0.629638239f,
+ 0.780737229f, 0.624859488f,
+ 0.784556597f, 0.620057212f,
+ 0.788346428f, 0.615231591f,
+ 0.792106577f, 0.610382806f,
+ 0.795836905f, 0.605511041f,
+ 0.799537269f, 0.600616479f,
+ 0.803207531f, 0.595699304f,
+ 0.806847554f, 0.590759702f,
+ 0.810457198f, 0.585797857f,
+ 0.814036330f, 0.580813958f,
+ 0.817584813f, 0.575808191f,
+ 0.821102515f, 0.570780746f,
+ 0.824589303f, 0.565731811f,
+ 0.828045045f, 0.560661576f,
+ 0.831469612f, 0.555570233f,
+ 0.834862875f, 0.550457973f,
+ 0.838224706f, 0.545324988f,
+ 0.841554977f, 0.540171473f,
+ 0.844853565f, 0.534997620f,
+ 0.848120345f, 0.529803625f,
+ 0.851355193f, 0.524589683f,
+ 0.854557988f, 0.519355990f,
+ 0.857728610f, 0.514102744f,
+ 0.860866939f, 0.508830143f,
+ 0.863972856f, 0.503538384f,
+ 0.867046246f, 0.498227667f,
+ 0.870086991f, 0.492898192f,
+ 0.873094978f, 0.487550160f,
+ 0.876070094f, 0.482183772f,
+ 0.879012226f, 0.476799230f,
+ 0.881921264f, 0.471396737f,
+ 0.884797098f, 0.465976496f,
+ 0.887639620f, 0.460538711f,
+ 0.890448723f, 0.455083587f,
+ 0.893224301f, 0.449611330f,
+ 0.895966250f, 0.444122145f,
+ 0.898674466f, 0.438616239f,
+ 0.901348847f, 0.433093819f,
+ 0.903989293f, 0.427555093f,
+ 0.906595705f, 0.422000271f,
+ 0.909167983f, 0.416429560f,
+ 0.911706032f, 0.410843171f,
+ 0.914209756f, 0.405241314f,
+ 0.916679060f, 0.399624200f,
+ 0.919113852f, 0.393992040f,
+ 0.921514039f, 0.388345047f,
+ 0.923879533f, 0.382683432f,
+ 0.926210242f, 0.377007410f,
+ 0.928506080f, 0.371317194f,
+ 0.930766961f, 0.365612998f,
+ 0.932992799f, 0.359895037f,
+ 0.935183510f, 0.354163525f,
+ 0.937339012f, 0.348418680f,
+ 0.939459224f, 0.342660717f,
+ 0.941544065f, 0.336889853f,
+ 0.943593458f, 0.331106306f,
+ 0.945607325f, 0.325310292f,
+ 0.947585591f, 0.319502031f,
+ 0.949528181f, 0.313681740f,
+ 0.951435021f, 0.307849640f,
+ 0.953306040f, 0.302005949f,
+ 0.955141168f, 0.296150888f,
+ 0.956940336f, 0.290284677f,
+ 0.958703475f, 0.284407537f,
+ 0.960430519f, 0.278519689f,
+ 0.962121404f, 0.272621355f,
+ 0.963776066f, 0.266712757f,
+ 0.965394442f, 0.260794118f,
+ 0.966976471f, 0.254865660f,
+ 0.968522094f, 0.248927606f,
+ 0.970031253f, 0.242980180f,
+ 0.971503891f, 0.237023606f,
+ 0.972939952f, 0.231058108f,
+ 0.974339383f, 0.225083911f,
+ 0.975702130f, 0.219101240f,
+ 0.977028143f, 0.213110320f,
+ 0.978317371f, 0.207111376f,
+ 0.979569766f, 0.201104635f,
+ 0.980785280f, 0.195090322f,
+ 0.981963869f, 0.189068664f,
+ 0.983105487f, 0.183039888f,
+ 0.984210092f, 0.177004220f,
+ 0.985277642f, 0.170961889f,
+ 0.986308097f, 0.164913120f,
+ 0.987301418f, 0.158858143f,
+ 0.988257568f, 0.152797185f,
+ 0.989176510f, 0.146730474f,
+ 0.990058210f, 0.140658239f,
+ 0.990902635f, 0.134580709f,
+ 0.991709754f, 0.128498111f,
+ 0.992479535f, 0.122410675f,
+ 0.993211949f, 0.116318631f,
+ 0.993906970f, 0.110222207f,
+ 0.994564571f, 0.104121634f,
+ 0.995184727f, 0.098017140f,
+ 0.995767414f, 0.091908956f,
+ 0.996312612f, 0.085797312f,
+ 0.996820299f, 0.079682438f,
+ 0.997290457f, 0.073564564f,
+ 0.997723067f, 0.067443920f,
+ 0.998118113f, 0.061320736f,
+ 0.998475581f, 0.055195244f,
+ 0.998795456f, 0.049067674f,
+ 0.999077728f, 0.042938257f,
+ 0.999322385f, 0.036807223f,
+ 0.999529418f, 0.030674803f,
+ 0.999698819f, 0.024541229f,
+ 0.999830582f, 0.018406730f,
+ 0.999924702f, 0.012271538f,
+ 0.999981175f, 0.006135885f,
+ 1.000000000f, 0.000000000f,
+ 0.999981175f, -0.006135885f,
+ 0.999924702f, -0.012271538f,
+ 0.999830582f, -0.018406730f,
+ 0.999698819f, -0.024541229f,
+ 0.999529418f, -0.030674803f,
+ 0.999322385f, -0.036807223f,
+ 0.999077728f, -0.042938257f,
+ 0.998795456f, -0.049067674f,
+ 0.998475581f, -0.055195244f,
+ 0.998118113f, -0.061320736f,
+ 0.997723067f, -0.067443920f,
+ 0.997290457f, -0.073564564f,
+ 0.996820299f, -0.079682438f,
+ 0.996312612f, -0.085797312f,
+ 0.995767414f, -0.091908956f,
+ 0.995184727f, -0.098017140f,
+ 0.994564571f, -0.104121634f,
+ 0.993906970f, -0.110222207f,
+ 0.993211949f, -0.116318631f,
+ 0.992479535f, -0.122410675f,
+ 0.991709754f, -0.128498111f,
+ 0.990902635f, -0.134580709f,
+ 0.990058210f, -0.140658239f,
+ 0.989176510f, -0.146730474f,
+ 0.988257568f, -0.152797185f,
+ 0.987301418f, -0.158858143f,
+ 0.986308097f, -0.164913120f,
+ 0.985277642f, -0.170961889f,
+ 0.984210092f, -0.177004220f,
+ 0.983105487f, -0.183039888f,
+ 0.981963869f, -0.189068664f,
+ 0.980785280f, -0.195090322f,
+ 0.979569766f, -0.201104635f,
+ 0.978317371f, -0.207111376f,
+ 0.977028143f, -0.213110320f,
+ 0.975702130f, -0.219101240f,
+ 0.974339383f, -0.225083911f,
+ 0.972939952f, -0.231058108f,
+ 0.971503891f, -0.237023606f,
+ 0.970031253f, -0.242980180f,
+ 0.968522094f, -0.248927606f,
+ 0.966976471f, -0.254865660f,
+ 0.965394442f, -0.260794118f,
+ 0.963776066f, -0.266712757f,
+ 0.962121404f, -0.272621355f,
+ 0.960430519f, -0.278519689f,
+ 0.958703475f, -0.284407537f,
+ 0.956940336f, -0.290284677f,
+ 0.955141168f, -0.296150888f,
+ 0.953306040f, -0.302005949f,
+ 0.951435021f, -0.307849640f,
+ 0.949528181f, -0.313681740f,
+ 0.947585591f, -0.319502031f,
+ 0.945607325f, -0.325310292f,
+ 0.943593458f, -0.331106306f,
+ 0.941544065f, -0.336889853f,
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+ 0.937339012f, -0.348418680f,
+ 0.935183510f, -0.354163525f,
+ 0.932992799f, -0.359895037f,
+ 0.930766961f, -0.365612998f,
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+ 0.926210242f, -0.377007410f,
+ 0.923879533f, -0.382683432f,
+ 0.921514039f, -0.388345047f,
+ 0.919113852f, -0.393992040f,
+ 0.916679060f, -0.399624200f,
+ 0.914209756f, -0.405241314f,
+ 0.911706032f, -0.410843171f,
+ 0.909167983f, -0.416429560f,
+ 0.906595705f, -0.422000271f,
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+ 0.901348847f, -0.433093819f,
+ 0.898674466f, -0.438616239f,
+ 0.895966250f, -0.444122145f,
+ 0.893224301f, -0.449611330f,
+ 0.890448723f, -0.455083587f,
+ 0.887639620f, -0.460538711f,
+ 0.884797098f, -0.465976496f,
+ 0.881921264f, -0.471396737f,
+ 0.879012226f, -0.476799230f,
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+ 0.870086991f, -0.492898192f,
+ 0.867046246f, -0.498227667f,
+ 0.863972856f, -0.503538384f,
+ 0.860866939f, -0.508830143f,
+ 0.857728610f, -0.514102744f,
+ 0.854557988f, -0.519355990f,
+ 0.851355193f, -0.524589683f,
+ 0.848120345f, -0.529803625f,
+ 0.844853565f, -0.534997620f,
+ 0.841554977f, -0.540171473f,
+ 0.838224706f, -0.545324988f,
+ 0.834862875f, -0.550457973f,
+ 0.831469612f, -0.555570233f,
+ 0.828045045f, -0.560661576f,
+ 0.824589303f, -0.565731811f,
+ 0.821102515f, -0.570780746f,
+ 0.817584813f, -0.575808191f,
+ 0.814036330f, -0.580813958f,
+ 0.810457198f, -0.585797857f,
+ 0.806847554f, -0.590759702f,
+ 0.803207531f, -0.595699304f,
+ 0.799537269f, -0.600616479f,
+ 0.795836905f, -0.605511041f,
+ 0.792106577f, -0.610382806f,
+ 0.788346428f, -0.615231591f,
+ 0.784556597f, -0.620057212f,
+ 0.780737229f, -0.624859488f,
+ 0.776888466f, -0.629638239f,
+ 0.773010453f, -0.634393284f,
+ 0.769103338f, -0.639124445f,
+ 0.765167266f, -0.643831543f,
+ 0.761202385f, -0.648514401f,
+ 0.757208847f, -0.653172843f,
+ 0.753186799f, -0.657806693f,
+ 0.749136395f, -0.662415778f,
+ 0.745057785f, -0.666999922f,
+ 0.740951125f, -0.671558955f,
+ 0.736816569f, -0.676092704f,
+ 0.732654272f, -0.680600998f,
+ 0.728464390f, -0.685083668f,
+ 0.724247083f, -0.689540545f,
+ 0.720002508f, -0.693971461f,
+ 0.715730825f, -0.698376249f,
+ 0.711432196f, -0.702754744f,
+ 0.707106781f, -0.707106781f,
+ 0.702754744f, -0.711432196f,
+ 0.698376249f, -0.715730825f,
+ 0.693971461f, -0.720002508f,
+ 0.689540545f, -0.724247083f,
+ 0.685083668f, -0.728464390f,
+ 0.680600998f, -0.732654272f,
+ 0.676092704f, -0.736816569f,
+ 0.671558955f, -0.740951125f,
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+ 0.634393284f, -0.773010453f,
+ 0.629638239f, -0.776888466f,
+ 0.624859488f, -0.780737229f,
+ 0.620057212f, -0.784556597f,
+ 0.615231591f, -0.788346428f,
+ 0.610382806f, -0.792106577f,
+ 0.605511041f, -0.795836905f,
+ 0.600616479f, -0.799537269f,
+ 0.595699304f, -0.803207531f,
+ 0.590759702f, -0.806847554f,
+ 0.585797857f, -0.810457198f,
+ 0.580813958f, -0.814036330f,
+ 0.575808191f, -0.817584813f,
+ 0.570780746f, -0.821102515f,
+ 0.565731811f, -0.824589303f,
+ 0.560661576f, -0.828045045f,
+ 0.555570233f, -0.831469612f,
+ 0.550457973f, -0.834862875f,
+ 0.545324988f, -0.838224706f,
+ 0.540171473f, -0.841554977f,
+ 0.534997620f, -0.844853565f,
+ 0.529803625f, -0.848120345f,
+ 0.524589683f, -0.851355193f,
+ 0.519355990f, -0.854557988f,
+ 0.514102744f, -0.857728610f,
+ 0.508830143f, -0.860866939f,
+ 0.503538384f, -0.863972856f,
+ 0.498227667f, -0.867046246f,
+ 0.492898192f, -0.870086991f,
+ 0.487550160f, -0.873094978f,
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+ 0.476799230f, -0.879012226f,
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+ 0.465976496f, -0.884797098f,
+ 0.460538711f, -0.887639620f,
+ 0.455083587f, -0.890448723f,
+ 0.449611330f, -0.893224301f,
+ 0.444122145f, -0.895966250f,
+ 0.438616239f, -0.898674466f,
+ 0.433093819f, -0.901348847f,
+ 0.427555093f, -0.903989293f,
+ 0.422000271f, -0.906595705f,
+ 0.416429560f, -0.909167983f,
+ 0.410843171f, -0.911706032f,
+ 0.405241314f, -0.914209756f,
+ 0.399624200f, -0.916679060f,
+ 0.393992040f, -0.919113852f,
+ 0.388345047f, -0.921514039f,
+ 0.382683432f, -0.923879533f,
+ 0.377007410f, -0.926210242f,
+ 0.371317194f, -0.928506080f,
+ 0.365612998f, -0.930766961f,
+ 0.359895037f, -0.932992799f,
+ 0.354163525f, -0.935183510f,
+ 0.348418680f, -0.937339012f,
+ 0.342660717f, -0.939459224f,
+ 0.336889853f, -0.941544065f,
+ 0.331106306f, -0.943593458f,
+ 0.325310292f, -0.945607325f,
+ 0.319502031f, -0.947585591f,
+ 0.313681740f, -0.949528181f,
+ 0.307849640f, -0.951435021f,
+ 0.302005949f, -0.953306040f,
+ 0.296150888f, -0.955141168f,
+ 0.290284677f, -0.956940336f,
+ 0.284407537f, -0.958703475f,
+ 0.278519689f, -0.960430519f,
+ 0.272621355f, -0.962121404f,
+ 0.266712757f, -0.963776066f,
+ 0.260794118f, -0.965394442f,
+ 0.254865660f, -0.966976471f,
+ 0.248927606f, -0.968522094f,
+ 0.242980180f, -0.970031253f,
+ 0.237023606f, -0.971503891f,
+ 0.231058108f, -0.972939952f,
+ 0.225083911f, -0.974339383f,
+ 0.219101240f, -0.975702130f,
+ 0.213110320f, -0.977028143f,
+ 0.207111376f, -0.978317371f,
+ 0.201104635f, -0.979569766f,
+ 0.195090322f, -0.980785280f,
+ 0.189068664f, -0.981963869f,
+ 0.183039888f, -0.983105487f,
+ 0.177004220f, -0.984210092f,
+ 0.170961889f, -0.985277642f,
+ 0.164913120f, -0.986308097f,
+ 0.158858143f, -0.987301418f,
+ 0.152797185f, -0.988257568f,
+ 0.146730474f, -0.989176510f,
+ 0.140658239f, -0.990058210f,
+ 0.134580709f, -0.990902635f,
+ 0.128498111f, -0.991709754f,
+ 0.122410675f, -0.992479535f,
+ 0.116318631f, -0.993211949f,
+ 0.110222207f, -0.993906970f,
+ 0.104121634f, -0.994564571f,
+ 0.098017140f, -0.995184727f,
+ 0.091908956f, -0.995767414f,
+ 0.085797312f, -0.996312612f,
+ 0.079682438f, -0.996820299f,
+ 0.073564564f, -0.997290457f,
+ 0.067443920f, -0.997723067f,
+ 0.061320736f, -0.998118113f,
+ 0.055195244f, -0.998475581f,
+ 0.049067674f, -0.998795456f,
+ 0.042938257f, -0.999077728f,
+ 0.036807223f, -0.999322385f,
+ 0.030674803f, -0.999529418f,
+ 0.024541229f, -0.999698819f,
+ 0.018406730f, -0.999830582f,
+ 0.012271538f, -0.999924702f,
+ 0.006135885f, -0.999981175f
+};
+
+const float32_t twiddleCoef_rfft_2048[2048] = {
+ 0.000000000f, 1.000000000f,
+ 0.003067957f, 0.999995294f,
+ 0.006135885f, 0.999981175f,
+ 0.009203755f, 0.999957645f,
+ 0.012271538f, 0.999924702f,
+ 0.015339206f, 0.999882347f,
+ 0.018406730f, 0.999830582f,
+ 0.021474080f, 0.999769405f,
+ 0.024541229f, 0.999698819f,
+ 0.027608146f, 0.999618822f,
+ 0.030674803f, 0.999529418f,
+ 0.033741172f, 0.999430605f,
+ 0.036807223f, 0.999322385f,
+ 0.039872928f, 0.999204759f,
+ 0.042938257f, 0.999077728f,
+ 0.046003182f, 0.998941293f,
+ 0.049067674f, 0.998795456f,
+ 0.052131705f, 0.998640218f,
+ 0.055195244f, 0.998475581f,
+ 0.058258265f, 0.998301545f,
+ 0.061320736f, 0.998118113f,
+ 0.064382631f, 0.997925286f,
+ 0.067443920f, 0.997723067f,
+ 0.070504573f, 0.997511456f,
+ 0.073564564f, 0.997290457f,
+ 0.076623861f, 0.997060070f,
+ 0.079682438f, 0.996820299f,
+ 0.082740265f, 0.996571146f,
+ 0.085797312f, 0.996312612f,
+ 0.088853553f, 0.996044701f,
+ 0.091908956f, 0.995767414f,
+ 0.094963495f, 0.995480755f,
+ 0.098017140f, 0.995184727f,
+ 0.101069863f, 0.994879331f,
+ 0.104121634f, 0.994564571f,
+ 0.107172425f, 0.994240449f,
+ 0.110222207f, 0.993906970f,
+ 0.113270952f, 0.993564136f,
+ 0.116318631f, 0.993211949f,
+ 0.119365215f, 0.992850414f,
+ 0.122410675f, 0.992479535f,
+ 0.125454983f, 0.992099313f,
+ 0.128498111f, 0.991709754f,
+ 0.131540029f, 0.991310860f,
+ 0.134580709f, 0.990902635f,
+ 0.137620122f, 0.990485084f,
+ 0.140658239f, 0.990058210f,
+ 0.143695033f, 0.989622017f,
+ 0.146730474f, 0.989176510f,
+ 0.149764535f, 0.988721692f,
+ 0.152797185f, 0.988257568f,
+ 0.155828398f, 0.987784142f,
+ 0.158858143f, 0.987301418f,
+ 0.161886394f, 0.986809402f,
+ 0.164913120f, 0.986308097f,
+ 0.167938295f, 0.985797509f,
+ 0.170961889f, 0.985277642f,
+ 0.173983873f, 0.984748502f,
+ 0.177004220f, 0.984210092f,
+ 0.180022901f, 0.983662419f,
+ 0.183039888f, 0.983105487f,
+ 0.186055152f, 0.982539302f,
+ 0.189068664f, 0.981963869f,
+ 0.192080397f, 0.981379193f,
+ 0.195090322f, 0.980785280f,
+ 0.198098411f, 0.980182136f,
+ 0.201104635f, 0.979569766f,
+ 0.204108966f, 0.978948175f,
+ 0.207111376f, 0.978317371f,
+ 0.210111837f, 0.977677358f,
+ 0.213110320f, 0.977028143f,
+ 0.216106797f, 0.976369731f,
+ 0.219101240f, 0.975702130f,
+ 0.222093621f, 0.975025345f,
+ 0.225083911f, 0.974339383f,
+ 0.228072083f, 0.973644250f,
+ 0.231058108f, 0.972939952f,
+ 0.234041959f, 0.972226497f,
+ 0.237023606f, 0.971503891f,
+ 0.240003022f, 0.970772141f,
+ 0.242980180f, 0.970031253f,
+ 0.245955050f, 0.969281235f,
+ 0.248927606f, 0.968522094f,
+ 0.251897818f, 0.967753837f,
+ 0.254865660f, 0.966976471f,
+ 0.257831102f, 0.966190003f,
+ 0.260794118f, 0.965394442f,
+ 0.263754679f, 0.964589793f,
+ 0.266712757f, 0.963776066f,
+ 0.269668326f, 0.962953267f,
+ 0.272621355f, 0.962121404f,
+ 0.275571819f, 0.961280486f,
+ 0.278519689f, 0.960430519f,
+ 0.281464938f, 0.959571513f,
+ 0.284407537f, 0.958703475f,
+ 0.287347460f, 0.957826413f,
+ 0.290284677f, 0.956940336f,
+ 0.293219163f, 0.956045251f,
+ 0.296150888f, 0.955141168f,
+ 0.299079826f, 0.954228095f,
+ 0.302005949f, 0.953306040f,
+ 0.304929230f, 0.952375013f,
+ 0.307849640f, 0.951435021f,
+ 0.310767153f, 0.950486074f,
+ 0.313681740f, 0.949528181f,
+ 0.316593376f, 0.948561350f,
+ 0.319502031f, 0.947585591f,
+ 0.322407679f, 0.946600913f,
+ 0.325310292f, 0.945607325f,
+ 0.328209844f, 0.944604837f,
+ 0.331106306f, 0.943593458f,
+ 0.333999651f, 0.942573198f,
+ 0.336889853f, 0.941544065f,
+ 0.339776884f, 0.940506071f,
+ 0.342660717f, 0.939459224f,
+ 0.345541325f, 0.938403534f,
+ 0.348418680f, 0.937339012f,
+ 0.351292756f, 0.936265667f,
+ 0.354163525f, 0.935183510f,
+ 0.357030961f, 0.934092550f,
+ 0.359895037f, 0.932992799f,
+ 0.362755724f, 0.931884266f,
+ 0.365612998f, 0.930766961f,
+ 0.368466830f, 0.929640896f,
+ 0.371317194f, 0.928506080f,
+ 0.374164063f, 0.927362526f,
+ 0.377007410f, 0.926210242f,
+ 0.379847209f, 0.925049241f,
+ 0.382683432f, 0.923879533f,
+ 0.385516054f, 0.922701128f,
+ 0.388345047f, 0.921514039f,
+ 0.391170384f, 0.920318277f,
+ 0.393992040f, 0.919113852f,
+ 0.396809987f, 0.917900776f,
+ 0.399624200f, 0.916679060f,
+ 0.402434651f, 0.915448716f,
+ 0.405241314f, 0.914209756f,
+ 0.408044163f, 0.912962190f,
+ 0.410843171f, 0.911706032f,
+ 0.413638312f, 0.910441292f,
+ 0.416429560f, 0.909167983f,
+ 0.419216888f, 0.907886116f,
+ 0.422000271f, 0.906595705f,
+ 0.424779681f, 0.905296759f,
+ 0.427555093f, 0.903989293f,
+ 0.430326481f, 0.902673318f,
+ 0.433093819f, 0.901348847f,
+ 0.435857080f, 0.900015892f,
+ 0.438616239f, 0.898674466f,
+ 0.441371269f, 0.897324581f,
+ 0.444122145f, 0.895966250f,
+ 0.446868840f, 0.894599486f,
+ 0.449611330f, 0.893224301f,
+ 0.452349587f, 0.891840709f,
+ 0.455083587f, 0.890448723f,
+ 0.457813304f, 0.889048356f,
+ 0.460538711f, 0.887639620f,
+ 0.463259784f, 0.886222530f,
+ 0.465976496f, 0.884797098f,
+ 0.468688822f, 0.883363339f,
+ 0.471396737f, 0.881921264f,
+ 0.474100215f, 0.880470889f,
+ 0.476799230f, 0.879012226f,
+ 0.479493758f, 0.877545290f,
+ 0.482183772f, 0.876070094f,
+ 0.484869248f, 0.874586652f,
+ 0.487550160f, 0.873094978f,
+ 0.490226483f, 0.871595087f,
+ 0.492898192f, 0.870086991f,
+ 0.495565262f, 0.868570706f,
+ 0.498227667f, 0.867046246f,
+ 0.500885383f, 0.865513624f,
+ 0.503538384f, 0.863972856f,
+ 0.506186645f, 0.862423956f,
+ 0.508830143f, 0.860866939f,
+ 0.511468850f, 0.859301818f,
+ 0.514102744f, 0.857728610f,
+ 0.516731799f, 0.856147328f,
+ 0.519355990f, 0.854557988f,
+ 0.521975293f, 0.852960605f,
+ 0.524589683f, 0.851355193f,
+ 0.527199135f, 0.849741768f,
+ 0.529803625f, 0.848120345f,
+ 0.532403128f, 0.846490939f,
+ 0.534997620f, 0.844853565f,
+ 0.537587076f, 0.843208240f,
+ 0.540171473f, 0.841554977f,
+ 0.542750785f, 0.839893794f,
+ 0.545324988f, 0.838224706f,
+ 0.547894059f, 0.836547727f,
+ 0.550457973f, 0.834862875f,
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+ 0.125454983f, -0.992099313f,
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+ 0.116318631f, -0.993211949f,
+ 0.113270952f, -0.993564136f,
+ 0.110222207f, -0.993906970f,
+ 0.107172425f, -0.994240449f,
+ 0.104121634f, -0.994564571f,
+ 0.101069863f, -0.994879331f,
+ 0.098017140f, -0.995184727f,
+ 0.094963495f, -0.995480755f,
+ 0.091908956f, -0.995767414f,
+ 0.088853553f, -0.996044701f,
+ 0.085797312f, -0.996312612f,
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+ 0.076623861f, -0.997060070f,
+ 0.073564564f, -0.997290457f,
+ 0.070504573f, -0.997511456f,
+ 0.067443920f, -0.997723067f,
+ 0.064382631f, -0.997925286f,
+ 0.061320736f, -0.998118113f,
+ 0.058258265f, -0.998301545f,
+ 0.055195244f, -0.998475581f,
+ 0.052131705f, -0.998640218f,
+ 0.049067674f, -0.998795456f,
+ 0.046003182f, -0.998941293f,
+ 0.042938257f, -0.999077728f,
+ 0.039872928f, -0.999204759f,
+ 0.036807223f, -0.999322385f,
+ 0.033741172f, -0.999430605f,
+ 0.030674803f, -0.999529418f,
+ 0.027608146f, -0.999618822f,
+ 0.024541229f, -0.999698819f,
+ 0.021474080f, -0.999769405f,
+ 0.018406730f, -0.999830582f,
+ 0.015339206f, -0.999882347f,
+ 0.012271538f, -0.999924702f,
+ 0.009203755f, -0.999957645f,
+ 0.006135885f, -0.999981175f,
+ 0.003067957f, -0.999995294f
+};
+
+const float32_t twiddleCoef_rfft_4096[4096] = {
+ 0.000000000f, 1.000000000f,
+ 0.001533980f, 0.999998823f,
+ 0.003067957f, 0.999995294f,
+ 0.004601926f, 0.999989411f,
+ 0.006135885f, 0.999981175f,
+ 0.007669829f, 0.999970586f,
+ 0.009203755f, 0.999957645f,
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+ 0.499557113f, -0.866280954f,
+ 0.498227667f, -0.867046246f,
+ 0.496897049f, -0.867809497f,
+ 0.495565262f, -0.868570706f,
+ 0.494232309f, -0.869329871f,
+ 0.492898192f, -0.870086991f,
+ 0.491562916f, -0.870842063f,
+ 0.490226483f, -0.871595087f,
+ 0.488888897f, -0.872346059f,
+ 0.487550160f, -0.873094978f,
+ 0.486210276f, -0.873841843f,
+ 0.484869248f, -0.874586652f,
+ 0.483527079f, -0.875329403f,
+ 0.482183772f, -0.876070094f,
+ 0.480839331f, -0.876808724f,
+ 0.479493758f, -0.877545290f,
+ 0.478147056f, -0.878279792f,
+ 0.476799230f, -0.879012226f,
+ 0.475450282f, -0.879742593f,
+ 0.474100215f, -0.880470889f,
+ 0.472749032f, -0.881197113f,
+ 0.471396737f, -0.881921264f,
+ 0.470043332f, -0.882643340f,
+ 0.468688822f, -0.883363339f,
+ 0.467333209f, -0.884081259f,
+ 0.465976496f, -0.884797098f,
+ 0.464618686f, -0.885510856f,
+ 0.463259784f, -0.886222530f,
+ 0.461899791f, -0.886932119f,
+ 0.460538711f, -0.887639620f,
+ 0.459176548f, -0.888345033f,
+ 0.457813304f, -0.889048356f,
+ 0.456448982f, -0.889749586f,
+ 0.455083587f, -0.890448723f,
+ 0.453717121f, -0.891145765f,
+ 0.452349587f, -0.891840709f,
+ 0.450980989f, -0.892533555f,
+ 0.449611330f, -0.893224301f,
+ 0.448240612f, -0.893912945f,
+ 0.446868840f, -0.894599486f,
+ 0.445496017f, -0.895283921f,
+ 0.444122145f, -0.895966250f,
+ 0.442747228f, -0.896646470f,
+ 0.441371269f, -0.897324581f,
+ 0.439994271f, -0.898000580f,
+ 0.438616239f, -0.898674466f,
+ 0.437237174f, -0.899346237f,
+ 0.435857080f, -0.900015892f,
+ 0.434475961f, -0.900683429f,
+ 0.433093819f, -0.901348847f,
+ 0.431710658f, -0.902012144f,
+ 0.430326481f, -0.902673318f,
+ 0.428941292f, -0.903332368f,
+ 0.427555093f, -0.903989293f,
+ 0.426167889f, -0.904644091f,
+ 0.424779681f, -0.905296759f,
+ 0.423390474f, -0.905947298f,
+ 0.422000271f, -0.906595705f,
+ 0.420609074f, -0.907241978f,
+ 0.419216888f, -0.907886116f,
+ 0.417823716f, -0.908528119f,
+ 0.416429560f, -0.909167983f,
+ 0.415034424f, -0.909805708f,
+ 0.413638312f, -0.910441292f,
+ 0.412241227f, -0.911074734f,
+ 0.410843171f, -0.911706032f,
+ 0.409444149f, -0.912335185f,
+ 0.408044163f, -0.912962190f,
+ 0.406643217f, -0.913587048f,
+ 0.405241314f, -0.914209756f,
+ 0.403838458f, -0.914830312f,
+ 0.402434651f, -0.915448716f,
+ 0.401029897f, -0.916064966f,
+ 0.399624200f, -0.916679060f,
+ 0.398217562f, -0.917290997f,
+ 0.396809987f, -0.917900776f,
+ 0.395401479f, -0.918508394f,
+ 0.393992040f, -0.919113852f,
+ 0.392581674f, -0.919717146f,
+ 0.391170384f, -0.920318277f,
+ 0.389758174f, -0.920917242f,
+ 0.388345047f, -0.921514039f,
+ 0.386931006f, -0.922108669f,
+ 0.385516054f, -0.922701128f,
+ 0.384100195f, -0.923291417f,
+ 0.382683432f, -0.923879533f,
+ 0.381265769f, -0.924465474f,
+ 0.379847209f, -0.925049241f,
+ 0.378427755f, -0.925630831f,
+ 0.377007410f, -0.926210242f,
+ 0.375586178f, -0.926787474f,
+ 0.374164063f, -0.927362526f,
+ 0.372741067f, -0.927935395f,
+ 0.371317194f, -0.928506080f,
+ 0.369892447f, -0.929074581f,
+ 0.368466830f, -0.929640896f,
+ 0.367040346f, -0.930205023f,
+ 0.365612998f, -0.930766961f,
+ 0.364184790f, -0.931326709f,
+ 0.362755724f, -0.931884266f,
+ 0.361325806f, -0.932439629f,
+ 0.359895037f, -0.932992799f,
+ 0.358463421f, -0.933543773f,
+ 0.357030961f, -0.934092550f,
+ 0.355597662f, -0.934639130f,
+ 0.354163525f, -0.935183510f,
+ 0.352728556f, -0.935725689f,
+ 0.351292756f, -0.936265667f,
+ 0.349856130f, -0.936803442f,
+ 0.348418680f, -0.937339012f,
+ 0.346980411f, -0.937872376f,
+ 0.345541325f, -0.938403534f,
+ 0.344101426f, -0.938932484f,
+ 0.342660717f, -0.939459224f,
+ 0.341219202f, -0.939983753f,
+ 0.339776884f, -0.940506071f,
+ 0.338333767f, -0.941026175f,
+ 0.336889853f, -0.941544065f,
+ 0.335445147f, -0.942059740f,
+ 0.333999651f, -0.942573198f,
+ 0.332553370f, -0.943084437f,
+ 0.331106306f, -0.943593458f,
+ 0.329658463f, -0.944100258f,
+ 0.328209844f, -0.944604837f,
+ 0.326760452f, -0.945107193f,
+ 0.325310292f, -0.945607325f,
+ 0.323859367f, -0.946105232f,
+ 0.322407679f, -0.946600913f,
+ 0.320955232f, -0.947094366f,
+ 0.319502031f, -0.947585591f,
+ 0.318048077f, -0.948074586f,
+ 0.316593376f, -0.948561350f,
+ 0.315137929f, -0.949045882f,
+ 0.313681740f, -0.949528181f,
+ 0.312224814f, -0.950008245f,
+ 0.310767153f, -0.950486074f,
+ 0.309308760f, -0.950961666f,
+ 0.307849640f, -0.951435021f,
+ 0.306389795f, -0.951906137f,
+ 0.304929230f, -0.952375013f,
+ 0.303467947f, -0.952841648f,
+ 0.302005949f, -0.953306040f,
+ 0.300543241f, -0.953768190f,
+ 0.299079826f, -0.954228095f,
+ 0.297615707f, -0.954685755f,
+ 0.296150888f, -0.955141168f,
+ 0.294685372f, -0.955594334f,
+ 0.293219163f, -0.956045251f,
+ 0.291752263f, -0.956493919f,
+ 0.290284677f, -0.956940336f,
+ 0.288816408f, -0.957384501f,
+ 0.287347460f, -0.957826413f,
+ 0.285877835f, -0.958266071f,
+ 0.284407537f, -0.958703475f,
+ 0.282936570f, -0.959138622f,
+ 0.281464938f, -0.959571513f,
+ 0.279992643f, -0.960002146f,
+ 0.278519689f, -0.960430519f,
+ 0.277046080f, -0.960856633f,
+ 0.275571819f, -0.961280486f,
+ 0.274096910f, -0.961702077f,
+ 0.272621355f, -0.962121404f,
+ 0.271145160f, -0.962538468f,
+ 0.269668326f, -0.962953267f,
+ 0.268190857f, -0.963365800f,
+ 0.266712757f, -0.963776066f,
+ 0.265234030f, -0.964184064f,
+ 0.263754679f, -0.964589793f,
+ 0.262274707f, -0.964993253f,
+ 0.260794118f, -0.965394442f,
+ 0.259312915f, -0.965793359f,
+ 0.257831102f, -0.966190003f,
+ 0.256348682f, -0.966584374f,
+ 0.254865660f, -0.966976471f,
+ 0.253382037f, -0.967366292f,
+ 0.251897818f, -0.967753837f,
+ 0.250413007f, -0.968139105f,
+ 0.248927606f, -0.968522094f,
+ 0.247441619f, -0.968902805f,
+ 0.245955050f, -0.969281235f,
+ 0.244467903f, -0.969657385f,
+ 0.242980180f, -0.970031253f,
+ 0.241491885f, -0.970402839f,
+ 0.240003022f, -0.970772141f,
+ 0.238513595f, -0.971139158f,
+ 0.237023606f, -0.971503891f,
+ 0.235533059f, -0.971866337f,
+ 0.234041959f, -0.972226497f,
+ 0.232550307f, -0.972584369f,
+ 0.231058108f, -0.972939952f,
+ 0.229565366f, -0.973293246f,
+ 0.228072083f, -0.973644250f,
+ 0.226578264f, -0.973992962f,
+ 0.225083911f, -0.974339383f,
+ 0.223589029f, -0.974683511f,
+ 0.222093621f, -0.975025345f,
+ 0.220597690f, -0.975364885f,
+ 0.219101240f, -0.975702130f,
+ 0.217604275f, -0.976037079f,
+ 0.216106797f, -0.976369731f,
+ 0.214608811f, -0.976700086f,
+ 0.213110320f, -0.977028143f,
+ 0.211611327f, -0.977353900f,
+ 0.210111837f, -0.977677358f,
+ 0.208611852f, -0.977998515f,
+ 0.207111376f, -0.978317371f,
+ 0.205610413f, -0.978633924f,
+ 0.204108966f, -0.978948175f,
+ 0.202607039f, -0.979260123f,
+ 0.201104635f, -0.979569766f,
+ 0.199601758f, -0.979877104f,
+ 0.198098411f, -0.980182136f,
+ 0.196594598f, -0.980484862f,
+ 0.195090322f, -0.980785280f,
+ 0.193585587f, -0.981083391f,
+ 0.192080397f, -0.981379193f,
+ 0.190574755f, -0.981672686f,
+ 0.189068664f, -0.981963869f,
+ 0.187562129f, -0.982252741f,
+ 0.186055152f, -0.982539302f,
+ 0.184547737f, -0.982823551f,
+ 0.183039888f, -0.983105487f,
+ 0.181531608f, -0.983385110f,
+ 0.180022901f, -0.983662419f,
+ 0.178513771f, -0.983937413f,
+ 0.177004220f, -0.984210092f,
+ 0.175494253f, -0.984480455f,
+ 0.173983873f, -0.984748502f,
+ 0.172473084f, -0.985014231f,
+ 0.170961889f, -0.985277642f,
+ 0.169450291f, -0.985538735f,
+ 0.167938295f, -0.985797509f,
+ 0.166425904f, -0.986053963f,
+ 0.164913120f, -0.986308097f,
+ 0.163399949f, -0.986559910f,
+ 0.161886394f, -0.986809402f,
+ 0.160372457f, -0.987056571f,
+ 0.158858143f, -0.987301418f,
+ 0.157343456f, -0.987543942f,
+ 0.155828398f, -0.987784142f,
+ 0.154312973f, -0.988022017f,
+ 0.152797185f, -0.988257568f,
+ 0.151281038f, -0.988490793f,
+ 0.149764535f, -0.988721692f,
+ 0.148247679f, -0.988950265f,
+ 0.146730474f, -0.989176510f,
+ 0.145212925f, -0.989400428f,
+ 0.143695033f, -0.989622017f,
+ 0.142176804f, -0.989841278f,
+ 0.140658239f, -0.990058210f,
+ 0.139139344f, -0.990272812f,
+ 0.137620122f, -0.990485084f,
+ 0.136100575f, -0.990695025f,
+ 0.134580709f, -0.990902635f,
+ 0.133060525f, -0.991107914f,
+ 0.131540029f, -0.991310860f,
+ 0.130019223f, -0.991511473f,
+ 0.128498111f, -0.991709754f,
+ 0.126976696f, -0.991905700f,
+ 0.125454983f, -0.992099313f,
+ 0.123932975f, -0.992290591f,
+ 0.122410675f, -0.992479535f,
+ 0.120888087f, -0.992666142f,
+ 0.119365215f, -0.992850414f,
+ 0.117842062f, -0.993032350f,
+ 0.116318631f, -0.993211949f,
+ 0.114794927f, -0.993389211f,
+ 0.113270952f, -0.993564136f,
+ 0.111746711f, -0.993736722f,
+ 0.110222207f, -0.993906970f,
+ 0.108697444f, -0.994074879f,
+ 0.107172425f, -0.994240449f,
+ 0.105647154f, -0.994403680f,
+ 0.104121634f, -0.994564571f,
+ 0.102595869f, -0.994723121f,
+ 0.101069863f, -0.994879331f,
+ 0.099543619f, -0.995033199f,
+ 0.098017140f, -0.995184727f,
+ 0.096490431f, -0.995333912f,
+ 0.094963495f, -0.995480755f,
+ 0.093436336f, -0.995625256f,
+ 0.091908956f, -0.995767414f,
+ 0.090381361f, -0.995907229f,
+ 0.088853553f, -0.996044701f,
+ 0.087325535f, -0.996179829f,
+ 0.085797312f, -0.996312612f,
+ 0.084268888f, -0.996443051f,
+ 0.082740265f, -0.996571146f,
+ 0.081211447f, -0.996696895f,
+ 0.079682438f, -0.996820299f,
+ 0.078153242f, -0.996941358f,
+ 0.076623861f, -0.997060070f,
+ 0.075094301f, -0.997176437f,
+ 0.073564564f, -0.997290457f,
+ 0.072034653f, -0.997402130f,
+ 0.070504573f, -0.997511456f,
+ 0.068974328f, -0.997618435f,
+ 0.067443920f, -0.997723067f,
+ 0.065913353f, -0.997825350f,
+ 0.064382631f, -0.997925286f,
+ 0.062851758f, -0.998022874f,
+ 0.061320736f, -0.998118113f,
+ 0.059789571f, -0.998211003f,
+ 0.058258265f, -0.998301545f,
+ 0.056726821f, -0.998389737f,
+ 0.055195244f, -0.998475581f,
+ 0.053663538f, -0.998559074f,
+ 0.052131705f, -0.998640218f,
+ 0.050599749f, -0.998719012f,
+ 0.049067674f, -0.998795456f,
+ 0.047535484f, -0.998869550f,
+ 0.046003182f, -0.998941293f,
+ 0.044470772f, -0.999010686f,
+ 0.042938257f, -0.999077728f,
+ 0.041405641f, -0.999142419f,
+ 0.039872928f, -0.999204759f,
+ 0.038340120f, -0.999264747f,
+ 0.036807223f, -0.999322385f,
+ 0.035274239f, -0.999377670f,
+ 0.033741172f, -0.999430605f,
+ 0.032208025f, -0.999481187f,
+ 0.030674803f, -0.999529418f,
+ 0.029141509f, -0.999575296f,
+ 0.027608146f, -0.999618822f,
+ 0.026074718f, -0.999659997f,
+ 0.024541229f, -0.999698819f,
+ 0.023007681f, -0.999735288f,
+ 0.021474080f, -0.999769405f,
+ 0.019940429f, -0.999801170f,
+ 0.018406730f, -0.999830582f,
+ 0.016872988f, -0.999857641f,
+ 0.015339206f, -0.999882347f,
+ 0.013805389f, -0.999904701f,
+ 0.012271538f, -0.999924702f,
+ 0.010737659f, -0.999942350f,
+ 0.009203755f, -0.999957645f,
+ 0.007669829f, -0.999970586f,
+ 0.006135885f, -0.999981175f,
+ 0.004601926f, -0.999989411f,
+ 0.003067957f, -0.999995294f,
+ 0.001533980f, -0.999998823f
+};
+
+
+/**
+ * \par
+ * Example code for the generation of the floating-point sine table:
+ *
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n]=sin(2*pi*n/tableSize);
+ * }
+ * \par
+ * where pi value is 3.14159265358979
+ */
+
+const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = {
+ 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f,
+ 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f,
+ 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f,
+ 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f,
+ 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f,
+ 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f,
+ 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f,
+ 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f,
+ 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f,
+ 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f,
+ 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f,
+ 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f,
+ 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f,
+ 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f,
+ 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f,
+ 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f,
+ 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f,
+ 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f,
+ 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f,
+ 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f,
+ 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f,
+ 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f,
+ 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f,
+ 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f,
+ 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f,
+ 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f,
+ 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f,
+ 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f,
+ 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f,
+ 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f,
+ 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f,
+ 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f,
+ 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f,
+ 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f,
+ 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f,
+ 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f,
+ 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f,
+ 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f,
+ 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f,
+ 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f,
+ 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f,
+ 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f,
+ 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f,
+ -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f,
+ -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f,
+ -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f,
+ -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f,
+ -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f,
+ -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f,
+ -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f,
+ -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f,
+ -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f,
+ -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f,
+ -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f,
+ -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f,
+ -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f,
+ -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f,
+ -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f,
+ -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f,
+ -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f,
+ -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f,
+ -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f,
+ -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f,
+ -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f,
+ -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f,
+ -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f,
+ -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f,
+ -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f,
+ -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f,
+ -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f,
+ -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f,
+ -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f,
+ -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f,
+ -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f,
+ -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f,
+ -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f,
+ -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f,
+ -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f,
+ -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f,
+ -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f,
+ -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f,
+ -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f,
+ -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f,
+ -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f,
+ -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f,
+ -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f,
+ -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f,
+ -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f,
+ -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f,
+ -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f,
+ -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f,
+ -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f,
+ -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f,
+ -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f
+};
+
+/**
+ * \par
+ * Table values are in Q31 (1.31 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ *
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n]= sin(2*pi*n/tableSize);
+ * }
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q31 (Fixed point):
+ * (sinTable[i] * pow(2, 31))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+ */
+const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = {
+ 0x00000000, 0x01921D20, 0x03242ABF, 0x04B6195D, 0x0647D97C, 0x07D95B9E,
+ 0x096A9049, 0x0AFB6805, 0x0C8BD35E, 0x0E1BC2E4, 0x0FAB272B, 0x1139F0CF,
+ 0x12C8106F, 0x145576B1, 0x15E21445, 0x176DD9DE, 0x18F8B83C, 0x1A82A026,
+ 0x1C0B826A, 0x1D934FE5, 0x1F19F97B, 0x209F701C, 0x2223A4C5, 0x23A6887F,
+ 0x25280C5E, 0x26A82186, 0x2826B928, 0x29A3C485, 0x2B1F34EB, 0x2C98FBBA,
+ 0x2E110A62, 0x2F875262, 0x30FBC54D, 0x326E54C7, 0x33DEF287, 0x354D9057,
+ 0x36BA2014, 0x382493B0, 0x398CDD32, 0x3AF2EEB7, 0x3C56BA70, 0x3DB832A6,
+ 0x3F1749B8, 0x4073F21D, 0x41CE1E65, 0x4325C135, 0x447ACD50, 0x45CD358F,
+ 0x471CECE7, 0x4869E665, 0x49B41533, 0x4AFB6C98, 0x4C3FDFF4, 0x4D8162C4,
+ 0x4EBFE8A5, 0x4FFB654D, 0x5133CC94, 0x5269126E, 0x539B2AF0, 0x54CA0A4B,
+ 0x55F5A4D2, 0x571DEEFA, 0x5842DD54, 0x59646498, 0x5A82799A, 0x5B9D1154,
+ 0x5CB420E0, 0x5DC79D7C, 0x5ED77C8A, 0x5FE3B38D, 0x60EC3830, 0x61F1003F,
+ 0x62F201AC, 0x63EF3290, 0x64E88926, 0x65DDFBD3, 0x66CF8120, 0x67BD0FBD,
+ 0x68A69E81, 0x698C246C, 0x6A6D98A4, 0x6B4AF279, 0x6C242960, 0x6CF934FC,
+ 0x6DCA0D14, 0x6E96A99D, 0x6F5F02B2, 0x7023109A, 0x70E2CBC6, 0x719E2CD2,
+ 0x72552C85, 0x7307C3D0, 0x73B5EBD1, 0x745F9DD1, 0x7504D345, 0x75A585CF,
+ 0x7641AF3D, 0x76D94989, 0x776C4EDB, 0x77FAB989, 0x78848414, 0x7909A92D,
+ 0x798A23B1, 0x7A05EEAD, 0x7A7D055B, 0x7AEF6323, 0x7B5D039E, 0x7BC5E290,
+ 0x7C29FBEE, 0x7C894BDE, 0x7CE3CEB2, 0x7D3980EC, 0x7D8A5F40, 0x7DD6668F,
+ 0x7E1D93EA, 0x7E5FE493, 0x7E9D55FC, 0x7ED5E5C6, 0x7F0991C4, 0x7F3857F6,
+ 0x7F62368F, 0x7F872BF3, 0x7FA736B4, 0x7FC25596, 0x7FD8878E, 0x7FE9CBC0,
+ 0x7FF62182, 0x7FFD885A, 0x7FFFFFFF, 0x7FFD885A, 0x7FF62182, 0x7FE9CBC0,
+ 0x7FD8878E, 0x7FC25596, 0x7FA736B4, 0x7F872BF3, 0x7F62368F, 0x7F3857F6,
+ 0x7F0991C4, 0x7ED5E5C6, 0x7E9D55FC, 0x7E5FE493, 0x7E1D93EA, 0x7DD6668F,
+ 0x7D8A5F40, 0x7D3980EC, 0x7CE3CEB2, 0x7C894BDE, 0x7C29FBEE, 0x7BC5E290,
+ 0x7B5D039E, 0x7AEF6323, 0x7A7D055B, 0x7A05EEAD, 0x798A23B1, 0x7909A92D,
+ 0x78848414, 0x77FAB989, 0x776C4EDB, 0x76D94989, 0x7641AF3D, 0x75A585CF,
+ 0x7504D345, 0x745F9DD1, 0x73B5EBD1, 0x7307C3D0, 0x72552C85, 0x719E2CD2,
+ 0x70E2CBC6, 0x7023109A, 0x6F5F02B2, 0x6E96A99D, 0x6DCA0D14, 0x6CF934FC,
+ 0x6C242960, 0x6B4AF279, 0x6A6D98A4, 0x698C246C, 0x68A69E81, 0x67BD0FBD,
+ 0x66CF8120, 0x65DDFBD3, 0x64E88926, 0x63EF3290, 0x62F201AC, 0x61F1003F,
+ 0x60EC3830, 0x5FE3B38D, 0x5ED77C8A, 0x5DC79D7C, 0x5CB420E0, 0x5B9D1154,
+ 0x5A82799A, 0x59646498, 0x5842DD54, 0x571DEEFA, 0x55F5A4D2, 0x54CA0A4B,
+ 0x539B2AF0, 0x5269126E, 0x5133CC94, 0x4FFB654D, 0x4EBFE8A5, 0x4D8162C4,
+ 0x4C3FDFF4, 0x4AFB6C98, 0x49B41533, 0x4869E665, 0x471CECE7, 0x45CD358F,
+ 0x447ACD50, 0x4325C135, 0x41CE1E65, 0x4073F21D, 0x3F1749B8, 0x3DB832A6,
+ 0x3C56BA70, 0x3AF2EEB7, 0x398CDD32, 0x382493B0, 0x36BA2014, 0x354D9057,
+ 0x33DEF287, 0x326E54C7, 0x30FBC54D, 0x2F875262, 0x2E110A62, 0x2C98FBBA,
+ 0x2B1F34EB, 0x29A3C485, 0x2826B928, 0x26A82186, 0x25280C5E, 0x23A6887F,
+ 0x2223A4C5, 0x209F701C, 0x1F19F97B, 0x1D934FE5, 0x1C0B826A, 0x1A82A026,
+ 0x18F8B83C, 0x176DD9DE, 0x15E21445, 0x145576B1, 0x12C8106F, 0x1139F0CF,
+ 0x0FAB272B, 0x0E1BC2E4, 0x0C8BD35E, 0x0AFB6805, 0x096A9049, 0x07D95B9E,
+ 0x0647D97C, 0x04B6195D, 0x03242ABF, 0x01921D20, 0x00000000, 0xFE6DE2E0,
+ 0xFCDBD541, 0xFB49E6A3, 0xF9B82684, 0xF826A462, 0xF6956FB7, 0xF50497FB,
+ 0xF3742CA2, 0xF1E43D1C, 0xF054D8D5, 0xEEC60F31, 0xED37EF91, 0xEBAA894F,
+ 0xEA1DEBBB, 0xE8922622, 0xE70747C4, 0xE57D5FDA, 0xE3F47D96, 0xE26CB01B,
+ 0xE0E60685, 0xDF608FE4, 0xDDDC5B3B, 0xDC597781, 0xDAD7F3A2, 0xD957DE7A,
+ 0xD7D946D8, 0xD65C3B7B, 0xD4E0CB15, 0xD3670446, 0xD1EEF59E, 0xD078AD9E,
+ 0xCF043AB3, 0xCD91AB39, 0xCC210D79, 0xCAB26FA9, 0xC945DFEC, 0xC7DB6C50,
+ 0xC67322CE, 0xC50D1149, 0xC3A94590, 0xC247CD5A, 0xC0E8B648, 0xBF8C0DE3,
+ 0xBE31E19B, 0xBCDA3ECB, 0xBB8532B0, 0xBA32CA71, 0xB8E31319, 0xB796199B,
+ 0xB64BEACD, 0xB5049368, 0xB3C0200C, 0xB27E9D3C, 0xB140175B, 0xB0049AB3,
+ 0xAECC336C, 0xAD96ED92, 0xAC64D510, 0xAB35F5B5, 0xAA0A5B2E, 0xA8E21106,
+ 0xA7BD22AC, 0xA69B9B68, 0xA57D8666, 0xA462EEAC, 0xA34BDF20, 0xA2386284,
+ 0xA1288376, 0xA01C4C73, 0x9F13C7D0, 0x9E0EFFC1, 0x9D0DFE54, 0x9C10CD70,
+ 0x9B1776DA, 0x9A22042D, 0x99307EE0, 0x9842F043, 0x9759617F, 0x9673DB94,
+ 0x9592675C, 0x94B50D87, 0x93DBD6A0, 0x9306CB04, 0x9235F2EC, 0x91695663,
+ 0x90A0FD4E, 0x8FDCEF66, 0x8F1D343A, 0x8E61D32E, 0x8DAAD37B, 0x8CF83C30,
+ 0x8C4A142F, 0x8BA0622F, 0x8AFB2CBB, 0x8A5A7A31, 0x89BE50C3, 0x8926B677,
+ 0x8893B125, 0x88054677, 0x877B7BEC, 0x86F656D3, 0x8675DC4F, 0x85FA1153,
+ 0x8582FAA5, 0x85109CDD, 0x84A2FC62, 0x843A1D70, 0x83D60412, 0x8376B422,
+ 0x831C314E, 0x82C67F14, 0x8275A0C0, 0x82299971, 0x81E26C16, 0x81A01B6D,
+ 0x8162AA04, 0x812A1A3A, 0x80F66E3C, 0x80C7A80A, 0x809DC971, 0x8078D40D,
+ 0x8058C94C, 0x803DAA6A, 0x80277872, 0x80163440, 0x8009DE7E, 0x800277A6,
+ 0x80000000, 0x800277A6, 0x8009DE7E, 0x80163440, 0x80277872, 0x803DAA6A,
+ 0x8058C94C, 0x8078D40D, 0x809DC971, 0x80C7A80A, 0x80F66E3C, 0x812A1A3A,
+ 0x8162AA04, 0x81A01B6D, 0x81E26C16, 0x82299971, 0x8275A0C0, 0x82C67F14,
+ 0x831C314E, 0x8376B422, 0x83D60412, 0x843A1D70, 0x84A2FC62, 0x85109CDD,
+ 0x8582FAA5, 0x85FA1153, 0x8675DC4F, 0x86F656D3, 0x877B7BEC, 0x88054677,
+ 0x8893B125, 0x8926B677, 0x89BE50C3, 0x8A5A7A31, 0x8AFB2CBB, 0x8BA0622F,
+ 0x8C4A142F, 0x8CF83C30, 0x8DAAD37B, 0x8E61D32E, 0x8F1D343A, 0x8FDCEF66,
+ 0x90A0FD4E, 0x91695663, 0x9235F2EC, 0x9306CB04, 0x93DBD6A0, 0x94B50D87,
+ 0x9592675C, 0x9673DB94, 0x9759617F, 0x9842F043, 0x99307EE0, 0x9A22042D,
+ 0x9B1776DA, 0x9C10CD70, 0x9D0DFE54, 0x9E0EFFC1, 0x9F13C7D0, 0xA01C4C73,
+ 0xA1288376, 0xA2386284, 0xA34BDF20, 0xA462EEAC, 0xA57D8666, 0xA69B9B68,
+ 0xA7BD22AC, 0xA8E21106, 0xAA0A5B2E, 0xAB35F5B5, 0xAC64D510, 0xAD96ED92,
+ 0xAECC336C, 0xB0049AB3, 0xB140175B, 0xB27E9D3C, 0xB3C0200C, 0xB5049368,
+ 0xB64BEACD, 0xB796199B, 0xB8E31319, 0xBA32CA71, 0xBB8532B0, 0xBCDA3ECB,
+ 0xBE31E19B, 0xBF8C0DE3, 0xC0E8B648, 0xC247CD5A, 0xC3A94590, 0xC50D1149,
+ 0xC67322CE, 0xC7DB6C50, 0xC945DFEC, 0xCAB26FA9, 0xCC210D79, 0xCD91AB39,
+ 0xCF043AB3, 0xD078AD9E, 0xD1EEF59E, 0xD3670446, 0xD4E0CB15, 0xD65C3B7B,
+ 0xD7D946D8, 0xD957DE7A, 0xDAD7F3A2, 0xDC597781, 0xDDDC5B3B, 0xDF608FE4,
+ 0xE0E60685, 0xE26CB01B, 0xE3F47D96, 0xE57D5FDA, 0xE70747C4, 0xE8922622,
+ 0xEA1DEBBB, 0xEBAA894F, 0xED37EF91, 0xEEC60F31, 0xF054D8D5, 0xF1E43D1C,
+ 0xF3742CA2, 0xF50497FB, 0xF6956FB7, 0xF826A462, 0xF9B82684, 0xFB49E6A3,
+ 0xFCDBD541, 0xFE6DE2E0, 0x00000000
+};
+
+/**
+ * \par
+ * Table values are in Q15 (1.15 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ *
+ * tableSize = 512;
+ * for(n = 0; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n]= sin(2*pi*n/tableSize);
+ * }
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q15 (Fixed point):
+ * (sinTable[i] * pow(2, 15))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+ */
+const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = {
+ 0x0000, 0x0192, 0x0324, 0x04B6, 0x0648, 0x07D9, 0x096B, 0x0AFB, 0x0C8C, 0x0E1C, 0x0FAB, 0x113A, 0x12C8,
+ 0x1455, 0x15E2, 0x176E, 0x18F9, 0x1A83, 0x1C0C, 0x1D93, 0x1F1A, 0x209F, 0x2224, 0x23A7, 0x2528, 0x26A8,
+ 0x2827, 0x29A4, 0x2B1F, 0x2C99, 0x2E11, 0x2F87, 0x30FC, 0x326E, 0x33DF, 0x354E, 0x36BA, 0x3825, 0x398D,
+ 0x3AF3, 0x3C57, 0x3DB8, 0x3F17, 0x4074, 0x41CE, 0x4326, 0x447B, 0x45CD, 0x471D, 0x486A, 0x49B4, 0x4AFB,
+ 0x4C40, 0x4D81, 0x4EC0, 0x4FFB, 0x5134, 0x5269, 0x539B, 0x54CA, 0x55F6, 0x571E, 0x5843, 0x5964, 0x5A82,
+ 0x5B9D, 0x5CB4, 0x5DC8, 0x5ED7, 0x5FE4, 0x60EC, 0x61F1, 0x62F2, 0x63EF, 0x64E9, 0x65DE, 0x66D0, 0x67BD,
+ 0x68A7, 0x698C, 0x6A6E, 0x6B4B, 0x6C24, 0x6CF9, 0x6DCA, 0x6E97, 0x6F5F, 0x7023, 0x70E3, 0x719E, 0x7255,
+ 0x7308, 0x73B6, 0x7460, 0x7505, 0x75A6, 0x7642, 0x76D9, 0x776C, 0x77FB, 0x7885, 0x790A, 0x798A, 0x7A06,
+ 0x7A7D, 0x7AEF, 0x7B5D, 0x7BC6, 0x7C2A, 0x7C89, 0x7CE4, 0x7D3A, 0x7D8A, 0x7DD6, 0x7E1E, 0x7E60, 0x7E9D,
+ 0x7ED6, 0x7F0A, 0x7F38, 0x7F62, 0x7F87, 0x7FA7, 0x7FC2, 0x7FD9, 0x7FEA, 0x7FF6, 0x7FFE, 0x7FFF, 0x7FFE,
+ 0x7FF6, 0x7FEA, 0x7FD9, 0x7FC2, 0x7FA7, 0x7F87, 0x7F62, 0x7F38, 0x7F0A, 0x7ED6, 0x7E9D, 0x7E60, 0x7E1E,
+ 0x7DD6, 0x7D8A, 0x7D3A, 0x7CE4, 0x7C89, 0x7C2A, 0x7BC6, 0x7B5D, 0x7AEF, 0x7A7D, 0x7A06, 0x798A, 0x790A,
+ 0x7885, 0x77FB, 0x776C, 0x76D9, 0x7642, 0x75A6, 0x7505, 0x7460, 0x73B6, 0x7308, 0x7255, 0x719E, 0x70E3,
+ 0x7023, 0x6F5F, 0x6E97, 0x6DCA, 0x6CF9, 0x6C24, 0x6B4B, 0x6A6E, 0x698C, 0x68A7, 0x67BD, 0x66D0, 0x65DE,
+ 0x64E9, 0x63EF, 0x62F2, 0x61F1, 0x60EC, 0x5FE4, 0x5ED7, 0x5DC8, 0x5CB4, 0x5B9D, 0x5A82, 0x5964, 0x5843,
+ 0x571E, 0x55F6, 0x54CA, 0x539B, 0x5269, 0x5134, 0x4FFB, 0x4EC0, 0x4D81, 0x4C40, 0x4AFB, 0x49B4, 0x486A,
+ 0x471D, 0x45CD, 0x447B, 0x4326, 0x41CE, 0x4074, 0x3F17, 0x3DB8, 0x3C57, 0x3AF3, 0x398D, 0x3825, 0x36BA,
+ 0x354E, 0x33DF, 0x326E, 0x30FC, 0x2F87, 0x2E11, 0x2C99, 0x2B1F, 0x29A4, 0x2827, 0x26A8, 0x2528, 0x23A7,
+ 0x2224, 0x209F, 0x1F1A, 0x1D93, 0x1C0C, 0x1A83, 0x18F9, 0x176E, 0x15E2, 0x1455, 0x12C8, 0x113A, 0x0FAB,
+ 0x0E1C, 0x0C8C, 0x0AFB, 0x096B, 0x07D9, 0x0648, 0x04B6, 0x0324, 0x0192, 0x0000, 0xFE6E, 0xFCDC, 0xFB4A,
+ 0xF9B8, 0xF827, 0xF695, 0xF505, 0xF374, 0xF1E4, 0xF055, 0xEEC6, 0xED38, 0xEBAB, 0xEA1E, 0xE892, 0xE707,
+ 0xE57D, 0xE3F4, 0xE26D, 0xE0E6, 0xDF61, 0xDDDC, 0xDC59, 0xDAD8, 0xD958, 0xD7D9, 0xD65C, 0xD4E1, 0xD367,
+ 0xD1EF, 0xD079, 0xCF04, 0xCD92, 0xCC21, 0xCAB2, 0xC946, 0xC7DB, 0xC673, 0xC50D, 0xC3A9, 0xC248, 0xC0E9,
+ 0xBF8C, 0xBE32, 0xBCDA, 0xBB85, 0xBA33, 0xB8E3, 0xB796, 0xB64C, 0xB505, 0xB3C0, 0xB27F, 0xB140, 0xB005,
+ 0xAECC, 0xAD97, 0xAC65, 0xAB36, 0xAA0A, 0xA8E2, 0xA7BD, 0xA69C, 0xA57E, 0xA463, 0xA34C, 0xA238, 0xA129,
+ 0xA01C, 0x9F14, 0x9E0F, 0x9D0E, 0x9C11, 0x9B17, 0x9A22, 0x9930, 0x9843, 0x9759, 0x9674, 0x9592, 0x94B5,
+ 0x93DC, 0x9307, 0x9236, 0x9169, 0x90A1, 0x8FDD, 0x8F1D, 0x8E62, 0x8DAB, 0x8CF8, 0x8C4A, 0x8BA0, 0x8AFB,
+ 0x8A5A, 0x89BE, 0x8927, 0x8894, 0x8805, 0x877B, 0x86F6, 0x8676, 0x85FA, 0x8583, 0x8511, 0x84A3, 0x843A,
+ 0x83D6, 0x8377, 0x831C, 0x82C6, 0x8276, 0x822A, 0x81E2, 0x81A0, 0x8163, 0x812A, 0x80F6, 0x80C8, 0x809E,
+ 0x8079, 0x8059, 0x803E, 0x8027, 0x8016, 0x800A, 0x8002, 0x8000, 0x8002, 0x800A, 0x8016, 0x8027, 0x803E,
+ 0x8059, 0x8079, 0x809E, 0x80C8, 0x80F6, 0x812A, 0x8163, 0x81A0, 0x81E2, 0x822A, 0x8276, 0x82C6, 0x831C,
+ 0x8377, 0x83D6, 0x843A, 0x84A3, 0x8511, 0x8583, 0x85FA, 0x8676, 0x86F6, 0x877B, 0x8805, 0x8894, 0x8927,
+ 0x89BE, 0x8A5A, 0x8AFB, 0x8BA0, 0x8C4A, 0x8CF8, 0x8DAB, 0x8E62, 0x8F1D, 0x8FDD, 0x90A1, 0x9169, 0x9236,
+ 0x9307, 0x93DC, 0x94B5, 0x9592, 0x9674, 0x9759, 0x9843, 0x9930, 0x9A22, 0x9B17, 0x9C11, 0x9D0E, 0x9E0F,
+ 0x9F14, 0xA01C, 0xA129, 0xA238, 0xA34C, 0xA463, 0xA57E, 0xA69C, 0xA7BD, 0xA8E2, 0xAA0A, 0xAB36, 0xAC65,
+ 0xAD97, 0xAECC, 0xB005, 0xB140, 0xB27F, 0xB3C0, 0xB505, 0xB64C, 0xB796, 0xB8E3, 0xBA33, 0xBB85, 0xBCDA,
+ 0xBE32, 0xBF8C, 0xC0E9, 0xC248, 0xC3A9, 0xC50D, 0xC673, 0xC7DB, 0xC946, 0xCAB2, 0xCC21, 0xCD92, 0xCF04,
+ 0xD079, 0xD1EF, 0xD367, 0xD4E1, 0xD65C, 0xD7D9, 0xD958, 0xDAD8, 0xDC59, 0xDDDC, 0xDF61, 0xE0E6, 0xE26D,
+ 0xE3F4, 0xE57D, 0xE707, 0xE892, 0xEA1E, 0xEBAB, 0xED38, 0xEEC6, 0xF055, 0xF1E4, 0xF374, 0xF505, 0xF695,
+ 0xF827, 0xF9B8, 0xFB4A, 0xFCDC, 0xFE6E, 0x0000
+};
diff --git a/drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c b/drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.c
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_const_structs.h"
+
+//Floating-point structs
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+ 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+ 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+ 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+ 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+ 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+ 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+ 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+ 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+ 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+};
+
+//Fixed-point structs
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = {
+ 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = {
+ 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = {
+ 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = {
+ 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = {
+ 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = {
+ 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = {
+ 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = {
+ 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = {
+ 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
+};
+
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = {
+ 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = {
+ 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = {
+ 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = {
+ 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = {
+ 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = {
+ 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = {
+ 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = {
+ 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = {
+ 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
+};
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_f32.c
+*
+* Description: Floating-point complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_conj Complex Conjugate
+ *
+ * Conjugates the elements of a complex data vector.
+ *
+ * The pSrc points to the source data and
+ * pDst points to the where the result should be written.
+ * numSamples specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of 2*numSamples values.
+ * The underlying algorithm is used:
+ *
+ *
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inR1, inR2, inR3, inR4;
+ float32_t inI1, inI2, inI3, inI4;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* read real input samples */
+ inR1 = pSrc[0];
+ /* store real samples to destination */
+ pDst[0] = inR1;
+ inR2 = pSrc[2];
+ pDst[2] = inR2;
+ inR3 = pSrc[4];
+ pDst[4] = inR3;
+ inR4 = pSrc[6];
+ pDst[6] = inR4;
+
+ /* read imaginary input samples */
+ inI1 = pSrc[1];
+ inI2 = pSrc[3];
+
+ /* conjugate input */
+ inI1 = -inI1;
+
+ /* read imaginary input samples */
+ inI3 = pSrc[5];
+
+ /* conjugate input */
+ inI2 = -inI2;
+
+ /* read imaginary input samples */
+ inI4 = pSrc[7];
+
+ /* conjugate input */
+ inI3 = -inI3;
+
+ /* store imaginary samples to destination */
+ pDst[1] = inI1;
+ pDst[3] = inI2;
+
+ /* conjugate input */
+ inI4 = -inI4;
+
+ /* store imaginary samples to destination */
+ pDst[5] = inI3;
+
+ /* increment source pointer by 8 to process next sampels */
+ pSrc += 8u;
+
+ /* store imaginary sample to destination */
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to store next samples */
+ pDst += 8u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_q15.c
+*
+* Description: Q15 complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t zero = 0;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ in1 = __QASX(zero, in1);
+ in2 = __QASX(zero, in2);
+ in3 = __QASX(zero, in3);
+ in4 = __QASX(zero, in4);
+
+#else
+
+ in1 = __QSAX(zero, in1);
+ in2 = __QSAX(zero, in2);
+ in3 = __QSAX(zero, in3);
+ in4 = __QSAX(zero, in4);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+ in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+ in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+ in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+ *__SIMD32(pDst)++ = in1;
+ *__SIMD32(pDst)++ = in2;
+ *__SIMD32(pDst)++ = in3;
+ *__SIMD32(pDst)++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = __SSAT(-*pSrc++, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ q15_t in;
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_q31.c
+*
+* Description: Q31 complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
+ q31_t inI1, inI2, inI3, inI4; /* Temporary imaginary variables */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ /* read real input sample */
+ inR1 = pSrc[0];
+ /* store real input sample */
+ pDst[0] = inR1;
+
+ /* read imaginary input sample */
+ inI1 = pSrc[1];
+
+ /* read real input sample */
+ inR2 = pSrc[2];
+ /* store real input sample */
+ pDst[2] = inR2;
+
+ /* read imaginary input sample */
+ inI2 = pSrc[3];
+
+ /* negate imaginary input sample */
+ inI1 = __QSUB(0, inI1);
+
+ /* read real input sample */
+ inR3 = pSrc[4];
+ /* store real input sample */
+ pDst[4] = inR3;
+
+ /* read imaginary input sample */
+ inI3 = pSrc[5];
+
+ /* negate imaginary input sample */
+ inI2 = __QSUB(0, inI2);
+
+ /* read real input sample */
+ inR4 = pSrc[6];
+ /* store real input sample */
+ pDst[6] = inR4;
+
+ /* negate imaginary input sample */
+ inI3 = __QSUB(0, inI3);
+
+ /* store imaginary input sample */
+ inI4 = pSrc[7];
+
+ /* store imaginary input samples */
+ pDst[1] = inI1;
+
+ /* negate imaginary input sample */
+ inI4 = __QSUB(0, inI4);
+
+ /* store imaginary input samples */
+ pDst[3] = inI2;
+
+ /* increment source pointer by 8 to proecess next samples */
+ pSrc += 8u;
+
+ /* store imaginary input samples */
+ pDst[5] = inI3;
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to process next samples */
+ pDst += 8u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_f32.c
+*
+* Description: Floating-point complex dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_dot_prod Complex Dot Product
+ *
+ * Computes the dot product of two complex vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * The pSrcA points to the first complex input vector and
+ * pSrcB points to the second complex input vector.
+ * numSamples specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of 2*numSamples values.
+ *
+ * The underlying algorithm is used:
+ *
+ * realResult=0;
+ * imagResult=0;
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult)
+{
+ float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
+ float32_t a0,b0,c0,d0;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples & 0x3u;
+
+ while(blkCnt > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in the destination buffers */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_q15.c
+*
+* Description: Processing function for the Q15 Complex Dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q15 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.
+ * As a final step, the accumulators are converted to 8.24 format.
+ * The return results realResult and imagResult are in 8.24 format.
+ */
+
+void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+ q15_t a0,b0,c0,d0;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in 8.24 format */
+ /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+ *realResult = (q31_t) (real_sum >> 6);
+ /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+ *imagResult = (q31_t) (imag_sum >> 6);
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,187 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_q31.c
+*
+* Description: Q31 complex dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q31 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
+ * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.
+ * The return results realResult and imagResult are in 16.48 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+ q31_t a0,b0,c0,d0;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in 16.48 format */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_f32.c
+*
+* Description: Floating-point complex magnitude.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag Complex Magnitude
+ *
+ * Computes the magnitude of the elements of a complex data vector.
+ *
+ * The pSrc points to the source data and
+ * pDst points to the where the result should be written.
+ * numSamples specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of 2*numSamples values;
+ * the output array has a total of numSamples values.
+ * The underlying algorithm is used:
+ *
+ *
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+/**
+ * @brief Floating-point complex magnitude.
+ * @param[in] *pSrc points to complex input buffer
+ * @param[out] *pDst points to real output buffer
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t realIn, imagIn; /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* out = sqrt((real * real) + (imag * imag)) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_q15.c
+*
+* Description: Q15 complex magnitude.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
+ */
+
+void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to hold input values */
+
+ while(numSamples > 0u)
+ {
+ /* out = sqrt(real * real + imag * imag) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_q31.c
+*
+* Description: Q31 complex magnitude
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+/**
+ * @brief Q31 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to hold input values */
+ q31_t acc0, acc1; /* Accumulators */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
+ q31_t out1, out2, out3, out4; /* Accumulators */
+ q63_t mul1, mul2, mul3, mul4; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read complex input from source buffer */
+ real1 = pSrc[0];
+ imag1 = pSrc[1];
+ real2 = pSrc[2];
+ imag2 = pSrc[3];
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* read complex input from source buffer */
+ real1 = pSrc[4];
+ imag1 = pSrc[5];
+ real2 = pSrc[6];
+ imag2 = pSrc[7];
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[0]);
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[1]);
+
+ /* calculate power of input values */
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[2]);
+
+ /* increment destination by 8 to process next samples */
+ pSrc += 8u;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[3]);
+
+ /* increment destination by 4 to process next samples */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 2.30 format in the destination buffer. */
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,215 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_f32.c
+*
+* Description: Floating-point complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared
+ *
+ * Computes the magnitude squared of the elements of a complex data vector.
+ *
+ * The pSrc points to the source data and
+ * pDst points to the where the result should be written.
+ * numSamples specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of 2*numSamples values;
+ * the output array has a total of numSamples values.
+ *
+ * The underlying algorithm is used:
+ *
+ *
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t real, imag; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
+ float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
+ float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
+ float32_t mul5, mul6, mul7, mul8; /* Temporary variables */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output values */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ /* read real input sample from source buffer */
+ real1 = pSrc[0];
+ /* read imaginary input sample from source buffer */
+ imag1 = pSrc[1];
+
+ /* calculate power of real value */
+ mul1 = real1 * real1;
+
+ /* read real input sample from source buffer */
+ real2 = pSrc[2];
+
+ /* calculate power of imaginary value */
+ mul2 = imag1 * imag1;
+
+ /* read imaginary input sample from source buffer */
+ imag2 = pSrc[3];
+
+ /* calculate power of real value */
+ mul3 = real2 * real2;
+
+ /* read real input sample from source buffer */
+ real3 = pSrc[4];
+
+ /* calculate power of imaginary value */
+ mul4 = imag2 * imag2;
+
+ /* read imaginary input sample from source buffer */
+ imag3 = pSrc[5];
+
+ /* calculate power of real value */
+ mul5 = real3 * real3;
+ /* calculate power of imaginary value */
+ mul6 = imag3 * imag3;
+
+ /* read real input sample from source buffer */
+ real4 = pSrc[6];
+
+ /* accumulate real and imaginary powers */
+ out1 = mul1 + mul2;
+
+ /* read imaginary input sample from source buffer */
+ imag4 = pSrc[7];
+
+ /* accumulate real and imaginary powers */
+ out2 = mul3 + mul4;
+
+ /* calculate power of real value */
+ mul7 = real4 * real4;
+ /* calculate power of imaginary value */
+ mul8 = imag4 * imag4;
+
+ /* store output to destination */
+ pDst[0] = out1;
+
+ /* accumulate real and imaginary powers */
+ out3 = mul5 + mul6;
+
+ /* store output to destination */
+ pDst[1] = out2;
+
+ /* accumulate real and imaginary powers */
+ out4 = mul7 + mul8;
+
+ /* store output to destination */
+ pDst[2] = out3;
+
+ /* increment destination pointer by 8 to process next samples */
+ pSrc += 8u;
+
+ /* store output to destination */
+ pDst[3] = out4;
+
+ /* increment destination pointer by 4 to process next samples */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ /* out = (real * real) + (imag * imag) */
+ /* store the result in the destination buffer. */
+ *pDst++ = (real * real) + (imag * imag);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_q15.c
+*
+* Description: Q15 complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+ *pDst++ = (q15_t) (acc1 >> 17);
+ *pDst++ = (q15_t) (acc2 >> 17);
+ *pDst++ = (q15_t) (acc3 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to store real and imaginary values */
+
+ while(numSamples > 0u)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_q31.c
+*
+* Description: Q31 complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to store real and imaginary values */
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_f32.c
+*
+* Description: Floating-point complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication
+ *
+ * Multiplies a complex vector by another complex vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter numSamples represents the number of complex
+ * samples processed. The complex arrays have a total of 2*numSamples
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ *
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
+ float32_t acc1, acc2, acc3, acc4;
+
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA; /* A[2 * i] */
+ c1 = *pSrcB; /* B[2 * i] */
+
+ b1 = *(pSrcA + 1); /* A[2 * i + 1] */
+ acc1 = a1 * c1; /* acc1 = A[2 * i] * B[2 * i] */
+
+ a2 = *(pSrcA + 2); /* A[2 * i + 2] */
+ acc2 = (b1 * c1); /* acc2 = A[2 * i + 1] * B[2 * i] */
+
+ d1 = *(pSrcB + 1); /* B[2 * i + 1] */
+ c2 = *(pSrcB + 2); /* B[2 * i + 2] */
+ acc1 -= b1 * d1; /* acc1 = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ d2 = *(pSrcB + 3); /* B[2 * i + 3] */
+ acc3 = a2 * c2; /* acc3 = A[2 * i + 2] * B[2 * i + 2] */
+
+ b2 = *(pSrcA + 3); /* A[2 * i + 3] */
+ acc2 += (a1 * d1); /* acc2 = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+
+ a1 = *(pSrcA + 4); /* A[2 * i + 4] */
+ acc4 = (a2 * d2); /* acc4 = A[2 * i + 2] * B[2 * i + 3] */
+
+ c1 = *(pSrcB + 4); /* B[2 * i + 4] */
+ acc3 -= (b2 * d2); /* acc3 = A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
+ *pDst = acc1; /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ b1 = *(pSrcA + 5); /* A[2 * i + 5] */
+ acc4 += b2 * c2; /* acc4 = A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
+
+ *(pDst + 1) = acc2; /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+ acc1 = (a1 * c1);
+
+ d1 = *(pSrcB + 5);
+ acc2 = (b1 * c1);
+
+ *(pDst + 2) = acc3;
+ *(pDst + 3) = acc4;
+
+ a2 = *(pSrcA + 6);
+ acc1 -= (b1 * d1);
+
+ c2 = *(pSrcB + 6);
+ acc2 += (a1 * d1);
+
+ b2 = *(pSrcA + 7);
+ acc3 = (a2 * c2);
+
+ d2 = *(pSrcB + 7);
+ acc4 = (b2 * c2);
+
+ *(pDst + 4) = acc1;
+ pSrcA += 8u;
+
+ acc3 -= (b2 * d2);
+ acc4 += (a2 * d2);
+
+ *(pDst + 5) = acc2;
+ pSrcB += 8u;
+
+ *(pDst + 6) = acc3;
+ *(pDst + 7) = acc4;
+
+ pDst += 8u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA++;
+ b1 = *pSrcA++;
+ c1 = *pSrcB++;
+ d1 = *pSrcB++;
+
+ /* store the result in the destination buffer. */
+ *pDst++ = (a1 * c1) - (b1 * d1);
+ *pDst++ = (a1 * d1) + (b1 * c1);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,193 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_q15.c
+*
+* Description: Q15 complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_q31.c
+*
+* Description: Q31 complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+ q31_t mul1, mul2, mul3, mul4;
+ q31_t out1, out2;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x2u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_f32.c
+*
+* Description: Floating-point complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication
+ *
+ * Multiplies a complex vector by a real vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter numSamples represents the number of complex
+ * samples processed. The complex arrays have a total of 2*numSamples
+ * real values while the real array has a total of numSamples
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ *
+ * for(n=0; n
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
+ float32_t inA5, inA6, inA7, inA8; /* Temporary variables to hold input data */
+ float32_t inB1, inB2, inB3, inB4; /* Temporary variables to hold input data */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ float32_t out5, out6, out7, out8; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read input from complex input buffer */
+ inA1 = pSrcCmplx[0];
+ inA2 = pSrcCmplx[1];
+ /* read input from real input buffer */
+ inB1 = pSrcReal[0];
+
+ /* read input from complex input buffer */
+ inA3 = pSrcCmplx[2];
+
+ /* multiply complex buffer real input with real buffer input */
+ out1 = inA1 * inB1;
+
+ /* read input from complex input buffer */
+ inA4 = pSrcCmplx[3];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out2 = inA2 * inB1;
+
+ /* read input from real input buffer */
+ inB2 = pSrcReal[1];
+ /* read input from complex input buffer */
+ inA5 = pSrcCmplx[4];
+
+ /* multiply complex buffer real input with real buffer input */
+ out3 = inA3 * inB2;
+
+ /* read input from complex input buffer */
+ inA6 = pSrcCmplx[5];
+ /* read input from real input buffer */
+ inB3 = pSrcReal[2];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out4 = inA4 * inB2;
+
+ /* read input from complex input buffer */
+ inA7 = pSrcCmplx[6];
+
+ /* multiply complex buffer real input with real buffer input */
+ out5 = inA5 * inB3;
+
+ /* read input from complex input buffer */
+ inA8 = pSrcCmplx[7];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out6 = inA6 * inB3;
+
+ /* read input from real input buffer */
+ inB4 = pSrcReal[3];
+
+ /* store result to destination bufer */
+ pCmplxDst[0] = out1;
+
+ /* multiply complex buffer real input with real buffer input */
+ out7 = inA7 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[1] = out2;
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out8 = inA8 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[2] = out3;
+ pCmplxDst[3] = out4;
+ pCmplxDst[4] = out5;
+
+ /* incremnet complex input buffer by 8 to process next samples */
+ pSrcCmplx += 8u;
+
+ /* store result to destination bufer */
+ pCmplxDst[5] = out6;
+
+ /* increment real input buffer by 4 to process next samples */
+ pSrcReal += 4u;
+
+ /* store result to destination bufer */
+ pCmplxDst[6] = out7;
+ pCmplxDst[7] = out8;
+
+ /* increment destination buffer by 8 to process next sampels */
+ pCmplxDst += 8u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_q15.c
+*
+* Description: Q15 complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q15_t in; /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA1, inA2; /* Temporary variables to hold input data */
+ q31_t inB1; /* Temporary variables to hold input data */
+ q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read complex number both real and imaginary from complex input buffer */
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ /* read two real values at a time from real input buffer */
+ inB1 = *__SIMD32(pSrcReal)++;
+ /* read complex number both real and imaginary from complex input buffer */
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+ /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* saturate the result */
+ out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+ /* pack real and imaginary outputs and store them to destination */
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ inB1 = *__SIMD32(pSrcReal)++;
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut = realA * realB. */
+ /* imagOut = imagA * realB. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,223 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_q31.c
+*
+* Description: Q31 complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q31_t inA1; /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA2, inA3, inA4; /* Temporary variables to hold input data */
+ q31_t inB1, inB2; /* Temporary variabels to hold input data */
+ q31_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut = realA * realB. */
+ /* imagReal = imagA * realB. */
+ inA1 = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_f32.c
+*
+* Description: Floating-point PID Control initialization function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state & 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The resetStateFlag specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: A0, A1 A2
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag)
+{
+
+ /* Derived coefficient A0 */
+ S->A0 = S->Kp + S->Ki + S->Kd;
+
+ /* Derived coefficient A1 */
+ S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(float32_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_q15.c
+*
+* Description: Q15 PID Control initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The resetStateFlag specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: A0, A1 A2
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficients and pack into A1 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+ S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp; /*to store the sum */
+
+ /* Derived coefficient A0 */
+ temp = S->Kp + S->Ki + S->Kd;
+ S->A0 = (q15_t) __SSAT(temp, 16);
+
+ /* Derived coefficients and pack into A1 */
+ temp = -(S->Kd + S->Kd + S->Kp);
+ S->A1 = (q15_t) __SSAT(temp, 16);
+ S->A2 = S->Kd;
+
+
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_q31.c
+*
+* Description: Q31 PID Control initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The resetStateFlag specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: A0, A1 A2
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficient A1 */
+ S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp;
+
+ /* Derived coefficient A0 */
+ temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+ S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+ /* Derived coefficient A1 */
+ temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+ S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q31_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_f32.c
+*
+* Description: Floating-point PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the floating-point PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_q15.c
+*
+* Description: Q15 PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q15 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S)
+{
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_q31.c
+*
+* Description: Q31 PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q31 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_cos_f32.c
+*
+* Description: Sine and Cosine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup SinCos Sine Cosine
+ *
+ * Computes the trigonometric sine and cosine values using a combination of table lookup
+ * and linear interpolation.
+ * There are separate functions for Q31 and floating-point data types.
+ * The input to the floating-point version is in degrees while the
+ * fixed-point Q31 have a scaled input with the range
+ * [-1 0.9999] mapping to [-180 +180] degrees.
+ *
+ * The floating point function also allows values that are out of the usual range. When this happens, the function will
+ * take extra time to adjust the input value to the range of [-180 180].
+ *
+ * The implementation is based on table lookup using 360 values together with linear interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index.
+ * -# Compute the fractional portion (fract) of the input.
+ * -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)).
+ * -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)).
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal)
+{
+ float32_t fract, in; /* Temporary variables for input, output */
+ uint16_t indexS, indexC; /* Index variable */
+ float32_t f1, f2, d1, d2; /* Two nearest output values */
+ int32_t n;
+ float32_t findex, Dn, Df, temp;
+
+ /* input x is in degrees */
+ /* Scale the input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */
+ in = theta * 0.00277777777778f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if(in < 0.0f)
+ {
+ n--;
+ }
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+ indexS = ((uint16_t)findex) & 0x1ff;
+ indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff;
+
+ /* fractional value calculation */
+ fract = findex - (float32_t) indexS;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_f32[indexC+0];
+ f2 = sinTable_f32[indexC+1];
+ d1 = -sinTable_f32[indexS+0];
+ d2 = -sinTable_f32[indexS+1];
+
+ Dn = 0.0122718463030f; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn*(d1 + d2) - 2*Df;
+ temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
+ temp = fract*temp + d1*Dn;
+
+ /* Calculation of cosine value */
+ *pCosVal = fract*temp + f1;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_f32[indexS+0];
+ f2 = sinTable_f32[indexS+1];
+ d1 = sinTable_f32[indexC+0];
+ d2 = sinTable_f32[indexC+1];
+
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn*(d1 + d2) - 2*Df;
+ temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
+ temp = fract*temp + d1*Dn;
+
+ /* Calculation of sine value */
+ *pSinVal = fract*temp + f1;
+}
+/**
+ * @} end of SinCos group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_cos_q31.c
+*
+* Description: Cosine & Sine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupController
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ *
+ * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].
+ *
+ */
+
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal)
+{
+ q31_t fract; /* Temporary variables for input, output */
+ uint16_t indexS, indexC; /* Index variable */
+ q31_t f1, f2, d1, d2; /* Two nearest output values */
+ q31_t Dn, Df;
+ q63_t temp;
+
+ /* Calculate the nearest index */
+ indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT;
+ indexC = (indexS + 128) & 0x1ff;
+
+ /* Calculation of fractional value */
+ fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_q31[indexC+0];
+ f2 = sinTable_q31[indexC+1];
+ d1 = -sinTable_q31[indexS+0];
+ d2 = -sinTable_q31[indexS+1];
+
+ Dn = 0x1921FB5; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn*((q63_t)d1 + d2);
+ temp = temp - ((q63_t)Df << 32);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + (q63_t)d1*Dn;
+ temp = (q63_t)fract*(temp >> 31);
+
+ /* Calculation of cosine value */
+ *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_q31[indexS+0];
+ f2 = sinTable_q31[indexS+1];
+ d1 = sinTable_q31[indexC+0];
+ d2 = sinTable_q31[indexC+1];
+
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn*((q63_t)d1 + d2);
+ temp = temp - ((q63_t)Df << 32);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
+ temp = (q63_t)fract*(temp >> 31);
+ temp = temp + (q63_t)d1*Dn;
+ temp = (q63_t)fract*(temp >> 31);
+
+ /* Calculation of sine value */
+ *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+}
+
+/**
+ * @} end of SinCos group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_f32.c
+*
+* Description: Fast cosine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup cos Cosine
+ *
+ * Computes the trigonometric cosine function using a combination of table lookup
+ * and cubic interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Fetch the four table values a, b, c, and d
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# Calculation of wa, wb, wc, wd
+ * -# The final result equals a*wa + b*wb + c*wc + d*wd
+ *
+ * where
+ *
+ * a=Table[index-1];
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * d=Table[index+2];
+ *
+ * and
+ *
+ * wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;
+ * wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;
+ * wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;
+ * wd=(1/6)*fract.^3 - (1/6)*fract;
+ *
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+float32_t arm_cos_f32(
+ float32_t x)
+{
+ float32_t cosVal, fract, in; /* Temporary variables for input, output */
+ uint16_t index; /* Index variable */
+ float32_t a, b; /* Two nearest output values */
+ int32_t n;
+ float32_t findex;
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */
+ in = x * 0.159154943092f + 0.25f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if(in < 0.0f)
+ {
+ n--;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+ index = ((uint16_t)findex) & 0x1ff;
+
+ /* fractional value calculation */
+ fract = findex - (float32_t) index;
+
+ /* Read two nearest values of input value from the cos table */
+ a = sinTable_f32[index];
+ b = sinTable_f32[index+1];
+
+ /* Linear interpolation process */
+ cosVal = (1.0f-fract)*a + fract*b;
+
+ /* Return the output value */
+ return (cosVal);
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_q15.c
+*
+* Description: Fast cosine calculation for Q15 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q15_t arm_cos_q15(
+ q15_t x)
+{
+ q15_t sinVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q15_t a, b; /* Four nearest output values */
+ q15_t fract; /* Temporary values for fractional values */
+
+ /* add 0.25 (pi/2) to read sine table */
+ x += 0x2000;
+ if(x < 0)
+ { /* convert negative numbers to corresponding positive ones */
+ x = x + 0x8000;
+ }
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q15[index];
+ b = sinTable_q15[index+1];
+
+ /* Linear interpolation process */
+ sinVal = (q31_t)(0x8000-fract)*a >> 16;
+ sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
+
+ return sinVal << 1;
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_q31.c
+*
+* Description: Fast cosine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q31_t arm_cos_q31(
+ q31_t x)
+{
+ q31_t cosVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q31_t a, b; /* Four nearest output values */
+ q31_t fract; /* Temporary values for fractional values */
+
+ /* add 0.25 (pi/2) to read sine table */
+ x += 0x20000000;
+ if(x < 0)
+ { /* convert negative numbers to corresponding positive ones */
+ x = x + 0x80000000;
+ }
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q31[index];
+ b = sinTable_q31[index+1];
+
+ /* Linear interpolation process */
+ cosVal = (q63_t)(0x80000000-fract)*a >> 32;
+ cosVal = (q31_t)((((q63_t)cosVal << 32) + ((q63_t)fract*b)) >> 32);
+
+ return cosVal << 1;
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_f32.c
+*
+* Description: Fast sine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup sin Sine
+ *
+ * Computes the trigonometric sine function using a combination of table lookup
+ * and cubic interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Fetch the four table values a, b, c, and d
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# Calculation of wa, wb, wc, wd
+ * -# The final result equals a*wa + b*wb + c*wc + d*wd
+ *
+ * where
+ *
+ * a=Table[index-1];
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * d=Table[index+2];
+ *
+ * and
+ *
+ * wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;
+ * wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;
+ * wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;
+ * wd=(1/6)*fract.^3 - (1/6)*fract;
+ *
+ */
+
+/**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+float32_t arm_sin_f32(
+ float32_t x)
+{
+ float32_t sinVal, fract, in; /* Temporary variables for input, output */
+ uint16_t index; /* Index variable */
+ float32_t a, b; /* Two nearest output values */
+ int32_t n;
+ float32_t findex;
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+ in = x * 0.159154943092f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if(x < 0.0f)
+ {
+ n--;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
+ index = ((uint16_t)findex) & 0x1ff;
+
+ /* fractional value calculation */
+ fract = findex - (float32_t) index;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_f32[index];
+ b = sinTable_f32[index+1];
+
+ /* Linear interpolation process */
+ sinVal = (1.0f-fract)*a + fract*b;
+
+ /* Return the output value */
+ return (sinVal);
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_q15.c
+*
+* Description: Fast sine calculation for Q15 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
+ */
+
+q15_t arm_sin_q15(
+ q15_t x)
+{
+ q15_t sinVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q15_t a, b; /* Four nearest output values */
+ q15_t fract; /* Temporary values for fractional values */
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q15[index];
+ b = sinTable_q15[index+1];
+
+ /* Linear interpolation process */
+ sinVal = (q31_t)(0x8000-fract)*a >> 16;
+ sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
+
+ return sinVal << 1;
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_q31.c
+*
+* Description: Fast sine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
+
+q31_t arm_sin_q31(
+ q31_t x)
+{
+ q31_t sinVal; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q31_t a, b; /* Four nearest output values */
+ q31_t fract; /* Temporary values for fractional values */
+
+ /* Calculate the nearest index */
+ index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
+
+ /* Calculation of fractional value */
+ fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
+
+ /* Read two nearest values of input value from the sin table */
+ a = sinTable_q31[index];
+ b = sinTable_q31[index+1];
+
+ /* Linear interpolation process */
+ sinVal = (q63_t)(0x80000000-fract)*a >> 32;
+ sinVal = (q31_t)((((q63_t)sinVal << 32) + ((q63_t)fract*b)) >> 32);
+
+ return sinVal << 1;
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sqrt_q15.c
+*
+* Description: Q15 square root function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut)
+{
+ q15_t number, temp1, var1, signBits1, half;
+ q31_t bits_val1;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if(number > 0)
+ {
+ signBits1 = __CLZ(number) - 17;
+
+ /* Shift by the number of signBits1 */
+ if((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /*Convert to float */
+ temp_float1 = number * 3.051757812500000e-005f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 16384);
+
+ /* 1st iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 2nd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 3rd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
+
+ /* Shift the output down accordingly */
+ if((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_sqrt_q31.c
+*
+* Description: Q31 square root function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut)
+{
+ q31_t number, temp1, bits_val1, var1, signBits1, half;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if(number > 0)
+ {
+ signBits1 = __CLZ(number) - 1;
+
+ /* Shift by the number of signBits1 */
+ if((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /*Convert to float */
+ temp_float1 = number * 4.6566128731e-010f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 1073741824);
+
+ /* 1st iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 2nd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 3rd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
+
+ /* Shift the output down accordingly */
+ if((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_32x64_init_q31.c
+*
+* Description: High precision Q31 Biquad cascade filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format.
+ * @return none
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ *
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ *
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on. The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState points to state variables array and size of each state variable is 1.63 format.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the state array as:
+ *
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ *
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,561 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_32x64_q31.c
+*
+* Description: High precision Q31 Biquad cascade filter processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter
+ *
+ * This function implements a high precision Biquad cascade filter which operates on
+ * Q31 data values. The filter coefficients are in 1.31 format and the state variables
+ * are in 1.63 format. The double precision state variables reduce quantization noise
+ * in the filter and provide a cleaner output.
+ * These filters are particularly useful when implementing filters in which the
+ * singularities are close to the unit circle. This is common for low pass or high
+ * pass filters with very low cutoff frequencies.
+ *
+ * The function operates on blocks of input and output data
+ * and each call to the function processes blockSize samples through
+ * the filter. pSrc and pDst points to input and output arrays
+ * containing blockSize Q31 values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ *
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ *
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ *
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ *
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * numStages refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+ *
+ * \par
+ * The pState points to state variables array .
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.
+ * The state variables are arranged in the array as:
+ *
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ *
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values of data in 1.63 format.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ *
+ * \par Init Function
+ * There is also an associated initialization function which performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * For example, to statically initialize the filter instance structure use
+ *
+ * arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+ *
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.
+ * \par Fixed-Point Behavior
+ * Care must be taken while using Biquad Cascade 32x64 filter function.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * Filter coefficients are represented as fractional values and
+ * restricted to lie in the range [-1 +1).
+ * The processing function has an additional scaling parameter postShift
+ * which allows the filter coefficients to exceed the range [+1 -1).
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by 2^postShift.
+ * For example, to realize the coefficients
+ *
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ *
+ * set the Coefficient array to:
+ *
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ *
+ * and set postShift=1
+ *
+ * \par
+ * The second thing to keep in mind is the gain through the filter.
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.
+ * This is described in the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Two related functions are provided in the CMSIS DSP library.
+ * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.
+ * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q63_t *pState = S->pState; /* state pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q63_t acc; /* accumulator */
+ q31_t Xn1, Xn2; /* Input Filter state variables */
+ q63_t Yn1, Yn2; /* Output Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+ q31_t acc_l, acc_h; /* temporary output */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = (q31_t) (pState[0]);
+ Xn2 = (q31_t) (pState[1]);
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut = acc_h;
+
+ /* Read the second input into Xn2, to reuse the value */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc += b1 * x[n-1] */
+ acc = (q63_t) Xn *b1;
+
+ /* acc = b0 * x[n] */
+ acc += (q63_t) Xn2 *b0;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn1 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Read the third input into Xn1, to reuse the value */
+ Xn1 = *pIn++;
+
+ /* The result is converted to 1.31 */
+ /* Store the output in the destination buffer. */
+ *(pOut + 1u) = acc_h;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn1 *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn2 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 2u) = acc_h;
+
+ /* Read the fourth input into Xn, to reuse the value */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 3u) = acc_h;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* update output pointer */
+ pOut += 4u;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+ //Yn1 = acc << shift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+// *pOut++ = (q31_t) (acc >> (32 - shift));
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+
+ //Yn1 = acc << shift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ //*pOut++ = (q31_t) (acc >> (32 - shift));
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+ /**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,425 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_f32.c
+*
+* Description: Processing function for the
+* floating-point Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
+ *
+ * This set of functions implements arbitrary order recursive (IIR) filters.
+ * The filters are implemented as a cascade of second order Biquad sections.
+ * The functions support Q15, Q31 and floating-point data types.
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
+ *
+ * The functions operate on blocks of input and output data and each call to the function
+ * processes blockSize samples through the filter.
+ * pSrc points to the array of input data and
+ * pDst points to the array of output data.
+ * Both arrays contain blockSize values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ *
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ *
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ *
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ *
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * numStages refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+ *
+ * \par
+ * The pState points to state variables array.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ *
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ *
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Init Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ *
+ * arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+ * arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+ * arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+ *
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * Scaling of coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range [-1 +1).
+ * The fixed-point functions have an additional scaling parameter postShift
+ * which allow the filter coefficients to exceed the range [+1 -1).
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by 2^postShift.
+ * For example, to realize the coefficients
+ *
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ *
+ * set the pCoeffs array to:
+ *
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ *
+ * and set postShift=1
+ *
+ * \par
+ * Filter gain:
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * Overflow and saturation:
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ */
+
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* pState pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc; /* Simulates the accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ float32_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the first input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = blockSize & 0x3u;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+ /**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_fast_q15.c
+*
+* Description: Fast processing function for the
+* Q15 Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).
+ * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.
+ *
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc; /* Accumulator */
+ int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = S->numStages; /* Stage loop counter */
+
+
+
+ do
+ {
+
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(sample > 0u)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+ /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if((blockSize & 0x1u) != 0u)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent (numStages - 1) occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_fast_q31.c
+*
+* Description: Processing function for the
+* Q31 Fast Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t acc = 0; /* accumulator */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variables acc ... acc3 hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
+ mult_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the second input */
+ Xn2 = *(pIn + 1u);
+
+ /* Store the output in the destination buffer. */
+ *pOut = Yn2;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn2);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn1);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Read the third input */
+ Xn1 = *(pIn + 2u);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 1u) = Yn1;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn1);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn2);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the forth input */
+ Xn = *(pIn + 3u);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 2u) = Yn2;
+ pIn += 4u;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ Xn2 = Xn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Xn1 = Xn */
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 3u) = Yn1;
+ pOut += 4u;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 */
+ acc = acc << shift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_f32.c
+*
+* Description: floating-point Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients array.
+ * @param[in] *pState points to the state array.
+ * @return none
+ *
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ *
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ *
+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on. The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ *
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ *
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_q15.c
+*
+* Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
+ * @return none
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ *
+ * {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+ *
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on. The pCoeffs array contains a total of 6*numStages values.
+ * The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4.
+ *
+ * \par
+ * The state variables are stored in the array pState.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ *
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ *
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_q31.c
+*
+* Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
+ * @return none
+ *
+ * Coefficient and State Ordering:
+ *
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ *
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ *
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on. The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState points to state variables array.
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ * The state variables are arranged in the pState array as:
+ *
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ *
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of 4*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,411 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_q15.c
+*
+* Description: Processing function for the
+* Q15 Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.
+ * Finally, the result is saturated to 1.15 format.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc_l, acc_h;
+ q63_t acc; /* Accumulator */
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+ int32_t uShift = (32 - lShift);
+
+ do
+ {
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(sample > 0u)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if((blockSize & 0x1u) != 0u)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input wire to the output wire. */
+ /* Subsequent numStages occur in-place in the output wire */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q15_t Xn; /* temporary input */
+ q63_t acc; /* Accumulator */
+ int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ pCoeffs++; // skip the 0 coefficient
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q31_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q31_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q31_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q31_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q31_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q15_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,405 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_q31.c
+*
+* Description: Processing function for the
+* Q31 Biquad cascade filter
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q63_t acc; /* accumulator */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ q31_t acc_l, acc_h; /* temporary output variables */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn2;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn1;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn1;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn2;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+}
+
+
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,603 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_f32.c
+*
+* Description: Processing function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes blockSize samples through the filter.
+* pSrc points to the array of input data and
+* pDst points to the array of output data.
+* Both arrays contain blockSize values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+*
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+*
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+*
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+*
+* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* numStages refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with numStages=4 second order stages.
+* A 9th order filter would be realized with numStages=5 second order stages with the
+* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+*
+* \par
+* pState points to the state variable array.
+* Each Biquad stage has 2 state variables d1 and d2.
+* The state variables are arranged in the pState array as:
+*
+* {d11, d12, d21, d22, ...}
+*
+* where d1x refers to the state variables for the first Biquad and
+* d2x refers to the state variables for the second Biquad.
+* The state array has a total length of 2*numStages values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+*
+* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+*
+* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
+* pCoeffs is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f32(
+const arm_biquad_cascade_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc1; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1; /* temporary input */
+ float32_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#if defined(ARM_MATH_CM7)
+
+ float32_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8; /* Input State variables */
+ float32_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+ float32_t acc2, acc3, acc4, acc5, acc6, acc7; /* Simulates the accumulator */
+ float32_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ /* Apply loop unrolling and compute 16 output values simultaneously. */
+ sample = blockSize >> 4u;
+ a2 = pCoeffs[4];
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ pCoeffs += 5u;
+
+
+ /* First part of the processing with loop unrolling. Compute 16 outputs at a time.
+ ** a second loop below computes the remaining 1 to 15 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the first 2 inputs. 2 cycles */
+ Xn1 = pIn[0 ];
+ Xn2 = pIn[1 ];
+
+ /* Sample 1. 5 cycles */
+ Xn3 = pIn[2 ];
+ acc1 = b0 * Xn1 + d1;
+
+ Xn4 = pIn[3 ];
+ d1 = b1 * Xn1 + d2;
+
+ Xn5 = pIn[4 ];
+ d2 = b2 * Xn1;
+
+ Xn6 = pIn[5 ];
+ d1 += a1 * acc1;
+
+ Xn7 = pIn[6 ];
+ d2 += a2 * acc1;
+
+ /* Sample 2. 5 cycles */
+ Xn8 = pIn[7 ];
+ acc2 = b0 * Xn2 + d1;
+
+ Xn9 = pIn[8 ];
+ d1 = b1 * Xn2 + d2;
+
+ Xn10 = pIn[9 ];
+ d2 = b2 * Xn2;
+
+ Xn11 = pIn[10];
+ d1 += a1 * acc2;
+
+ Xn12 = pIn[11];
+ d2 += a2 * acc2;
+
+ /* Sample 3. 5 cycles */
+ Xn13 = pIn[12];
+ acc3 = b0 * Xn3 + d1;
+
+ Xn14 = pIn[13];
+ d1 = b1 * Xn3 + d2;
+
+ Xn15 = pIn[14];
+ d2 = b2 * Xn3;
+
+ Xn16 = pIn[15];
+ d1 += a1 * acc3;
+
+ pIn += 16;
+ d2 += a2 * acc3;
+
+ /* Sample 4. 5 cycles */
+ acc4 = b0 * Xn4 + d1;
+ d1 = b1 * Xn4 + d2;
+ d2 = b2 * Xn4;
+ d1 += a1 * acc4;
+ d2 += a2 * acc4;
+
+ /* Sample 5. 5 cycles */
+ acc5 = b0 * Xn5 + d1;
+ d1 = b1 * Xn5 + d2;
+ d2 = b2 * Xn5;
+ d1 += a1 * acc5;
+ d2 += a2 * acc5;
+
+ /* Sample 6. 5 cycles */
+ acc6 = b0 * Xn6 + d1;
+ d1 = b1 * Xn6 + d2;
+ d2 = b2 * Xn6;
+ d1 += a1 * acc6;
+ d2 += a2 * acc6;
+
+ /* Sample 7. 5 cycles */
+ acc7 = b0 * Xn7 + d1;
+ d1 = b1 * Xn7 + d2;
+ d2 = b2 * Xn7;
+ d1 += a1 * acc7;
+ d2 += a2 * acc7;
+
+ /* Sample 8. 5 cycles */
+ acc8 = b0 * Xn8 + d1;
+ d1 = b1 * Xn8 + d2;
+ d2 = b2 * Xn8;
+ d1 += a1 * acc8;
+ d2 += a2 * acc8;
+
+ /* Sample 9. 5 cycles */
+ acc9 = b0 * Xn9 + d1;
+ d1 = b1 * Xn9 + d2;
+ d2 = b2 * Xn9;
+ d1 += a1 * acc9;
+ d2 += a2 * acc9;
+
+ /* Sample 10. 5 cycles */
+ acc10 = b0 * Xn10 + d1;
+ d1 = b1 * Xn10 + d2;
+ d2 = b2 * Xn10;
+ d1 += a1 * acc10;
+ d2 += a2 * acc10;
+
+ /* Sample 11. 5 cycles */
+ acc11 = b0 * Xn11 + d1;
+ d1 = b1 * Xn11 + d2;
+ d2 = b2 * Xn11;
+ d1 += a1 * acc11;
+ d2 += a2 * acc11;
+
+ /* Sample 12. 5 cycles */
+ acc12 = b0 * Xn12 + d1;
+ d1 = b1 * Xn12 + d2;
+ d2 = b2 * Xn12;
+ d1 += a1 * acc12;
+ d2 += a2 * acc12;
+
+ /* Sample 13. 5 cycles */
+ acc13 = b0 * Xn13 + d1;
+ d1 = b1 * Xn13 + d2;
+ d2 = b2 * Xn13;
+
+ pOut[0 ] = acc1 ;
+ d1 += a1 * acc13;
+
+ pOut[1 ] = acc2 ;
+ d2 += a2 * acc13;
+
+ /* Sample 14. 5 cycles */
+ pOut[2 ] = acc3 ;
+ acc14 = b0 * Xn14 + d1;
+
+ pOut[3 ] = acc4 ;
+ d1 = b1 * Xn14 + d2;
+
+ pOut[4 ] = acc5 ;
+ d2 = b2 * Xn14;
+
+ pOut[5 ] = acc6 ;
+ d1 += a1 * acc14;
+
+ pOut[6 ] = acc7 ;
+ d2 += a2 * acc14;
+
+ /* Sample 15. 5 cycles */
+ pOut[7 ] = acc8 ;
+ pOut[8 ] = acc9 ;
+ acc15 = b0 * Xn15 + d1;
+
+ pOut[9 ] = acc10;
+ d1 = b1 * Xn15 + d2;
+
+ pOut[10] = acc11;
+ d2 = b2 * Xn15;
+
+ pOut[11] = acc12;
+ d1 += a1 * acc15;
+
+ pOut[12] = acc13;
+ d2 += a2 * acc15;
+
+ /* Sample 16. 5 cycles */
+ pOut[13] = acc14;
+ acc16 = b0 * Xn16 + d1;
+
+ pOut[14] = acc15;
+ d1 = b1 * Xn16 + d2;
+
+ pOut[15] = acc16;
+ d2 = b2 * Xn16;
+
+ sample--;
+ d1 += a1 * acc16;
+
+ pOut += 16;
+ d2 += a2 * acc16;
+ }
+
+ sample = blockSize & 0xFu;
+ while(sample > 0u) {
+ Xn1 = *pIn;
+ acc1 = b0 * Xn1 + d1;
+
+ pIn++;
+ d1 = b1 * Xn1 + d2;
+
+ *pOut = acc1;
+ d2 = b2 * Xn1;
+
+ pOut++;
+ d1 += a1 * acc1;
+
+ sample--;
+ d2 += a2 * acc1;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1;
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ pState[1] = d2;
+ /* decrement the loop counter */
+ stage--;
+
+ pState += 2u;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ } while(stage > 0u);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn1 = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1 = (b0 * Xn1) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn1) + (a2 * acc1);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ float32_t Xn2, Xn3, Xn4; /* Input State variables */
+ float32_t acc2, acc3, acc4; /* accumulator */
+
+
+ float32_t p0, p1, p2, p3, p4, A1;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1 = pIn[0];
+ Xn2 = pIn[1];
+ Xn3 = pIn[2];
+ Xn4 = pIn[3];
+ pIn += 4;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p0 = b0 * Xn2;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn2;
+ acc2 = p0 + d1;
+ p0 = b0 * Xn3;
+ p3 = a1 * acc2;
+ p2 = b2 * Xn2;
+ A1 = p1 + p3;
+ p4 = a2 * acc2;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn3;
+ acc3 = p0 + d1;
+ p0 = b0 * Xn4;
+ p3 = a1 * acc3;
+ p2 = b2 * Xn3;
+ A1 = p1 + p3;
+ p4 = a2 * acc3;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ acc4 = p0 + d1;
+ p1 = b1 * Xn4;
+ p3 = a1 * acc4;
+ p2 = b2 * Xn4;
+ A1 = p1 + p3;
+ p4 = a2 * acc4;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ pOut[0] = acc1;
+ pOut[1] = acc2;
+ pOut[2] = acc3;
+ pOut[3] = acc4;
+ pOut += 4;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3u;
+ while(sample > 0u) {
+ Xn1 = *pIn++;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ *pOut++ = acc1;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
@@ -0,0 +1,603 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_f64.c
+*
+* Description: Processing function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes blockSize samples through the filter.
+* pSrc points to the array of input data and
+* pDst points to the array of output data.
+* Both arrays contain blockSize values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+*
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+*
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+*
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+*
+* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* numStages refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with numStages=4 second order stages.
+* A 9th order filter would be realized with numStages=5 second order stages with the
+* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+*
+* \par
+* pState points to the state variable array.
+* Each Biquad stage has 2 state variables d1 and d2.
+* The state variables are arranged in the pState array as:
+*
+* {d11, d12, d21, d22, ...}
+*
+* where d1x refers to the state variables for the first Biquad and
+* d2x refers to the state variables for the second Biquad.
+* The state array has a total length of 2*numStages values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+*
+* arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+*
+* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
+* pCoeffs is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f64(
+const arm_biquad_cascade_df2T_instance_f64 * S,
+float64_t * pSrc,
+float64_t * pDst,
+uint32_t blockSize)
+{
+
+ float64_t *pIn = pSrc; /* source pointer */
+ float64_t *pOut = pDst; /* destination pointer */
+ float64_t *pState = S->pState; /* State pointer */
+ float64_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float64_t acc1; /* accumulator */
+ float64_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float64_t Xn1; /* temporary input */
+ float64_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#if defined(ARM_MATH_CM7)
+
+ float64_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8; /* Input State variables */
+ float64_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
+ float64_t acc2, acc3, acc4, acc5, acc6, acc7; /* Simulates the accumulator */
+ float64_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ /* Apply loop unrolling and compute 16 output values simultaneously. */
+ sample = blockSize >> 4u;
+ a2 = pCoeffs[4];
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ pCoeffs += 5u;
+
+
+ /* First part of the processing with loop unrolling. Compute 16 outputs at a time.
+ ** a second loop below computes the remaining 1 to 15 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the first 2 inputs. 2 cycles */
+ Xn1 = pIn[0 ];
+ Xn2 = pIn[1 ];
+
+ /* Sample 1. 5 cycles */
+ Xn3 = pIn[2 ];
+ acc1 = b0 * Xn1 + d1;
+
+ Xn4 = pIn[3 ];
+ d1 = b1 * Xn1 + d2;
+
+ Xn5 = pIn[4 ];
+ d2 = b2 * Xn1;
+
+ Xn6 = pIn[5 ];
+ d1 += a1 * acc1;
+
+ Xn7 = pIn[6 ];
+ d2 += a2 * acc1;
+
+ /* Sample 2. 5 cycles */
+ Xn8 = pIn[7 ];
+ acc2 = b0 * Xn2 + d1;
+
+ Xn9 = pIn[8 ];
+ d1 = b1 * Xn2 + d2;
+
+ Xn10 = pIn[9 ];
+ d2 = b2 * Xn2;
+
+ Xn11 = pIn[10];
+ d1 += a1 * acc2;
+
+ Xn12 = pIn[11];
+ d2 += a2 * acc2;
+
+ /* Sample 3. 5 cycles */
+ Xn13 = pIn[12];
+ acc3 = b0 * Xn3 + d1;
+
+ Xn14 = pIn[13];
+ d1 = b1 * Xn3 + d2;
+
+ Xn15 = pIn[14];
+ d2 = b2 * Xn3;
+
+ Xn16 = pIn[15];
+ d1 += a1 * acc3;
+
+ pIn += 16;
+ d2 += a2 * acc3;
+
+ /* Sample 4. 5 cycles */
+ acc4 = b0 * Xn4 + d1;
+ d1 = b1 * Xn4 + d2;
+ d2 = b2 * Xn4;
+ d1 += a1 * acc4;
+ d2 += a2 * acc4;
+
+ /* Sample 5. 5 cycles */
+ acc5 = b0 * Xn5 + d1;
+ d1 = b1 * Xn5 + d2;
+ d2 = b2 * Xn5;
+ d1 += a1 * acc5;
+ d2 += a2 * acc5;
+
+ /* Sample 6. 5 cycles */
+ acc6 = b0 * Xn6 + d1;
+ d1 = b1 * Xn6 + d2;
+ d2 = b2 * Xn6;
+ d1 += a1 * acc6;
+ d2 += a2 * acc6;
+
+ /* Sample 7. 5 cycles */
+ acc7 = b0 * Xn7 + d1;
+ d1 = b1 * Xn7 + d2;
+ d2 = b2 * Xn7;
+ d1 += a1 * acc7;
+ d2 += a2 * acc7;
+
+ /* Sample 8. 5 cycles */
+ acc8 = b0 * Xn8 + d1;
+ d1 = b1 * Xn8 + d2;
+ d2 = b2 * Xn8;
+ d1 += a1 * acc8;
+ d2 += a2 * acc8;
+
+ /* Sample 9. 5 cycles */
+ acc9 = b0 * Xn9 + d1;
+ d1 = b1 * Xn9 + d2;
+ d2 = b2 * Xn9;
+ d1 += a1 * acc9;
+ d2 += a2 * acc9;
+
+ /* Sample 10. 5 cycles */
+ acc10 = b0 * Xn10 + d1;
+ d1 = b1 * Xn10 + d2;
+ d2 = b2 * Xn10;
+ d1 += a1 * acc10;
+ d2 += a2 * acc10;
+
+ /* Sample 11. 5 cycles */
+ acc11 = b0 * Xn11 + d1;
+ d1 = b1 * Xn11 + d2;
+ d2 = b2 * Xn11;
+ d1 += a1 * acc11;
+ d2 += a2 * acc11;
+
+ /* Sample 12. 5 cycles */
+ acc12 = b0 * Xn12 + d1;
+ d1 = b1 * Xn12 + d2;
+ d2 = b2 * Xn12;
+ d1 += a1 * acc12;
+ d2 += a2 * acc12;
+
+ /* Sample 13. 5 cycles */
+ acc13 = b0 * Xn13 + d1;
+ d1 = b1 * Xn13 + d2;
+ d2 = b2 * Xn13;
+
+ pOut[0 ] = acc1 ;
+ d1 += a1 * acc13;
+
+ pOut[1 ] = acc2 ;
+ d2 += a2 * acc13;
+
+ /* Sample 14. 5 cycles */
+ pOut[2 ] = acc3 ;
+ acc14 = b0 * Xn14 + d1;
+
+ pOut[3 ] = acc4 ;
+ d1 = b1 * Xn14 + d2;
+
+ pOut[4 ] = acc5 ;
+ d2 = b2 * Xn14;
+
+ pOut[5 ] = acc6 ;
+ d1 += a1 * acc14;
+
+ pOut[6 ] = acc7 ;
+ d2 += a2 * acc14;
+
+ /* Sample 15. 5 cycles */
+ pOut[7 ] = acc8 ;
+ pOut[8 ] = acc9 ;
+ acc15 = b0 * Xn15 + d1;
+
+ pOut[9 ] = acc10;
+ d1 = b1 * Xn15 + d2;
+
+ pOut[10] = acc11;
+ d2 = b2 * Xn15;
+
+ pOut[11] = acc12;
+ d1 += a1 * acc15;
+
+ pOut[12] = acc13;
+ d2 += a2 * acc15;
+
+ /* Sample 16. 5 cycles */
+ pOut[13] = acc14;
+ acc16 = b0 * Xn16 + d1;
+
+ pOut[14] = acc15;
+ d1 = b1 * Xn16 + d2;
+
+ pOut[15] = acc16;
+ d2 = b2 * Xn16;
+
+ sample--;
+ d1 += a1 * acc16;
+
+ pOut += 16;
+ d2 += a2 * acc16;
+ }
+
+ sample = blockSize & 0xFu;
+ while(sample > 0u) {
+ Xn1 = *pIn;
+ acc1 = b0 * Xn1 + d1;
+
+ pIn++;
+ d1 = b1 * Xn1 + d2;
+
+ *pOut = acc1;
+ d2 = b2 * Xn1;
+
+ pOut++;
+ d1 += a1 * acc1;
+
+ sample--;
+ d2 += a2 * acc1;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1;
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ pState[1] = d2;
+ /* decrement the loop counter */
+ stage--;
+
+ pState += 2u;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ } while(stage > 0u);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn1 = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1 = (b0 * Xn1) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn1) + (a2 * acc1);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ float64_t Xn2, Xn3, Xn4; /* Input State variables */
+ float64_t acc2, acc3, acc4; /* accumulator */
+
+
+ float64_t p0, p1, p2, p3, p4, A1;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1 = pIn[0];
+ Xn2 = pIn[1];
+ Xn3 = pIn[2];
+ Xn4 = pIn[3];
+ pIn += 4;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p0 = b0 * Xn2;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn2;
+ acc2 = p0 + d1;
+ p0 = b0 * Xn3;
+ p3 = a1 * acc2;
+ p2 = b2 * Xn2;
+ A1 = p1 + p3;
+ p4 = a2 * acc2;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn3;
+ acc3 = p0 + d1;
+ p0 = b0 * Xn4;
+ p3 = a1 * acc3;
+ p2 = b2 * Xn3;
+ A1 = p1 + p3;
+ p4 = a2 * acc3;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ acc4 = p0 + d1;
+ p1 = b1 * Xn4;
+ p3 = a1 * acc4;
+ p2 = b2 * Xn4;
+ A1 = p1 + p3;
+ p4 = a2 * acc4;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ pOut[0] = acc1;
+ pOut[1] = acc2;
+ pOut[2] = acc3;
+ pOut[3] = acc4;
+ pOut += 4;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3u;
+ while(sample > 0u) {
+ Xn1 = *pIn++;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ *pOut++ = acc1;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_init_f32.c
+*
+* Description: Initialization function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * Coefficient and State Ordering:
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ *
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ *
+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on. The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 2 state variables d1, and d2.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of 2*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 2 * numStages */
+ memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_init_f64.c
+*
+* Description: Initialization function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * Coefficient and State Ordering:
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ *
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ *
+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on. The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 2 state variables d1, and d2.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of 2*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 2 * numStages */
+ memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float64_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
@@ -0,0 +1,683 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_stereo_df2T_f32.c
+*
+* Description: Processing function for the floating-point transposed
+* direct form II Biquad cascade filter. 2 channels
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes blockSize samples through the filter.
+* pSrc points to the array of input data and
+* pDst points to the array of output data.
+* Both arrays contain blockSize values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+*
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+*
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+*
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+*
+* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* numStages refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with numStages=4 second order stages.
+* A 9th order filter would be realized with numStages=5 second order stages with the
+* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+*
+* \par
+* pState points to the state variable array.
+* Each Biquad stage has 2 state variables d1 and d2.
+* The state variables are arranged in the pState array as:
+*
+* {d11, d12, d21, d22, ...}
+*
+* where d1x refers to the state variables for the first Biquad and
+* d2x refers to the state variables for the second Biquad.
+* The state array has a total length of 2*numStages values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+*
+* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+*
+* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.
+* pCoeffs is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_stereo_df2T_f32(
+const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc1a, acc1b; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1a, Xn1b; /* temporary input */
+ float32_t d1a, d2a, d1b, d2b; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#if defined(ARM_MATH_CM7)
+
+ float32_t Xn2a, Xn3a, Xn4a, Xn5a, Xn6a, Xn7a, Xn8a; /* Input State variables */
+ float32_t Xn2b, Xn3b, Xn4b, Xn5b, Xn6b, Xn7b, Xn8b; /* Input State variables */
+ float32_t acc2a, acc3a, acc4a, acc5a, acc6a, acc7a, acc8a; /* Simulates the accumulator */
+ float32_t acc2b, acc3b, acc4b, acc5b, acc6b, acc7b, acc8b; /* Simulates the accumulator */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ /* Apply loop unrolling and compute 8 output values simultaneously. */
+ sample = blockSize >> 3u;
+ a2 = pCoeffs[4];
+
+ /*Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+ pCoeffs += 5u;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the first 2 inputs. 2 cycles */
+ Xn1a = pIn[0 ];
+ Xn1b = pIn[1 ];
+
+ /* Sample 1. 5 cycles */
+ Xn2a = pIn[2 ];
+ acc1a = b0 * Xn1a + d1a;
+
+ Xn2b = pIn[3 ];
+ d1a = b1 * Xn1a + d2a;
+
+ Xn3a = pIn[4 ];
+ d2a = b2 * Xn1a;
+
+ Xn3b = pIn[5 ];
+ d1a += a1 * acc1a;
+
+ Xn4a = pIn[6 ];
+ d2a += a2 * acc1a;
+
+ /* Sample 2. 5 cycles */
+ Xn4b = pIn[7 ];
+ acc1b = b0 * Xn1b + d1b;
+
+ Xn5a = pIn[8 ];
+ d1b = b1 * Xn1b + d2b;
+
+ Xn5b = pIn[9 ];
+ d2b = b2 * Xn1b;
+
+ Xn6a = pIn[10];
+ d1b += a1 * acc1b;
+
+ Xn6b = pIn[11];
+ d2b += a2 * acc1b;
+
+ /* Sample 3. 5 cycles */
+ Xn7a = pIn[12];
+ acc2a = b0 * Xn2a + d1a;
+
+ Xn7b = pIn[13];
+ d1a = b1 * Xn2a + d2a;
+
+ Xn8a = pIn[14];
+ d2a = b2 * Xn2a;
+
+ Xn8b = pIn[15];
+ d1a += a1 * acc2a;
+
+ pIn += 16;
+ d2a += a2 * acc2a;
+
+ /* Sample 4. 5 cycles */
+ acc2b = b0 * Xn2b + d1b;
+ d1b = b1 * Xn2b + d2b;
+ d2b = b2 * Xn2b;
+ d1b += a1 * acc2b;
+ d2b += a2 * acc2b;
+
+ /* Sample 5. 5 cycles */
+ acc3a = b0 * Xn3a + d1a;
+ d1a = b1 * Xn3a + d2a;
+ d2a = b2 * Xn3a;
+ d1a += a1 * acc3a;
+ d2a += a2 * acc3a;
+
+ /* Sample 6. 5 cycles */
+ acc3b = b0 * Xn3b + d1b;
+ d1b = b1 * Xn3b + d2b;
+ d2b = b2 * Xn3b;
+ d1b += a1 * acc3b;
+ d2b += a2 * acc3b;
+
+ /* Sample 7. 5 cycles */
+ acc4a = b0 * Xn4a + d1a;
+ d1a = b1 * Xn4a + d2a;
+ d2a = b2 * Xn4a;
+ d1a += a1 * acc4a;
+ d2a += a2 * acc4a;
+
+ /* Sample 8. 5 cycles */
+ acc4b = b0 * Xn4b + d1b;
+ d1b = b1 * Xn4b + d2b;
+ d2b = b2 * Xn4b;
+ d1b += a1 * acc4b;
+ d2b += a2 * acc4b;
+
+ /* Sample 9. 5 cycles */
+ acc5a = b0 * Xn5a + d1a;
+ d1a = b1 * Xn5a + d2a;
+ d2a = b2 * Xn5a;
+ d1a += a1 * acc5a;
+ d2a += a2 * acc5a;
+
+ /* Sample 10. 5 cycles */
+ acc5b = b0 * Xn5b + d1b;
+ d1b = b1 * Xn5b + d2b;
+ d2b = b2 * Xn5b;
+ d1b += a1 * acc5b;
+ d2b += a2 * acc5b;
+
+ /* Sample 11. 5 cycles */
+ acc6a = b0 * Xn6a + d1a;
+ d1a = b1 * Xn6a + d2a;
+ d2a = b2 * Xn6a;
+ d1a += a1 * acc6a;
+ d2a += a2 * acc6a;
+
+ /* Sample 12. 5 cycles */
+ acc6b = b0 * Xn6b + d1b;
+ d1b = b1 * Xn6b + d2b;
+ d2b = b2 * Xn6b;
+ d1b += a1 * acc6b;
+ d2b += a2 * acc6b;
+
+ /* Sample 13. 5 cycles */
+ acc7a = b0 * Xn7a + d1a;
+ d1a = b1 * Xn7a + d2a;
+
+ pOut[0 ] = acc1a ;
+ d2a = b2 * Xn7a;
+
+ pOut[1 ] = acc1b ;
+ d1a += a1 * acc7a;
+
+ pOut[2 ] = acc2a ;
+ d2a += a2 * acc7a;
+
+ /* Sample 14. 5 cycles */
+ pOut[3 ] = acc2b ;
+ acc7b = b0 * Xn7b + d1b;
+
+ pOut[4 ] = acc3a ;
+ d1b = b1 * Xn7b + d2b;
+
+ pOut[5 ] = acc3b ;
+ d2b = b2 * Xn7b;
+
+ pOut[6 ] = acc4a ;
+ d1b += a1 * acc7b;
+
+ pOut[7 ] = acc4b ;
+ d2b += a2 * acc7b;
+
+ /* Sample 15. 5 cycles */
+ pOut[8 ] = acc5a ;
+ acc8a = b0 * Xn8a + d1a;
+
+ pOut[9 ] = acc5b;
+ d1a = b1 * Xn8a + d2a;
+
+ pOut[10] = acc6a;
+ d2a = b2 * Xn8a;
+
+ pOut[11] = acc6b;
+ d1a += a1 * acc8a;
+
+ pOut[12] = acc7a;
+ d2a += a2 * acc8a;
+
+ /* Sample 16. 5 cycles */
+ pOut[13] = acc7b;
+ acc8b = b0 * Xn8b + d1b;
+
+ pOut[14] = acc8a;
+ d1b = b1 * Xn8b + d2b;
+
+ pOut[15] = acc8b;
+ d2b = b2 * Xn8b;
+
+ sample--;
+ d1b += a1 * acc8b;
+
+ pOut += 16;
+ d2b += a2 * acc8b;
+ }
+
+ sample = blockSize & 0x7u;
+ while(sample > 0u) {
+ /* Read the input */
+ Xn1a = *pIn++; //Channel a
+ Xn1b = *pIn++; //Channel b
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1a;
+ pState[1] = d2a;
+
+ pState[2] = d1b;
+ pState[3] = d2b;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+ /* decrement the loop counter */
+ stage--;
+
+ pState += 4u;
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ } while(stage > 0u);
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn1a = *pIn++; //Channel a
+ Xn1b = *pIn++; //Channel b
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1a;
+ *pState++ = d2a;
+ *pState++ = d1b;
+ *pState++ = d2b;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ float32_t Xn2a, Xn3a, Xn4a; /* Input State variables */
+ float32_t Xn2b, Xn3b, Xn4b; /* Input State variables */
+ float32_t acc2a, acc3a, acc4a; /* accumulator */
+ float32_t acc2b, acc3b, acc4b; /* accumulator */
+ float32_t p0a, p1a, p2a, p3a, p4a, A1a;
+ float32_t p0b, p1b, p2b, p3b, p4b, A1b;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1a = pIn[0];
+ Xn1b = pIn[1];
+ Xn2a = pIn[2];
+ Xn2b = pIn[3];
+ Xn3a = pIn[4];
+ Xn3b = pIn[5];
+ Xn4a = pIn[6];
+ Xn4b = pIn[7];
+ pIn += 8;
+
+ p0a = b0 * Xn1a;
+ p0b = b0 * Xn1b;
+ p1a = b1 * Xn1a;
+ p1b = b1 * Xn1b;
+ acc1a = p0a + d1a;
+ acc1b = p0b + d1b;
+ p0a = b0 * Xn2a;
+ p0b = b0 * Xn2b;
+ p3a = a1 * acc1a;
+ p3b = a1 * acc1b;
+ p2a = b2 * Xn1a;
+ p2b = b2 * Xn1b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc1a;
+ p4b = a2 * acc1b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ p1a = b1 * Xn2a;
+ p1b = b1 * Xn2b;
+ acc2a = p0a + d1a;
+ acc2b = p0b + d1b;
+ p0a = b0 * Xn3a;
+ p0b = b0 * Xn3b;
+ p3a = a1 * acc2a;
+ p3b = a1 * acc2b;
+ p2a = b2 * Xn2a;
+ p2b = b2 * Xn2b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc2a;
+ p4b = a2 * acc2b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ p1a = b1 * Xn3a;
+ p1b = b1 * Xn3b;
+ acc3a = p0a + d1a;
+ acc3b = p0b + d1b;
+ p0a = b0 * Xn4a;
+ p0b = b0 * Xn4b;
+ p3a = a1 * acc3a;
+ p3b = a1 * acc3b;
+ p2a = b2 * Xn3a;
+ p2b = b2 * Xn3b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc3a;
+ p4b = a2 * acc3b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ acc4a = p0a + d1a;
+ acc4b = p0b + d1b;
+ p1a = b1 * Xn4a;
+ p1b = b1 * Xn4b;
+ p3a = a1 * acc4a;
+ p3b = a1 * acc4b;
+ p2a = b2 * Xn4a;
+ p2b = b2 * Xn4b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc4a;
+ p4b = a2 * acc4b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ pOut[0] = acc1a;
+ pOut[1] = acc1b;
+ pOut[2] = acc2a;
+ pOut[3] = acc2b;
+ pOut[4] = acc3a;
+ pOut[5] = acc3b;
+ pOut[6] = acc4a;
+ pOut[7] = acc4b;
+ pOut += 8;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3u;
+ while(sample > 0u) {
+ Xn1a = *pIn++;
+ Xn1b = *pIn++;
+
+ p0a = b0 * Xn1a;
+ p0b = b0 * Xn1b;
+ p1a = b1 * Xn1a;
+ p1b = b1 * Xn1b;
+ acc1a = p0a + d1a;
+ acc1b = p0b + d1b;
+ p3a = a1 * acc1a;
+ p3b = a1 * acc1b;
+ p2a = b2 * Xn1a;
+ p2b = b2 * Xn1b;
+ A1a = p1a + p3a;
+ A1b = p1b + p3b;
+ p4a = a2 * acc1a;
+ p4b = a2 * acc1b;
+ d1a = A1a + d2a;
+ d1b = A1b + d2b;
+ d2a = p2a + p4a;
+ d2b = p2b + p4b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1a;
+ *pState++ = d2a;
+ *pState++ = d1b;
+ *pState++ = d2b;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_stereo_df2T_init_f32.c
+*
+* Description: Initialization function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * Coefficient and State Ordering:
+ * \par
+ * The coefficients are stored in the array pCoeffs in the following order:
+ *
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ *
+ *
+ * \par
+ * where b1x and a1x are the coefficients for the first stage,
+ * b2x and a2x are the coefficients for the second stage,
+ * and so on. The pCoeffs array contains a total of 5*numStages values.
+ *
+ * \par
+ * The pState is a pointer to state array.
+ * Each Biquad stage has 2 state variables d1, and d2 for each channel.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of 2*numStages values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,647 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_f32.c
+*
+* Description: Convolution of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Conv Convolution
+ *
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.
+ *
+ * \par Algorithm
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.
+ * Then the convolution
+ *
+ *
+ * c[n] = a[n] * b[n]
+ *
+ *
+ * \par
+ * is defined as
+ * \image html ConvolutionEquation.gif
+ * \par
+ * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.
+ * pSrcA points to the first input vector of length srcALen and
+ * pSrcB points to the second input vector of length srcBLen.
+ * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.
+ *
+ * \par
+ * Conceptually, when two signals a[n] and b[n] are convolved,
+ * the signal b[n] slides over a[n].
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
+ *
+ * \par
+ * Note that convolution is a commutative operation:
+ *
+ *
+ * a[n] * b[n] = b[n] * a[n].
+ *
+ *
+ * \par
+ * This means that switching the A and B arguments to the convolution functions has no effect.
+ *
+ * Fixed-Point Behavior
+ *
+ * \par
+ * Convolution requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * Fast Versions
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * Opt Versions
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counters */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px + 3u);
+ px += 4u;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+ {
+ /* Initialize sum with zero to carry out MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,543 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_opt_q15.c
+*
+* Description: Fast Q15 Convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,1410 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_q15.c
+*
+* Description: Fast Q15 Convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+ q15_t a, b;
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,577 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_q31.c
+*
+* Description: Q31 Convolution (fast version).
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ *
+ * \par
+ * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,545 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_opt_q15.c
+*
+* Description: Convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ *
+ * \par
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,435 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_opt_q7.c
+*
+* Description: Convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ */
+
+void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,669 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_f32.c
+*
+* Description: Partial convolution of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup PartialConv Partial Convolution
+ *
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.
+ * Each function has two additional arguments.
+ * firstIndex specifies the starting index of the subset of output samples.
+ * numPoints is the number of output samples to compute.
+ * The function computes the output in the range
+ * [firstIndex, ..., firstIndex+numPoints-1].
+ * The output array pDst contains numPoints values.
+ *
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.
+ * Otherwise the functions return ARM_MATH_SUCCESS.
+ * \note Refer arm_conv_f32() for details on fixed point behavior.
+ *
+ *
+ * Fast Versions
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15 of partial convolution. Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * Opt Versions
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count = 0u, blkCnt, check;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = ((int32_t) check - blockSize3) -
+ (blockSize1 + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + firstIndex;
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc1;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations for inputs */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,768 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_opt_q15.c
+*
+* Description: Fast Q15 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status;
+
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2u);
+ y11 = *(pIn2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,1492 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_q15.c
+*
+* Description: Fast Q15 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+ q15_t a, b;
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = ((int32_t) check - blockSize3) -
+ (blockSize1 + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,611 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_q31.c
+*
+* Description: Fast Q31 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ */
+
+arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,765 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_opt_q15.c
+*
+* Description: Partial convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+ acc2 += (q63_t) x20 *y10;
+ acc2 += (q63_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q63_t) x11 *y10;
+ acc1 += (q63_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x21 *y10;
+ acc3 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2u);
+ y11 = *(pIn2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x20 *y10;
+ acc0 += (q63_t) x21 *y11;
+ acc2 += (q63_t) x10 *y10;
+ acc2 += (q63_t) x11 *y11;
+ acc1 += (q63_t) x21 *y10;
+ acc1 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x11 *y10;
+ acc3 += (q63_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,803 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_opt_q7.c
+*
+* Description: Partial convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ *
+ */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pScr2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+
+ }
+
+ return (status);
+
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q15_t x10, x11, x20, x21; /* Temporary input variables */
+ q15_t y10, y11; /* Temporary input variables */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y10 = *pScr2;
+ y11 = *(pScr2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pScr2 + 2u);
+ y11 = *(pScr2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+
+ pScr1 += 4u;
+ pScr2 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pScr2++;
+ y11 = *pScr2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ return (status);
+
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,786 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q15.c
+*
+* Description: Partial convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+
+arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary input variables */
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,607 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q31.c
+*
+* Description: Partial convolution of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum, acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blkCnt */
+
+ blkCnt = blockSize2 / 3;
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1u);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += (q63_t) x1 *c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += (q63_t) x2 *c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += (q63_t) x0 *c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2u);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += (q63_t) x2 *c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += (q63_t) x0 *c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += (q63_t) x1 *c0;
+
+
+ px += 3u;
+
+ py -= 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,741 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q7.c
+*
+* Description: Partial convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function.
+ *
+ */
+
+arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2;
+ q15_t in1, in2;
+ q7_t x0, x1, x2, x3, c0, c1;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status;
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ px = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ px = pIn1;
+ }
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q31_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q31_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q31_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q31_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB; /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,734 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q15.c
+*
+* Description: Convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ blockSize3 = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* input pointer */
+ q15_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,565 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q31.c
+*
+* Description: Convolution of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum; /* Accumulator */
+ q63_t acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (q31_t *) pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = (q31_t *) pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll by 3 */
+ blkCnt = blockSize2 / 3;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[3] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1u);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += ((q63_t) x1 * c0);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x2 * c0);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2u);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += ((q63_t) x2 * c0);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x0 * c0);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x1 * c0);
+
+ /* update scratch pointers */
+ px += 3u;
+ py -= 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* input pointer */
+ q31_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,690 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q7.c
+*
+* Description: Convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function arm_conv_opt_q7() for a faster implementation of this function.
+ *
+ */
+
+void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2; /* Temporary input variables */
+ q15_t in1, in2; /* Temporary input variables */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = (srcALen - srcBLen) + 1u;
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* input pointer */
+ q7_t *pIn2 = pSrcB; /* coefficient pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,739 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_f32.c
+*
+* Description: Correlation of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Corr Correlation
+ *
+ * Correlation is a mathematical operation that is similar to convolution.
+ * As with convolution, correlation uses two signals to produce a third signal.
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.
+ * Correlation is commonly used to measure the similarity between two signals.
+ * It has applications in pattern recognition, cryptanalysis, and searching.
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.
+ * Fast versions of the Q15 and Q31 functions are also provided.
+ *
+ * \par Algorithm
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.
+ * The convolution of the two signals is denoted by
+ *
+ * c[n] = a[n] * b[n]
+ *
+ * In correlation, one of the signals is flipped in time
+ *
+ * c[n] = a[n] * b[-n]
+ *
+ *
+ * \par
+ * and this is mathematically defined as
+ * \image html CorrelateEquation.gif
+ * \par
+ * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.
+ * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).
+ * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.
+ *
+ * Note
+ * \par
+ * The pDst should be initialized to all zeros before being used.
+ *
+ * Fixed-Point Behavior
+ * \par
+ * Correlation requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * Fast Versions
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * Opt Versions
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ float32_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counters */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we assume zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding has to be done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ //while(j > 0u)
+ //{
+ // /* Zero is stored in the destination buffer */
+ // *pOut++ = 0.0f;
+
+ // /* Decrement the loop counter */
+ // j--;
+ //}
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum += *px++ * *py++;
+ /* x[1] * y[srcBLen - 3] */
+ sum += *px++ * *py++;
+ /* x[2] * y[srcBLen - 2] */
+ sum += *px++ * *py++;
+ /* x[3] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py++);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 += x0 * c0;
+ /* acc1 += x[1] * y[0] */
+ acc1 += x1 * c0;
+ /* acc2 += x[2] * y[0] */
+ acc2 += x2 * c0;
+ /* acc3 += x[3] * y[0] */
+ acc3 += x3 * c0;
+
+ /* Read y[1] sample */
+ c0 = *(py++);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[1] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[1] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[1] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[1] */
+ acc3 += x0 * c0;
+
+ /* Read y[2] sample */
+ c0 = *(py++);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[2] */
+ acc3 += x1 * c0;
+
+ /* Read y[3] sample */
+ c0 = *(py++);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[3] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[3] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[3] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[4] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[4] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[4] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = acc0;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = acc1;
+ pOut += inc;
+
+ *pOut = acc2;
+ pOut += inc;
+
+ *pOut = acc3;
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we assume zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = sum;
+ else
+ *pDst++ = sum;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_opt_q15.c
+*
+* Description: Fast Q15 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t x1, x2, x3; /* temporary variables for holding input and coefficient values */
+ uint32_t j, blkCnt, outBlockSize; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ uint32_t tapCnt;
+ q31_t y1, y2;
+ q15_t *pScr; /* Intermediate pointers */
+ q15_t *pOut = pDst; /* output pointer */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ pScr = pScratch;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr, srcALen);
+
+ /* Update pointers */
+ pScr += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = srcALen % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = (srcBLen - 1u) % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read four samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr)++;
+
+ /* Read next four samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x1 = _SIMD32_OFFSET(pScr);
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr;
+ b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr + 2);
+ b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+
+ pScr += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2);
+ acc1 += (*pScr++ * *pIn2);
+ acc2 += (*pScr++ * *pIn2);
+ acc3 += (*pScr++ * *pIn2++);
+
+ pScr -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15u, 16));
+ pOut += inc;
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr++ * *pIn2++);
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1u;
+
+ }
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,1319 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_q15.c
+*
+* Description: Fast Q15 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px + 3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py)++;
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px + 2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ q15_t a, b;
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3], x[4] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ a = *(py + 2);
+ b = *(py + 3);
+
+ py += 4u;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px + 1);
+
+ px++;;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ py += 2u;
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,612 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_q31.c
+*
+* Description: Fast Q31 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ *
+ * \par
+ * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[1] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[3] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py++);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[1] * y[0] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[2] * y[0] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[3] * y[0] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[1] sample */
+ c0 = *(py++);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[1] * y[1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[2] sample */
+ c0 = *(py++);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[3] sample */
+ c0 = *(py++);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (acc0 << 1);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q31_t) (acc1 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc2 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc3 << 1);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
@@ -0,0 +1,513 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_opt_q15.c
+*
+* Description: Correlation of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+
+void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t x1, x2, x3; /* temporary variables for holding input1 and input2 values */
+ uint32_t j, blkCnt, outBlockSize; /* loop counter */
+ int32_t inc = 1; /* output pointer increment */
+ uint32_t tapCnt;
+ q31_t y1, y2;
+ q15_t *pScr; /* Intermediate pointers */
+ q15_t *pOut = pDst; /* output pointer */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ pScr = pScratch;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr, srcALen);
+
+ /* Update pointers */
+ //pIn1 += srcALen;
+ pScr += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = srcALen % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = (srcBLen - 1u) % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read four samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr)++;
+
+ /* Read next four samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ x1 = _SIMD32_OFFSET(pScr);
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ a = *pScr;
+ b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ a = *(pScr + 2);
+ b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+
+ pScr += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2);
+ acc1 += (*pScr++ * *pIn2);
+ acc2 += (*pScr++ * *pIn2);
+ acc3 += (*pScr++ * *pIn2++);
+
+ pScr -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15u, 16));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr++ * *pIn2++);
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1u;
+
+ }
+
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_opt_q7.c
+*
+* Description: Correlation of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ *
+ */
+
+
+
+void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q7_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t j, k = 0u, blkCnt; /* loop counter */
+ int32_t inc = 1; /* output pointer increment */
+ uint32_t outBlockSize; /* loop counter */
+ q15_t x4; /* Temporary input variable */
+ uint32_t tapCnt; /* loop counter */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+
+ /* Copy (srcBLen) samples in scratch buffer */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for second sequence */
+ py = pScratch2;
+
+ /* Initialization of pScr2 pointer */
+ pScr2 = pScratch2;
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,719 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q15.c
+*
+* Description: Correlation of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLALD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLALD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLALD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px + 3);
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLALD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x3, c0, acc2);
+ acc3 = __SMLALD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py)++;
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x3, c0, acc2);
+ acc3 = __SMLALD(x2, c0, acc3);
+
+ c0 = (*py);
+
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px + 2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+ pOut += inc;
+
+ /* Increment the count by 4 as 4 output values are computed */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment count by 1, as one output value is computed */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+ else
+ *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+
+#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,665 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q31.c
+*
+* Description: Correlation of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1; /* Intermediate pointers */
+ q63_t sum, acc0, acc1, acc2; /* Accumulators */
+ q31_t x0, x1, x2, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[1] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[2] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[3] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll by 3 */
+ blkCnt = blockSize2 / 3;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[1] * y[0] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[2] * y[0] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read y[1] sample */
+ c0 = *(py + 1u);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[1] * y[1] */
+ acc0 += ((q63_t) x1 * c0);
+ /* acc1 += x[2] * y[1] */
+ acc1 += ((q63_t) x2 * c0);
+ /* acc2 += x[3] * y[1] */
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read y[2] sample */
+ c0 = *(py + 2u);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 += ((q63_t) x2 * c0);
+ /* acc1 += x[3] * y[2] */
+ acc1 += ((q63_t) x0 * c0);
+ /* acc2 += x[4] * y[2] */
+ acc2 += ((q63_t) x1 * c0);
+
+ /* update scratch pointers */
+ px += 3u;
+ py += 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[5] * y[4] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[6] * y[4] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (acc0 >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q31_t) (acc1 >> 31);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc2 >> 31);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using correlation but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate correlation for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to correlation equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q31_t) (sum >> 31u);
+ else
+ *pDst++ = (q31_t) (sum >> 31u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,790 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q7.c
+*
+* Description: Correlation of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function arm_correlate_opt_q7() for a faster implementation of this function.
+ *
+ */
+
+void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t input1, input2; /* temporary variables */
+ q15_t in1, in2; /* temporary variables */
+ q7_t x0, x1, x2, x3, c0, c1; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1;
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 4] , y[srcBLen - 3] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 4] */
+ /* x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 2] , y[srcBLen - 1] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 2] */
+ /* x[3] * y[srcBLen - 1] */
+ sum = __SMLAD(input1, input2, sum);
+
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q31_t) ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *py++;
+ /* Read y[1] sample */
+ c1 = *py++;
+
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[0] and y[1] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[2] sample */
+ c0 = *py++;
+ /* Read y[3] sample */
+ c1 = *py++;
+
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[2] and y[3] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *py++;
+
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[4] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[4] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[4] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+ pOut += inc;
+
+ count += 4u;
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[0] , y[1] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[2] , y[3] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+ else
+ *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,524 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_f32.c
+*
+* Description: FIR decimation for floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator
+ *
+ * These functions combine an FIR filter together with a decimator.
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"
+ * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized
+ * cutoff frequency of 1/M in order to prevent aliasing distortion.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.
+ * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the
+ * samples output by the decimator are computed.
+ * The functions operate on blocks of input and output data.
+ * pSrc points to an array of blockSize input values and
+ * pDst points to an array of blockSize/M output values.
+ * In order to have an integer number of output samples blockSize
+ * must always be a multiple of the decimation factor M.
+ *
+ * The library provides separate functions for Q15, Q31 and floating-point data types.
+ *
+ * \par Algorithm:
+ * The FIR portion of the algorithm uses the standard form filter:
+ *
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ *
+ * where, b[n] are the filter coefficients.
+ * \par
+ * The pCoeffs points to a coefficient array of size numTaps.
+ * Coefficients are stored in time reversed order.
+ * \par
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to a state array of size numTaps + blockSize - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ *
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ *
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ *
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+ *
+ * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;
+ * pCoeffs is the address of the coefficient buffer;
+ * pState is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t sum0; /* Accumulator */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t blkCntN4;
+ float32_t *px0, *px1, *px2, *px3;
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 4;
+ blkCntN4 = outBlockSize - (4 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy 4 * decimation factor number of new input samples into the state buffer */
+ i = 4 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+ px2 = pState + 2 * S->M;
+ px3 = pState + 3 * S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample for acc0 */
+ x0 = *(px0++);
+ /* Read x[n-numTaps-1] sample for acc1 */
+ x1 = *(px1++);
+ /* Read x[n-numTaps-1] sample for acc2 */
+ x2 = *(px2++);
+ /* Read x[n-numTaps-1] sample for acc3 */
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch state variables for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + 4 * S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN4 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ i = (numTaps - 1u);
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,598 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_fast_q15.c
+*
+* Description: Fast Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c1 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c1, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,351 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_fast_q31.c
+*
+* Description: Fast Q31 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.
+ */
+
+void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t *px; /* Temporary pointers for state buffer */
+ q31_t *pb; /* Temporary pointers for coefficient buffer */
+ q31_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+ uint32_t blkCntN2;
+ q31_t x1;
+ q31_t acc0, acc1;
+ q31_t *px0, *px1;
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+
+ blkCnt = outBlockSize / 2;
+ blkCntN2 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+ px1 = pState + S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb);
+
+ /* Read x[n-numTaps-1] for sample 0 sample 1 */
+ x0 = *(px0);
+ x1 = *(px1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb + 1u);
+
+ /* Read x[n-numTaps-2] for sample 0 sample 1 */
+ x0 = *(px0 + 1u);
+ x1 = *(px1 + 1u);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb + 2u);
+
+ /* Read x[n-numTaps-3] for sample 0 sample 1 */
+ x0 = *(px0 + 2u);
+ x1 = *(px1 + 2u);
+ pb += 4u;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb - 1u);
+
+ /* Read x[n-numTaps-4] for sample 0 sample 1 */
+ x0 = *(px0 + 3u);
+ x1 = *(px1 + 3u);
+
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* update state pointers */
+ px0 += 4u;
+ px1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px0++);
+ x1 = *(px1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN2 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 << 1);
+
+ /* Decrement the loop counter */
+ blkCntN2--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,117 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_f32.c
+*
+* Description: Floating-point FIR Decimator initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().
+ * M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation Factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_q15.c
+*
+* Description: Initialization function for the Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples
+ * to the call arm_fir_decimate_q15().
+ * M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size of buffer is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_q31.c
+*
+* Description: Initialization function for Q31 FIR Decimation filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().
+ * M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,696 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_q15.c
+*
+* Description: Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c1 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c1, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else
+
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q31_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /*Store filter output , smlad will return the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+}
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_q31.c
+*
+* Description: Q31 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ *
+ * \par
+ * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t *px; /* Temporary pointers for state buffer */
+ q31_t *pb; /* Temporary pointers for coefficient buffer */
+ q63_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,997 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_f32.c
+*
+* Description: Floating-point FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup FIR Finite Impulse Response (FIR) Filters
+*
+* This set of functions implements Finite Impulse Response (FIR) filters
+* for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided.
+* The functions operate on blocks of input and output data and each call to the function processes
+* blockSize samples through the filter. pSrc and
+* pDst points to input and output arrays containing blockSize values.
+*
+* \par Algorithm:
+* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.
+* Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].
+*
+* y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+*
+* \par
+* \image html FIR.gif "Finite Impulse Response filter"
+* \par
+* pCoeffs points to a coefficient array of size numTaps.
+* Coefficients are stored in time reversed order.
+* \par
+*
+* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+*
+* \par
+* pState points to a state array of size numTaps + blockSize - 1.
+* Samples in the state buffer are stored in the following order.
+* \par
+*
+* {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+*
+* \par
+* Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.
+* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,
+* to be avoided and yields a significant speed improvement.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+* There are separate instance structure declarations for each of the 4 supported data types.
+*
+* \par Initialization Functions
+* There is also an associated initialization function for each data type.
+* The initialization function performs the following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numTaps, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* The code below statically initializes each of the 4 different data type filter instance structures
+*
+*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q7 S = {numTaps, pState, pCoeffs};
+*
+*
+* where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;
+* pCoeffs is the address of the coefficient buffer.
+*
+* \par Fixed-Point Behavior
+* Care must be taken when using the fixed-point versions of the FIR filter functions.
+* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+* Refer to the function specific documentation below for usage guidelines.
+*/
+
+/**
+* @addtogroup FIR
+* @{
+*/
+
+/**
+*
+* @param[in] *S points to an instance of the floating-point FIR filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data.
+* @param[in] blockSize number of samples to process per call.
+* @return none.
+*
+*/
+
+#if defined(ARM_MATH_CM7)
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */
+ float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 8 output values simultaneously.
+ * The variables acc0 ... acc7 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 3;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+ acc4 = 0.0f;
+ acc5 = 0.0f;
+ acc6 = 0.0f;
+ acc7 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* This is separated from the others to avoid
+ * a call to __aeabi_memmove which would be slower
+ */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Read the first seven samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+ x3 = *px++;
+ x4 = *px++;
+ x5 = *px++;
+ x6 = *px++;
+
+ /* Loop unrolling. Process 8 taps at a time. */
+ tapCnt = numTaps >> 3u;
+
+ /* Loop over the number of taps. Unroll by a factor of 8.
+ ** Repeat until we've computed numTaps-8 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x7 = *(px++);
+
+ /* acc0 += b[numTaps-1] * x[n-numTaps] */
+ acc0 += x0 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-2] */
+ acc2 += x2 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-3] */
+ acc3 += x3 * c0;
+
+ /* acc4 += b[numTaps-1] * x[n-numTaps-4] */
+ acc4 += x4 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-5] */
+ acc5 += x5 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-6] */
+ acc6 += x6 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-7] */
+ acc7 += x7 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x1 * c0;
+ acc1 += x2 * c0;
+ acc2 += x3 * c0;
+ acc3 += x4 * c0;
+ acc4 += x5 * c0;
+ acc5 += x6 * c0;
+ acc6 += x7 * c0;
+ acc7 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += x2 * c0;
+ acc1 += x3 * c0;
+ acc2 += x4 * c0;
+ acc3 += x5 * c0;
+ acc4 += x6 * c0;
+ acc5 += x7 * c0;
+ acc6 += x0 * c0;
+ acc7 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += x3 * c0;
+ acc1 += x4 * c0;
+ acc2 += x5 * c0;
+ acc3 += x6 * c0;
+ acc4 += x7 * c0;
+ acc5 += x0 * c0;
+ acc6 += x1 * c0;
+ acc7 += x2 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x3 = *(px++);
+ /* Perform the multiply-accumulates */
+ acc0 += x4 * c0;
+ acc1 += x5 * c0;
+ acc2 += x6 * c0;
+ acc3 += x7 * c0;
+ acc4 += x0 * c0;
+ acc5 += x1 * c0;
+ acc6 += x2 * c0;
+ acc7 += x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x4 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += x5 * c0;
+ acc1 += x6 * c0;
+ acc2 += x7 * c0;
+ acc3 += x0 * c0;
+ acc4 += x1 * c0;
+ acc5 += x2 * c0;
+ acc6 += x3 * c0;
+ acc7 += x4 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x5 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += x6 * c0;
+ acc1 += x7 * c0;
+ acc2 += x0 * c0;
+ acc3 += x1 * c0;
+ acc4 += x2 * c0;
+ acc5 += x3 * c0;
+ acc6 += x4 * c0;
+ acc7 += x5 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x6 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += x7 * c0;
+ acc1 += x0 * c0;
+ acc2 += x1 * c0;
+ acc3 += x2 * c0;
+ acc4 += x3 * c0;
+ acc5 += x4 * c0;
+ acc6 += x5 * c0;
+ acc7 += x6 * c0;
+
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+ tapCnt = numTaps % 0x8u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x7 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+ acc4 += x4 * c0;
+ acc5 += x5 * c0;
+ acc6 += x6 * c0;
+ acc7 += x7 * c0;
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+ x3 = x4;
+ x4 = x5;
+ x5 = x6;
+ x6 = x7;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by 8 to process the next group of 8 samples */
+ pState = pState + 8;
+
+ /* The results in the 8 accumulators, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+ *pDst++ = acc4;
+ *pDst++ = acc5;
+ *pDst++ = acc6;
+ *pDst++ = acc7;
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x8u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += *px++ * *pb++;
+ i--;
+
+ } while(i > 0u);
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc0;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#elif defined(ARM_MATH_CM0_FAMILY)
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += *px++ * *pb++;
+ i--;
+
+ } while(i > 0u);
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = numTaps - 1u;
+
+ /* Copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#else
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */
+ float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+ float32_t p0,p1,p2,p3,p4,p5,p6,p7; /* Temporary product values */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 8 output values simultaneously.
+ * The variables acc0 ... acc7 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 3;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+ acc4 = 0.0f;
+ acc5 = 0.0f;
+ acc6 = 0.0f;
+ acc7 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* This is separated from the others to avoid
+ * a call to __aeabi_memmove which would be slower
+ */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Read the first seven samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+ x3 = *px++;
+ x4 = *px++;
+ x5 = *px++;
+ x6 = *px++;
+
+ /* Loop unrolling. Process 8 taps at a time. */
+ tapCnt = numTaps >> 3u;
+
+ /* Loop over the number of taps. Unroll by a factor of 8.
+ ** Repeat until we've computed numTaps-8 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x7 = *(px++);
+
+ /* acc0 += b[numTaps-1] * x[n-numTaps] */
+ p0 = x0 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-1] */
+ p1 = x1 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-2] */
+ p2 = x2 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-3] */
+ p3 = x3 * c0;
+
+ /* acc4 += b[numTaps-1] * x[n-numTaps-4] */
+ p4 = x4 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-5] */
+ p5 = x5 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-6] */
+ p6 = x6 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-7] */
+ p7 = x7 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+
+ /* Perform the multiply-accumulate */
+ p0 = x1 * c0;
+ p1 = x2 * c0;
+ p2 = x3 * c0;
+ p3 = x4 * c0;
+ p4 = x5 * c0;
+ p5 = x6 * c0;
+ p6 = x7 * c0;
+ p7 = x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x2 * c0;
+ p1 = x3 * c0;
+ p2 = x4 * c0;
+ p3 = x5 * c0;
+ p4 = x6 * c0;
+ p5 = x7 * c0;
+ p6 = x0 * c0;
+ p7 = x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x3 * c0;
+ p1 = x4 * c0;
+ p2 = x5 * c0;
+ p3 = x6 * c0;
+ p4 = x7 * c0;
+ p5 = x0 * c0;
+ p6 = x1 * c0;
+ p7 = x2 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x3 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x4 * c0;
+ p1 = x5 * c0;
+ p2 = x6 * c0;
+ p3 = x7 * c0;
+ p4 = x0 * c0;
+ p5 = x1 * c0;
+ p6 = x2 * c0;
+ p7 = x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x4 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x5 * c0;
+ p1 = x6 * c0;
+ p2 = x7 * c0;
+ p3 = x0 * c0;
+ p4 = x1 * c0;
+ p5 = x2 * c0;
+ p6 = x3 * c0;
+ p7 = x4 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x5 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x6 * c0;
+ p1 = x7 * c0;
+ p2 = x0 * c0;
+ p3 = x1 * c0;
+ p4 = x2 * c0;
+ p5 = x3 * c0;
+ p6 = x4 * c0;
+ p7 = x5 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x6 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x7 * c0;
+ p1 = x0 * c0;
+ p2 = x1 * c0;
+ p3 = x2 * c0;
+ p4 = x3 * c0;
+ p5 = x4 * c0;
+ p6 = x5 * c0;
+ p7 = x6 * c0;
+
+ tapCnt--;
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+ }
+
+ /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+ tapCnt = numTaps % 0x8u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x7 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ p0 = x0 * c0;
+ p1 = x1 * c0;
+ p2 = x2 * c0;
+ p3 = x3 * c0;
+ p4 = x4 * c0;
+ p5 = x5 * c0;
+ p6 = x6 * c0;
+ p7 = x7 * c0;
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+ x3 = x4;
+ x4 = x5;
+ x5 = x6;
+ x6 = x7;
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by 8 to process the next group of 8 samples */
+ pState = pState + 8;
+
+ /* The results in the 8 accumulators, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+ *pDst++ = acc4;
+ *pDst++ = acc5;
+ *pDst++ = acc6;
+ *pDst++ = acc7;
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x8u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += *px++ * *pb++;
+ i--;
+
+ } while(i > 0u);
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc0;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#endif
+
+/**
+* @} end of FIR group
+*/
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,345 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_fast_q15.c
+*
+* Description: Q15 Fast FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_init_q15() to initialize the filter structure.
+ */
+
+void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+ px = pState;
+
+ /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+ x2 = *__SIMD32(px)++;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* Read state x[n-N-6], x[n-N-7] with offset */
+ x2 = _SIMD32_OFFSET(px + 2u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Update state pointer for next state reading */
+ px += 4u;
+
+ /* Decrement tap count */
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+
+ /* Read last two coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read last state variables */
+ x0 = *__SIMD32(px);
+
+ /* Perform the multiply-accumulates */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* Perform the multiply-accumulates */
+ acc3 = __SMLADX(x1, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Use SIMD to hold states and coefficients */
+ px = pState;
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1u;
+
+ do
+ {
+
+ acc0 += (q31_t) * px++ * *pb++;
+ acc0 += (q31_t) * px++ * *pb++;
+
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_fast_q31.c
+*
+* Description: Processing function for the Q31 Fast FIR filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ *
+ * \par
+ * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ * Use the function arm_fir_init_q31() to initialize the filter structure.
+ */
+
+IAR_ONLY_LOW_OPTIMIZATION_ENTER
+void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, x1, x2, x3; /* Temporary variables to hold state */
+ q31_t c0; /* Temporary variable to hold coefficient value */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first three samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *pb;
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *px;
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb + 1u);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x1, c0);
+ multAcc_32x32_keep32_R(acc1, x2, c0);
+ multAcc_32x32_keep32_R(acc2, x3, c0);
+ multAcc_32x32_keep32_R(acc3, x0, c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb + 2u);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x2, c0);
+ multAcc_32x32_keep32_R(acc1, x3, c0);
+ multAcc_32x32_keep32_R(acc2, x0, c0);
+ multAcc_32x32_keep32_R(acc3, x1, c0);
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb + 3u);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px + 3u);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x3, c0);
+ multAcc_32x32_keep32_R(acc1, x0, c0);
+ multAcc_32x32_keep32_R(acc2, x1, c0);
+ multAcc_32x32_keep32_R(acc3, x2, c0);
+
+ /* update coefficient pointer */
+ pb += 4u;
+ px += 4u;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+ i = numTaps - (tapCnt * 4u);
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31
+ ** Then store the 4 outputs in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+ *pDst++ = (q31_t) (acc2 << 1);
+ *pDst++ = (q31_t) (acc3 << 1);
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+}
+IAR_ONLY_LOW_OPTIMIZATION_EXIT
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_f32.c
+*
+* Description: Floating-point FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().
+ */
+
+void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q15.c
+*
+* Description: Q15 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize is number of samples processed per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not greater than or equal to 4 and even.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * Note that numTaps must be even and greater than or equal to 4.
+ * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.
+ * For example, to implement a filter with numTaps=3 and coefficients
+ *
+ * {0.3, -0.8, 0.3}
+ *
+ * set numTaps=4 and use the coefficients:
+ *
+ * {0.3, -0.8, 0.3, 0}.
+ *
+ * Similarly, to implement a two point filter
+ *
+ * {0.3, -0.3}
+ *
+ * set numTaps=4 and use the coefficients:
+ *
+ * {0.3, -0.3, 0, 0}.
+ *
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15().
+ */
+
+arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* The Number of filter coefficients in the filter must be even and at least 4 */
+ if(numTaps & 0x1u)
+ {
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps ) */
+ memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q31.c
+*
+* Description: Q31 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().
+ */
+
+void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+ memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q7.c
+*
+* Description: Q7 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+/**
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().
+ */
+
+void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize)
+{
+
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,581 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_f32.c
+*
+* Description: FIR interpolation for floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator
+ *
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"
+ * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized
+ * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.
+ * The upsampler inserts L-1 zeros between each sample.
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.
+ * This leads to an efficient implementation without any wasted effort.
+ * The functions operate on blocks of input and output data.
+ * pSrc points to an array of blockSize input values and
+ * pDst points to an array of blockSize*L output values.
+ *
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ *
+ * \par Algorithm:
+ * The functions use a polyphase filter structure:
+ *
+ * y[n] = b[0] * x[n] + b[L] * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+ * y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+ * ...
+ * y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+ *
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.
+ * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.
+ * \par
+ * pCoeffs points to a coefficient array of size numTaps.
+ * numTaps must be a multiple of the interpolation factor L and this is checked by the
+ * initialization functions.
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length
+ * phaseLength=numTaps/L.
+ * Coefficients are stored in time reversed order.
+ * \par
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to a state array of size blockSize + phaseLength - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ *
+ * {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+ *
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ *
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+ *
+ * where L is the interpolation factor; phaseLength=numTaps/L is the
+ * length of each of the shorter FIR filters used internally,
+ * pCoeffs is the address of the coefficient buffer;
+ * pState is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ float32_t sum0; /* Accumulators */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+ uint32_t blkCntN4;
+ float32_t c1, c2, c3;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 4;
+ blkCntN4 = blockSize - (4 * blkCnt);
+
+ /* Samples loop unrolled by 4 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+ x1 = *(ptr1++);
+ x2 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the coefficient */
+ c1 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x1 * c1;
+ acc1 += x2 * c1;
+ acc2 += x3 * c1;
+ acc3 += x0 * c1;
+
+ /* Read the coefficient */
+ c2 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x2 * c2;
+ acc1 += x3 * c2;
+ acc2 += x0 * c2;
+ acc3 += x1 * c2;
+
+ /* Read the coefficient */
+ c3 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x2 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x3 * c3;
+ acc1 += x0 * c3;
+ acc2 += x1 * c3;
+ acc3 += x2 * c3;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = acc0;
+ *(pDst + S->L) = acc1;
+ *(pDst + 2 * S->L) = acc2;
+ *(pDst + 3 * S->L) = acc3;
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 4;
+
+ pDst += S->L * 3;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ while(blkCntN4 > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += *(ptr1++) * (*ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (phaseLen - 1u) % 0x04u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+
+
+ float32_t sum; /* Accumulator */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ /* Loop over the polyPhase length */
+ tapCnt = phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *ptr1++ * *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1u;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_f32.c
+*
+* Description: Floating-point FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ *
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length (numTaps/L)+blockSize-1 words
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize +
+ ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,120 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_q15.c
+*
+* Description: Q15 FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ *
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length (numTaps/L)+blockSize-1 words
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_q31.c
+*
+* Description: Q31 FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+
+/**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ *
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.
+ * \par
+ * pState points to the array of state variables.
+ * pState is of length (numTaps/L)+blockSize-1 words
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,508 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_q15.c
+*
+* Description: Q15 FIR interpolation.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum0; /* Accumulators */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j, tapCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+ uint32_t blkCntN2;
+ q63_t acc0, acc1;
+ q15_t x1;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 2;
+ blkCntN2 = blockSize - (2 * blkCnt);
+
+ /* Samples loop unrolled by 2 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 2;
+
+ pDst += S->L;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blkCntN2;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen & 0x3u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum; /* Accumulator */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ /* Loop over the polyPhase length */
+ tapCnt = (uint32_t) phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) x0 * c0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Store the result after converting to 1.15 format in the destination buffer */
+ *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (uint32_t) phaseLen - 1u;
+
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,504 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_q31.c
+*
+* Description: Q31 FIR interpolation.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).
+ * since numTaps/L additions occur per output sample.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum0; /* Accumulators */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+ uint32_t blkCntN2;
+ q63_t acc0, acc1;
+ q31_t x1;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 2;
+ blkCntN2 = blockSize - (2 * blkCnt);
+
+ /* Samples loop unrolled by 2 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = (q31_t) (acc0 >> 31);
+ *(pDst + S->L) = (q31_t) (acc1 >> 31);
+
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 2;
+
+ pDst += S->L;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blkCntN2;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen & 0x3u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (phaseLen - 1u) % 0x04u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+
+#else
+
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+
+ /* Run the below code for Cortex-M0 */
+
+ q63_t sum; /* Accumulator */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ tapCnt = phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum >> 31);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,506 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_f32.c
+*
+* Description: Processing function for the floating-point FIR Lattice filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters
+ *
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters
+ * for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ * variety of adaptive filter applications. The filter structure is feedforward and
+ * the net impulse response is finite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * blockSize samples through the filter. pSrc and
+ * pDst point to input and output arrays containing blockSize values.
+ *
+ * \par Algorithm:
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"
+ * The following difference equation is implemented:
+ *
+ * f0[n] = g0[n] = x[n]
+ * fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+ * gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+ * y[n] = fM[n]
+ *
+ * \par
+ * pCoeffs points to tha array of reflection coefficients of size numStages.
+ * Reflection Coefficients are stored in the following order.
+ * \par
+ *
+ * {k1, k2, ..., kM}
+ *
+ * where M is number of stages
+ * \par
+ * pState points to a state array of size numStages.
+ * The state variables (g values) hold previous inputs and are stored in the following order.
+ *
+ * {g0[n], g1[n], g2[n] ...gM-1[n]}
+ *
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ *
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+ *
+ * \par
+ * where numStages is the number of stages in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* temporary state pointer */
+ float32_t *pk; /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t fcurr1, fnext1, gcurr1, gnext1; /* temporary variables for first sample in loop unrolling */
+ float32_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ float32_t fcurr3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
+ float32_t fcurr4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ gcurr1 = 0.0f;
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+ fcurr2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Read g0(n-1) from state */
+ gcurr1 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+ /* Process second sample for first tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * fcurr1);
+ gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurr3 = *pSrc++;
+ fcurr4 = *pSrc++;
+
+ /* Copy only last input samples into the state buffer
+ which will be used for next four samples processing */
+ *px++ = fcurr4;
+
+ /* Process third sample for first tap */
+ fnext3 = fcurr3 + ((*pk) * fcurr2);
+ gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+ /* Process fourth sample for first tap */
+ fnext4 = fcurr4 + ((*pk) * fcurr3);
+ gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+ fcurr4 = fnext4;
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1u) >> 2u;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while(stageCnt > 0u)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ /* Process fourth sample for 2nd, 6th .. tap */
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g2(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurr1 = fnext1 + ((*pk) * gcurr1);
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurr2 = fnext2 + ((*pk) * gnext1);
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurr3 = fnext3 + ((*pk) * gnext2);
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurr4 = fnext4 + ((*pk) * gnext3);
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext4 = (fnext4 * (*pk)) + gnext3;
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+ gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g3(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ /* Process third sample for 4th, 8th .. tap */
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurr1 = fnext1 + ((*pk) * gcurr1);
+ /* Process second sample for 5th, 9th .. tap */
+ fcurr2 = fnext2 + ((*pk) * gnext1);
+ /* Process third sample for 5th, 9th .. tap */
+ fcurr3 = fnext3 + ((*pk) * gnext2);
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurr4 = fnext4 + ((*pk) * gnext3);
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext4 = (fnext4 * (*pk)) + gnext3;
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+ gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1u) % 0x4u;
+
+ while(stageCnt > 0u)
+ {
+ gcurr1 = *px;
+
+ /* save g value in state buffer */
+ *px++ = gnext4;
+
+ /* Process four samples for last three taps here */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+ fcurr4 = fnext4;
+
+ stageCnt--;
+
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+ *pDst++ = fcurr3;
+ *pDst++ = fcurr4;
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+
+ blkCnt--;
+
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* save f0(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_f32.c
+*
+* Description: Floating-point FIR Lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_q15.c
+*
+* Description: Q15 FIR Lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_q31.c
+*
+* Description: Q31 FIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,536 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_q15.c
+*
+* Description: Q15 FIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* temporary state pointer */
+ q15_t *pk; /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
+ q31_t fcurnt2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ q31_t fcurnt3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
+ q31_t fcurnt4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurnt1 = *pSrc++;
+ fcurnt2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Read g0(n-1) from state */
+ gcurnt1 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Process second sample for first tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+ gnext2 = __SSAT(gnext2, 16);
+
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurnt3 = *pSrc++;
+ fcurnt4 = *pSrc++;
+
+ /* Copy only last input samples into the state buffer
+ which is used for next four samples processing */
+ *px++ = (q15_t) fcurnt4;
+
+ /* Process third sample for first tap */
+ fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ /* Process fourth sample for first tap */
+ fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+ gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ /* Update of f values for next coefficient set processing */
+ fcurnt1 = fnext1;
+ fcurnt2 = fnext2;
+ fcurnt3 = fnext3;
+ fcurnt4 = fnext4;
+
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1u) >> 2;
+
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while(stageCnt > 0u)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+ /* Process fourth sample for 2nd, 6th .. tap */
+ /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+ fcurnt1 = __SSAT(fcurnt1, 16);
+
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+ fcurnt2 = __SSAT(fcurnt2, 16);
+
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+ fcurnt3 = __SSAT(fcurnt3, 16);
+
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+ fcurnt4 = __SSAT(fcurnt4, 16);
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ /* Process third sample for 4th, 8th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+ fcurnt1 = __SSAT(fcurnt1, 16);
+
+ /* Process second sample for 5th, 9th .. tap */
+ fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+ fcurnt2 = __SSAT(fcurnt2, 16);
+
+ /* Process third sample for 5th, 9th .. tap */
+ fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+ fcurnt3 = __SSAT(fcurnt3, 16);
+
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+ fcurnt4 = __SSAT(fcurnt4, 16);
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1u) % 0x4u;
+
+ while(stageCnt > 0u)
+ {
+ gcurnt1 = *px;
+
+ /* save g value in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Process four samples for last three taps here */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Update of f values for next coefficient set processing */
+ fcurnt1 = fnext1;
+ fcurnt2 = fnext2;
+ fcurnt3 = fnext3;
+ fcurnt4 = fnext4;
+
+ stageCnt--;
+
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurnt1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g2(n) from state buffer */
+ gcurnt1 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) fcurnt1;
+
+ /* f1(n) is saved in fcurnt1
+ for next stage processing */
+ fcurnt1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* f1(n) is saved in fcurnt1
+ for next stage processing */
+ fcurnt1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurnt1, 16);
+
+
+ blkCnt--;
+
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurnt = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+ fnext = __SSAT(fnext, 16);
+
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+ gnext = __SSAT(gnext, 16);
+
+ /* save f0(n) in state buffer */
+ *px++ = (q15_t) fcurnt;
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g1(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* save g0(n-1) in state buffer */
+ *px++ = (q15_t) gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+ fnext = __SSAT(fnext, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+ gnext = __SSAT(gnext, 16);
+
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurnt, 16);
+
+
+ blkCnt--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_q31.c
+*
+* Description: Q31 FIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* temporary state pointer */
+ q31_t *pk; /* temporary coefficient pointer */
+ q31_t fcurr1, fnext1, gcurr1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
+ q31_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+ q31_t k;
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ a second loop below computes the remaining 1 sample. */
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* f0(n) = x(n) */
+ fcurr2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n - 1) from state buffer */
+ gcurr1 = *px;
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+ fnext2 = fcurr2 + (fnext2 << 1u);
+ gnext2 = fcurr1 + (gnext2 << 1u);
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr2;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext2;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
+
+ fnext1 = fcurr1 + (fnext1 << 1u);
+ fnext2 = fcurr2 + (fnext2 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+ gnext2 = gnext1 + (gnext2 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+
+ blkCnt--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x2u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n - 1) from state buffer */
+ gcurr1 = *px;
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+
+ blkCnt--;
+
+ }
+
+
+}
+
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* temporary state pointer */
+ q31_t *pk; /* temporary coefficient pointer */
+ q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+ /* save g1(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,691 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q15.c
+*
+* Description: Q15 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px1; /* Temporary q15 pointer for state buffer */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer of type q15 */
+ px1 = pState;
+
+ /* Initialize coeff pointer of type q31 */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = _SIMD32_OFFSET(px1);
+
+ /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+ x1 = _SIMD32_OFFSET(px1 + 1u);
+
+ px1 += 2u;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read state x[n-N-2], x[n-N-3] */
+ x2 = _SIMD32_OFFSET(px1);
+
+ /* Read state x[n-N-3], x[n-N-4] */
+ x3 = _SIMD32_OFFSET(px1 + 1u);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLALD(x3, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLALD(x3, c0, acc1);
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px1 + 2u);
+
+ /* Read state x[n-N-5], x[n-N-6] */
+ x1 = _SIMD32_OFFSET(px1 + 3u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLALD(x1, c0, acc3);
+
+ px1 += 4u;
+
+ tapCnt--;
+
+ }
+
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+ /* Read 2 coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Fetch 4 state variables */
+ x2 = _SIMD32_OFFSET(px1);
+
+ x3 = _SIMD32_OFFSET(px1 + 1u);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ px1 += 2u;
+
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x2, c0, acc2);
+ acc3 = __SMLALD(x3, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer of type q15 */
+ px1 = pState;
+
+ /* Initialize coeff pointer of type q31 */
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1;
+
+ do
+ {
+
+ c0 = *__SIMD32(pb)++;
+ x0 = *__SIMD32(px1)++;
+
+ acc0 = __SMLALD(x0, c0, acc0);
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Copy state values to start of state buffer */
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else /* UNALIGNED_SUPPORT_DISABLE */
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+ px = pState;
+
+ /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+ x2 = *__SIMD32(px)++;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* pack x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* Read state x[n-N-6], x[n-N-7] with offset */
+ x2 = _SIMD32_OFFSET(px + 2u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ /* Update state pointer for next state reading */
+ px += 4u;
+
+ /* Decrement tap count */
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+
+ /* Read last two coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read last state variables */
+ x0 = *__SIMD32(px);
+
+ /* Perform the multiply-accumulates */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* Perform the multiply-accumulates */
+ acc3 = __SMLALDX(x1, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Use SIMD to hold states and coefficients */
+ px = pState;
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1u;
+
+ do
+ {
+ acc0 += (q31_t) * px++ * *pb++;
+ acc0 += (q31_t) * px++ * *pb++;
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else /* ARM_MATH_CM0_FAMILY */
+
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of nTaps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q31_t) * px++ * *pb++;
+ tapCnt--;
+ } while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = (numTaps - 1u);
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,365 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q31.c
+*
+* Description: Q31 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t x0, x1, x2; /* Temporary variables to hold state */
+ q31_t c0; /* Temporary variable to hold coefficient value */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc0, acc1, acc2; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, tapCntN3; /* Loop counters */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize / 3;
+ blockSize = blockSize - (3 * blkCnt);
+
+ tapCnt = numTaps / 3;
+ tapCntN3 = numTaps - (3 * tapCnt);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy three new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1] */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Loop unrolling. Process 3 taps at a time. */
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *pb;
+
+ /* Read x[n-numTaps-2] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x0 * c0);
+ acc1 += ((q63_t) x1 * c0);
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read the coefficient and state */
+ c0 = *(pb + 1u);
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x1 * c0);
+ acc1 += ((q63_t) x2 * c0);
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read the coefficient and state */
+ c0 = *(pb + 2u);
+ x1 = *(px++);
+
+ /* update coefficient pointer */
+ pb += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x2 * c0);
+ acc1 += ((q63_t) x0 * c0);
+ acc2 += ((q63_t) x1 * c0);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 3, compute the remaining filter taps */
+
+ i = tapCntN3;
+
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x0 * c0);
+ acc1 += ((q63_t) x1 * c0);
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 3 to process the next group of 3 samples */
+ pState = pState + 3;
+
+ /* The results in the 3 accumulators are in 2.30 format. Convert to 1.31
+ ** Then store the 3 outputs in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31u);
+ *pDst++ = (q31_t) (acc1 >> 31u);
+ *pDst++ = (q31_t) (acc2 >> 31u);
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ while(blockSize > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += (q63_t) * (px++) * (*(pb++));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.62 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31u);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Length of the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q63_t) * px++ * *pb++;
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.62 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = numTaps - 1u;
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,397 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q7.c
+*
+* Description: Q7 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+ q7_t x0, x1, x2, x3; /* Temporary variables to hold state */
+ q7_t c0; /* Temporary variable to hold coefficient value */
+ q7_t *px; /* Temporary pointer for state */
+ q7_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first three samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *pb;
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *px;
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ acc0 += ((q15_t) x0 * c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ acc1 += ((q15_t) x1 * c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ acc2 += ((q15_t) x2 * c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb + 1u);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x1 * c0);
+ acc1 += ((q15_t) x2 * c0);
+ acc2 += ((q15_t) x3 * c0);
+ acc3 += ((q15_t) x0 * c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb + 2u);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x2 * c0);
+ acc1 += ((q15_t) x3 * c0);
+ acc2 += ((q15_t) x0 * c0);
+ acc3 += ((q15_t) x1 * c0);
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb + 3u);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px + 3u);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x3 * c0);
+ acc1 += ((q15_t) x0 * c0);
+ acc2 += ((q15_t) x1 * c0);
+ acc3 += ((q15_t) x2 * c0);
+
+ /* update coefficient pointer */
+ pb += 4u;
+ px += 4u;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+ i = numTaps - (tapCnt * 4u);
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x0 * c0);
+ acc1 += ((q15_t) x1 * c0);
+ acc2 += ((q15_t) x2 * c0);
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31
+ ** Then store the 4 outputs in the destination buffer. */
+ acc0 = __SSAT((acc0 >> 7u), 8);
+ *pDst++ = acc0;
+ acc1 = __SSAT((acc1 >> 7u), 8);
+ *pDst++ = acc1;
+ acc2 = __SSAT((acc2 >> 7u), 8);
+ *pDst++ = acc2;
+ acc3 = __SSAT((acc3 >> 7u), 8);
+ *pDst++ = acc3;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += (q15_t) * (px++) * (*(pb++));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.14 format. Convert to 1.7
+ ** Then store the output in the destination buffer. */
+ *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t i, blkCnt; /* Loop counters */
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px, *pb; /* Temporary pointers to state and coeff */
+ q31_t acc = 0; /* Accumlator */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ /* Perform filtering upto BlockSize - BlockSize%4 */
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer of type q7 */
+ px = pState;
+
+ /* Initialize coeff pointer of type q7 */
+ pb = pCoeffs;
+
+
+ i = numTaps;
+
+ while(i > 0u)
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q15_t) * px++ * *pb++;
+ i--;
+ }
+
+ /* Store the 1.7 format filter output in destination buffer */
+ *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+ /* Advance the state pointer by 1 to process the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+
+ /* Copy numTaps number of values */
+ i = (numTaps - 1u);
+
+ /* Copy q7_t data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,444 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_f32.c
+*
+* Description: Floating-point sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters
+ *
+ * This group of functions implements sparse FIR filters.
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.
+ * Sparse filters are used for simulating reflections in communications and audio applications.
+ *
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.
+ * The functions operate on blocks of input and output data and each call to the function processes
+ * blockSize samples through the filter. pSrc and
+ * pDst points to input and output arrays respectively containing blockSize values.
+ *
+ * \par Algorithm:
+ * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.
+ * This is in addition to the coefficient array b.
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.
+ *
+ * y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+ *
+ * \par
+ * \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients"
+ * \par
+ * pCoeffs points to a coefficient array of size numTaps;
+ * pTapDelay points to an array of nonzero indices and is also of size numTaps;
+ * pState points to a state array of size maxDelay + blockSize, where
+ * maxDelay is the largest offset value that is ever used in the pTapDelay array.
+ * Some of the processing functions also require temporary working buffers.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 4 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 4 different data type filter instance structures
+ *
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q7 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *
+ * \par
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize)
+{
+
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* Scratch buffer pointer */
+ float32_t *py = pState; /* Temporary pointers for state buffer */
+ float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ float32_t *pOut; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ float32_t coeff = *pCoeffs++; /* Read the first coefficient value */
+
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 Multiplications at a time. */
+ blkCnt = blockSize >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex -
+ (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex =
+ ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_f32.c
+*
+* Description: Floating-point sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the
+ * number of samples processed by the arm_fir_sparse_f32() function.
+ */
+
+void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q15.c
+*
+* Description: Q15 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the
+ * number of words processed by arm_fir_sparse_q15() function.
+ */
+
+void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q31.c
+*
+* Description: Q31 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the number of words processed by arm_fir_sparse_q31() function.
+ */
+
+void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q7.c
+*
+* Description: Q7 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * Description:
+ * \par
+ * pCoeffs holds the filter coefficients and has length numTaps.
+ * pState holds the filter's state variables and must be of length
+ * maxDelay + blockSize, where maxDelay
+ * is the maximum number of delay line values.
+ * blockSize is the
+ * number of samples processed by the arm_fir_sparse_q7() function.
+ */
+
+void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,481 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q15.c
+*
+* Description: Q15 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.
+ * If the accumulator result overflows it will wrap around rather than saturate.
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+
+void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pIn = pSrc; /* Working pointer for input */
+ q15_t *pOut = pDst; /* Working pointer for output */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* Temporary pointers for scratch buffer */
+ q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q15_t *py = pState; /* Temporary pointers for state buffer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q15_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2; /* Temporary variables */
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in1 = *pScr2++;
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+ 16);
+
+#else
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+ 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pScr2++;
+
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+ 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+ 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ blkCnt--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ remaining samples are processed in the below loop */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q31.c
+*
+* Description: Q31 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.
+ * If the accumulator result overflows, it wraps around rather than saturate.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize)
+{
+
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* Scratch buffer pointer */
+ q31_t *py = pState; /* Temporary pointers for state buffer */
+ q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q31_t *pOut; /* Destination pointer */
+ q63_t out; /* Temporary output variable */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q31_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t in;
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 Multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * process 4 output samples at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * process the remaining output samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,480 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q7.c
+*
+* Description: Q7 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px; /* Scratch buffer pointer */
+ q7_t *py = pState; /* Temporary pointers for state buffer */
+ q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q7_t *pOut = pDst; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q7_t coeff = *pCoeffs++; /* Read the coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */
+ q31_t in;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t in1, in2, in3, in4;
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+ blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex -
+ (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ remaining samples are processed in the below loop */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+ blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex =
+ ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,447 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_f32.c
+*
+* Description: Floating-point IIR Lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters
+ *
+ * This set of functions implements lattice filters
+ * for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ * variety of adaptive filter applications. The filter structure has feedforward and
+ * feedback components and the net impulse response is infinite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * blockSize samples through the filter. pSrc and
+ * pDst point to input and output arrays containing blockSize values.
+
+ * \par Algorithm:
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"
+ *
+ * fN(n) = x(n)
+ * fm-1(n) = fm(n) - km * gm-1(n-1) for m = N, N-1, ...1
+ * gm(n) = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1
+ * y(n) = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+ *
+ * \par
+ * pkCoeffs points to array of reflection coefficients of size numStages.
+ * Reflection coefficients are stored in time-reversed order.
+ * \par
+ *
+ * {kN, kN-1, ....k1}
+ *
+ * pvCoeffs points to the array of ladder coefficients of size (numStages+1).
+ * Ladder coefficients are stored in time-reversed order.
+ * \par
+ *
+ * {vN, vN-1, ...v0}
+ *
+ * pState points to a state array of size numStages + blockSize.
+ * The state variables shown in the figure above (the g values) are stored in the pState array.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ *
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *
+ * \par
+ * where numStages is the number of stages in the filter; pState points to the state buffer array;
+ * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t fnext1, gcurr1, gnext; /* Temporary variables for lattice stages */
+ float32_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* temporary variables for counts */
+ float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ float32_t *pState; /* State pointer */
+ float32_t *pStateCurnt; /* State current pointer */
+ float32_t k1, k2;
+ float32_t v1, v2, v3, v4;
+ float32_t gcurr2;
+ float32_t fnext2;
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ /* initialise state pointer */
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fnext2 = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0.0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Read gN-1(n-1) from state buffer */
+ gcurr1 = *px1;
+
+ /* read reflection coefficient kN */
+ k1 = *pk;
+
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* read ladder coefficient vN */
+ v1 = *pv;
+
+ /* read next reflection coefficient kN-1 */
+ k2 = *(pk + 1u);
+
+ /* Read gN-2(n-1) from state buffer */
+ gcurr2 = *(px1 + 1u);
+
+ /* read next ladder coefficient vN-1 */
+ v2 = *(pv + 1u);
+
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read reflection coefficient kN-2 */
+ k1 = *(pk + 2u);
+
+ /* write gN(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Read gN-3(n-1) from state buffer */
+ gcurr1 = *(px1 + 2u);
+
+ /* y(n) += gN(n) * vN */
+ acc += (gnext * v1);
+
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = gcurr2 + (k2 * fnext2);
+
+ /* Read gN-4(n-1) from state buffer */
+ gcurr2 = *(px1 + 3u);
+
+ /* y(n) += gN-1(n) * vN-1 */
+ acc += (gnext * v2);
+
+ /* read reflection coefficient kN-3 */
+ k2 = *(pk + 3u);
+
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read ladder coefficient vN-2 */
+ v3 = *(pv + 2u);
+
+ /* y(n) += gN-2(n) * vN-2 */
+ acc += (gnext * v3);
+
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointer */
+ pk += 4u;
+
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = (fnext2 * k2) + gcurr2;
+
+ /* read next ladder coefficient vN-3 */
+ v4 = *(pv + 3u);
+
+ /* y(n) += gN-4(n) * vN-4 */
+ acc += (gnext * v4);
+
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointers */
+ px1 += 4u;
+ pv += 4u;
+
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr1 = *px1++;
+ /* Process sample for last taps */
+ fnext1 = fnext2 - ((*pk) * gcurr1);
+ gnext = (fnext1 * (*pk++)) + gcurr1;
+ /* Output samples for last taps */
+ acc += (gnext * (*pv++));
+ *px2++ = gnext;
+ fnext2 = fnext1;
+
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (fnext2 * (*pv));
+
+ *px2++ = fnext2;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numStages) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t fcurr, fnext = 0, gcurr, gnext; /* Temporary variables for lattice stages */
+ float32_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* temporary variables for counts */
+ float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ float32_t *pState; /* State pointer */
+ float32_t *pStateCurnt; /* State current pointer */
+
+
+ /* Run the below code for Cortex-M0 */
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0.0f;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for numStages */
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - ((*pk) * gcurr);
+ gnext = (fnext * (*pk++)) + gcurr;
+
+ /* Output samples for last taps */
+ acc += (gnext * (*pv++));
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ /* Decrementing loop counter */
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (fnext * (*pv));
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_f32.c
+*
+* Description: Floating-point IIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+ /**
+ * @} end of IIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_q15.c
+*
+* Description: Q15 IIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_q31.c
+*
+* Description: Initialization function for the Q31 IIR lattice filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_q15.c
+*
+* Description: Q15 IIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t fcurr, fnext, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q15_t gnext1, gnext2; /* Temporary variables for lattice stages */
+ uint32_t stgCnt; /* Temporary variables for counts */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q15_t *pState; /* State pointer */
+ q15_t *pStateCurnt; /* State current pointer */
+ q15_t out; /* Temporary variable for output */
+ q31_t v; /* Temporary variable for ladder coefficient */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ q15_t v1, v2;
+#endif
+
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Process sample for 2nd, 6th ...taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 2nd, 6th .. taps */
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-1(n) into state */
+ *px2++ = (q15_t) gnext1;
+
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-2(n) into state */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-1 and vN-2 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ v = *__SIMD32(pv)++;
+
+#else
+
+ v1 = *pv++;
+ v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ v = __PKHBT(v1, v2, 16);
+
+#else
+
+ v = __PKHBT(v2, v1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+ /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+ gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-3(n) for the next sample process */
+ *px2++ = (q15_t) gnext1;
+
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-4(n) for the next sample process */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-3 and vN-4 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ v = *__SIMD32(pv)++;
+
+#else
+
+ v1 = *pv++;
+ v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ v = __PKHBT(v1, v2, 16);
+
+#else
+
+ v = __PKHBT(v2, v1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+ /* Pack gN-3(n) and gN-4(n) */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+ gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+ tapCnt--;
+
+ }
+
+ fnext = fcurr;
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages - 1u) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* Output samples for last taps */
+ acc += (q31_t) (((q31_t) gnext * (*pv++)));
+ *px2++ = (q15_t) gnext;
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ stgCnt = (numStages >> 2u);
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ stgCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ stgCnt = (numStages) % 0x4u;
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ stgCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ uint32_t stgCnt; /* Temporary variables for counts */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q15_t *pState; /* State pointer */
+ q15_t *pStateCurnt; /* State current pointer */
+ q15_t out; /* Temporary variable for output */
+
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - ((gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) ((fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ stgCnt = numStages;
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ stgCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,350 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_q31.c
+*
+* Description: Q31 IIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.
+ */
+
+void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q31_t *pState; /* State pointer */
+ q31_t *pStateCurnt; /* State current pointer */
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Process sample for 2nd, 6th .. taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-4(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ tapCnt--;
+
+ }
+
+ fnext = fcurr;
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages - 1u) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* Output samples for last taps */
+ acc += ((q63_t) gnext * *pv++);
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q63_t) fnext *(
+ *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numStages) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ };
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext =
+ clip_q63_to_q31(((q63_t) fcurr -
+ ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext =
+ clip_q63_to_q31(((q63_t) gcurr +
+ ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q63_t) fnext *(
+ *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,442 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_f32.c
+*
+* Description: Processing function for the floating-point LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS Least Mean Square (LMS) Filters
+ *
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.
+ *
+ * An LMS filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The LMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * blockSize samples through the filter.
+ * pSrc points to input signal, pRef points to reference signal,
+ * pOut points to output signal and pErr points to error signal.
+ * All arrays contain blockSize values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal y[n] is computed by a standard FIR filter:
+ *
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ *
+ *
+ * \par
+ * The error signal equals the difference between the reference signal d[n] and the filter output:
+ *
+ * e[n] = d[n] - y[n].
+ *
+ *
+ * \par
+ * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:
+ *
+ * b[k] = b[k] + e[n] * mu * x[n-k], for k=0, 1, ..., numTaps-1
+ *
+ * where mu is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.
+ * Coefficients are stored in time reversed order.
+ * \par
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to a state array of size numTaps + blockSize - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ *
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ *
+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ *
+ * arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+ * arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+ * arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+ *
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;
+ * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.
+ *
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range [-1 +1).
+ * The fixed-point functions have an additional scaling parameter postShift.
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * This essentially scales the filter coefficients by 2^postShift and
+ * allows the filter coefficients to exceed the range [+1 -1).
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+ * @details
+ * This function operates on floating-point data types.
+ *
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w = 0.0f; /* weight factor */
+
+ e = 0.0f;
+ d = 0.0f;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for the updating filter coefficients */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Weighting factor for the LMS version */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ * start of the state buffer. This prepares the state buffer for the
+ * next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,95 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_f32.c
+*
+* Description: Floating-point LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+/**
+ * \par Description:
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().
+ */
+
+void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps */
+ memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_q15.c
+*
+* Description: Q15 LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 LMS filter.
+* @param[in] *S points to an instance of the Q15 LMS filter structure.
+* @param[in] numTaps number of filter coefficients.
+* @param[in] *pCoeffs points to the coefficient buffer.
+* @param[in] *pState points to the state buffer.
+* @param[in] mu step size that controls filter coefficient updates.
+* @param[in] blockSize number of samples to process.
+* @param[in] postShift bit shift applied to coefficients.
+* @return none.
+*
+* \par Description:
+* pCoeffs points to the array of filter coefficients stored in time reversed order:
+*
+* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+*
+* The initial filter coefficients serve as a starting point for the adaptive filter.
+* pState points to the array of state variables and size of array is
+* numTaps+blockSize-1 samples, where blockSize is the number of
+* input samples processed by each call to arm_lms_q15().
+*/
+
+void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_q31.c
+*
+* Description: Q31 LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * \par Description:
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples,
+ * where blockSize is the number of input samples processed by each call to
+ * arm_lms_q31().
+ */
+
+void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_f32.c
+*
+* Description: Processing function for the floating-point Normalised LMS.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS_NORM Normalized LMS Filters
+ *
+ * This set of functions implements a commonly used adaptive filter.
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization
+ * factor which increases the adaptation rate of the filter.
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ *
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The NLMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * blockSize samples through the filter.
+ * pSrc points to input signal, pRef points to reference signal,
+ * pOut points to output signal and pErr points to error signal.
+ * All arrays contain blockSize values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal y[n] is computed by a standard FIR filter:
+ *
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ *
+ *
+ * \par
+ * The error signal equals the difference between the reference signal d[n] and the filter output:
+ *
+ * e[n] = d[n] - y[n].
+ *
+ *
+ * \par
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:
+ *
+ * E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+ *
+ * The filter coefficients b[k] are then updated on a sample-by-sample basis:
+ *
+ * b[k] = b[k] + e[n] * (mu/E) * x[n-k], for k=0, 1, ..., numTaps-1
+ *
+ * where mu is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.
+ * Coefficients are stored in time reversed order.
+ * \par
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * \par
+ * pState points to a state array of size numTaps + blockSize - 1.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ *
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ *
+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero.
+ * For Q7, Q15, and Q31 the following fields must also be initialized;
+ * recipTable, postShift
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range [-1 +1).
+ * The fixed-point functions have an additional scaling parameter postShift.
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ * This essentially scales the filter coefficients by 2^postShift and
+ * allows the filter coefficients to exceed the range [+1 -1).
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t energy; /* Energy of the input */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */
+
+ /* Initializations of error, difference, Coefficient update */
+ e = 0.0f;
+ d = 0.0f;
+ w = 0.0f;
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCcoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_f32.c
+*
+* Description: Floating-point NLMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Description:
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples,
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().
+ */
+
+void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialise Energy to zero */
+ S->energy = 0.0f;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0.0f;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_q15.c
+*
+* Description: Q15 NLMS initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to the array of state variables and size of array is
+ * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed
+ * by each call to arm_lms_norm_q15().
+ */
+
+void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q15_t *) armRecipTableQ15;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_q31.c
+*
+* Description: Q31 NLMS initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * Description:
+ * \par
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:
+ *
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ *
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * pState points to an array of length numTaps+blockSize-1 samples,
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().
+ */
+
+void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q31_t *) armRecipTableQ31;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_q15.c
+*
+* Description: Q15 NLMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q15 normalized LMS filter.
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* Scaling and Overflow Behavior:
+* \par
+* The function is implemented using a 64-bit internal accumulator.
+* Both coefficients and state variables are represented in 1.15 format and
+* multiplications yield a 2.30 result. The 2.30 intermediate results are
+* accumulated in a 64-bit accumulator in 34.30 format.
+* There is no risk of internal overflow with this approach and the full
+* precision of intermediate multiplications is preserved. After all additions
+* have been performed, the accumulator is truncated to 34.15 format by
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a
+* result in 1.15 format.
+*
+* \par
+* In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+*
+ */
+
+void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q15_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q31_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0, d = 0; /* error, reference data sample */
+ q15_t w = 0, in; /* weight factor and state */
+ q15_t x0; /* temporary variable to hold input sample */
+ //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */
+ q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Teporary variable for coefficient */
+ q31_t acc_l, acc_h;
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t) x0 * (x0)) >> 15);
+ energy += (((q31_t) in * (in)) >> 15);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (((q31_t) * px++ * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16u);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+ &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = (q15_t) __SSAT((q31_t) acc, 16);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t) x0 * (x0)) >> 15);
+ energy += (((q31_t) in * (in)) >> 15);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (((q31_t) * px++ * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16u);
+
+ /* Converting the result to 1.15 format */
+ //acc = __SSAT((acc >> (16u - shift)), 16u);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+ &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = (q15_t) __SSAT((q31_t) acc, 16);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy (numTaps - 1u) data */
+ tapCnt = (numTaps - 1u);
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,431 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_q31.c
+*
+* Description: Processing function for the Q31 NLMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q31 normalized LMS filter.
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* Scaling and Overflow Behavior:
+* \par
+* The function is implemented using an internal 64-bit accumulator.
+* The accumulator has a 2.62 format and maintains full precision of the intermediate
+* multiplication results but provides only a single guard bit.
+* Thus, if the accumulator result overflows it wraps around rather than clip.
+* In order to avoid overflows completely the input signal must be scaled down by
+* log2(numTaps) bits. The reference signal should not be scaled down.
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+* and saturated to 1.31 format to yield the final result.
+* The output signal and error signal are in 1.31 format.
+*
+* \par
+* In this filter, filter coefficients are updated for each sample and the
+* updation of filter cofficients are saturted.
+*
+*/
+
+void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q31_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0, d = 0; /* error, reference data sample */
+ q31_t w = 0, in; /* weight factor and state */
+ q31_t x0; /* temporary variable to hold input sample */
+// uint32_t shift = 32u - ((uint32_t) S->postShift + 1u); /* Shift to be applied to the output */
+ q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy = (q31_t) ((((q63_t) energy << 32) -
+ (((q63_t) x0 * x0) << 1)) >> 32);
+ energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Calculates the reciprocal of energy */
+ postShift = arm_recip_q31(energy + DELTA_Q31,
+ &oneByEnergy, &S->recipTable[0]);
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Weighting factor for the normalized version */
+ w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy =
+ (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+ energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+
+ //acc = (q31_t) (acc >> shift);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Calculates the reciprocal of energy */
+ postShift =
+ arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Weighting factor for the normalized version */
+ w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_q15.c
+*
+* Description: Processing function for the Q15 LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ *
+ */
+
+void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t mu = S->mu; /* Adaptive factor */
+ q15_t *px; /* Temporary pointer for state */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0; /* error of data sample */
+ q15_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Teporary variable for coefficient */
+ q31_t acc_l, acc_h;
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initializing blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t) acc;
+
+ *pErr++ = (q15_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+ /* Initialize state pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2u;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+#else
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+#endif
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t) acc;
+
+ *pErr++ = (q15_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_q31.c
+*
+* Description: Processing function for the Q31 LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clips.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(numTaps) bits.
+ * The reference signal should not be scaled down.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+ * and saturated to 1.31 format to yield the final result.
+ * The output signal and error signal are in 1.31 format.
+ *
+ * \par
+ * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ */
+
+void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t mu = S->mu; /* Adaptive factor */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0; /* error of data sample */
+ q31_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initializing blkCnt with blockSize */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* acc += b[N] * x[n-N] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-1] * x[n-N-1] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-2] * x[n-N-2] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-3] * x[n-N-3] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+
+ *pErr++ = (q31_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Initialize state pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Store the result from accumulator into the destination buffer. */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+
+ *pErr++ = (q31_t) e;
+
+ /* Weighting factor for the LMS version */
+ alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_f32.c
+*
+* Description: Floating-point matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixAdd Matrix Addition
+ *
+ * Adds two matrices.
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * pSrcA, pSrcB, and pDst have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Loop unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* out = sourceA + sourceB */
+ out1 = inA1 + inB1;
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* out = sourceA + sourceB */
+ out2 = inA2 + inB2;
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* out = sourceA + sourceB */
+ out1 = inA1 + inB1;
+
+ /* out = sourceA + sourceB */
+ out2 = inA2 + inB2;
+
+ /* Store result in destination */
+ pOut[2] = out1;
+
+ /* Store result in destination */
+ pOut[3] = out2;
+
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add and then store the results in the destination buffer. */
+ *pOut++ = (*pIn1++) + (*pIn2++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_q15.c
+*
+* Description: Q15 matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint16_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop unrolling */
+ blkCnt = (uint32_t) numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+ *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) numSamples % 0x4u;
+
+ /* q15 pointers of input and output are initialized */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (uint32_t) numSamples;
+
+
+ /* q15 pointers of input and output are initialized */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_q31.c
+*
+* Description: Q31 matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t inA1, inB1; /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t inA2, inB2; /* temporary variables */
+ q31_t out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, saturate and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* Add and saturate */
+ out1 = __QADD(inA1, inB1);
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* Add and saturate */
+ out2 = __QADD(inA2, inB2);
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* Add and saturate */
+ out1 = __QADD(inA1, inB1);
+ out2 = __QADD(inA2, inB2);
+
+ /* Store result in destination */
+ pOut[2] = out1;
+ pOut[3] = out2;
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, saturate and then store the results in the destination buffer. */
+ inA1 = *pIn1++;
+ inB1 = *pIn2++;
+
+ inA1 = __QADD(inA1, inB1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ *pOut++ = inA1;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_cmplx_mult_f32.c
+*
+* Description: Floating-point matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup CmplxMatrixMult Complex Matrix Multiplication
+ *
+ * Complex Matrix multiplication is only defined if the number of columns of the
+ * first matrix equals the number of rows of the second matrix.
+ * Multiplying an M x N matrix with an N x P matrix results
+ * in an M x P matrix.
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
+ * pSrcA and pSrcB are equal; and (2) that the size of the output
+ * matrix equals the outer dimensions of pSrcA and pSrcB.
+ */
+
+
+/**
+ * @addtogroup CmplxMatrixMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point Complex matrix multiplication.
+ * @param[in] *pSrcA points to the first input complex matrix structure
+ * @param[in] *pSrcB points to the second input complex matrix structure
+ * @param[out] *pDst points to output complex matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ float32_t sumReal1, sumImag1; /* accumulator */
+ float32_t a0, b0, c0, d0;
+ float32_t a1, b1, c1, d1;
+ float32_t sumReal2, sumImag2; /* accumulator */
+
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + 2 * i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sumReal1 = 0.0f;
+ sumImag1 = 0.0f;
+
+ sumReal2 = 0.0f;
+ sumImag2 = 0.0f;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+
+ /* Reading real part of complex matrix A */
+ a0 = *pIn1;
+
+ /* Reading real part of complex matrix B */
+ c0 = *pIn2;
+
+ /* Reading imaginary part of complex matrix A */
+ b0 = *(pIn1 + 1u);
+
+ /* Reading imaginary part of complex matrix B */
+ d0 = *(pIn2 + 1u);
+
+ sumReal1 += a0 * c0;
+ sumImag1 += b0 * c0;
+
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ sumReal2 -= b0 * d0;
+ sumImag2 += a0 * d0;
+
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+ a1 = *pIn1;
+ c1 = *pIn2;
+
+ b1 = *(pIn1 + 1u);
+ d1 = *(pIn2 + 1u);
+
+ sumReal1 += a1 * c1;
+ sumImag1 += b1 * c1;
+
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ sumReal2 -= b1 * d1;
+ sumImag2 += a1 * d1;
+
+ a0 = *pIn1;
+ c0 = *pIn2;
+
+ b0 = *(pIn1 + 1u);
+ d0 = *(pIn2 + 1u);
+
+ sumReal1 += a0 * c0;
+ sumImag1 += b0 * c0;
+
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ sumReal2 -= b0 * d0;
+ sumImag2 += a0 * d0;
+
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+ a1 = *pIn1;
+ c1 = *pIn2;
+
+ b1 = *(pIn1 + 1u);
+ d1 = *(pIn2 + 1u);
+
+ sumReal1 += a1 * c1;
+ sumImag1 += b1 * c1;
+
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ sumReal2 -= b1 * d1;
+ sumImag2 += a1 * d1;
+
+ /* Decrement the loop count */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ a1 = *pIn1;
+ c1 = *pIn2;
+
+ b1 = *(pIn1 + 1u);
+ d1 = *(pIn2 + 1u);
+
+ sumReal1 += a1 * c1;
+ sumImag1 += b1 * c1;
+
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ sumReal2 -= b1 * d1;
+ sumImag2 += a1 * d1;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ sumReal1 += sumReal2;
+ sumImag1 += sumImag2;
+
+ /* Store the result in the destination buffer */
+ *px++ = sumReal1;
+ *px++ = sumImag1;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + 2u * j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + 2 * numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mat_mult_q15.c
+*
+* Description: Q15 complex matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup CmplxMatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 Complex matrix multiplication
+ * @param[in] *pSrcA points to the first input complex matrix structure
+ * @param[in] *pSrcB points to the second input complex matrix structure
+ * @param[out] *pDst points to output complex matrix structure
+ * @param[in] *pScratch points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * \par Conditions for optimum performance
+ * Input, output and state buffers should be aligned by 32-bit
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to
+ * 1.15 format.
+ *
+ * \par
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function.
+ *
+ */
+
+
+
+
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch)
+{
+ /* accumulator */
+ q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ q63_t sumReal, sumImag;
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t a, b, c, d;
+#else
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t prod1, prod2;
+ q31_t pSourceA, pSourceB;
+#endif
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pSrcBT + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ /* Read two elements from the row */
+ in = *pInB++;
+ *px = in;
+ in = *pInB++;
+ px[1] = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from the row */
+ in = *pInB++;
+ *px = in;
+ in = *pInB++;
+ px[1] = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from the row */
+ in = *pInB++;
+ *px = in;
+ in = *pInB++;
+ px[1] = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from the row */
+ in = *pInB++;
+ *px = in;
+ in = *pInB++;
+ px[1] = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read two elements from the row */
+ in = *pInB++;
+ *px = in;
+ in = *pInB++;
+ px[1] = in;
+#else
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ *__SIMD32(px) = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ *__SIMD32(px) = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ *__SIMD32(px) = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ *__SIMD32(px) = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ *__SIMD32(px) = in;
+#endif
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB * 2;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i = i + 2u;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Reset the variables for the usage in the following multiplication process */
+ row = numRowsA;
+ i = 0u;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sumReal = 0;
+ sumImag = 0;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 1;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pInA = pSrcA->pData + i * 2;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ /* read real and imag values from pSrcA buffer */
+ a = *pInA;
+ b = *(pInA + 1u);
+ /* read real and imag values from pSrcB buffer */
+ c = *pInB;
+ d = *(pInB + 1u);
+
+ /* Multiply and Accumlates */
+ sumReal += (q31_t) a *c;
+ sumImag += (q31_t) a *d;
+ sumReal -= (q31_t) b *d;
+ sumImag += (q31_t) b *c;
+
+ /* read next real and imag values from pSrcA buffer */
+ a = *(pInA + 2u);
+ b = *(pInA + 3u);
+ /* read next real and imag values from pSrcB buffer */
+ c = *(pInB + 2u);
+ d = *(pInB + 3u);
+
+ /* update pointer */
+ pInA += 4u;
+
+ /* Multiply and Accumlates */
+ sumReal += (q31_t) a *c;
+ sumImag += (q31_t) a *d;
+ sumReal -= (q31_t) b *d;
+ sumImag += (q31_t) b *c;
+ /* update pointer */
+ pInB += 4u;
+#else
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA = *__SIMD32(pInA)++;
+ pSourceB = *__SIMD32(pInB)++;
+
+ /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+ prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+ prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+ prod2 = __SMUADX(pSourceA, pSourceB);
+ sumReal += (q63_t) prod1;
+ sumImag += (q63_t) prod2;
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA = *__SIMD32(pInA)++;
+ pSourceB = *__SIMD32(pInB)++;
+
+ /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+ prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+ prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+ prod2 = __SMUADX(pSourceA, pSourceB);
+ sumReal += (q63_t) prod1;
+ sumImag += (q63_t) prod2;
+
+#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* process odd column samples */
+ if((numColsA & 0x1u) > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ a = *pInA++;
+ b = *pInA++;
+ c = *pInB++;
+ d = *pInB++;
+
+ /* Multiply and Accumlates */
+ sumReal += (q31_t) a *c;
+ sumImag += (q31_t) a *d;
+ sumReal -= (q31_t) b *d;
+ sumImag += (q31_t) b *c;
+
+#else
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA = *__SIMD32(pInA)++;
+ pSourceB = *__SIMD32(pInB)++;
+
+ /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+ prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+ prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+ prod2 = __SMUADX(pSourceA, pSourceB);
+ sumReal += (q63_t) prod1;
+ sumImag += (q63_t) prod2;
+
+#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+ }
+
+ /* Saturate and store the result in the destination buffer */
+
+ *px++ = (q15_t) (__SSAT(sumReal >> 15, 16));
+ *px++ = (q15_t) (__SSAT(sumImag >> 15, 16));
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ i = i + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
@@ -0,0 +1,293 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_cmplx_mult_q31.c
+*
+* Description: Floating-point matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup CmplxMatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 Complex matrix multiplication
+ * @param[in] *pSrcA points to the first input complex matrix structure
+ * @param[in] *pSrcB points to the second input complex matrix structure
+ * @param[out] *pDst points to output complex matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit. There is no saturation
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and
+ * distorts the result. The input signals should be scaled down to avoid intermediate
+ * overflows. The input is thus scaled down by log2(numColsA) bits
+ * to avoid overflows, as a total of numColsA additions are performed internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ *
+ */
+
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ q63_t sumReal1, sumImag1; /* accumulator */
+ q31_t a0, b0, c0, d0;
+ q31_t a1, b1, c1, d1;
+
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + 2 * i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sumReal1 = 0.0;
+ sumImag1 = 0.0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+
+ /* Reading real part of complex matrix A */
+ a0 = *pIn1;
+
+ /* Reading real part of complex matrix B */
+ c0 = *pIn2;
+
+ /* Reading imaginary part of complex matrix A */
+ b0 = *(pIn1 + 1u);
+
+ /* Reading imaginary part of complex matrix B */
+ d0 = *(pIn2 + 1u);
+
+ /* Multiply and Accumlates */
+ sumReal1 += (q63_t) a0 *c0;
+ sumImag1 += (q63_t) b0 *c0;
+
+ /* update pointers */
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal1 -= (q63_t) b0 *d0;
+ sumImag1 += (q63_t) a0 *d0;
+
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ a1 = *pIn1;
+ c1 = *pIn2;
+ b1 = *(pIn1 + 1u);
+ d1 = *(pIn2 + 1u);
+
+ /* Multiply and Accumlates */
+ sumReal1 += (q63_t) a1 *c1;
+ sumImag1 += (q63_t) b1 *c1;
+
+ /* update pointers */
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal1 -= (q63_t) b1 *d1;
+ sumImag1 += (q63_t) a1 *d1;
+
+ a0 = *pIn1;
+ c0 = *pIn2;
+
+ b0 = *(pIn1 + 1u);
+ d0 = *(pIn2 + 1u);
+
+ /* Multiply and Accumlates */
+ sumReal1 += (q63_t) a0 *c0;
+ sumImag1 += (q63_t) b0 *c0;
+
+ /* update pointers */
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal1 -= (q63_t) b0 *d0;
+ sumImag1 += (q63_t) a0 *d0;
+
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+
+ a1 = *pIn1;
+ c1 = *pIn2;
+
+ b1 = *(pIn1 + 1u);
+ d1 = *(pIn2 + 1u);
+
+ /* Multiply and Accumlates */
+ sumReal1 += (q63_t) a1 *c1;
+ sumImag1 += (q63_t) b1 *c1;
+
+ /* update pointers */
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal1 -= (q63_t) b1 *d1;
+ sumImag1 += (q63_t) a1 *d1;
+
+ /* Decrement the loop count */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ a1 = *pIn1;
+ c1 = *pIn2;
+
+ b1 = *(pIn1 + 1u);
+ d1 = *(pIn2 + 1u);
+
+ /* Multiply and Accumlates */
+ sumReal1 += (q63_t) a1 *c1;
+ sumImag1 += (q63_t) b1 *c1;
+
+ /* update pointers */
+ pIn1 += 2u;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal1 -= (q63_t) b1 *d1;
+ sumImag1 += (q63_t) a1 *d1;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Store the result in the destination buffer */
+ *px++ = (q31_t) clip_q63_to_q31(sumReal1 >> 31);
+ *px++ = (q31_t) clip_q63_to_q31(sumImag1 >> 31);
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + 2u * j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + 2 * numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_f32.c
+*
+* Description: Floating-point matrix initialization.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ * Initializes the underlying matrix data structure.
+ * The functions set the numRows,
+ * numCols, and pData fields
+ * of the matrix data structure.
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_q15.c
+*
+* Description: Q15 matrix initialization.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_q31.c
+*
+* Description: Q31 matrix initialization.
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,703 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_inverse_f32.c
+*
+* Description: Floating-point matrix inverse.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInv Matrix Inverse
+ *
+ * Computes the inverse of a matrix.
+ *
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant
+ * is non-zero). The function checks that the input and output matrices are square and of the
+ * same size.
+ *
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
+ * inversion of floating-point matrices.
+ *
+ * \par Algorithm
+ * The Gauss-Jordan method is used to find the inverse.
+ * The algorithm performs a sequence of elementary row-operations until it
+ * reduces the input matrix to an identity matrix. Applying the same sequence
+ * of elementary row-operations to an identity matrix yields the inverse matrix.
+ * If the input matrix is singular, then the algorithm terminates and returns error status
+ * ARM_MATH_SINGULAR.
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
+ */
+
+/**
+ * @addtogroup MatrixInv
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *pSrc points to input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size
+ * of the output matrix does not match the size of the input matrix.
+ * If the input matrix is found to be singular (non-invertible), then the function returns
+ * ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS.
+ */
+
+arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */
+ float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */
+ float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */
+ uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */
+ uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float32_t maxC; /* maximum value in the column */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t Xchg, in = 0.0f, in1; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _
+ * | a11 a12 | 1 0 | | X11 X12 |
+ * | | | = | |
+ * |_ a21 a22 | 0 1 _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for column i is the greatest of the column.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is not the most significant of the columns, exchange that row with a row
+ * below it that does contain the most significant value in column i. If the most
+ * significant value of the column is zero, then an inverse to that matrix does not exist.
+ * The most significant value of the column is the absolute maximum.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
+ * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pOutT1 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pOutT1++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pOutT1 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Grab the most significant value from column l */
+ maxC = 0;
+ for (i = l; i < numRows; i++)
+ {
+ maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+ pInT1 += numCols;
+ }
+
+ /* Update the status if the matrix is singular */
+ if(maxC == 0.0f)
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Restore pInT1 */
+ pInT1 = pIn;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Check if the pivot element is the most significant of the column */
+ if( (in > 0.0f ? in : -in) != maxC)
+ {
+ /* Loop over the number rows present below */
+ i = numRows - (l + 1u);
+
+ while(i > 0u)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pOutT2 = pOutT1 + (numCols * k);
+
+ /* Look for the most significant element to
+ * replace in the rows below */
+ if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = numCols - l;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the destination matrix */
+ Xchg = *pOutT2;
+ *pOutT2++ = *pOutT1;
+ *pOutT1++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pInT2 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *pPivotRowIn;
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ in1 = *pInT1;
+ *pInT1++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ in1 = *pInT2;
+ *pInT2++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pInT2 = pOut;
+
+ /* index used to check for pivot element */
+ i = 0u;
+
+ /* Loop over number of rows */
+ /* to be replaced by the sum of that row and a multiple of row i */
+ k = numRows;
+
+ while(k > 0u)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+
+ pInT2 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT1;
+ *pInT1++ = in1 - (in * *pPRT_in++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT2;
+ *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ }
+
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+
+ /* Decrement the loop counter */
+ k--;
+
+ /* Increment the pivot index */
+ i++;
+ }
+
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t Xchg, in = 0.0f; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _ _ _ _ _
+ * | | a11 a12 | | | 1 0 | | | X11 X12 |
+ * | | | | | | | = | |
+ * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for row i is zero.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is zero, exchange that row with a row below it that does not
+ * contain a zero in column i. If this is not possible, then an inverse
+ * to that matrix does not exist.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, src).
+ * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pOutT1 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pOutT1++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+ //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pOutT1 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Check if the pivot element is zero */
+ if(*pInT1 == 0.0f)
+ {
+ /* Loop over the number rows present below */
+ for (i = (l + 1u); i < numRows; i++)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pOutT2 = pOutT1 + (numCols * k);
+
+ /* Check if there is a non zero pivot element to
+ * replace in the rows below */
+ if(*pInT2 != 0.0f)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+ }
+
+ for (j = 0u; j < numCols; j++)
+ {
+ Xchg = *pOutT2;
+ *pOutT2++ = *pOutT1;
+ *pOutT1++ = Xchg;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pOutT1 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *(pIn + (l * numCols));
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ *pInT1 = *pInT1 / in;
+ pInT1++;
+ }
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ *pOutT1 = *pOutT1 / in;
+ pOutT1++;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pOutT1 = pOut;
+
+ for (i = 0u; i < numRows; i++)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+ pOutT1 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pInT1 = *pInT1 - (in * *pPRT_in++);
+ pInT1++;
+ }
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
+ pOutT1++;
+ }
+
+ }
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+ }
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ if((flag != 1u) && (in == 0.0f))
+ {
+ pIn = pSrc->pData;
+ for (i = 0; i < numRows * numCols; i++)
+ {
+ if (pIn[i] != 0.0f)
+ break;
+ }
+
+ if (i == numRows * numCols)
+ status = ARM_MATH_SINGULAR;
+ }
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixInv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c
@@ -0,0 +1,703 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_inverse_f64.c
+*
+* Description: Floating-point matrix inverse.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInv Matrix Inverse
+ *
+ * Computes the inverse of a matrix.
+ *
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant
+ * is non-zero). The function checks that the input and output matrices are square and of the
+ * same size.
+ *
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
+ * inversion of floating-point matrices.
+ *
+ * \par Algorithm
+ * The Gauss-Jordan method is used to find the inverse.
+ * The algorithm performs a sequence of elementary row-operations until it
+ * reduces the input matrix to an identity matrix. Applying the same sequence
+ * of elementary row-operations to an identity matrix yields the inverse matrix.
+ * If the input matrix is singular, then the algorithm terminates and returns error status
+ * ARM_MATH_SINGULAR.
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
+ */
+
+/**
+ * @addtogroup MatrixInv
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *pSrc points to input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size
+ * of the output matrix does not match the size of the input matrix.
+ * If the input matrix is found to be singular (non-invertible), then the function returns
+ * ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS.
+ */
+
+arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * pSrc,
+ arm_matrix_instance_f64 * pDst)
+{
+ float64_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float64_t *pOut = pDst->pData; /* output data matrix pointer */
+ float64_t *pInT1, *pInT2; /* Temporary input data matrix pointer */
+ float64_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */
+ float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */
+ uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */
+ uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float64_t maxC; /* maximum value in the column */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float64_t Xchg, in = 0.0f, in1; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _
+ * | a11 a12 | 1 0 | | X11 X12 |
+ * | | | = | |
+ * |_ a21 a22 | 0 1 _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for column i is the greatest of the column.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is not the most significant of the columns, exchange that row with a row
+ * below it that does contain the most significant value in column i. If the most
+ * significant value of the column is zero, then an inverse to that matrix does not exist.
+ * The most significant value of the column is the absolute maximum.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
+ * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pOutT1 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pOutT1++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pOutT1 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Grab the most significant value from column l */
+ maxC = 0;
+ for (i = l; i < numRows; i++)
+ {
+ maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+ pInT1 += numCols;
+ }
+
+ /* Update the status if the matrix is singular */
+ if(maxC == 0.0f)
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Restore pInT1 */
+ pInT1 = pIn;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Check if the pivot element is the most significant of the column */
+ if( (in > 0.0f ? in : -in) != maxC)
+ {
+ /* Loop over the number rows present below */
+ i = numRows - (l + 1u);
+
+ while(i > 0u)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pOutT2 = pOutT1 + (numCols * k);
+
+ /* Look for the most significant element to
+ * replace in the rows below */
+ if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = numCols - l;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the destination matrix */
+ Xchg = *pOutT2;
+ *pOutT2++ = *pOutT1;
+ *pOutT1++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pInT2 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *pPivotRowIn;
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ in1 = *pInT1;
+ *pInT1++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ in1 = *pInT2;
+ *pInT2++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pInT2 = pOut;
+
+ /* index used to check for pivot element */
+ i = 0u;
+
+ /* Loop over number of rows */
+ /* to be replaced by the sum of that row and a multiple of row i */
+ k = numRows;
+
+ while(k > 0u)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+
+ pInT2 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT1;
+ *pInT1++ = in1 - (in * *pPRT_in++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT2;
+ *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ }
+
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+
+ /* Decrement the loop counter */
+ k--;
+
+ /* Increment the pivot index */
+ i++;
+ }
+
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float64_t Xchg, in = 0.0f; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _ _ _ _ _
+ * | | a11 a12 | | | 1 0 | | | X11 X12 |
+ * | | | | | | | = | |
+ * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for row i is zero.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is zero, exchange that row with a row below it that does not
+ * contain a zero in column i. If this is not possible, then an inverse
+ * to that matrix does not exist.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, src).
+ * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pOutT1 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pOutT1++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pOutT1++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+ //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pOutT1 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Check if the pivot element is zero */
+ if(*pInT1 == 0.0f)
+ {
+ /* Loop over the number rows present below */
+ for (i = (l + 1u); i < numRows; i++)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pOutT2 = pOutT1 + (numCols * k);
+
+ /* Check if there is a non zero pivot element to
+ * replace in the rows below */
+ if(*pInT2 != 0.0f)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+ }
+
+ for (j = 0u; j < numCols; j++)
+ {
+ Xchg = *pOutT2;
+ *pOutT2++ = *pOutT1;
+ *pOutT1++ = Xchg;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pOutT1 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *(pIn + (l * numCols));
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ *pInT1 = *pInT1 / in;
+ pInT1++;
+ }
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ *pOutT1 = *pOutT1 / in;
+ pOutT1++;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pOutT1 = pOut;
+
+ for (i = 0u; i < numRows; i++)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+ pOutT1 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pInT1 = *pInT1 - (in * *pPRT_in++);
+ pInT1++;
+ }
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
+ pOutT1++;
+ }
+
+ }
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+ }
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ if((flag != 1u) && (in == 0.0f))
+ {
+ pIn = pSrc->pData;
+ for (i = 0; i < numRows * numCols; i++)
+ {
+ if (pIn[i] != 0.0f)
+ break;
+ }
+
+ if (i == numRows * numCols)
+ status = ARM_MATH_SINGULAR;
+ }
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixInv group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_f32.c
+*
+* Description: Floating-point matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixMult Matrix Multiplication
+ *
+ * Multiplies two matrices.
+ *
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"
+
+ * Matrix multiplication is only defined if the number of columns of the
+ * first matrix equals the number of rows of the second matrix.
+ * Multiplying an M x N matrix with an N x P matrix results
+ * in an M x P matrix.
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
+ * pSrcA and pSrcB are equal; and (2) that the size of the output
+ * matrix equals the outer dimensions of pSrcA and pSrcB.
+ */
+
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ float32_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t in1, in2, in3, in4;
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0.0f;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2u;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ in3 = *pIn2;
+ pIn2 += numColsB;
+ in1 = pIn1[0];
+ in2 = pIn1[1];
+ sum += in1 * in3;
+ in4 = *pIn2;
+ pIn2 += numColsB;
+ sum += in2 * in4;
+
+ in3 = *pIn2;
+ pIn2 += numColsB;
+ in1 = pIn1[2];
+ in2 = pIn1[3];
+ sum += in1 * in3;
+ in4 = *pIn2;
+ pIn2 += numColsB;
+ sum += in2 * in4;
+ pIn1 += 4u;
+
+ /* Decrement the loop count */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pIn1++ * (*pIn2);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Store the result in the destination buffer */
+ *px++ = sum;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0.0f;
+
+ /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pIn1++ * (*pIn2);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Store the result in the destination buffer */
+ *px++ = sum;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_fast_q15.c
+*
+* Description: Q15 matrix multiplication (fast variant)
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.15 x 1.15 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 16 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See arm_mat_mult_q15() for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState)
+{
+ q31_t sum; /* accumulator */
+ q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t inA1, inA2, inB1, inB2;
+
+#else
+
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t inA1, inA2, inB1, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pSrcBT + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#else
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pInB++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Reset the variables for the usage in the following multiplication process */
+ row = numRowsA;
+ i = 0u;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pInA = pSrcA->pData + i;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ inA1 = *__SIMD32(pInA)++;
+ inB1 = *__SIMD32(pInB)++;
+ inA2 = *__SIMD32(pInA)++;
+ inB2 = *__SIMD32(pInB)++;
+
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+#else
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ inA2 = *pInA++;
+ sum += inA1 * inB1;
+ inB2 = *pInB++;
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ sum += inA2 * inB2;
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+
+ sum += inA1 * inB1;
+ sum += inA2 * inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* process odd column samples */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += (q31_t) (*pInA++) * (*pInB++);
+
+ colCnt--;
+ }
+
+ /* Saturate and store the result in the destination buffer */
+ *px = (q15_t) (sum >> 15);
+ px++;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ i = i + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_fast_q31.c
+*
+* Description: Q31 matrix multiplication (fast variant).
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.31 x 1.31 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See arm_mat_mult_q31() for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+// q31_t *pSrcB = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ q31_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ inB1 = *pIn2;
+ pIn2 += numColsB;
+
+ inA1 = pIn1[0];
+ inA2 = pIn1[1];
+
+ inB2 = *pIn2;
+ pIn2 += numColsB;
+
+ inB3 = *pIn2;
+ pIn2 += numColsB;
+
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);
+
+ inA3 = pIn1[2];
+ inA4 = pIn1[3];
+
+ inB4 = *pIn2;
+ pIn2 += numColsB;
+
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);
+
+ pIn1 += 4u;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+ *px++ = sum << 1;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,469 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_q15.c
+*
+* Description: Q15 matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results (Unused)
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to
+ * 1.15 format.
+ *
+ * \par
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState CMSIS_UNUSED)
+{
+ q63_t sum; /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
+
+#else
+
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t inA1, inB1, inA2, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pSrcBT + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+#else
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pInB++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Reset the variables for the usage in the following multiplication process */
+ row = numRowsA;
+ i = 0u;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pInA = pSrcA->pData + i;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA1 = *__SIMD32(pInA)++;
+ pSourceB1 = *__SIMD32(pInB)++;
+
+ pSourceA2 = *__SIMD32(pInA)++;
+ pSourceB2 = *__SIMD32(pInB)++;
+
+ /* Multiply and Accumlates */
+ sum = __SMLALD(pSourceA1, pSourceB1, sum);
+ sum = __SMLALD(pSourceA2, pSourceB2, sum);
+
+#else
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ inA2 = *pInA++;
+ /* Multiply and Accumlates */
+ sum += inA1 * inB1;
+ inB2 = *pInB++;
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ /* Multiply and Accumlates */
+ sum += inA2 * inB2;
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+
+ /* Multiply and Accumlates */
+ sum += inA1 * inB1;
+ sum += inA2 * inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* process remaining column samples */
+ colCnt = numColsA & 3u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pInA++ * *pInB++;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Saturate and store the result in the destination buffer */
+ *px = (q15_t) (__SSAT((sum >> 15), 16));
+ px++;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ i = i + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q31_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+ /* Saturate and store the result in the destination buffer */
+ *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+ /* Update the pointer pSrcA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,294 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_q31.c
+*
+* Description: Q31 matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit. There is no saturation
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and
+ * distorts the result. The input signals should be scaled down to avoid intermediate
+ * overflows. The input is thus scaled down by log2(numColsA) bits
+ * to avoid overflows, as a total of numColsA additions are performed internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ q63_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ q31_t a0, a1, a2, a3, b0, b1, b2, b3;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ b0 = *pIn2;
+ pIn2 += numColsB;
+
+ a0 = *pIn1++;
+ a1 = *pIn1++;
+
+ b1 = *pIn2;
+ pIn2 += numColsB;
+ b2 = *pIn2;
+ pIn2 += numColsB;
+
+ sum += (q63_t) a0 *b0;
+ sum += (q63_t) a1 *b1;
+
+ a2 = *pIn1++;
+ a3 = *pIn1++;
+
+ b3 = *pIn2;
+ pIn2 += numColsB;
+
+ sum += (q63_t) a2 *b2;
+ sum += (q63_t) a3 *b3;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+ *px++ = (q31_t) (sum >> 31);
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = (pSrcB->pData) + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+ *px++ = (q31_t) clip_q63_to_q31(sum >> 31);
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+#endif
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_f32.c
+*
+* Description: Multiplies a floating-point matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixScale Matrix Scale
+ *
+ * Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the
+ * matrix by the scalar. For example:
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"
+ *
+ * The function checks to make sure that the input and output matrices are of the same size.
+ *
+ * In the fixed-point Q15 and Q31 functions, scale is represented by
+ * a fractional multiplication scaleFract and an arithmetic shift shift.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The overall scale factor applied to the fixed-point data is
+ *
+ * scale = scaleFract * 2^shift.
+ *
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to input matrix structure
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ */
+
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t in1, in2, in3, in4; /* temporary variables */
+ float32_t out1, out2, out3, out4; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * scale */
+ /* Scaling and results are stored in the destination buffer. */
+ in1 = pIn[0];
+ in2 = pIn[1];
+ in3 = pIn[2];
+ in4 = pIn[3];
+
+ out1 = in1 * scale;
+ out2 = in2 * scale;
+ out3 = in3 * scale;
+ out4 = in4 * scale;
+
+
+ pOut[0] = out1;
+ pOut[1] = out2;
+ pOut[2] = out3;
+ pOut[3] = out4;
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * scale */
+ /* The results are stored in the destination buffer. */
+ *pOut++ = (*pIn++) * scale;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_q15.c
+*
+* Description: Multiplies a Q15 matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The input data *pSrc and scaleFract are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = 15 - shift; /* total shift to apply after scaling */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q15_t in1, in2, in3, in4;
+ q31_t out1, out2, out3, out4;
+ q31_t inA1, inA2;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif // #ifdef ARM_MATH_MATRIX_CHECK
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ /* Reading 2 inputs from memory */
+ inA1 = _SIMD32_OFFSET(pIn);
+ inA2 = _SIMD32_OFFSET(pIn + 2);
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the 2 results in the destination buffer
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+ out1 = out1 >> totShift;
+ inA1 = _SIMD32_OFFSET(pIn + 4);
+ out2 = out2 >> totShift;
+ inA2 = _SIMD32_OFFSET(pIn + 6);
+ out3 = out3 >> totShift;
+ out4 = out4 >> totShift;
+
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
+ _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ *pOut++ =
+ (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_q31.c
+*
+* Description: Multiplies a Q31 matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The input data *pSrc and scaleFract are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = shift + 1; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+ q31_t in1, in2, out1; /* temporary variabels */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in3, in4, out2, out3, out4; /* temporary variables */
+
+#endif // #ifndef ARM_MAT_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif // #ifdef ARM_MATH_MATRIX_CHECK
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Read values from input */
+ in1 = *pIn;
+ in2 = *(pIn + 1);
+ in3 = *(pIn + 2);
+ in4 = *(pIn + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 << totShift;
+ out2 = in2 << totShift;
+
+ /* saturate the results. */
+ if(in1 != (out1 >> totShift))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> totShift))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ out3 = in3 << totShift;
+ out4 = in4 << totShift;
+
+ *pOut = out1;
+ *(pOut + 1) = out2;
+
+ if(in3 != (out3 >> totShift))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> totShift))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+
+ *(pOut + 2) = out3;
+ *(pOut + 3) = out4;
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ in1 = *pIn++;
+
+ in2 = ((q63_t) in1 * scaleFract) >> 32;
+
+ out1 = in2 << totShift;
+
+ if(in2 != (out1 >> totShift))
+ out1 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ *pOut++ = out1;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_f32.c
+*
+* Description: Floating-point matrix subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixSub Matrix Subtraction
+ *
+ * Subtract two matrices.
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * pSrcA, pSrcB, and pDst have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* out = sourceA - sourceB */
+ out1 = inA1 - inB1;
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* out = sourceA - sourceB */
+ out2 = inA2 - inB2;
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* out = sourceA - sourceB */
+ out1 = inA1 - inB1;
+
+
+ /* out = sourceA - sourceB */
+ out2 = inA2 - inB2;
+
+ /* Store result in destination */
+ pOut[2] = out1;
+
+ /* Store result in destination */
+ pOut[3] = out2;
+
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (*pIn1++) - (*pIn2++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_q15.c
+*
+* Description: Q15 Matrix subtraction
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix subtraction.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Apply loop unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, Saturate and then store the results in the destination buffer. */
+ *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+ *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_q31.c
+*
+* Description: Q31 matrix subtraction
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix subtraction.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t inA1, inB1; /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t inA2, inB2; /* temporary variables */
+ q31_t out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, saturate and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* Subtract and saturate */
+ out1 = __QSUB(inA1, inB1);
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* Subtract and saturate */
+ out2 = __QSUB(inA2, inB2);
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* Subtract and saturate */
+ out1 = __QSUB(inA1, inB1);
+
+ /* Subtract and saturate */
+ out2 = __QSUB(inA2, inB2);
+
+ /* Store result in destination */
+ pOut[2] = out1;
+ pOut[3] = out2;
+
+ /* update pointers to process next samples */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, saturate and then store the results in the destination buffer. */
+ inA1 = *pIn1++;
+ inB1 = *pIn2++;
+
+ inA1 = __QSUB(inA1, inB1);
+
+ *pOut++ = inA1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,218 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_f32.c
+*
+* Description: Floating-point matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @defgroup MatrixTrans Matrix Transpose
+ *
+ * Tranposes a matrix.
+ * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of rows */
+ uint16_t nColumns = pSrc->numCols; /* number of columns */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* Loop Unrolling */
+ blkCnt = nColumns >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u) /* column loop */
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ blkCnt = nColumns % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ uint16_t col, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u); /* row loop end */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_q15.c
+*
+* Description: Q15 matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of nRows */
+ uint16_t nColumns = pSrc->numCols; /* number of nColumns */
+ uint16_t col, row = nRows, i = 0u; /* row and column loop counters */
+ arm_status status; /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* variable to hold temporary output */
+
+#else
+
+ q15_t in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = nColumns >> 2u;
+
+ /* The pointer pOut is set to starting address of the column being processed */
+ pOut = pDst->pData + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pSrcA)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) in;
+
+#else
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *pOut = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ in = *__SIMD32(pSrcA)++;
+
+#else
+
+ in = *__SIMD32(pSrcA)++;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) in;
+
+#else
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *pOut = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#else
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ col = nColumns % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer pOut is set to starting address of the column being processed */
+ pOut = pDst->pData + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *pOut = *pSrcA++;
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_q31.c
+*
+* Description: Q31 matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of nRows */
+ uint16_t nColumns = pSrc->numCols; /* number of nColumns */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ blkCnt = nColumns >> 2u;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ blkCnt = nColumns % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ uint16_t col, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ }
+ while(row > 0u); /* row loop end */
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_f32.c
+*
+* Description: Maximum value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Max Maximum
+ *
+ * Computes the maximum value of an array of data.
+ * The function returns both the maximum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q15.c
+*
+* Description: Maximum value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q31.c
+*
+* Description: Maximum value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q31_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q7.c
+*
+* Description: Maximum value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q7_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_f32.c
+*
+* Description: Mean value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup mean Mean
+ *
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.
+ * The underlying algorithm is used:
+ *
+ *
+ * Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+ *
+ *
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ */
+
+
+void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ sum += in1;
+ sum += in2;
+ sum += in3;
+ sum += in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = sum / (float32_t) blockSize;
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q15.c
+*
+* Description: Mean value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.15 format and is accumulated in a 32-bit
+ * accumulator in 17.15 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.
+ *
+ */
+
+
+void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q15_t) (sum / (q31_t)blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q31.c
+*
+* Description: Mean value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *\par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format and is accumulated in a 64-bit
+ * accumulator in 33.31 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.
+ *
+ */
+
+
+void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ sum += in1;
+ sum += in2;
+ sum += in3;
+ sum += in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q7.c
+*
+* Description: Mean value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format and is accumulated in a 32-bit
+ * accumulator in 25.7 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.
+ *
+ */
+
+
+void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = *__SIMD32(pSrc)++;
+
+ sum += ((in << 24) >> 24);
+ sum += ((in << 16) >> 24);
+ sum += ((in << 8) >> 24);
+ sum += (in >> 24);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_f32.c
+*
+* Description: Minimum value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Min Minimum
+ *
+ * Computes the minimum value of an array of data.
+ * The function returns both the minimum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q15.c
+*
+* Description: Minimum value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q31.c
+*
+* Description: Minimum value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q31_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q7.c
+*
+* Description: Minimum value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+
+
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_f32.c
+*
+* Description: Sum of the squares of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup power Power
+ *
+ * Calculates the sum of the squares of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ *
+ * Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+ *
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* accumulator */
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* compute power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result to the destination */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q15.c
+*
+* Description: Sum of the squares of the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 34.30 format.
+ *
+ */
+
+void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in32; /* Temporary variable to store input value */
+ q15_t in16; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in32 = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in32, in32, sum);
+ in32 = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in32, in32, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in16 = *pSrc++;
+ sum = __SMLALD(in16, in16, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the results in 34.30 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q31.c
+*
+* Description: Sum of the squares of the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format.
+ * Intermediate multiplication yields a 2.62 format, and this
+ * result is truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 16.48 format.
+ *
+ */
+
+void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ q31_t in;
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the results in 16.48 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q7.c
+*
+* Description: Sum of the squares of the elements of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format.
+ * Intermediate multiplication yields a 2.14 format, and this
+ * result is added without saturation to an accumulator in 18.14 format.
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 18.14 format.
+ *
+ */
+
+void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ q7_t in; /* Temporary variable to store input */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t input1; /* Temporary variable to store packed input */
+ q31_t in1, in2; /* Temporary variables to store input */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading two inputs of pSrc vector and packing */
+ input1 = *__SIMD32(pSrc)++;
+
+ in1 = __SXTB16(__ROR(input1, 8));
+ in2 = __SXTB16(input1);
+
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* calculate power and accumulate to accumulator */
+ sum = __SMLAD(in1, in1, sum);
+ sum = __SMLAD(in2, in2, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result in 18.14 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_f32.c
+*
+* Description: Root mean square value of an array of F32 type
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup RMS Root mean square (RMS)
+ *
+ *
+ * Calculates the Root Mean Sqaure of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ *
+ * Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+ *
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ */
+
+void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Accumulator */
+ float32_t in; /* Tempoprary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the result in a temporary variable, sum */
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Rms and store the result in the destination */
+ arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_q15.c
+*
+* Description: Root Mean Square of the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ *
+ */
+
+void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q63_t sum = 0; /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* temporary variable to store the input value */
+ q15_t in1; /* temporary variable to store the input value */
+ uint32_t blkCnt; /* loop counter */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in, in, sum);
+ in = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in, in, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in1 = *pSrc++;
+ sum = __SMLALD(in1, in1, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Truncating and saturating the accumulator to 1.15 format */
+ /* Store the result in the destination */
+ arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* temporary variable to store the input value */
+ uint32_t blkCnt; /* loop counter */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Truncating and saturating the accumulator to 1.15 format */
+ /* Store the result in the destination */
+ arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_q31.c
+*
+* Description: Root Mean Square of the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows, it wraps around and distorts the result.
+ * In order to avoid overflows completely, the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* accumulator */
+ q31_t in; /* Temporary variable to store the input */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the result in a temporary variable, sum */
+ /* read two samples from source buffer */
+ in1 = pSrc[0];
+ in2 = pSrc[1];
+
+ /* calculate power and accumulate to accumulator */
+ sum += (q63_t) in1 *in1;
+ sum += (q63_t) in2 *in2;
+
+ /* read two samples from source buffer */
+ in3 = pSrc[2];
+ in4 = pSrc[3];
+
+ /* calculate power and accumulate to accumulator */
+ sum += (q63_t) in3 *in3;
+ sum += (q63_t) in4 *in4;
+
+
+ /* update source buffer to process next samples */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += (q63_t) in *in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
+ /* Compute Rms and store the result in the destination vector */
+ arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_f32.c
+*
+* Description: Standard deviation of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup STD Standard deviation
+ *
+ * Calculates the standard deviation of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ *
+ * Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+ *
+ * where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ *
+ * sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+ *
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t sumOfSquares = 0.0f; /* Sum of squares */
+ float32_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t meanOfSquares, mean, squareOfMean;
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+ /* Compute mean of all input values */
+ mean = sum / (float32_t) blockSize;
+
+ /* Compute square of mean */
+ squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+ ((float32_t) blockSize - 1.0f));
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t squareOfSum; /* Square of Sum */
+ float32_t var; /* Temporary varaince storage */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += in * in;
+
+ /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+ /* Compute Sum of the input samples
+ * and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute the square of sum */
+ squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+ /* Compute the variance */
+ var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_q15.c
+*
+* Description: Standard deviation of an array of Q15 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ uint32_t blkCnt; /* loop counter */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* input value */
+ q15_t in1; /* input value */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in1 = *pSrc++;
+ sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+ sum += in1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1));
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) ((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+ /* mean of the squares minus the square of the mean. */
+ /* Compute standard deviation and store the result to the destination */
+ arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15, 16u), pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t in; /* input value */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1));
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) ((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+ /* mean of the squares minus the square of the mean. */
+ /* Compute standard deviation and store the result to the destination */
+ arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15, 16u), pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_q31.c
+*
+* Description: Standard deviation of an array of Q31 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, which is then downshifted by 8 bits
+ * which yields 1.23, and intermediate multiplication yields a 2.46 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a 16 guard bits.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
+ * After division, internal variables should be Q18.46
+ * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
+ *
+ */
+
+
+void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* Accumulator */
+ q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q31_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++ >> 8;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Compute square of mean */
+ squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15, pResult);
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_f32.c
+*
+* Description: Variance of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup variance Variance
+ *
+ * Calculates the variance of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ *
+ * Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)
+ *
+ * where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ *
+ * sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+ *
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t sumOfSquares = 0.0f; /* Sum of squares */
+ float32_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t meanOfSquares, mean, squareOfMean; /* Temporary variables */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+ /* Compute mean of all input values */
+ mean = sum / (float32_t) blockSize;
+
+ /* Compute square of mean */
+ squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+ ((float32_t) blockSize - 1.0f));
+
+ /* Compute variance and then store the result to the destination */
+ *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t squareOfSum; /* Square of Sum */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += in * in;
+
+ /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+ /* Compute Sum of the input samples
+ * and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute the square of sum */
+ squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+ /* Compute the variance */
+ *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_q15.c
+*
+* Description: Variance of an array of Q15 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ *
+ */
+
+
+void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ uint32_t blkCnt; /* loop counter */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* input value */
+ q15_t in1; /* input value */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in1 = *pSrc++;
+ sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+ sum += in1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1));
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+ /* mean of the squares minus the square of the mean. */
+ *pResult = (meanOfSquares - squareOfMean) >> 15;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t in; /* input value */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1));
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
+
+ /* mean of the squares minus the square of the mean. */
+ *pResult = (meanOfSquares - squareOfMean) >> 15;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,187 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_q31.c
+*
+* Description: Variance of an array of Q31 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ * @details
+ * Scaling and Overflow Behavior:
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, which is then downshifted by 8 bits
+ * which yields 1.23, and intermediate multiplication yields a 2.46 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a 16 guard bits.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
+ * After division, internal variables should be Q18.46
+ * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
+ *
+ */
+
+
+void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* Accumulator */
+ q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q31_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+ if(blockSize == 1)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++ >> 8;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++ >> 8;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Compute square of mean */
+ squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
+
+
+ /* Compute standard deviation and then store the result to the destination */
+ *pResult = (meanOfSquares - squareOfMean) >> 15;
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_f32.c
+*
+* Description: Copies the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup copy Vector Copy
+ *
+ * Copies sample by sample from source vector to destination vector.
+ *
+ *
+ * pDst[n] = pSrc[n]; 0 <= n < blockSize.
+ *
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q15.c
+*
+* Description: Copies the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Read two inputs */
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the value in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q31.c
+*
+* Description: Copies the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the values in the destination buffer */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the value in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q7.c
+*
+* Description: Copies the elements of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ /* 4 samples are copied and stored at a time using SIMD */
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_f32.c
+*
+* Description: Fills a constant value into a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup Fill Vector Fill
+ *
+ * Fills the destination vector with a constant value.
+ *
+ *
+ * pDst[n] = value; 0 <= n < blockSize.
+ *
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+
+void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1 = value;
+ float32_t in2 = value;
+ float32_t in3 = value;
+ float32_t in4 = value;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q15.c
+*
+* Description: Fills a constant value into a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t packedValue; /* value packed to 32 bits */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PKHBT(value, value, 16u);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *__SIMD32(pDst)++ = packedValue;
+ *__SIMD32(pDst)++ = packedValue;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q31.c
+*
+* Description: Fills a constant value into a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1 = value;
+ q31_t in2 = value;
+ q31_t in3 = value;
+ q31_t in4 = value;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q7.c
+*
+* Description: Fills a constant value into a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t packedValue; /* value packed to 32 bits */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PACKq7(value, value, value, value);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *__SIMD32(pDst)++ = packedValue;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q15.c
+*
+* Description: Converts the elements of the floating-point vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ * \par
+ * The equation used for the conversion process is:
+ *
+ * pDst[n] = (q15_t)(pSrc[n] * 32768); 0 <= n < blockSize.
+ *
+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ *
+ */
+
+
+void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,211 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q31.c
+*
+* Description: Converts the elements of the floating-point vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup float_to_x Convert 32-bit floating point value
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (q31_t)(pSrc[n] * 2147483648); 0 <= n < blockSize.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ *
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 32768 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q7.c
+*
+* Description: Converts the elements of the floating-point vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ *
+ * pDst[n] = (q7_t)(pSrc[n] * 128); 0 <= n < blockSize.
+ *
+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_float.c
+*
+* Description: Converts the elements of the Q15 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q15_to_x Convert 16-bit Integer value
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (float32_t) pSrc[n] / 32768; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_q31.c
+*
+* Description: Converts the elements of the Q15 vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (q31_t) pSrc[n] << 16; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2;
+ q31_t out1, out2, out3, out4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t)A << 16 */
+ /* convert from q15 to q31 and then store the results in the destination buffer */
+ in1 = *__SIMD32(pIn)++;
+ in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* extract lower 16 bits to 32 bit result */
+ out1 = in1 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out2 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out3 = in2 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out4 = in2 & 0xFFFF0000;
+
+#else
+
+ /* extract upper 16 bits to 32 bit result */
+ out1 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out2 = in1 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out3 = in2 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out4 = in2 << 16u;
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ *pDst++ = out1;
+ *pDst++ = out2;
+ *pDst++ = out3;
+ *pDst++ = out4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t)A << 16 */
+ /* convert from q15 to q31 and then store the results in the destination buffer */
+ *pDst++ = (q31_t) * pIn++ << 16;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_q7.c
+*
+* Description: Converts the elements of the Q15 vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (q7_t) pSrc[n] >> 8; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2;
+ q31_t out1, out2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 8 */
+ /* convert from q15 to q7 and then store the results in the destination buffer */
+ in1 = *__SIMD32(pIn)++;
+ in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHBT(in2, in1, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in1, in2, 16);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* rotate packed value by 24 */
+ out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
+
+ /* anding with 0xff00ff00 to get two 8 bit values */
+ out1 = out1 & 0xFF00FF00;
+ /* anding with 0x00ff00ff to get two 8 bit values */
+ out2 = out2 & 0x00FF00FF;
+
+ /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
+ out1 = out1 | out2;
+
+ /* store 4 samples at a time to destiantion buffer */
+ *__SIMD32(pDst)++ = out1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 8 */
+ /* convert from q15 to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_float.c
+*
+* Description: Converts the elements of the Q31 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q31_to_x Convert 32-bit Integer value
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (float32_t) pSrc[n] / 2147483648; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* convert from q31 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* convert from q31 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_q15.c
+*
+* Description: Converts the elements of the Q31 vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (q15_t) pSrc[n] >> 16; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+ q31_t out1, out2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A >> 16 */
+ /* convert from q31 to q15 and then store the results in the destination buffer */
+ in1 = *pIn++;
+ in2 = *pIn++;
+ in3 = *pIn++;
+ in4 = *pIn++;
+
+ /* pack two higher 16-bit values from two 32-bit values */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHTB(in4, in3, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHTB(in3, in4, 16);
+
+#endif // #ifdef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = out1;
+ *__SIMD32(pDst)++ = out2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A >> 16 */
+ /* convert from q31 to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_q7.c
+*
+* Description: Converts the elements of the Q31 vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (q7_t) pSrc[n] >> 24; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+ q7_t out1, out2, out3, out4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 24 */
+ /* convert from q31 to q7 and then store the results in the destination buffer */
+ in1 = *pIn++;
+ in2 = *pIn++;
+ in3 = *pIn++;
+ in4 = *pIn++;
+
+ out1 = (q7_t) (in1 >> 24);
+ out2 = (q7_t) (in2 >> 24);
+ out3 = (q7_t) (in3 >> 24);
+ out4 = (q7_t) (in4 >> 24);
+
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 24 */
+ /* convert from q31 to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 24);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_float.c
+*
+* Description: Converts the elements of the Q7 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q7_to_x Convert 8-bit Integer value
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (float32_t) pSrc[n] / 128; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 128 */
+ /* convert from q7 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 128 */
+ /* convert from q7 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_q15.c
+*
+* Description: Converts the elements of the Q7 vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (q15_t) pSrc[n] << 8; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ q31_t in;
+ q31_t in1, in2;
+ q31_t out1, out2;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A << 8 */
+ /* convert from q7 to q15 and then store the results in the destination buffer */
+ in = *__SIMD32(pIn)++;
+
+ /* rotatate in by 8 and extend two q7_t values to q15_t values */
+ in1 = __SXTB16(__ROR(in, 8));
+
+ /* extend remainig two q7_t values to q15_t values */
+ in2 = __SXTB16(in);
+
+ in1 = in1 << 8u;
+ in2 = in2 << 8u;
+
+ in1 = in1 & 0xFF00FF00;
+ in2 = in2 & 0xFF00FF00;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out2 = __PKHTB(in1, in2, 16);
+ out1 = __PKHBT(in2, in1, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in2, in1, 16);
+
+#endif
+
+ *__SIMD32(pDst)++ = out1;
+ *__SIMD32(pDst)++ = out2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A << 8 */
+ /* convert from q7 to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) * pIn++ << 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_q31.c
+*
+* Description: Converts the elements of the Q7 vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ *
+ * pDst[n] = (q31_t) pSrc[n] << 24; 0 <= n < blockSize.
+ *
+ *
+ */
+
+
+void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t) A << 24 */
+ /* convert from q7 to q31 and then store the results in the destination buffer */
+ in = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (in & 0xFF000000);
+
+#else
+
+ *pDst++ = (in & 0xFF000000);
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t) A << 24 */
+ /* convert from q7 to q31 and then store the results in the destination buffer */
+ *pDst++ = (q31_t) * pIn++ << 24;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
@@ -0,0 +1,242 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_bitreversal.c
+*
+* Description: This file has common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/*
+* @brief In-place bit reversal function.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftSize length of the FFT.
+* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+* @param[in] *pBitRevTab points to the bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+ uint16_t fftLenBy2, fftLenBy2p1;
+ uint16_t i, j;
+ float32_t in;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftSize >> 1u;
+ fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ in = pSrc[2u * i];
+ pSrc[2u * i] = pSrc[2u * j];
+ pSrc[2u * j] = in;
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[(2u * i) + 1u];
+ pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+ pSrc[(2u * j) + 1u] = in;
+
+ /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+ in = pSrc[2u * (i + fftLenBy2p1)];
+ pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+ pSrc[2u * (j + fftLenBy2p1)] = in;
+
+ /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+ in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[2u * (i + 1u)];
+ pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+ pSrc[2u * (j + fftLenBy2)] = in;
+
+ /* pSrc[i+2u] <-> pSrc[j+2u] */
+ in = pSrc[(2u * (i + 1u)) + 1u];
+ pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+ pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTab;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTab += bitRevFactor;
+ }
+}
+
+
+
+/*
+* @brief In-place bit reversal function.
+* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+* @param[in] *pBitRevTab points to bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTable)
+{
+ uint32_t fftLenBy2, fftLenBy2p1, i, j;
+ q31_t in;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftLen / 2u;
+ fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ in = pSrc[2u * i];
+ pSrc[2u * i] = pSrc[2u * j];
+ pSrc[2u * j] = in;
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[(2u * i) + 1u];
+ pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+ pSrc[(2u * j) + 1u] = in;
+
+ /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+ in = pSrc[2u * (i + fftLenBy2p1)];
+ pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+ pSrc[2u * (j + fftLenBy2p1)] = in;
+
+ /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+ in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[2u * (i + 1u)];
+ pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+ pSrc[2u * (j + fftLenBy2)] = in;
+
+ /* pSrc[i+2u] <-> pSrc[j+2u] */
+ in = pSrc[(2u * (i + 1u)) + 1u];
+ pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+ pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTable;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTable += bitRevFactor;
+ }
+}
+
+
+
+/*
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+*/
+
+void arm_bitreversal_q15(
+q15_t * pSrc16,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+ q31_t *pSrc = (q31_t *) pSrc16;
+ q31_t in;
+ uint32_t fftLenBy2, fftLenBy2p1;
+ uint32_t i, j;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftLen / 2u;
+ fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[i];
+ pSrc[i] = pSrc[j];
+ pSrc[j] = in;
+
+ /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */
+ /* pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+ in = pSrc[i + fftLenBy2p1];
+ pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+ pSrc[j + fftLenBy2p1] = in;
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+fftLenBy2]; */
+ /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1u] */
+ in = pSrc[i + 1u];
+ pSrc[i + 1u] = pSrc[j + fftLenBy2];
+ pSrc[j + fftLenBy2] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTab;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTab += bitRevFactor;
+ }
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c
@@ -0,0 +1,632 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_f32.c
+*
+* Description: Combined Radix Decimation in Frequency CFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern void arm_radix8_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+ uint32_t * pSrc,
+ const uint16_t bitRevLen,
+ const uint16_t * pBitRevTable);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @defgroup ComplexFFT Complex FFT Functions
+*
+* \par
+* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
+* Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster
+* than the DFT, especially for long lengths.
+* The algorithms described in this section
+* operate on complex data. A separate set of functions is devoted to handling
+* of real sequences.
+* \par
+* There are separate algorithms for handling floating-point, Q15, and Q31 data
+* types. The algorithms available for each data type are described next.
+* \par
+* The FFT functions operate in-place. That is, the array holding the input data
+* will also be used to hold the corresponding result. The input data is complex
+* and contains 2*fftLen interleaved values as shown below.
+* {real[0], imag[0], real[1], imag[1],..}
+* The FFT result will be contained in the same array and the frequency domain
+* values will have the same interleaving.
+*
+* \par Floating-point
+* The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8
+* stages are performed along with a single radix-2 or radix-4 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of fftLen when computing the forward transform. The
+* inverse transform includes a scale of 1/fftLen as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Pre-initialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in arm_const_structs.h. Include
+* this header in your function and then pass one of the constant structures as
+* an argument to arm_cfft_f32. For example:
+* \par
+* arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation. The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data. These functions are still
+* provided but are deprecated. The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_f32 function follows:
+* \code
+* const static arm_cfft_instance_f32 *S;
+* ...
+* switch (length) {
+* case 16:
+* S = &arm_cfft_sR_f32_len16;
+* break;
+* case 32:
+* S = &arm_cfft_sR_f32_len32;
+* break;
+* case 64:
+* S = &arm_cfft_sR_f32_len64;
+* break;
+* case 128:
+* S = &arm_cfft_sR_f32_len128;
+* break;
+* case 256:
+* S = &arm_cfft_sR_f32_len256;
+* break;
+* case 512:
+* S = &arm_cfft_sR_f32_len512;
+* break;
+* case 1024:
+* S = &arm_cfft_sR_f32_len1024;
+* break;
+* case 2048:
+* S = &arm_cfft_sR_f32_len2048;
+* break;
+* case 4096:
+* S = &arm_cfft_sR_f32_len4096;
+* break;
+* }
+* \endcode
+* \par Q15 and Q31
+* The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4
+* stages are performed along with a single radix-2 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of fftLen when computing the forward transform. The
+* inverse transform includes a scale of 1/fftLen as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Pre-initialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in arm_const_structs.h. Include
+* this header in your function and then pass one of the constant structures as
+* an argument to arm_cfft_q31. For example:
+* \par
+* arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1)
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation. The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data. These functions are still
+* provided but are deprecated. The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_q31 function follows:
+* \code
+* const static arm_cfft_instance_q31 *S;
+* ...
+* switch (length) {
+* case 16:
+* S = &arm_cfft_sR_q31_len16;
+* break;
+* case 32:
+* S = &arm_cfft_sR_q31_len32;
+* break;
+* case 64:
+* S = &arm_cfft_sR_q31_len64;
+* break;
+* case 128:
+* S = &arm_cfft_sR_q31_len128;
+* break;
+* case 256:
+* S = &arm_cfft_sR_q31_len256;
+* break;
+* case 512:
+* S = &arm_cfft_sR_q31_len512;
+* break;
+* case 1024:
+* S = &arm_cfft_sR_q31_len1024;
+* break;
+* case 2048:
+* S = &arm_cfft_sR_q31_len2048;
+* break;
+* case 4096:
+* S = &arm_cfft_sR_q31_len4096;
+* break;
+* }
+* \endcode
+*
+*/
+
+void arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen;
+ float32_t * pCol1, * pCol2, * pMid1, * pMid2;
+ float32_t * p2 = p1 + L;
+ const float32_t * tw = (float32_t *) S->pTwiddle;
+ float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
+ float32_t m0, m1, m2, m3;
+ uint32_t l;
+
+ pCol1 = p1;
+ pCol2 = p2;
+
+ // Define new length
+ L >>= 1;
+ // Initialize mid pointers
+ pMid1 = p1 + L;
+ pMid2 = p2 + L;
+
+ // do two dot Fourier transform
+ for ( l = L >> 2; l > 0; l-- )
+ {
+ t1[0] = p1[0];
+ t1[1] = p1[1];
+ t1[2] = p1[2];
+ t1[3] = p1[3];
+
+ t2[0] = p2[0];
+ t2[1] = p2[1];
+ t2[2] = p2[2];
+ t2[3] = p2[3];
+
+ t3[0] = pMid1[0];
+ t3[1] = pMid1[1];
+ t3[2] = pMid1[2];
+ t3[3] = pMid1[3];
+
+ t4[0] = pMid2[0];
+ t4[1] = pMid2[1];
+ t4[2] = pMid2[2];
+ t4[3] = pMid2[3];
+
+ *p1++ = t1[0] + t2[0];
+ *p1++ = t1[1] + t2[1];
+ *p1++ = t1[2] + t2[2];
+ *p1++ = t1[3] + t2[3]; // col 1
+
+ t2[0] = t1[0] - t2[0];
+ t2[1] = t1[1] - t2[1];
+ t2[2] = t1[2] - t2[2];
+ t2[3] = t1[3] - t2[3]; // for col 2
+
+ *pMid1++ = t3[0] + t4[0];
+ *pMid1++ = t3[1] + t4[1];
+ *pMid1++ = t3[2] + t4[2];
+ *pMid1++ = t3[3] + t4[3]; // col 1
+
+ t4[0] = t4[0] - t3[0];
+ t4[1] = t4[1] - t3[1];
+ t4[2] = t4[2] - t3[2];
+ t4[3] = t4[3] - t3[3]; // for col 2
+
+ twR = *tw++;
+ twI = *tw++;
+
+ // multiply by twiddle factors
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ // R = R * Tr - I * Ti
+ *p2++ = m0 + m1;
+ // I = I * Tr + R * Ti
+ *p2++ = m2 - m3;
+
+ // use vertical symmetry
+ // 0.9988 - 0.0491i <==> -0.0491 - 0.9988i
+ m0 = t4[0] * twI;
+ m1 = t4[1] * twR;
+ m2 = t4[1] * twI;
+ m3 = t4[0] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+
+ twR = *tw++;
+ twI = *tw++;
+
+ m0 = t2[2] * twR;
+ m1 = t2[3] * twI;
+ m2 = t2[3] * twR;
+ m3 = t2[2] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+
+ m0 = t4[2] * twI;
+ m1 = t4[3] * twR;
+ m2 = t4[3] * twI;
+ m3 = t4[2] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+ }
+
+ // first col
+ arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2u);
+ // second col
+ arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2u);
+}
+
+void arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen >> 1;
+ float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
+ const float32_t *tw2, *tw3, *tw4;
+ float32_t * p2 = p1 + L;
+ float32_t * p3 = p2 + L;
+ float32_t * p4 = p3 + L;
+ float32_t t2[4], t3[4], t4[4], twR, twI;
+ float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
+ float32_t m0, m1, m2, m3;
+ uint32_t l, twMod2, twMod3, twMod4;
+
+ pCol1 = p1; // points to real values by default
+ pCol2 = p2;
+ pCol3 = p3;
+ pCol4 = p4;
+ pEnd1 = p2 - 1; // points to imaginary values by default
+ pEnd2 = p3 - 1;
+ pEnd3 = p4 - 1;
+ pEnd4 = pEnd3 + L;
+
+ tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
+
+ L >>= 1;
+
+ // do four dot Fourier transform
+
+ twMod2 = 2;
+ twMod3 = 4;
+ twMod4 = 6;
+
+ // TOP
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // Twiddle factors are ones
+ *p2++ = t2[0];
+ *p2++ = t2[1];
+ *p3++ = t3[0];
+ *p3++ = t3[1];
+ *p4++ = t4[0];
+ *p4++ = t4[1];
+
+ tw2 += twMod2;
+ tw3 += twMod3;
+ tw4 += twMod4;
+
+ for (l = (L - 2) >> 1; l > 0; l-- )
+ {
+ // TOP
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1 - top
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // BOTTOM
+ p1ap3_1 = pEnd1[-1] + pEnd3[-1];
+ p1sp3_1 = pEnd1[-1] - pEnd3[-1];
+ p1ap3_0 = pEnd1[0] + pEnd3[0];
+ p1sp3_0 = pEnd1[0] - pEnd3[0];
+ // col 2
+ t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1;
+ t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
+ // col 3
+ t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
+ t3[3] = p1ap3_0 - pEnd2[0] - pEnd4[0];
+ // col 4
+ t4[2] = pEnd2[0] - pEnd4[0] - p1sp3_1;
+ t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
+ // col 1 - Bottom
+ *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];
+ *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
+
+ // COL 2
+ // read twiddle factors
+ twR = *tw2++;
+ twI = *tw2++;
+ // multiply by twiddle factors
+ // let Z1 = a + i(b), Z2 = c + i(d)
+ // => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d)
+
+ // Top
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ // use vertical symmetry col 2
+ // 0.9997 - 0.0245i <==> 0.0245 - 0.9997i
+ // Bottom
+ m0 = t2[3] * twI;
+ m1 = t2[2] * twR;
+ m2 = t2[2] * twI;
+ m3 = t2[3] * twR;
+
+ *pEnd2-- = m0 - m1;
+ *pEnd2-- = m2 + m3;
+
+ // COL 3
+ twR = tw3[0];
+ twI = tw3[1];
+ tw3 += twMod3;
+ // Top
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ // use vertical symmetry col 3
+ // 0.9988 - 0.0491i <==> -0.9988 - 0.0491i
+ // Bottom
+ m0 = -t3[3] * twR;
+ m1 = t3[2] * twI;
+ m2 = t3[2] * twR;
+ m3 = t3[3] * twI;
+
+ *pEnd3-- = m0 - m1;
+ *pEnd3-- = m3 - m2;
+
+ // COL 4
+ twR = tw4[0];
+ twI = tw4[1];
+ tw4 += twMod4;
+ // Top
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+ // use vertical symmetry col 4
+ // 0.9973 - 0.0736i <==> -0.0736 + 0.9973i
+ // Bottom
+ m0 = t4[3] * twI;
+ m1 = t4[2] * twR;
+ m2 = t4[2] * twI;
+ m3 = t4[3] * twR;
+
+ *pEnd4-- = m0 - m1;
+ *pEnd4-- = m2 + m3;
+ }
+
+ //MIDDLE
+ // Twiddle factors are
+ // 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1 - Top
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // COL 2
+ twR = tw2[0];
+ twI = tw2[1];
+
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ // COL 3
+ twR = tw3[0];
+ twI = tw3[1];
+
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ // COL 4
+ twR = tw4[0];
+ twI = tw4[1];
+
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+
+ // first col
+ arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4u);
+ // second col
+ arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4u);
+ // third col
+ arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4u);
+ // fourth col
+ arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4u);
+}
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the floating-point complex FFT.
+* @param[in] *S points to an instance of the floating-point CFFT structure.
+* @param[in, out] *p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ uint32_t L = S->fftLen, l;
+ float32_t invL, * pSrc;
+
+ if(ifftFlag == 1u)
+ {
+ /* Conjugate input data */
+ pSrc = p1 + 1;
+ for(l=0; lpTwiddle, 1);
+ break;
+ }
+
+ if( bitReverseFlag )
+ arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
+
+ if(ifftFlag == 1u)
+ {
+ invL = 1.0f/(float32_t)L;
+ /* Conjugate and scale output data */
+ pSrc = p1;
+ for(l=0; l2*fftLen. Processing occurs in-place.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ uint32_t L = S->fftLen;
+
+ if(ifftFlag == 1u)
+ {
+ switch (L)
+ {
+ case 16:
+ case 64:
+ case 256:
+ case 1024:
+ case 4096:
+ arm_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 );
+ break;
+
+ case 32:
+ case 128:
+ case 512:
+ case 2048:
+ arm_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle );
+ break;
+ }
+ }
+ else
+ {
+ switch (L)
+ {
+ case 16:
+ case 64:
+ case 256:
+ case 1024:
+ case 4096:
+ arm_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 );
+ break;
+
+ case 32:
+ case 128:
+ case 512:
+ case 2048:
+ arm_cfft_radix4by2_q15 ( p1, L, S->pTwiddle );
+ break;
+ }
+ }
+
+ if( bitReverseFlag )
+ arm_bitreversal_16((uint16_t*)p1,S->bitRevLength,S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_cfft_radix4by2_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ const q15_t * pCoef)
+{
+ uint32_t i;
+ uint32_t n2;
+ q15_t p0, p1, p2, p3;
+#ifndef ARM_MATH_CM0_FAMILY
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+ const q15_t *pC = pCoef;
+ q15_t *pSi = pSrc;
+ q15_t *pSl = pSrc + fftLen;
+#else
+ uint32_t ia, l;
+ q15_t xt, yt, cosVal, sinVal;
+#endif
+
+ n2 = fftLen >> 1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ for (i = n2; i > 0; i--)
+ {
+ coeff = _SIMD32_OFFSET(pC);
+ pC += 2;
+
+ T = _SIMD32_OFFSET(pSi);
+ T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+
+ S = _SIMD32_OFFSET(pSl);
+ S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
+ pSi += 2;
+
+ #ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+ #else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+ #endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSl) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSl += 2;
+ }
+
+#else // #ifndef ARM_MATH_CM0_FAMILY
+
+ ia = 0;
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia++;
+
+ l = i + n2;
+
+ xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+ }
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ // first col
+ arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2u);
+ // second col
+ arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
+
+ for (i = 0; i < fftLen >> 1; i++)
+ {
+ p0 = pSrc[4*i+0];
+ p1 = pSrc[4*i+1];
+ p2 = pSrc[4*i+2];
+ p3 = pSrc[4*i+3];
+
+ p0 <<= 1;
+ p1 <<= 1;
+ p2 <<= 1;
+ p3 <<= 1;
+
+ pSrc[4*i+0] = p0;
+ pSrc[4*i+1] = p1;
+ pSrc[4*i+2] = p2;
+ pSrc[4*i+3] = p3;
+ }
+}
+
+void arm_cfft_radix4by2_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ const q15_t * pCoef)
+{
+ uint32_t i;
+ uint32_t n2;
+ q15_t p0, p1, p2, p3;
+#ifndef ARM_MATH_CM0_FAMILY
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+ const q15_t *pC = pCoef;
+ q15_t *pSi = pSrc;
+ q15_t *pSl = pSrc + fftLen;
+#else
+ uint32_t ia, l;
+ q15_t xt, yt, cosVal, sinVal;
+#endif
+
+ n2 = fftLen >> 1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ for (i = n2; i > 0; i--)
+ {
+ coeff = _SIMD32_OFFSET(pC);
+ pC += 2;
+
+ T = _SIMD32_OFFSET(pSi);
+ T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+
+ S = _SIMD32_OFFSET(pSl);
+ S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
+ pSi += 2;
+
+ #ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+ #else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+ #endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSl) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSl += 2;
+ }
+
+#else // #ifndef ARM_MATH_CM0_FAMILY
+
+ ia = 0;
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia++;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+ }
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ // first col
+ arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2u);
+ // second col
+ arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
+
+ for (i = 0; i < fftLen >> 1; i++)
+ {
+ p0 = pSrc[4*i+0];
+ p1 = pSrc[4*i+1];
+ p2 = pSrc[4*i+2];
+ p3 = pSrc[4*i+3];
+
+ p0 <<= 1;
+ p1 <<= 1;
+ p2 <<= 1;
+ p3 <<= 1;
+
+ pSrc[4*i+0] = p0;
+ pSrc[4*i+1] = p1;
+ pSrc[4*i+2] = p2;
+ pSrc[4*i+3] = p3;
+ }
+}
+
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c
@@ -0,0 +1,264 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_q31.c
+*
+* Description: Combined Radix Decimation in Frequency CFFT fixed point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+ uint32_t * pSrc,
+ const uint16_t bitRevLen,
+ const uint16_t * pBitRevTable);
+
+void arm_cfft_radix4by2_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ const q31_t * pCoef);
+
+void arm_cfft_radix4by2_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ const q31_t * pCoef);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the fixed-point complex FFT in Q31 format.
+* @param[in] *S points to an instance of the fixed-point CFFT structure.
+* @param[in, out] *p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ uint32_t L = S->fftLen;
+
+ if(ifftFlag == 1u)
+ {
+ switch (L)
+ {
+ case 16:
+ case 64:
+ case 256:
+ case 1024:
+ case 4096:
+ arm_radix4_butterfly_inverse_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 );
+ break;
+
+ case 32:
+ case 128:
+ case 512:
+ case 2048:
+ arm_cfft_radix4by2_inverse_q31 ( p1, L, S->pTwiddle );
+ break;
+ }
+ }
+ else
+ {
+ switch (L)
+ {
+ case 16:
+ case 64:
+ case 256:
+ case 1024:
+ case 4096:
+ arm_radix4_butterfly_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 );
+ break;
+
+ case 32:
+ case 128:
+ case 512:
+ case 2048:
+ arm_cfft_radix4by2_q31 ( p1, L, S->pTwiddle );
+ break;
+ }
+ }
+
+ if( bitReverseFlag )
+ arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_cfft_radix4by2_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ const q31_t * pCoef)
+{
+ uint32_t i, l;
+ uint32_t n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ n2 = fftLen >> 1;
+ ia = 0;
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[2*ia];
+ sinVal = pCoef[2*ia + 1];
+ ia++;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
+ pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
+
+ yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multAcc_32x32_keep32_R(p0, yt, sinVal);
+ multSub_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0 << 1;
+ pSrc[2u * l + 1u] = p1 << 1;
+
+ }
+
+ // first col
+ arm_radix4_butterfly_q31( pSrc, n2, (q31_t*)pCoef, 2u);
+ // second col
+ arm_radix4_butterfly_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
+
+ for (i = 0; i < fftLen >> 1; i++)
+ {
+ p0 = pSrc[4*i+0];
+ p1 = pSrc[4*i+1];
+ xt = pSrc[4*i+2];
+ yt = pSrc[4*i+3];
+
+ p0 <<= 1;
+ p1 <<= 1;
+ xt <<= 1;
+ yt <<= 1;
+
+ pSrc[4*i+0] = p0;
+ pSrc[4*i+1] = p1;
+ pSrc[4*i+2] = xt;
+ pSrc[4*i+3] = yt;
+ }
+
+}
+
+void arm_cfft_radix4by2_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ const q31_t * pCoef)
+{
+ uint32_t i, l;
+ uint32_t n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ n2 = fftLen >> 1;
+ ia = 0;
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[2*ia];
+ sinVal = pCoef[2*ia + 1];
+ ia++;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
+ pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
+
+ yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multSub_32x32_keep32_R(p0, yt, sinVal);
+ multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0 << 1;
+ pSrc[2u * l + 1u] = p1 << 1;
+
+ }
+
+ // first col
+ arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2u);
+ // second col
+ arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
+
+ for (i = 0; i < fftLen >> 1; i++)
+ {
+ p0 = pSrc[4*i+0];
+ p1 = pSrc[4*i+1];
+ xt = pSrc[4*i+2];
+ yt = pSrc[4*i+3];
+
+ p0 <<= 1;
+ p1 <<= 1;
+ xt <<= 1;
+ yt <<= 1;
+
+ pSrc[4*i+0] = p0;
+ pSrc[4*i+1] = p1;
+ pSrc[4*i+2] = xt;
+ pSrc[4*i+3] = yt;
+ }
+}
+
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
@@ -0,0 +1,485 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_f32.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Radix-2 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in] *S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_f32(
+const arm_cfft_radix2_instance_f32 * S,
+float32_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-2 */
+ arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-2 */
+ arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+
+/**
+* @} end of ComplexFFT group
+*/
+
+
+
+/* ----------------------------------------------------------------------
+** Internal helper function used by the FFTs
+** ------------------------------------------------------------------- */
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix2_butterfly_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Initializations for the first stage */
+ n2 = fftLen >> 1;
+ ia = 0;
+ i = 0;
+
+ // loop for groups
+ for (k = n2; k > 0; k--)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ /* Twiddle coefficients index modifier */
+ ia += twidCoefModifier;
+
+ /* index calculation for the input as, */
+ /* pSrc[i + 0], pSrc[i + fftLen/1] */
+ l = i + n2;
+
+ /* Butterfly implementation */
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i++;
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = n2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while( j < n2); // groups loop end
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+ pSrc[2 * i + 2] = xt;
+ pSrc[2 * i + 3] = yt;
+ } // groups loop end
+
+#else
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 1; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while(i < fftLen);
+ j++;
+ } while(j < n2);
+ twidCoefModifier <<= 1u;
+ }
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ n2 = fftLen >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while(j < n2); // groups loop end
+
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2 * i + 1] = p1;
+ pSrc[2 * i + 2] = p2;
+ pSrc[2 * i + 3] = p3;
+ } // butterfly loop end
+
+#else
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while( j < n2 ); // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2u * l] = p2;
+
+ pSrc[2 * i + 1] = p1;
+ pSrc[2u * l + 1u] = p3;
+ } // butterfly loop end
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_f32.c
+*
+* Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 2048u:
+ /* Initializations of structure parameters for 2048 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.00048828125;
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+ case 512u:
+ /* Initializations of structure parameters for 512 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 8u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 8u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.001953125;
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+ S->onebyfftLen = 0.0078125;
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+ S->onebyfftLen = 0.03125;
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_init_q15.c
+*
+* Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
+* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+ break;
+
+ case 2048u:
+ /* Initializations of structure parameters for 2048 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+ S->twidCoefModifier = 4u;
+ S->bitRevFactor = 4u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+ break;
+
+ case 512u:
+ /* Initializations of structure parameters for 512 point FFT */
+ S->twidCoefModifier = 8u;
+ S->bitRevFactor = 8u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 32 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
@@ -0,0 +1,187 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_init_q31.c
+*
+* Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+*
+* @brief Initialization function for the Q31 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of Instance structure depending on the FFT length */
+ switch (S->fftLen)
+ {
+ /* Initializations of structure parameters for 4096 point FFT */
+ case 4096u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ break;
+
+ /* Initializations of structure parameters for 2048 point FFT */
+ case 2048u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+ break;
+
+ /* Initializations of structure parameters for 1024 point FFT */
+ case 1024u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ break;
+
+ /* Initializations of structure parameters for 512 point FFT */
+ case 512u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 8u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 8u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 32 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
@@ -0,0 +1,742 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_q15.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the fixed-point CFFT/CIFFT.
+ * @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
+ * @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+ * @return none.
+ */
+
+void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+ else
+ {
+ arm_radix2_butterfly_q15(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+
+ arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t in;
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 1;
+ T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 1;
+ S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i++;
+ l++;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 1;
+ T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 1;
+ S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ i += n1;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ i += n1;
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ } // groups loop end
+
+
+#else
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t xt, yt, cosVal, sinVal;
+
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t in;
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 1;
+ T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 1;
+ S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i++;
+ l++;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 1;
+ T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 1;
+ S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ i += n1;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+#else
+
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t xt, yt, cosVal, sinVal;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // groups loop end
+
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
@@ -0,0 +1,351 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_q31.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the fixed-point CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_q31(
+const arm_cfft_radix2_instance_q31 * S,
+q31_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+ else
+ {
+ arm_radix2_butterfly_q31(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+
+ arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_radix2_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ unsigned i, j, k, l, m;
+ unsigned n1, n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multAcc_32x32_keep32_R(p0, yt, sinVal);
+ multSub_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ m = fftLen / n1;
+ do
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multAcc_32x32_keep32_R(p0, yt, sinVal);
+ multSub_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ i += n1;
+ m--;
+ } while( m > 0); // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ i += n1;
+ l = i + n2;
+
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+}
+
+
+void arm_radix2_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multSub_32x32_keep32_R(p0, yt, sinVal);
+ multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multSub_32x32_keep32_R(p0, yt, sinVal);
+ multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ i += n1;
+ l = i + n2;
+
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1210 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_f32.c
+*
+* Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/* ----------------------------------------------------------------------
+** Internal helper function used by the FFTs
+** ------------------------------------------------------------------- */
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix4_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ /* Updating input index */
+ i0++;
+
+ }
+ while(--j);
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ i0 += n1;
+ } while(i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = ya + yb + yc + yd */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa+yb-xc-yd) */
+ a4 = (Xaminusc + Ybminusd);
+ /* yb' = (ya-xb-yc+xd) */
+ a5 = (Yaminusc - Xbminusd);
+ /* xd' = (xa-yb-xc+yd)) */
+ a6 = (Xaminusc - Ybminusd);
+ /* yd' = (ya+xb-yc-xd) */
+ a7 = (Xbminusd + Yaminusc);
+
+ ptr1[0] = a0;
+ ptr1[1] = a1;
+ ptr1[2] = a2;
+ ptr1[3] = a3;
+ ptr1[4] = a4;
+ ptr1[5] = a5;
+ ptr1[6] = a6;
+ ptr1[7] = a7;
+
+ /* increment pointer by 8 */
+ ptr1 += 8u;
+ } while(--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializations for the fft calculation */
+ n2 = fftLen;
+ n1 = n2;
+ for (k = fftLen; k > 1u; k >>= 2u)
+ {
+ /* Initializations for the fft calculation */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* FFT Calculation */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+
+ i0 += n1;
+ } while( i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+
+}
+
+/*
+* @brief Core function for the floating-point CIFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @param[in] onebyfftLen value of 1/fftLen.
+* @return none.
+*/
+
+void arm_radix4_butterfly_inverse_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5,p6,p7;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ i0 += n1;
+ } while(i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+ /* Initializations of last stage */
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ a4 = (Xaminusc - Ybminusd);
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ a5 = (Yaminusc + Xbminusd);
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ a6 = (Xaminusc + Ybminusd);
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ a7 = (Yaminusc - Xbminusd);
+
+ p0 = a0 * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p2 = a2 * onebyfftLen;
+ p3 = a3 * onebyfftLen;
+ p4 = a4 * onebyfftLen;
+ p5 = a5 * onebyfftLen;
+ p6 = a6 * onebyfftLen;
+ p7 = a7 * onebyfftLen;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ ptr1[0] = p0;
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ ptr1[1] = p1;
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ ptr1[2] = p2;
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ ptr1[3] = p3;
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[4] = p4;
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ ptr1[5] = p5;
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[6] = p6;
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ ptr1[7] = p7;
+
+ /* increment source pointer by 8 for next calculations */
+ ptr1 = ptr1 + 8u;
+
+ } while(--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* Calculation of first stage */
+ for (k = fftLen; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+
+ i0 += n1;
+ } while( i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+ /* Initializations of last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* Calculations of last stage */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xc + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+ /* (xa + xb) - (xc + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb-yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb-xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = r1 * onebyfftLen;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+ /* (xa - xc) - (yb-yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb-yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb-xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb-xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = r1 * onebyfftLen;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = r2 * onebyfftLen;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+}
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in] *S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix4_f32(
+const arm_cfft_radix4_instance_f32 * S,
+float32_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_f32.c
+*
+* Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_q15.c
+*
+* Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
+* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+ S->twidCoefModifier = 4u;
+ S->bitRevFactor = 4u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_q31.c
+*
+* Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+*
+* @brief Initialization function for the Q31 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
+* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of Instance structure depending on the FFT length */
+ switch (S->fftLen)
+ {
+ /* Initializations of structure parameters for 4096 point FFT */
+ case 4096u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ break;
+
+ /* Initializations of structure parameters for 1024 point FFT */
+ case 1024u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1924 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_q15.c
+*
+* Description: This file has function definition of Radix-4 FFT & IFFT function and
+* In-place bit reversal using bit reversal table
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+ * @details
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"
+ */
+
+void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc)
+{
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t R, S, T, U;
+ q31_t C1, C2, C3, out1, out2;
+ uint32_t n1, n2, ic, i0, j, k;
+
+ q15_t *ptr1;
+ q15_t *pSi0;
+ q15_t *pSi1;
+ q15_t *pSi2;
+ q15_t *pSi3;
+
+ q31_t xaya, xbyb, xcyc, xdyd;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ j = n2;
+
+ pSi0 = pSrc16;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSi0);
+ T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
+ T = __SHADD16(T, 0); // it turns out doing this twice is 2 cycles, the alternative takes 3 cycles
+ //in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles
+ //T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSi2);
+ S = __SHADD16(S, 0);
+ S = __SHADD16(S, 0);
+
+ /* R = packed((ya + yc), (xa + xc) ) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc) ) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSi1);
+ T = __SHADD16(T, 0);
+ T = __SHADD16(T, 0);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSi3);
+ U = __SHADD16(U, 0);
+ U = __SHADD16(U, 0);
+
+ /* T = packed((yb + yd), (xb + xd) ) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
+ pSi0 += 2;
+
+ /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+ R = __QSUB16(R, T);
+
+ /* co2 & si2 are read from SIMD Coefficient pointer */
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = __SMUAD(C2, R) >> 16u;
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUSDX(C2, R);
+
+#else
+
+ /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUSDX(R, C2) >> 16u;
+ /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out2 = __SMUAD(C2, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+fftLen/4 */
+ /* T = packed(yb, xb) */
+ T = _SIMD32_OFFSET(pSi1);
+ T = __SHADD16(T, 0);
+ T = __SHADD16(T, 0);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ _SIMD32_OFFSET(pSi1) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi1 += 2;
+
+ /* Butterfly calculations */
+ /* U = packed(yd, xd) */
+ U = _SIMD32_OFFSET(pSi3);
+ U = __SHADD16(U, 0);
+ U = __SHADD16(U, 0);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QASX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QSAX(S, T);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QSAX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QASX(S, T);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* co1 & si1 are read from SIMD Coefficient pointer */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ /* Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = __SMUAD(C1, S) >> 16u;
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = __SMUSDX(C1, S);
+
+#else
+
+ /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out1 = __SMUSDX(S, C1) >> 16u;
+ /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out2 = __SMUAD(C1, S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xb', yb') in little endian format */
+ _SIMD32_OFFSET(pSi2) =
+ ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+ pSi2 += 2;
+
+
+ /* co3 & si3 are read from SIMD Coefficient pointer */
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = __SMUAD(C3, R) >> 16u;
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = __SMUSDX(C3, R);
+
+#else
+
+ /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out1 = __SMUSDX(R, C3) >> 16u;
+ /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out2 = __SMUAD(C3, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xd', yd') in little endian format */
+ _SIMD32_OFFSET(pSi3) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi3 += 2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ pSi0 = pSrc16 + 2 * j;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSi0);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSi2);
+
+ /* R = packed( (ya + yc), (xa + xc)) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSi1);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSi3);
+
+ /* T = packed( (yb + yd), (xb + xd)) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = __SHADD16(R, T);
+ out1 = __SHADD16(out1, 0);
+ _SIMD32_OFFSET(pSi0) = out1;
+ pSi0 += 2 * n1;
+
+ /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+ R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = __SMUAD(C2, R) >> 16u;
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUSDX(C2, R);
+
+#else
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUSDX(R, C2) >> 16u;
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out2 = __SMUAD(C2, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSi1);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ _SIMD32_OFFSET(pSi1) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi1 += 2 * n1;
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSi3);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHASX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHSAX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUAD(C1, S) >> 16u;
+ out2 = __SMUSDX(C1, S);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHSAX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHASX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUSDX(S, C1) >> 16u;
+ out2 = __SMUAD(C1, S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ _SIMD32_OFFSET(pSi2) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi2 += 2 * n1;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(C3, R) >> 16u;
+ out2 = __SMUSDX(C3, R);
+
+#else
+
+ out1 = __SMUSDX(R, C3) >> 16u;
+ out2 = __SMUAD(C3, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ _SIMD32_OFFSET(pSi3) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi3 += 2 * n1;
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+
+ ptr1 = &pSrc16[0];
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ do
+ {
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD32(ptr1)++;
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD32(ptr1)++;
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD32(ptr1)++;
+
+ /* Read xd (real), yd(imag) input */
+ xdyd = *__SIMD32(ptr1)++;
+
+ /* R = packed((ya + yc), (xa + xc)) */
+ R = __QADD16(xaya, xcyc);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(xaya, xcyc);
+
+ /* Read yd (real), xd(imag) input */
+ /* T = packed( (yb - yd), (xb - xd)) */
+ U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+#else
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ } while(--j);
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+ q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u] >> 2u;
+ T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u] >> 2u;
+ S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+ /* R0 = (ya + yc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ /* R1 = (xa + xc) */
+ R1 = __SSAT(T1 + S1, 16u);
+
+ /* S0 = (ya - yc) */
+ S0 = __SSAT(T0 - S0, 16);
+ /* S1 = (xa - xc) */
+ S1 = __SSAT(T1 - S1, 16);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+ /* T0 = (yb + yd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ /* T1 = (xb + xd) */
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* ya' = ya + yb + yc + yd */
+ /* xa' = xa + xb + xc + xd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd) */
+ /* R1 = (xa + xc) - (xb + xd) */
+ R0 = __SSAT(R0 - T0, 16u);
+ R1 = __SSAT(R1 - T1, 16u);
+
+ /* co2 & si2 are read from Coefficient pointer */
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+fftLen/4 */
+ /* input is down scale by 4 to avoid overflow */
+ /* T0 = yb, T1 = xb */
+ T0 = pSrc16[i1 * 2u] >> 2;
+ T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1] = out2;
+
+ /* Butterfly calculations */
+ /* input is down scale by 4 to avoid overflow */
+ /* U0 = yd, U1 = xd */
+ U0 = pSrc16[i3 * 2u] >> 2;
+ U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+ /* T0 = yb-yd */
+ T0 = __SSAT(T0 - U0, 16);
+ /* T1 = xb-xd */
+ T1 = __SSAT(T1 - U1, 16);
+
+ /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */
+ R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
+ R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
+
+ /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+ S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16u);
+ S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16u);
+
+ /* co1 & si1 are read from Coefficient pointer */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1];
+ /* Butterfly process for the i0+fftLen/2 sample */
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16);
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+ /* writing output(xb', yb') in little endian format */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1] = out2;
+
+ /* Co3 & si3 are read from Coefficient pointer */
+ Co3 = pCoef16[3u * (ic * 2u)];
+ Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
+ /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
+ /* writing output(xd', yd') in little endian format */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1] = out2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ Co2 = pCoef16[2u * (ic * 2u)];
+ Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+ Co3 = pCoef16[3u * (ic * 2u)];
+ Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16);
+ R1 = __SSAT(T1 + S1, 16);
+
+ /* S0 = (ya - yc), S1 =(xa - xc) */
+ S0 = __SSAT(T0 - S0, 16);
+ S1 = __SSAT(T1 - S1, 16);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16);
+ T1 = __SSAT(T1 + U1, 16);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+ out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+ pSrc16[i0 * 2u] = out1;
+ pSrc16[(2u * i0) + 1u] = out2;
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = yb-yd, T1 = xb-xd */
+ T0 = __SSAT(T0 - U0, 16);
+ T1 = __SSAT(T1 - U1, 16);
+
+ /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+ R0 = (S0 >> 1u) - (T1 >> 1u);
+ R1 = (S1 >> 1u) + (T0 >> 1u);
+
+ /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+ S0 = (S0 >> 1u) + (T1 >> 1u);
+ S1 = (S1 >> 1u) - (T0 >> 1u);
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+ out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+ out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
+ /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd)) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ pSrc16[i1 * 2u] = R0;
+ pSrc16[(i1 * 2u) + 1u] = R1;
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+ /* T0 = (yb - yd), T1 = (xb - xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* writing the butterfly processed i0 + fftLen/2 sample */
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+ pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+ /* writing the butterfly processed i0 + 3fftLen/4 sample */
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+ pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+ }
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @brief Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT function
+* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t R, S, T, U;
+ q31_t C1, C2, C3, out1, out2;
+ uint32_t n1, n2, ic, i0, j, k;
+
+ q15_t *ptr1;
+ q15_t *pSi0;
+ q15_t *pSi1;
+ q15_t *pSi2;
+ q15_t *pSi3;
+
+ q31_t xaya, xbyb, xcyc, xdyd;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ j = n2;
+
+ pSi0 = pSrc16;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSi0);
+ T = __SHADD16(T, 0);
+ T = __SHADD16(T, 0);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSi2);
+ S = __SHADD16(S, 0);
+ S = __SHADD16(S, 0);
+
+ /* R = packed((ya + yc), (xa + xc) ) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc) ) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSi1);
+ T = __SHADD16(T, 0);
+ T = __SHADD16(T, 0);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSi3);
+ U = __SHADD16(U, 0);
+ U = __SHADD16(U, 0);
+
+ /* T = packed((yb + yd), (xb + xd) ) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
+ pSi0 += 2;
+
+ /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+ R = __QSUB16(R, T);
+
+ /* co2 & si2 are read from SIMD Coefficient pointer */
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = __SMUSD(C2, R) >> 16u;
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUADX(C2, R);
+
+#else
+
+ /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUADX(C2, R) >> 16u;
+ /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+fftLen/4 */
+ /* T = packed(yb, xb) */
+ T = _SIMD32_OFFSET(pSi1);
+ T = __SHADD16(T, 0);
+ T = __SHADD16(T, 0);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ _SIMD32_OFFSET(pSi1) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi1 += 2;
+
+ /* Butterfly calculations */
+ /* U = packed(yd, xd) */
+ U = _SIMD32_OFFSET(pSi3);
+ U = __SHADD16(U, 0);
+ U = __SHADD16(U, 0);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QSAX(S, T);
+ /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */
+ S = __QASX(S, T);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QASX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QSAX(S, T);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* co1 & si1 are read from SIMD Coefficient pointer */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ /* Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = __SMUSD(C1, S) >> 16u;
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = __SMUADX(C1, S);
+
+#else
+
+ /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out1 = __SMUADX(C1, S) >> 16u;
+ /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xb', yb') in little endian format */
+ _SIMD32_OFFSET(pSi2) =
+ ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+ pSi2 += 2;
+
+
+ /* co3 & si3 are read from SIMD Coefficient pointer */
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = __SMUSD(C3, R) >> 16u;
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = __SMUADX(C3, R);
+
+#else
+
+ /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out1 = __SMUADX(C3, R) >> 16u;
+ /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xd', yd') in little endian format */
+ _SIMD32_OFFSET(pSi3) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi3 += 2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ pSi0 = pSrc16 + 2 * j;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSi0);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSi2);
+
+ /* R = packed( (ya + yc), (xa + xc)) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSi1);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSi3);
+
+ /* T = packed( (yb + yd), (xb + xd)) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = __SHADD16(R, T);
+ out1 = __SHADD16(out1, 0);
+ _SIMD32_OFFSET(pSi0) = out1;
+ pSi0 += 2 * n1;
+
+ /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+ R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = __SMUSD(C2, R) >> 16u;
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUADX(C2, R);
+
+#else
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUADX(R, C2) >> 16u;
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSi1);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ _SIMD32_OFFSET(pSi1) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi1 += 2 * n1;
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSi3);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHSAX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHASX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUSD(C1, S) >> 16u;
+ out2 = __SMUADX(C1, S);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHASX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHSAX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUADX(S, C1) >> 16u;
+ out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ _SIMD32_OFFSET(pSi2) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi2 += 2 * n1;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(C3, R) >> 16u;
+ out2 = __SMUADX(C3, R);
+
+#else
+
+ out1 = __SMUADX(C3, R) >> 16u;
+ out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ _SIMD32_OFFSET(pSi3) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ pSi3 += 2 * n1;
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+
+ ptr1 = &pSrc16[0];
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ do
+ {
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD32(ptr1)++;
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD32(ptr1)++;
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD32(ptr1)++;
+
+ /* Read xd (real), yd(imag) input */
+ xdyd = *__SIMD32(ptr1)++;
+
+ /* R = packed((ya + yc), (xa + xc)) */
+ R = __QADD16(xaya, xcyc);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(xaya, xcyc);
+
+ /* Read yd (real), xd(imag) input */
+ /* T = packed( (yb - yd), (xb - xd)) */
+ U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#else
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ } while(--j);
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+ q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* Start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u] >> 2u;
+ T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u] >> 2u;
+ S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+ /* Read yd (real), xd(imag) input */
+ /* input is down scale by 4 to avoid overflow */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+ R0 = __SSAT(R0 - T0, 16u);
+ R1 = __SSAT(R1 - T1, 16u);
+ /* co2 & si2 are read from Coefficient pointer */
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[(2u * ic * 2u) + 1u];
+ /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+ out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16u);
+ /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+fftLen/4 */
+ /* input is down scale by 4 to avoid overflow */
+ /* T0 = yb, T1 = xb */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+ /* input is down scale by 4 to avoid overflow */
+ /* U0 = yd, U1 = xd) */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+ /* T0 = yb-yd, T1 = xb-xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+ /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+ R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16);
+ R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16);
+ /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+ S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
+ S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
+
+ /* co1 & si1 are read from Coefficient pointer */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ /* Butterfly process for the i0+fftLen/2 sample */
+ /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+ out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
+ /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+ out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
+ /* writing output(xb', yb') in little endian format */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Co3 & si3 are read from Coefficient pointer */
+ Co3 = pCoef16[3u * ic * 2u];
+ Si3 = pCoef16[(3u * ic * 2u) + 1u];
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+ out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
+ /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+ out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
+ /* writing output(xd', yd') in little endian format */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* End of first stage process */
+
+ /* data is in 4.11(q11) format */
+
+
+ /* Start of Middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[2u * ic * 2u + 1u];
+ Co3 = pCoef16[3u * ic * 2u];
+ Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+ pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+ out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16);
+ /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16);
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = yb-yd, T1 = xb-xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+ R0 = (S0 >> 1u) + (T1 >> 1u);
+ R1 = (S1 >> 1u) - (T0 >> 1u);
+
+ /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+ S0 = (S0 >> 1u) - (T1 >> 1u);
+ S1 = (S1 >> 1u) + (T0 >> 1u);
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
+ out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
+ /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+ /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+ out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
+ /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+ /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* End of Middle stages process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* start of last stage process */
+
+
+ /* Initializations for the last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* Butterfly implementation */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ pSrc16[i1 * 2u] = R0;
+ pSrc16[(i1 * 2u) + 1u] = R1;
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+ /* T0 = (yb - yd), T1 = (xb - xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* writing the butterfly processed i0 + fftLen/2 sample */
+ /* xb' = (xa-yb-xc+yd) */
+ /* yb' = (ya+xb-yc-xd) */
+ pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+ pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+ /* writing the butterfly processed i0 + 3fftLen/4 sample */
+ /* xd' = (xa+yb-xc-yd) */
+ /* yd' = (ya-xb-yc+xd) */
+ pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+ pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+ }
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,1404 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_q31.c
+*
+* Description: This file has function definition of Radix-4 FFT & IFFT function and
+* In-place bit reversal using bit reversal table
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"
+ *
+ */
+
+void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc)
+{
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+*
+* Butterfly implementation:
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier)
+{
+#if defined(ARM_MATH_CM7)
+ uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q63_t xaya, xbyb, xcyc, xdyd;
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+
+ /* start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+ /* xa - xc */
+ r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+ /* ya - yc */
+ s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+ /* xb - xd */
+ t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* end of first stage process */
+
+ /* data is in 5.27(q27) format */
+
+
+ /* start of Middle stages process */
+
+
+ /* each stage in middle stages provides two down scaling of the input */
+
+ twidCoefModifier <<= 2u;
+
+
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+#else
+ uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q31_t *pSi0;
+ q31_t *pSi1;
+ q31_t *pSi2;
+ q31_t *pSi3;
+ q63_t xaya, xbyb, xcyc, xdyd;
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+
+ /* start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ ia1 = 0u;
+
+ j = n2;
+
+ pSi0 = pSrc;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
+ /* xa - xc */
+ r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
+ /* ya - yc */
+ s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ *pSi0++ = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
+
+ /* ya' = ya + yb + yc + yd */
+ *pSi0++ = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
+ /* xb - xd */
+ t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ } while(--j);
+
+ /* end of first stage process */
+
+ /* data is in 5.27(q27) format */
+
+
+ /* start of Middle stages process */
+
+
+ /* each stage in middle stages provides two down scaling of the input */
+
+ twidCoefModifier <<= 2u;
+
+
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ pSi0 = pSrc + 2 * j;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSi0[0] + pSi2[0];
+
+ /* xa - xc */
+ r2 = pSi0[0] - pSi2[0];
+
+
+ /* ya + yc */
+ s1 = pSi0[1] + pSi2[1];
+
+ /* ya - yc */
+ s2 = pSi0[1] - pSi2[1];
+
+
+ /* xb + xd */
+ t1 = pSi1[0] + pSi3[0];
+
+
+ /* xa' = xa + xb + xc + xd */
+ pSi0[0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSi1[1] + pSi3[1];
+
+ /* ya' = ya + yb + yc + yd */
+ pSi0[1] = (s1 + t2) >> 2u;
+ pSi0 += 2 * n1;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSi1[1] - pSi3[1];
+
+ /* (xb - xd) */
+ t2 = pSi1[0] - pSi3[0];
+
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSi1[1] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+ pSi1 += 2 * n1;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+ pSi2 += 2 * n1;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ pSi3 += 2 * n1;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+#endif
+
+ /* End of Middle stages process */
+
+ /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+ /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+ /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+ /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+ /* start of Last stage process */
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ xa = (q31_t) xaya;
+ ya = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ xb = (q31_t) xbyb;
+ yb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ xc = (q31_t) xcyc;
+ yc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ xd = (q31_t) xdyd;
+ yd = (q31_t) (xdyd >> 32);
+
+#else
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ ya = (q31_t) xaya;
+ xa = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ yb = (q31_t) xbyb;
+ xb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ yc = (q31_t) xcyc;
+ xc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ yd = (q31_t) xdyd;
+ xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+ /* xa' = xa + xb + xc + xd */
+ xa_out = xa + xb + xc + xd;
+
+ /* ya' = ya + yb + yc + yd */
+ ya_out = ya + yb + yc + yd;
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+ /* writing xa' and ya' */
+ *ptr1++ = xa_out;
+ *ptr1++ = ya_out;
+
+ xc_out = (xa - xb + xc - xd);
+ yc_out = (ya - yb + yc - yd);
+
+ /* writing xc' and yc' */
+ *ptr1++ = xc_out;
+ *ptr1++ = yc_out;
+
+ xb_out = (xa + yb - xc - yd);
+ yb_out = (ya - xb - yc + xd);
+
+ /* writing xb' and yb' */
+ *ptr1++ = xb_out;
+ *ptr1++ = yb_out;
+
+ xd_out = (xa - yb - xc + yd);
+ yd_out = (ya + xb - yc - xd);
+
+ /* writing xd' and yd' */
+ *ptr1++ = xd_out;
+ *ptr1++ = yd_out;
+
+
+ } while(--j);
+
+ /* output is in 11.21(q21) format for the 1024 point */
+ /* output is in 9.23(q23) format for the 256 point */
+ /* output is in 7.25(q25) format for the 64 point */
+ /* output is in 5.27(q27) format for the 16 point */
+
+ /* End of last stage process */
+
+}
+
+
+/**
+ * @brief Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT Function
+* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier)
+{
+#if defined(ARM_MATH_CM7)
+ uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q63_t xaya, xbyb, xcyc, xdyd;
+
+ /* input is be 1.31(q31) format for all FFT sizes */
+ /* Total process is divided into three stages */
+ /* process first stage, middle stages, & last stage */
+
+ /* Start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ do
+ {
+
+ /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+ /* xa - xc */
+ r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+ /* ya - yc */
+ s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+ /* xb - xd */
+ t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* data is in 5.27(q27) format */
+ /* each stage provides two down scaling of the input */
+
+
+ /* Start of Middle stages process */
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ for (j = 0; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] =
+ (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+#else
+ uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q31_t *pSi0;
+ q31_t *pSi1;
+ q31_t *pSi2;
+ q31_t *pSi3;
+ q63_t xaya, xbyb, xcyc, xdyd;
+
+ /* input is be 1.31(q31) format for all FFT sizes */
+ /* Total process is divided into three stages */
+ /* process first stage, middle stages, & last stage */
+
+ /* Start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ ia1 = 0u;
+
+ j = n2;
+
+ pSi0 = pSrc;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ do
+ {
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
+ /* xa - xc */
+ r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
+ /* ya - yc */
+ s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ *pSi0++ = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
+ /* ya' = ya + yb + yc + yd */
+ *pSi0++ = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
+ /* xb - xd */
+ t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ } while(--j);
+
+ /* data is in 5.27(q27) format */
+ /* each stage provides two down scaling of the input */
+
+
+ /* Start of Middle stages process */
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ for (j = 0; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ pSi0 = pSrc + 2 * j;
+ pSi1 = pSi0 + 2 * n2;
+ pSi2 = pSi1 + 2 * n2;
+ pSi3 = pSi2 + 2 * n2;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSi0[0] + pSi2[0];
+
+ /* xa - xc */
+ r2 = pSi0[0] - pSi2[0];
+
+
+ /* ya + yc */
+ s1 = pSi0[1] + pSi2[1];
+
+ /* ya - yc */
+ s2 = pSi0[1] - pSi2[1];
+
+
+ /* xb + xd */
+ t1 = pSi1[0] + pSi3[0];
+
+
+ /* xa' = xa + xb + xc + xd */
+ pSi0[0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = pSi1[1] + pSi3[1];
+
+ /* ya' = ya + yb + yc + yd */
+ pSi0[1] = (s1 + t2) >> 2u;
+ pSi0 += 2 * n1;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSi1[1] - pSi3[1];
+
+ /* (xb - xd) */
+ t2 = pSi1[0] - pSi3[0];
+
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSi1[1] =
+
+ (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+ pSi1 += 2 * n1;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+ pSi2 += 2 * n1;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ pSi3 += 2 * n1;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+#endif
+
+ /* End of Middle stages process */
+
+ /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+ /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+ /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+ /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+ /* Start of last stage process */
+
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+#ifndef ARM_MATH_BIG_ENDIAN
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ xa = (q31_t) xaya;
+ ya = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ xb = (q31_t) xbyb;
+ yb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ xc = (q31_t) xcyc;
+ yc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ xd = (q31_t) xdyd;
+ yd = (q31_t) (xdyd >> 32);
+
+#else
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ ya = (q31_t) xaya;
+ xa = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ yb = (q31_t) xbyb;
+ xb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ yc = (q31_t) xcyc;
+ xc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ yd = (q31_t) xdyd;
+ xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+ /* xa' = xa + xb + xc + xd */
+ xa_out = xa + xb + xc + xd;
+
+ /* ya' = ya + yb + yc + yd */
+ ya_out = ya + yb + yc + yd;
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+ /* writing xa' and ya' */
+ *ptr1++ = xa_out;
+ *ptr1++ = ya_out;
+
+ xc_out = (xa - xb + xc - xd);
+ yc_out = (ya - yb + yc - yd);
+
+ /* writing xc' and yc' */
+ *ptr1++ = xc_out;
+ *ptr1++ = yc_out;
+
+ xb_out = (xa - yb - xc + yd);
+ yb_out = (ya + xb - yc - xd);
+
+ /* writing xb' and yb' */
+ *ptr1++ = xb_out;
+ *ptr1++ = yb_out;
+
+ xd_out = (xa + yb - xc - yd);
+ yd_out = (ya - xb - yc + xd);
+
+ /* writing xd' and yd' */
+ *ptr1++ = xd_out;
+ *ptr1++ = yd_out;
+
+ } while(--j);
+
+ /* output is in 11.21(q21) format for the 1024 point */
+ /* output is in 9.23(q23) format for the 256 point */
+ /* output is in 7.25(q25) format for the 64 point */
+ /* output is in 5.27(q27) format for the 16 point */
+
+ /* End of last stage process */
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix8_f32.c
+*
+* Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @defgroup Radix8_CFFT_CIFFT Radix-8 Complex FFT Functions
+*
+* \par
+* Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).
+* Computational complexity of CFFT reduces drastically when compared to DFT.
+* \par
+* This set of functions implements CFFT/CIFFT
+* for floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output.
+* Complex input is stored in input buffer in an interleaved fashion.
+*
+* \par
+* The functions operate on blocks of input and output data and each call to the function processes
+* 2*fftLen samples through the transform. pSrc points to In-place arrays containing 2*fftLen values.
+* \par
+* The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.
+* {real[0], imag[0], real[1], imag[1],..}
+*
+* \par Lengths supported by the transform:
+* \par
+* Internally, the function utilize a Radix-8 decimation in frequency(DIF) algorithm
+* and the size of the FFT supported are of the lengths [ 64, 512, 4096].
+*
+*
+* \par Algorithm:
+*
+* Complex Fast Fourier Transform:
+* \par
+* Input real and imaginary data:
+*
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+* where N is length of FFT
+* \par
+* Output real and imaginary data:
+*
+* X(4r) = xa'+ j * ya'
+* X(4r+1) = xb'+ j * yb'
+* X(4r+2) = xc'+ j * yc'
+* X(4r+3) = xd'+ j * yd'
+*
+* \par
+* Twiddle factors for Radix-8 FFT:
+*
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+*
+*
+* \par
+* \image html CFFT.gif "Radix-8 Decimation-in Frequency Complex Fast Fourier Transform"
+*
+* \par
+* Output from Radix-8 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.
+* \par
+* Butterfly CFFT equations:
+*
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*
+* \par
+* where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);
+* bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);
+* pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.
+* twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;
+* pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.
+* onebyfftLen value of 1/fftLen to calculate CIFFT;
+*
+* \par Fixed-Point Behavior
+* Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.
+* Refer to the function specific documentation below for usage guidelines.
+*/
+
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix8_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+const float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+ uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
+ uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
+ uint32_t id;
+ uint32_t n1, n2, j;
+
+ float32_t r1, r2, r3, r4, r5, r6, r7, r8;
+ float32_t t1, t2;
+ float32_t s1, s2, s3, s4, s5, s6, s7, s8;
+ float32_t p1, p2, p3, p4;
+ float32_t co2, co3, co4, co5, co6, co7, co8;
+ float32_t si2, si3, si4, si5, si6, si7, si8;
+ const float32_t C81 = 0.70710678118f;
+
+ n2 = fftLen;
+
+ do
+ {
+ n1 = n2;
+ n2 = n2 >> 3;
+ i1 = 0;
+
+ do
+ {
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ pSrc[2 * i5] = r1 - r2;
+ r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = r1 - s3;
+ r1 = r1 + s3;
+ s3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1 + 1] = r1 + r2;
+ pSrc[2 * i5 + 1] = r1 - r2;
+ pSrc[2 * i3] = t1 + s3;
+ pSrc[2 * i7] = t1 - s3;
+ pSrc[2 * i3 + 1] = t2 - r3;
+ pSrc[2 * i7 + 1] = t2 + r3;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ r2 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - r2;
+ s5 = s5 + r2;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ pSrc[2 * i2] = r5 + s7;
+ pSrc[2 * i8] = r5 - s7;
+ pSrc[2 * i6] = t1 + s8;
+ pSrc[2 * i4] = t1 - s8;
+ pSrc[2 * i2 + 1] = s5 - r7;
+ pSrc[2 * i8 + 1] = s5 + r7;
+ pSrc[2 * i6 + 1] = t2 - r8;
+ pSrc[2 * i4 + 1] = t2 + r8;
+
+ i1 += n1;
+ } while(i1 < fftLen);
+
+ if(n2 < 8)
+ break;
+
+ ia1 = 0;
+ j = 1;
+
+ do
+ {
+ /* index calculation for the coefficients */
+ id = ia1 + twidCoefModifier;
+ ia1 = id;
+ ia2 = ia1 + id;
+ ia3 = ia2 + id;
+ ia4 = ia3 + id;
+ ia5 = ia4 + id;
+ ia6 = ia5 + id;
+ ia7 = ia6 + id;
+
+ co2 = pCoef[2 * ia1];
+ co3 = pCoef[2 * ia2];
+ co4 = pCoef[2 * ia3];
+ co5 = pCoef[2 * ia4];
+ co6 = pCoef[2 * ia5];
+ co7 = pCoef[2 * ia6];
+ co8 = pCoef[2 * ia7];
+ si2 = pCoef[2 * ia1 + 1];
+ si3 = pCoef[2 * ia2 + 1];
+ si4 = pCoef[2 * ia3 + 1];
+ si5 = pCoef[2 * ia4 + 1];
+ si6 = pCoef[2 * ia5 + 1];
+ si7 = pCoef[2 * ia6 + 1];
+ si8 = pCoef[2 * ia7 + 1];
+
+ i1 = j;
+
+ do
+ {
+ /* index calculation for the input */
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ r2 = r1 - r2;
+ s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = s1 - s3;
+ s1 = s1 + s3;
+ s3 = s2 - s4;
+ s2 = s2 + s4;
+ r1 = t1 + s3;
+ t1 = t1 - s3;
+ pSrc[2 * i1 + 1] = s1 + s2;
+ s2 = s1 - s2;
+ s1 = t2 - r3;
+ t2 = t2 + r3;
+ p1 = co5 * r2;
+ p2 = si5 * s2;
+ p3 = co5 * s2;
+ p4 = si5 * r2;
+ pSrc[2 * i5] = p1 + p2;
+ pSrc[2 * i5 + 1] = p3 - p4;
+ p1 = co3 * r1;
+ p2 = si3 * s1;
+ p3 = co3 * s1;
+ p4 = si3 * r1;
+ pSrc[2 * i3] = p1 + p2;
+ pSrc[2 * i3 + 1] = p3 - p4;
+ p1 = co7 * t1;
+ p2 = si7 * t2;
+ p3 = co7 * t2;
+ p4 = si7 * t1;
+ pSrc[2 * i7] = p1 + p2;
+ pSrc[2 * i7 + 1] = p3 - p4;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ s1 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - s1;
+ s5 = s5 + s1;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ r1 = r5 + s7;
+ r5 = r5 - s7;
+ r6 = t1 + s8;
+ t1 = t1 - s8;
+ s1 = s5 - r7;
+ s5 = s5 + r7;
+ s6 = t2 - r8;
+ t2 = t2 + r8;
+ p1 = co2 * r1;
+ p2 = si2 * s1;
+ p3 = co2 * s1;
+ p4 = si2 * r1;
+ pSrc[2 * i2] = p1 + p2;
+ pSrc[2 * i2 + 1] = p3 - p4;
+ p1 = co8 * r5;
+ p2 = si8 * s5;
+ p3 = co8 * s5;
+ p4 = si8 * r5;
+ pSrc[2 * i8] = p1 + p2;
+ pSrc[2 * i8 + 1] = p3 - p4;
+ p1 = co6 * r6;
+ p2 = si6 * s6;
+ p3 = co6 * s6;
+ p4 = si6 * r6;
+ pSrc[2 * i6] = p1 + p2;
+ pSrc[2 * i6 + 1] = p3 - p4;
+ p1 = co4 * t1;
+ p2 = si4 * t2;
+ p3 = co4 * t2;
+ p4 = si4 * t1;
+ pSrc[2 * i4] = p1 + p2;
+ pSrc[2 * i4 + 1] = p3 - p4;
+
+ i1 += n1;
+ } while(i1 < fftLen);
+
+ j++;
+ } while(j < n2);
+
+ twidCoefModifier <<= 3;
+ } while(n2 > 7);
+}
+
+/**
+* @} end of Radix8_CFFT_CIFFT group
+*/
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_f32.c
+*
+* Description: Processing function of DCT4 & IDCT4 F32.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions
+ * Representation of signals by minimum number of values is important for storage and transmission.
+ * The possibility of large discontinuity between the beginning and end of a period of a signal
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the
+ * spectrum and is very widely used in signal and image coding applications.
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.
+ *
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.
+ * Reordering of the input data makes the computation of DCT just a problem of
+ * computing the DFT of a real signal with a few additional operations.
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.
+ *
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.
+ * DCT2 implementation can be described in the following steps:
+ * - Re-ordering input
+ * - Calculating Real FFT
+ * - Multiplication of weights and Real FFT output and getting real part from the product.
+ *
+ * This process is explained by the block diagram below:
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"
+ *
+ * \par Algorithm:
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:
+ * \image html DCT4Equation.gif
+ * where k = 0,1,2,.....N-1
+ *\par
+ * Its inverse is defined as follows:
+ * \image html IDCT4Equation.gif
+ * where n = 0,1,2,.....N-1
+ *\par
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward
+ * and inverse transform computation are identical.
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.
+ *
+ * \par Lengths supported by the transform:
+ * As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ * \par Instance Structure
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.
+ * A separate instance structure must be defined for each transform.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Manually initialize the instance structure as follows:
+ *
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;
+ * \c normalize is normalizing factor used and is equal to sqrt(2/N);
+ * \c pTwiddle points to the twiddle factor table;
+ * \c pCosFactor points to the cosFactor table;
+ * \c pRfft points to the real FFT instance;
+ * \c pCfft points to the complex FFT instance;
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()
+ * and arm_rfft_f32() respectively for details regarding static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer)
+{
+ uint32_t i; /* Loop counter */
+ float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ float32_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+ arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as,
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = (uint32_t) S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = ((uint32_t) S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = ((uint32_t) S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = (uint32_t) S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* Initializing the loop counter */
+ i = ((uint32_t) S->N - 1u);
+
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,16519 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_f32.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 F32
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : weights[n] = e^(-j*n*pi/(2*N))
+* \par
+* C command to generate the table
+*
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* }
+* \par
+* Where N is the Number of weights to be calculated and c is pi/(2*N)
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is 2*N.
+*/
+
+static const float32_t Weights_128[256] = {
+ 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+ -0.012271538285719925f,
+ 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+ -0.036807222941358832f,
+ 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+ -0.061320736302208578f,
+ 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+ -0.085797312344439894f,
+ 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+ -0.110222207293883060f,
+ 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+ -0.134580708507126170f,
+ 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+ -0.158858143333861450f,
+ 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+ -0.183039887955140950f,
+ 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+ -0.207111376192218560f,
+ 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+ -0.231058108280671110f,
+ 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+ -0.254865659604514570f,
+ 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+ -0.278519689385053060f,
+ 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+ -0.302005949319228080f,
+ 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+ -0.325310292162262930f,
+ 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+ -0.348418680249434560f,
+ 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+ -0.371317193951837540f,
+ 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+ -0.393992040061048100f,
+ 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+ -0.416429560097637150f,
+ 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+ -0.438616238538527660f,
+ 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+ -0.460538710958240010f,
+ 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+ -0.482183772079122720f,
+ 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+ -0.503538383725717580f,
+ 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+ -0.524589682678468950f,
+ 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+ -0.545324988422046460f,
+ 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+ -0.565731810783613120f,
+ 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+ -0.585797857456438860f,
+ 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+ -0.605511041404325550f,
+ 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+ -0.624859488142386340f,
+ 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+ -0.643831542889791390f,
+ 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+ -0.662415777590171780f,
+ 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+ -0.680600997795453020f,
+ 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+ -0.698376249408972920f,
+ 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+ -0.715730825283818590f,
+ 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+ -0.732654271672412820f,
+ 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+ -0.749136394523459260f,
+ 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+ -0.765167265622458960f,
+ 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+ -0.780737228572094380f,
+ 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+ -0.795836904608883460f,
+ 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+ -0.810457198252594770f,
+ 0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+ -0.824589302785025290f,
+ 0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+ -0.838224705554837970f,
+ 0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+ -0.851355193105265200f,
+ 0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+ -0.863972856121586700f,
+ 0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+ -0.876070094195406600f,
+ 0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+ -0.887639620402853930f,
+ 0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+ -0.898674465693953820f,
+ 0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+ -0.909167983090522270f,
+ 0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+ -0.919113851690057770f,
+ 0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+ -0.928506080473215480f,
+ 0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+ -0.937339011912574960f,
+ 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+ -0.945607325380521280f,
+ 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+ -0.953306040354193750f,
+ 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+ -0.960430519415565790f,
+ 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+ -0.966976471044852070f,
+ 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+ -0.972939952205560070f,
+ 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+ -0.978317370719627650f,
+ 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+ -0.983105487431216290f,
+ 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+ -0.987301418157858430f,
+ 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+ -0.990902635427780010f,
+ 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+ -0.993906970002356060f,
+ 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+ -0.996312612182778000f,
+ 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+ -0.998118112900149180f,
+ 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+ -0.999322384588349540f,
+ 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+ -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+ 1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+ -0.003067956762965976f,
+ 0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+ -0.009203754782059819f,
+ 0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+ -0.015339206284988100f,
+ 0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+ -0.021474080275469508f,
+ 0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+ -0.027608145778965740f,
+ 0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+ -0.033741171851377580f,
+ 0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+ -0.039872927587739811f,
+ 0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+ -0.046003182130914623f,
+ 0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+ -0.052131704680283324f,
+ 0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+ -0.058258264500435752f,
+ 0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+ -0.064382630929857465f,
+ 0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+ -0.070504573389613856f,
+ 0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
+ -0.076623861392031492f,
+ 0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
+ -0.082740264549375692f,
+ 0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
+ -0.088853552582524600f,
+ 0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
+ -0.094963495329638992f,
+ 0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
+ -0.101069862754827820f,
+ 0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
+ -0.107172424956808840f,
+ 0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,
+ -0.113270952177564350f,
+ 0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,
+ -0.119365214810991350f,
+ 0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,
+ -0.125454983411546230f,
+ 0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,
+ -0.131540028702883120f,
+ 0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,
+ -0.137620121586486040f,
+ 0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,
+ -0.143695033150294470f,
+ 0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,
+ -0.149764534677321510f,
+ 0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,
+ -0.155828397654265230f,
+ 0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,
+ -0.161886393780111830f,
+ 0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,
+ -0.167938294974731170f,
+ 0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,
+ -0.173983873387463820f,
+ 0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,
+ -0.180022901405699510f,
+ 0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,
+ -0.186055151663446630f,
+ 0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,
+ -0.192080397049892440f,
+ 0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,
+ -0.198098410717953560f,
+ 0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,
+ -0.204108966092816870f,
+ 0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,
+ -0.210111836880469610f,
+ 0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,
+ -0.216106797076219520f,
+ 0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,
+ -0.222093620973203510f,
+ 0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,
+ -0.228072083170885730f,
+ 0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,
+ -0.234041958583543430f,
+ 0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,
+ -0.240003022448741500f,
+ 0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f,
+ -0.245955050335794590f,
+ 0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f,
+ -0.251897818154216970f,
+ 0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f,
+ -0.257831102162158990f,
+ 0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f,
+ -0.263754678974831350f,
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+ 0.009203754782059960, -0.999957644551963900, 0.009012015137106642,
+ -0.999959390967037450,
+ 0.008820275160807512, -0.999961100616462820, 0.008628534860211857,
+ -0.999962773500176930,
+ 0.008436794242369860, -0.999964409618118280, 0.008245053314331058,
+ -0.999966008970226920,
+ 0.008053312083144991, -0.999967571556443780, 0.007861570555861883,
+ -0.999969097376711580,
+ 0.007669828739531077, -0.999970586430974140, 0.007478086641202815,
+ -0.999972038719176730,
+ 0.007286344267926684, -0.999973454241265940, 0.007094601626752279,
+ -0.999974832997189810,
+ 0.006902858724729877, -0.999976174986897610, 0.006711115568908869,
+ -0.999977480210339940,
+ 0.006519372166339549, -0.999978748667468830, 0.006327628524071549,
+ -0.999979980358237650,
+ 0.006135884649154515, -0.999981175282601110, 0.005944140548638765,
+ -0.999982333440515350,
+ 0.005752396229573737, -0.999983454831937730, 0.005560651699009764,
+ -0.999984539456826970,
+ 0.005368906963996303, -0.999985587315143200, 0.005177162031583702,
+ -0.999986598406848000,
+ 0.004985416908821652, -0.999987572731904080, 0.004793671602759852,
+ -0.999988510290275690,
+ 0.004601926120448672, -0.999989411081928400, 0.004410180468937601,
+ -0.999990275106828920,
+ 0.004218434655277024, -0.999991102364945590, 0.004026688686516664,
+ -0.999991892856248010,
+ 0.003834942569706248, -0.999992646580707190, 0.003643196311896179,
+ -0.999993363538295150,
+ 0.003451449920135975, -0.999994043728985820, 0.003259703401476044,
+ -0.999994687152754080,
+ 0.003067956762966138, -0.999995293809576190, 0.002876210011656010,
+ -0.999995863699429940,
+ 0.002684463154596083, -0.999996396822294350, 0.002492716198835898,
+ -0.999996893178149880,
+ 0.002300969151425887, -0.999997352766978210, 0.002109222019415816,
+ -0.999997775588762350,
+ 0.001917474809855460, -0.999998161643486980, 0.001725727529795258,
+ -0.999998510931137790,
+ 0.001533980186284766, -0.999998823451701880, 0.001342232786374430,
+ -0.999999099205167830,
+ 0.001150485337113809, -0.999999338191525530, 0.000958737845553352,
+ -0.999999540410766110,
+ 0.000766990318742846, -0.999999705862882230, 0.000575242763732077,
+ -0.999999834547867670,
+ 0.000383495187571497, -0.999999926465717890, 0.000191747597310674,
+ -0.999999981616429330,
+
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+* \par
+* C command to generate the table
+* \par
+* for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* }
+* \par
+* where N is the number of factors to generate and c is pi/(2*N)
+*/
+static const float32_t cos_factors_128[128] = {
+ 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+ 0.999077727752645360f,
+ 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+ 0.995767414467659820f,
+ 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+ 0.990058210262297120f,
+ 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+ 0.981963869109555240f,
+ 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+ 0.971503890986251780f,
+ 0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+ 0.958703474895871600f,
+ 0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+ 0.943593458161960390f,
+ 0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+ 0.926210242138311380f,
+ 0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+ 0.906595704514915330f,
+ 0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+ 0.884797098430937790f,
+ 0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+ 0.860866938637767310f,
+ 0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+ 0.834862874986380010f,
+ 0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+ 0.806847553543799330f,
+ 0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+ 0.776888465673232440f,
+ 0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+ 0.745057785441466060f,
+ 0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+ 0.711432195745216430f,
+ 0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+ 0.676092703575316030f,
+ 0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+ 0.639124444863775730f,
+ 0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+ 0.600616479383868970f,
+ 0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+ 0.560661576197336030f,
+ 0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+ 0.519355990165589530f,
+ 0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+ 0.476799230063322250f,
+ 0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+ 0.433093818853152010f,
+ 0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+ 0.388345046698826300f,
+ 0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+ 0.342660717311994380f,
+ 0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+ 0.296150888243623960f,
+ 0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+ 0.248927605745720260f,
+ 0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+ 0.201104634842091960f,
+ 0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+ 0.152797185258443410f,
+ 0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+ 0.104121633872054730f,
+ 0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+ 0.055195244349690031f,
+ 0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+ 0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+ 0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+ 0.999942349676023910f,
+ 0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+ 0.999735288260561680f,
+ 0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+ 0.999377670388002850f,
+ 0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+ 0.998869549914283560f,
+ 0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+ 0.998211003360478190f,
+ 0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+ 0.997402129901275300f,
+ 0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+ 0.996443051350042630f,
+ 0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+ 0.995333912140482280f,
+ 0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+ 0.994074879304879370f,
+ 0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+ 0.992666142448948020f,
+ 0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+ 0.991107913723276890f,
+ 0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+ 0.989400427791380380f,
+ 0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+ 0.987543941794359230f,
+ 0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+ 0.985538735312176060f,
+ 0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+ 0.983385110321551180f,
+ 0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+ 0.981083391150486710f,
+ 0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+ 0.978633924429423210f,
+ 0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+ 0.976037079039039020f,
+ 0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+ 0.973293246054698250f,
+ 0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+ 0.970402838687555500f,
+ 0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+ 0.967366292222328510f,
+ 0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+ 0.964184063951745830f,
+ 0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+ 0.960856633107679660f,
+ 0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+ 0.957384500788975860f,
+ 0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+ 0.953768189885990330f,
+ 0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+ 0.950008245001843000f,
+ 0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+ 0.946105232370403450f,
+ 0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+ 0.942059739771017310f,
+ 0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+ 0.937872376439989890f,
+ 0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+ 0.933543772978836170f,
+ 0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+ 0.929074581259315860f,
+ 0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+ 0.924465474325262600f,
+ 0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+ 0.919717146291227360f,
+ 0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+ 0.914830312237946200f,
+ 0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+ 0.909805708104652220f,
+ 0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+ 0.904644090578246240f,
+ 0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+ 0.899346236979341570f,
+ 0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+ 0.893912945145203250f,
+ 0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+ 0.888345033309596350f,
+ 0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+ 0.882643339979562790f,
+ 0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+ 0.876808723809145650f,
+ 0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+ 0.870842063470078980f,
+ 0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+ 0.864744257519462380f,
+ 0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+ 0.858516224264442740f,
+ 0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+ 0.852158901623919830f,
+ 0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+ 0.845673246987299070f,
+ 0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+ 0.839060237070312740f,
+ 0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+ 0.832320867767929680f,
+ 0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+ 0.825456154004377550f,
+ 0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+ 0.818467129580298660f,
+ 0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+ 0.811354847017063730f,
+ 0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+ 0.804120377398265810f,
+ 0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+ 0.796764810208418830f,
+ 0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+ 0.789289253168885650f,
+ 0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+ 0.781694832071059390f,
+ 0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+ 0.773982690606822900f,
+ 0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+ 0.766153990196312920f,
+ 0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+ 0.758209909813015280f,
+ 0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+ 0.750151645806215070f,
+ 0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+ 0.741980411720831070f,
+ 0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+ 0.733697438114660370f,
+ 0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+ 0.725303972373060770f,
+ 0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+ 0.716801278521099540f,
+ 0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+ 0.708190637033195400f,
+ 0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+ 0.699473344640283770f,
+ 0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+ 0.690650714134534720f,
+ 0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+ 0.681724074171649820f,
+ 0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+ 0.672694769070772970f,
+ 0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+ 0.663564158612039880f,
+ 0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+ 0.654333617831800550f,
+ 0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+ 0.645004536815544040f,
+ 0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+ 0.635578320488556230f,
+ 0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+ 0.626056388404343520f,
+ 0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+ 0.616440174530853650f,
+ 0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+ 0.606731127034524480f,
+ 0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+ 0.596930708062196500f,
+ 0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+ 0.587040393520918080f,
+ 0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+ 0.577061672855679550f,
+ 0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+ 0.566996048825108680f,
+ 0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+ 0.556845037275160100f,
+ 0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+ 0.546610166910834860f,
+ 0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+ 0.536292979065963180f,
+ 0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+ 0.525895027471084740f,
+ 0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+ 0.515417878019463150f,
+ 0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+ 0.504863108531267480f,
+ 0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+ 0.494232308515959730f,
+ 0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+ 0.483527078932918740f,
+ 0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+ 0.472749031950342900f,
+ 0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+ 0.461899790702462840f,
+ 0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+ 0.450980989045103810f,
+ 0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+ 0.439994271309633260f,
+ 0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+ 0.428941292055329550f,
+ 0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+ 0.417823715820212380f,
+ 0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+ 0.406643216870369140f,
+ 0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+ 0.395401478947816300f,
+ 0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+ 0.384100195016935040f,
+ 0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+ 0.372741067009515810f,
+ 0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+ 0.361325805568454340f,
+ 0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+ 0.349856129790135030f,
+ 0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+ 0.338333766965541290f,
+ 0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+ 0.326760452320131790f,
+ 0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+ 0.315137928752522440f,
+ 0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+ 0.303467946572011370f,
+ 0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+ 0.291752263234989370f,
+ 0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+ 0.279992643080273380f,
+ 0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+ 0.268190857063403180f,
+ 0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+ 0.256348682489942910f,
+ 0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+ 0.244467902747824210f,
+ 0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+ 0.232550307038775330f,
+ 0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+ 0.220597690108873650f,
+ 0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+ 0.208611851978263460f,
+ 0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+ 0.196594597670080220f,
+ 0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+ 0.184547736938619640f,
+ 0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+ 0.172473083996796030f,
+ 0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+ 0.160372457242928400f,
+ 0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+ 0.148247678986896200f,
+ 0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+ 0.136100575175706200f,
+ 0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+ 0.123932975118512200f,
+ 0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+ 0.111746711211126660f,
+ 0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+ 0.099543618660069444f,
+ 0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+ 0.087325535206192226f,
+ 0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+ 0.075094300847921291f,
+ 0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+ 0.062851757564161420f,
+ 0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+ 0.050599749036899337f,
+ 0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+ 0.038340120373552791f,
+ 0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+ 0.026074717829104040f,
+ 0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+ 0.013805388528060349f,
+ 0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+ 0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+ 0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+ 0.999996396822294350f,
+ 0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+ 0.999983454831937730f,
+ 0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+ 0.999961100616462820f,
+ 0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+ 0.999929334386276070f,
+ 0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+ 0.999888156440373320f,
+ 0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+ 0.999837567166337090f,
+ 0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+ 0.999777567040332940f,
+ 0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+ 0.999708156627104880f,
+ 0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+ 0.999629336579970110f,
+ 0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+ 0.999541107640812940f,
+ 0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+ 0.999443470640077770f,
+ 0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+ 0.999336426496761240f,
+ 0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+ 0.999219976218403530f,
+ 0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+ 0.999094120901079070f,
+ 0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+ 0.998958861729386080f,
+ 0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+ 0.998814199976435390f,
+ 0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+ 0.998660137003838490f,
+ 0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+ 0.998496674261694640f,
+ 0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+ 0.998323813288577560f,
+ 0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+ 0.998141555711520520f,
+ 0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+ 0.997949903246001190f,
+ 0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+ 0.997748857695925690f,
+ 0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+ 0.997538420953611340f,
+ 0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+ 0.997318594999768600f,
+ 0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+ 0.997089381903483400f,
+ 0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
+ 0.996850783822196610f,
+ 0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
+ 0.996602803001684130f,
+ 0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
+ 0.996345441776035900f,
+ 0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
+ 0.996078702567633980f,
+ 0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
+ 0.995802587887129160f,
+ 0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
+ 0.995517100333418110f,
+ 0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
+ 0.995222242593618360f,
+ 0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
+ 0.994918017443043200f,
+ 0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
+ 0.994604427745175660f,
+ 0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
+ 0.994281476451641550f,
+ 0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
+ 0.993949166602181130f,
+ 0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
+ 0.993607501324621610f,
+ 0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
+ 0.993256483834846440f,
+ 0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
+ 0.992896117436765980f,
+ 0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
+ 0.992526405522286100f,
+ 0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
+ 0.992147351571276090f,
+ 0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
+ 0.991758959151536110f,
+ 0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
+ 0.991361231918763460f,
+ 0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
+ 0.990954173616518500f,
+ 0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
+ 0.990537788076188750f,
+ 0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
+ 0.990112079216953770f,
+ 0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
+ 0.989677051045747210f,
+ 0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
+ 0.989232707657220050f,
+ 0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
+ 0.988779053233701520f,
+ 0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
+ 0.988316092045159690f,
+ 0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
+ 0.987843828449161740f,
+ 0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
+ 0.987362266890832400f,
+ 0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
+ 0.986871411902812470f,
+ 0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
+ 0.986371268105216030f,
+ 0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
+ 0.985861840205586980f,
+ 0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
+ 0.985343132998854790f,
+ 0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
+ 0.984815151367289140f,
+ 0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,
+ 0.984277900280454370f,
+ 0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f,
+ 0.983731384795162090f,
+ 0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f,
+ 0.983175610055424420f,
+ 0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f,
+ 0.982610581292404750f,
+ 0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f,
+ 0.982036303824369020f,
+ 0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f,
+ 0.981452783056635520f,
+ 0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f,
+ 0.980860024481523870f,
+ 0.980710392082253970f, 0.980560182756327840f, 0.980409396592109910f,
+ 0.980258033678303550f,
+ 0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f,
+ 0.979646816313141210f,
+ 0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f,
+ 0.979026378139047580f,
+ 0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f,
+ 0.978396724995823090f,
+ 0.978237872563701090f, 0.978078444659442380f, 0.977918441376834370f,
+ 0.977757862810002760f,
+ 0.977596709053411890f, 0.977434980201864260f, 0.977272676350500860f,
+ 0.977109797594800880f,
+ 0.976946344030581670f, 0.976782315753998650f, 0.976617712861545640f,
+ 0.976452535450054060f,
+ 0.976286783616693630f, 0.976120457458971910f, 0.975953557074734300f,
+ 0.975786082562163930f,
+ 0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f,
+ 0.975110445204038890f,
+ 0.974940101534371830f, 0.974769184332561770f, 0.974597693699155050f,
+ 0.974425629735034990f,
+ 0.974252992541422500f, 0.974079782219875680f, 0.973905998872289570f,
+ 0.973731642600896400f,
+ 0.973556713508265560f, 0.973381211697303290f, 0.973205137271252800f,
+ 0.973028490333694210f,
+ 0.972851270988544180f, 0.972673479340056430f, 0.972495115492821190f,
+ 0.972316179551765300f,
+ 0.972136671622152230f, 0.971956591809581720f, 0.971775940219990140f,
+ 0.971594716959650160f,
+ 0.971412922135170940f, 0.971230555853497380f, 0.971047618221911100f,
+ 0.970864109348029470f,
+ 0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f,
+ 0.970124363593660280f,
+ 0.969938000134323960f, 0.969751066085452140f, 0.969563561557013180f,
+ 0.969375486659311280f,
+ 0.969186841502985950f, 0.968997626199012420f, 0.968807840858700970f,
+ 0.968617485593697540f,
+ 0.968426560515983190f, 0.968235065737874320f, 0.968043001372022260f,
+ 0.967850367531413620f,
+ 0.967657164329369880f, 0.967463391879547550f, 0.967269050295937790f,
+ 0.967074139692867040f,
+ 0.966878660184995910f, 0.966682611887320080f, 0.966485994915169840f,
+ 0.966288809384209690f,
+ 0.966091055410438830f, 0.965892733110190860f, 0.965693842600133690f,
+ 0.965494383997269500f,
+ 0.965294357418934660f, 0.965093762982799590f, 0.964892600806868890f,
+ 0.964690871009481030f,
+ 0.964488573709308410f, 0.964285709025357480f, 0.964082277076968140f,
+ 0.963878277983814200f,
+ 0.963673711865903230f, 0.963468578843575950f, 0.963262879037507070f,
+ 0.963056612568704340f,
+ 0.962849779558509030f, 0.962642380128595710f, 0.962434414400972100f,
+ 0.962225882497979020f,
+ 0.962016784542290560f, 0.961807120656913540f, 0.961596890965187860f,
+ 0.961386095590786250f,
+ 0.961174734657714080f, 0.960962808290309780f, 0.960750316613243950f,
+ 0.960537259751520050f,
+ 0.960323637830473920f, 0.960109450975773940f, 0.959894699313420530f,
+ 0.959679382969746750f,
+ 0.959463502071417510f, 0.959247056745430090f, 0.959030047119113660f,
+ 0.958812473320129310f,
+ 0.958594335476470220f, 0.958375633716461170f, 0.958156368168758820f,
+ 0.957936538962351420f,
+ 0.957716146226558870f, 0.957495190091032570f, 0.957273670685755200f,
+ 0.957051588141040970f,
+ 0.956828942587535370f, 0.956605734156215080f, 0.956381962978387730f,
+ 0.956157629185692140f,
+ 0.955932732910098280f, 0.955707274283906560f, 0.955481253439748770f,
+ 0.955254670510586990f,
+ 0.955027525629714160f, 0.954799818930753720f, 0.954571550547659630f,
+ 0.954342720614716480f,
+ 0.954113329266538800f, 0.953883376638071770f, 0.953652862864590500f,
+ 0.953421788081700310f,
+ 0.953190152425336670f, 0.952957956031764700f, 0.952725199037579570f,
+ 0.952491881579706320f,
+ 0.952258003795399600f, 0.952023565822243570f, 0.951788567798152130f,
+ 0.951553009861368590f,
+ 0.951316892150465550f, 0.951080214804345010f, 0.950842977962238160f,
+ 0.950605181763705340f,
+ 0.950366826348635780f, 0.950127911857248100f, 0.949888438430089300f,
+ 0.949648406208035480f,
+ 0.949407815332291570f, 0.949166665944390700f, 0.948924958186195160f,
+ 0.948682692199895090f,
+ 0.948439868128009620f, 0.948196486113385580f, 0.947952546299198670f,
+ 0.947708048828952100f,
+ 0.947462993846477700f, 0.947217381495934820f, 0.946971211921810880f,
+ 0.946724485268921170f,
+ 0.946477201682408680f, 0.946229361307743820f, 0.945980964290724760f,
+ 0.945732010777477150f,
+ 0.945482500914453740f, 0.945232434848435000f, 0.944981812726528150f,
+ 0.944730634696167800f,
+ 0.944478900905115550f, 0.944226611501459810f, 0.943973766633615980f,
+ 0.943720366450326200f,
+ 0.943466411100659320f, 0.943211900734010620f, 0.942956835500102120f,
+ 0.942701215548981900f,
+ 0.942445041031024890f, 0.942188312096931770f, 0.941931028897729620f,
+ 0.941673191584771360f,
+ 0.941414800309736340f, 0.941155855224629190f, 0.940896356481780830f,
+ 0.940636304233847590f,
+ 0.940375698633811540f, 0.940114539834980280f, 0.939852827990986680f,
+ 0.939590563255789270f,
+ 0.939327745783671400f, 0.939064375729241950f, 0.938800453247434770f,
+ 0.938535978493508560f,
+ 0.938270951623047190f, 0.938005372791958840f, 0.937739242156476970f,
+ 0.937472559873159250f,
+ 0.937205326098887960f, 0.936937540990869900f, 0.936669204706636170f,
+ 0.936400317404042060f,
+ 0.936130879241267030f, 0.935860890376814640f, 0.935590350969512370f,
+ 0.935319261178511610f,
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+ 0.080064707899690932f,
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+ 0.077006223496245585f,
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+ 0.058641104054683348f,
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+ 0.055578150871004817f,
+ 0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
+ 0.052514674564603257f,
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+ 0.049450703970084824f,
+ 0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
+ 0.046386267926707213f,
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+ 0.043321395278109784f,
+ 0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
+ 0.040256114872041358f,
+ 0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
+ 0.037190455560088091f,
+ 0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+ 0.034124446197403423f,
+ 0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+ 0.031058115642434700f,
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+ 0.027991492756653365f,
+ 0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+ 0.024924606404281485f,
+ 0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+ 0.021857485452021874f,
+ 0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+ 0.018790158768784596f,
+ 0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+ 0.015722655225417017f,
+ 0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+ 0.012655003694430301f,
+ 0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+ 0.009587233049729183f,
+ 0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+ 0.006519372166339549f,
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+ 0.003451449920135975f,
+ 0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+ 0.000383495187571497f
+};
+
+static const float32_t cos_factors_8192[8192] = {
+ 1.999999990808214700, 1.999999917273932200, 1.999999770205369800,
+ 1.999999549602533100,
+ 1.999999255465430200, 1.999998887794072000, 1.999998446588471700,
+ 1.999997931848645600,
+ 1.999997343574612800, 1.999996681766395000, 1.999995946424016200,
+ 1.999995137547503600,
+ 1.999994255136887000, 1.999993299192198700, 1.999992269713474200,
+ 1.999991166700750800,
+ 1.999989990154069600, 1.999988740073473500, 1.999987416459008600,
+ 1.999986019310723500,
+ 1.999984548628669600, 1.999983004412901000, 1.999981386663474400,
+ 1.999979695380449400,
+ 1.999977930563888100, 1.999976092213855400, 1.999974180330418700,
+ 1.999972194913648900,
+ 1.999970135963618400, 1.999968003480403000, 1.999965797464081200,
+ 1.999963517914734100,
+ 1.999961164832445800, 1.999958738217302300, 1.999956238069392900,
+ 1.999953664388809800,
+ 1.999951017175647600, 1.999948296430003500, 1.999945502151977600,
+ 1.999942634341672600,
+ 1.999939692999193900, 1.999936678124649700, 1.999933589718150700,
+ 1.999930427779810900,
+ 1.999927192309745900, 1.999923883308075200, 1.999920500774920300,
+ 1.999917044710405500,
+ 1.999913515114657900, 1.999909911987807200, 1.999906235329986100,
+ 1.999902485141329400,
+ 1.999898661421975400, 1.999894764172064600, 1.999890793391740000,
+ 1.999886749081147800,
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+ 1.999869836539117700,
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+ 1.999851747525188200,
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+ 1.999832482050000900,
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+ 1.999812040124888700,
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+ 1.999790421761877400,
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+ 1.999767626973684400,
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+ 1.999743655773719400,
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+ 1.999542919116081000,
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+ 1.999474978999432800,
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+ 1.999364247081633500,
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+ 1.999284544894541100,
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+ 1.999242929597719200,
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+ 1.999200138197791100,
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+ 1.999156170719930100,
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+ 1.999111027190001000,
+ 1.999099557552479900, 1.999088014413782800, 1.999076397774334000,
+ 1.999064707634560700,
+ 1.999052943994892300, 1.999041106855761900, 1.999029196217604100,
+ 1.999017212080857400,
+ 1.999005154445962200, 1.998993023313361700, 1.998980818683502100,
+ 1.998968540556831800,
+ 1.998956188933802800, 1.998943763814868800, 1.998931265200486900,
+ 1.998918693091116200,
+ 1.998906047487219600, 1.998893328389261400, 1.998880535797709700,
+ 1.998867669713034500,
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+ 1.998815470452602400,
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+ 1.998594915211895600,
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+ 1.998477583128690100,
+ 1.998462585960185000, 1.998447515313923400, 1.998432371190459500,
+ 1.998417153590349900,
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+ 1.998355548434686400,
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+ 1.998292767697940100,
+ 1.998276888833522300, 1.998260936498175400, 1.998244910692486000,
+ 1.998228811417043700,
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+ 1.998163679629620500,
+ 1.998147213014344900, 1.998130672932908000, 1.998114059385918400,
+ 1.998097372373986300,
+ 1.998080611897725700, 1.998063777957752600, 1.998046870554686100,
+ 1.998029889689147700,
+ 1.998012835361761900, 1.997995707573155600, 1.997978506323958600,
+ 1.997961231614803200,
+ 1.997943883446324800, 1.997926461819161000, 1.997908966733952500,
+ 1.997891398191342400,
+ 1.997873756191977000, 1.997856040736504500, 1.997838251825576400,
+ 1.997820389459846700,
+ 1.997802453639972300, 1.997784444366612600, 1.997766361640429800,
+ 1.997748205462088500,
+ 1.997729975832256600, 1.997711672751604200, 1.997693296220804000,
+ 1.997674846240532000,
+ 1.997656322811466500, 1.997637725934288300, 1.997619055609681600,
+ 1.997600311838332500,
+ 1.997581494620930300, 1.997562603958166600, 1.997543639850736200,
+ 1.997524602299336500,
+ 1.997505491304667000, 1.997486306867430900, 1.997467048988333000,
+ 1.997447717668082000,
+ 1.997428312907388200, 1.997408834706965000, 1.997389283067528800,
+ 1.997369657989798400,
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+ 1.997290423310406100,
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+ 1.997210013676516700,
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+ 1.997128429135433400,
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+ 1.997045669735150000,
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+ 1.996961735524351900,
+ 1.996940568413280600, 1.996919327880412900, 1.996898013926530000,
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+
+};
+
+/**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingF32Table.gif
+ */
+
+arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize)
+{
+ /* Initialize the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ float32_t *twiddlePtr[4] =
+ { (float32_t *) Weights_128, (float32_t *) Weights_512,
+ (float32_t *) Weights_2048, (float32_t *) Weights_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ float32_t *pCosFactor[4] =
+ { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+ (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT */
+ arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,4284 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_q15.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 Q15
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : weights[n] = e^(-j*n*pi/(2*N))
+* \par
+* C command to generate the table
+*
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* }
+* \par
+* where N is the Number of weights to be calculated and c is pi/(2*N)
+* \par
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is 2*N.
+*/
+
+static const q15_t ALIGN4 WeightsQ15_128[256] = {
+ 0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+ 0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+ 0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+ 0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+ 0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+ 0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+ 0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+ 0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+ 0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+ 0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+ 0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+ 0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+ 0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+ 0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+ 0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+ 0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+ 0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+ 0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+ 0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+ 0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+ 0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+ 0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+ 0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+ 0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+ 0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+ 0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+ 0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+ 0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+ 0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+ 0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+ 0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+ 0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t ALIGN4 WeightsQ15_512[1024] = {
+ 0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+ 0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+ 0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+ 0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+ 0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+ 0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+ 0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+ 0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+ 0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+ 0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+ 0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+ 0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+ 0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+ 0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+ 0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+ 0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+ 0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+ 0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+ 0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+ 0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+ 0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+ 0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+ 0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+ 0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+ 0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+ 0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+ 0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+ 0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+ 0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+ 0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+ 0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+ 0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+ 0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+ 0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+ 0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+ 0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+ 0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+ 0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+ 0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+ 0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+ 0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+ 0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+ 0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+ 0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+ 0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+ 0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+ 0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+ 0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+ 0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+ 0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+ 0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+ 0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+ 0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+ 0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+ 0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+ 0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+ 0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+ 0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+ 0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+ 0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+ 0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+ 0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+ 0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+ 0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+ 0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+ 0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+ 0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+ 0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+ 0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+ 0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+ 0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+ 0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+ 0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+ 0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+ 0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+ 0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+ 0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+ 0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+ 0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+ 0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+ 0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+ 0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+ 0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+ 0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+ 0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+ 0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+ 0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+ 0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+ 0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+ 0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+ 0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+ 0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+ 0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+ 0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+ 0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+ 0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+ 0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+ 0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+ 0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+ 0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+ 0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+ 0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+ 0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+ 0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+ 0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+ 0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+ 0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+ 0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+ 0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+ 0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+ 0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+ 0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+ 0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+ 0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+ 0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+ 0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+ 0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+ 0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+ 0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+ 0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+ 0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+ 0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+ 0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+ 0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+ 0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+ 0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+ 0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+ 0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
+ 0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+ 0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+ 0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+ 0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+ 0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+ 0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+ 0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+ 0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+ 0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+ 0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+ 0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+ 0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+ 0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+ 0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+ 0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+ 0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+ 0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+ 0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+ 0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+ 0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+ 0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+ 0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+ 0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+ 0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+ 0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+ 0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+ 0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+ 0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+ 0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+ 0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+ 0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+ 0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+ 0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+ 0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+ 0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+ 0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+ 0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+ 0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+ 0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+ 0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+ 0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+ 0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+ 0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+ 0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+ 0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+ 0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+ 0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+ 0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+ 0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+ 0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+ 0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+ 0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+ 0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+ 0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+ 0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+ 0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+ 0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+ 0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+ 0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+ 0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+ 0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+ 0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+ 0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+ 0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+ 0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+ 0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+ 0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+ 0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+ 0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+ 0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+ 0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+ 0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+ 0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+ 0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+ 0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+ 0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+ 0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+ 0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+ 0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+ 0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+ 0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+ 0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+ 0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+ 0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+ 0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+ 0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+ 0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+ 0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+ 0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+ 0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+ 0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+ 0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+ 0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+ 0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+ 0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+ 0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+ 0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+ 0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+ 0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+ 0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+ 0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+ 0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+ 0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+ 0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+ 0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+ 0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+ 0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+ 0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+ 0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+ 0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+ 0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+ 0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+ 0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+ 0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+ 0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+ 0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+ 0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+ 0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+ 0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+ 0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+ 0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+ 0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+ 0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+ 0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+ 0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+ 0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+ 0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+ 0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+ 0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+ 0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+ 0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+ 0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+ 0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+ 0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+ 0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+ 0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+ 0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+ 0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+ 0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+ 0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+ 0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+ 0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+ 0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+ 0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+ 0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+ 0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+ 0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+ 0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+ 0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+ 0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+ 0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+ 0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+ 0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+ 0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+ 0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+ 0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+ 0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+ 0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+ 0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+ 0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+ 0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+ 0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+ 0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+ 0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+ 0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+ 0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+ 0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+ 0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+ 0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+ 0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+ 0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+ 0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+ 0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+ 0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+ 0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+ 0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+ 0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+ 0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+ 0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+ 0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+ 0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+ 0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+ 0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+ 0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+ 0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+ 0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+ 0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+ 0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+ 0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+ 0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+ 0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+ 0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+ 0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+ 0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+ 0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+ 0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+ 0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+ 0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+ 0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+ 0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+ 0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+ 0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+ 0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+ 0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+ 0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+ 0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+ 0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+ 0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+ 0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+ 0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+ 0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+ 0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+ 0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+ 0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+ 0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+ 0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+ 0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+ 0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+ 0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+ 0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+ 0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+ 0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+ 0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+ 0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+ 0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+ 0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+ 0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+ 0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+ 0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+ 0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+ 0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+ 0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+ 0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+ 0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+ 0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+ 0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+ 0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+ 0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+ 0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+ 0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+ 0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+ 0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+ 0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+ 0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+ 0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+ 0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+ 0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+ 0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+ 0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+ 0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+ 0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+ 0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+ 0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+ 0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+ 0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+ 0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+ 0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+ 0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+ 0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+ 0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+ 0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+ 0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+ 0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+ 0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+ 0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+ 0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+ 0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+ 0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+ 0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+ 0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+ 0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+ 0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+ 0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+ 0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+ 0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+ 0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+ 0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+ 0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+ 0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+ 0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+ 0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+ 0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+ 0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+ 0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+ 0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+ 0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+ 0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
+ 0x5181, 0x9d4e, 0x516e, 0x9d3e, 0x515a, 0x9d2e, 0x5147, 0x9d1e,
+ 0x5133, 0x9d0e, 0x5120, 0x9cff, 0x510c, 0x9cef, 0x50f9, 0x9cdf,
+ 0x50e5, 0x9ccf, 0x50d2, 0x9cbf, 0x50bf, 0x9caf, 0x50ab, 0x9c9f,
+ 0x5097, 0x9c8f, 0x5084, 0x9c80, 0x5070, 0x9c70, 0x505d, 0x9c60,
+ 0x5049, 0x9c50, 0x5036, 0x9c40, 0x5022, 0x9c31, 0x500f, 0x9c21,
+ 0x4ffb, 0x9c11, 0x4fe7, 0x9c02, 0x4fd4, 0x9bf2, 0x4fc0, 0x9be2,
+ 0x4fac, 0x9bd3, 0x4f99, 0x9bc3, 0x4f85, 0x9bb3, 0x4f71, 0x9ba4,
+ 0x4f5e, 0x9b94, 0x4f4a, 0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,
+ 0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,
+ 0x4ebf, 0x9b18, 0x4eac, 0x9b09, 0x4e98, 0x9af9, 0x4e84, 0x9aea,
+ 0x4e70, 0x9ada, 0x4e5c, 0x9acb, 0x4e48, 0x9abb, 0x4e34, 0x9aac,
+ 0x4e21, 0x9a9d, 0x4e0d, 0x9a8d, 0x4df9, 0x9a7e, 0x4de5, 0x9a6f,
+ 0x4dd1, 0x9a60, 0x4dbd, 0x9a50, 0x4da9, 0x9a41, 0x4d95, 0x9a32,
+ 0x4d81, 0x9a23, 0x4d6d, 0x9a13, 0x4d59, 0x9a04, 0x4d45, 0x99f5,
+ 0x4d31, 0x99e6, 0x4d1d, 0x99d7, 0x4d09, 0x99c7, 0x4cf5, 0x99b8,
+ 0x4ce1, 0x99a9, 0x4ccc, 0x999a, 0x4cb8, 0x998b, 0x4ca4, 0x997c,
+ 0x4c90, 0x996d, 0x4c7c, 0x995e, 0x4c68, 0x994f, 0x4c54, 0x9940,
+ 0x4c3f, 0x9931, 0x4c2b, 0x9922, 0x4c17, 0x9913, 0x4c03, 0x9904,
+ 0x4bef, 0x98f5, 0x4bda, 0x98e6, 0x4bc6, 0x98d7, 0x4bb2, 0x98c9,
+ 0x4b9e, 0x98ba, 0x4b89, 0x98ab, 0x4b75, 0x989c, 0x4b61, 0x988d,
+ 0x4b4c, 0x987e, 0x4b38, 0x9870, 0x4b24, 0x9861, 0x4b0f, 0x9852,
+ 0x4afb, 0x9843, 0x4ae7, 0x9835, 0x4ad2, 0x9826, 0x4abe, 0x9817,
+ 0x4aa9, 0x9809, 0x4a95, 0x97fa, 0x4a81, 0x97eb, 0x4a6c, 0x97dd,
+ 0x4a58, 0x97ce, 0x4a43, 0x97c0, 0x4a2f, 0x97b1, 0x4a1a, 0x97a2,
+ 0x4a06, 0x9794, 0x49f1, 0x9785, 0x49dd, 0x9777, 0x49c8, 0x9768,
+ 0x49b4, 0x975a, 0x499f, 0x974b, 0x498a, 0x973d, 0x4976, 0x972f,
+ 0x4961, 0x9720, 0x494d, 0x9712, 0x4938, 0x9703, 0x4923, 0x96f5,
+ 0x490f, 0x96e7, 0x48fa, 0x96d8, 0x48e6, 0x96ca, 0x48d1, 0x96bc,
+ 0x48bc, 0x96ad, 0x48a8, 0x969f, 0x4893, 0x9691, 0x487e, 0x9683,
+ 0x4869, 0x9674, 0x4855, 0x9666, 0x4840, 0x9658, 0x482b, 0x964a,
+ 0x4816, 0x963c, 0x4802, 0x962d, 0x47ed, 0x961f, 0x47d8, 0x9611,
+ 0x47c3, 0x9603, 0x47ae, 0x95f5, 0x479a, 0x95e7, 0x4785, 0x95d9,
+ 0x4770, 0x95cb, 0x475b, 0x95bd, 0x4746, 0x95af, 0x4731, 0x95a1,
+ 0x471c, 0x9593, 0x4708, 0x9585, 0x46f3, 0x9577, 0x46de, 0x9569,
+ 0x46c9, 0x955b, 0x46b4, 0x954d, 0x469f, 0x953f, 0x468a, 0x9532,
+ 0x4675, 0x9524, 0x4660, 0x9516, 0x464b, 0x9508, 0x4636, 0x94fa,
+ 0x4621, 0x94ed, 0x460c, 0x94df, 0x45f7, 0x94d1, 0x45e2, 0x94c3,
+ 0x45cd, 0x94b6, 0x45b8, 0x94a8, 0x45a3, 0x949a, 0x458d, 0x948d,
+ 0x4578, 0x947f, 0x4563, 0x9471, 0x454e, 0x9464, 0x4539, 0x9456,
+ 0x4524, 0x9448, 0x450f, 0x943b, 0x44fa, 0x942d, 0x44e4, 0x9420,
+ 0x44cf, 0x9412, 0x44ba, 0x9405, 0x44a5, 0x93f7, 0x4490, 0x93ea,
+ 0x447a, 0x93dc, 0x4465, 0x93cf, 0x4450, 0x93c1, 0x443b, 0x93b4,
+ 0x4425, 0x93a7, 0x4410, 0x9399, 0x43fb, 0x938c, 0x43e5, 0x937f,
+ 0x43d0, 0x9371, 0x43bb, 0x9364, 0x43a5, 0x9357, 0x4390, 0x9349,
+ 0x437b, 0x933c, 0x4365, 0x932f, 0x4350, 0x9322, 0x433b, 0x9314,
+ 0x4325, 0x9307, 0x4310, 0x92fa, 0x42fa, 0x92ed, 0x42e5, 0x92e0,
+ 0x42d0, 0x92d3, 0x42ba, 0x92c6, 0x42a5, 0x92b8, 0x428f, 0x92ab,
+ 0x427a, 0x929e, 0x4264, 0x9291, 0x424f, 0x9284, 0x4239, 0x9277,
+ 0x4224, 0x926a, 0x420e, 0x925d, 0x41f9, 0x9250, 0x41e3, 0x9243,
+ 0x41ce, 0x9236, 0x41b8, 0x922a, 0x41a2, 0x921d, 0x418d, 0x9210,
+ 0x4177, 0x9203, 0x4162, 0x91f6, 0x414c, 0x91e9, 0x4136, 0x91dc,
+ 0x4121, 0x91d0, 0x410b, 0x91c3, 0x40f6, 0x91b6, 0x40e0, 0x91a9,
+ 0x40ca, 0x919d, 0x40b5, 0x9190, 0x409f, 0x9183, 0x4089, 0x9177,
+ 0x4073, 0x916a, 0x405e, 0x915d, 0x4048, 0x9151, 0x4032, 0x9144,
+ 0x401d, 0x9137, 0x4007, 0x912b, 0x3ff1, 0x911e, 0x3fdb, 0x9112,
+ 0x3fc5, 0x9105, 0x3fb0, 0x90f9, 0x3f9a, 0x90ec, 0x3f84, 0x90e0,
+ 0x3f6e, 0x90d3, 0x3f58, 0x90c7, 0x3f43, 0x90ba, 0x3f2d, 0x90ae,
+ 0x3f17, 0x90a1, 0x3f01, 0x9095, 0x3eeb, 0x9089, 0x3ed5, 0x907c,
+ 0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,
+ 0x3e68, 0x903f, 0x3e52, 0x9033, 0x3e3c, 0x9026, 0x3e26, 0x901a,
+ 0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,
+ 0x3db8, 0x8fdd, 0x3da2, 0x8fd1, 0x3d8c, 0x8fc5, 0x3d76, 0x8fb9,
+ 0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,
+ 0x3d07, 0x8f7d, 0x3cf1, 0x8f71, 0x3cdb, 0x8f65, 0x3cc5, 0x8f59,
+ 0x3caf, 0x8f4d, 0x3c99, 0x8f41, 0x3c83, 0x8f35, 0x3c6c, 0x8f2a,
+ 0x3c56, 0x8f1e, 0x3c40, 0x8f12, 0x3c2a, 0x8f06, 0x3c14, 0x8efa,
+ 0x3bfd, 0x8eee, 0x3be7, 0x8ee3, 0x3bd1, 0x8ed7, 0x3bbb, 0x8ecb,
+ 0x3ba5, 0x8ebf, 0x3b8e, 0x8eb4, 0x3b78, 0x8ea8, 0x3b62, 0x8e9c,
+ 0x3b4c, 0x8e91, 0x3b35, 0x8e85, 0x3b1f, 0x8e7a, 0x3b09, 0x8e6e,
+ 0x3af2, 0x8e62, 0x3adc, 0x8e57, 0x3ac6, 0x8e4b, 0x3aaf, 0x8e40,
+ 0x3a99, 0x8e34, 0x3a83, 0x8e29, 0x3a6c, 0x8e1d, 0x3a56, 0x8e12,
+ 0x3a40, 0x8e06, 0x3a29, 0x8dfb, 0x3a13, 0x8def, 0x39fd, 0x8de4,
+ 0x39e6, 0x8dd9, 0x39d0, 0x8dcd, 0x39b9, 0x8dc2, 0x39a3, 0x8db7,
+ 0x398c, 0x8dab, 0x3976, 0x8da0, 0x395f, 0x8d95, 0x3949, 0x8d8a,
+ 0x3932, 0x8d7e, 0x391c, 0x8d73, 0x3906, 0x8d68, 0x38ef, 0x8d5d,
+ 0x38d8, 0x8d51, 0x38c2, 0x8d46, 0x38ab, 0x8d3b, 0x3895, 0x8d30,
+ 0x387e, 0x8d25, 0x3868, 0x8d1a, 0x3851, 0x8d0f, 0x383b, 0x8d04,
+ 0x3824, 0x8cf9, 0x380d, 0x8cee, 0x37f7, 0x8ce3, 0x37e0, 0x8cd8,
+ 0x37ca, 0x8ccd, 0x37b3, 0x8cc2, 0x379c, 0x8cb7, 0x3786, 0x8cac,
+ 0x376f, 0x8ca1, 0x3758, 0x8c96, 0x3742, 0x8c8b, 0x372b, 0x8c81,
+ 0x3714, 0x8c76, 0x36fe, 0x8c6b, 0x36e7, 0x8c60, 0x36d0, 0x8c55,
+ 0x36ba, 0x8c4b, 0x36a3, 0x8c40, 0x368c, 0x8c35, 0x3675, 0x8c2a,
+ 0x365f, 0x8c20, 0x3648, 0x8c15, 0x3631, 0x8c0a, 0x361a, 0x8c00,
+ 0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,
+ 0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,
+ 0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,
+ 0x34f2, 0x8b77, 0x34db, 0x8b6d, 0x34c4, 0x8b62, 0x34ad, 0x8b58,
+ 0x3496, 0x8b4e, 0x347f, 0x8b43, 0x3468, 0x8b39, 0x3451, 0x8b2f,
+ 0x343a, 0x8b25, 0x3423, 0x8b1a, 0x340c, 0x8b10, 0x33f5, 0x8b06,
+ 0x33de, 0x8afc, 0x33c7, 0x8af1, 0x33b0, 0x8ae7, 0x3399, 0x8add,
+ 0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,
+ 0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,
+ 0x32ca, 0x8a83, 0x32b3, 0x8a79, 0x329c, 0x8a6f, 0x3285, 0x8a65,
+ 0x326e, 0x8a5b, 0x3257, 0x8a51, 0x3240, 0x8a47, 0x3228, 0x8a3d,
+ 0x3211, 0x8a34, 0x31fa, 0x8a2a, 0x31e3, 0x8a20, 0x31cc, 0x8a16,
+ 0x31b5, 0x8a0c, 0x319e, 0x8a03, 0x3186, 0x89f9, 0x316f, 0x89ef,
+ 0x3158, 0x89e5, 0x3141, 0x89dc, 0x312a, 0x89d2, 0x3112, 0x89c8,
+ 0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,
+ 0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,
+ 0x3041, 0x8972, 0x302a, 0x8969, 0x3013, 0x8960, 0x2ffb, 0x8956,
+ 0x2fe4, 0x894d, 0x2fcd, 0x8943, 0x2fb5, 0x893a, 0x2f9e, 0x8931,
+ 0x2f87, 0x8927, 0x2f6f, 0x891e, 0x2f58, 0x8915, 0x2f41, 0x890b,
+ 0x2f29, 0x8902, 0x2f12, 0x88f9, 0x2efb, 0x88f0, 0x2ee3, 0x88e6,
+ 0x2ecc, 0x88dd, 0x2eb5, 0x88d4, 0x2e9d, 0x88cb, 0x2e86, 0x88c2,
+ 0x2e6e, 0x88b9, 0x2e57, 0x88af, 0x2e3f, 0x88a6, 0x2e28, 0x889d,
+ 0x2e11, 0x8894, 0x2df9, 0x888b, 0x2de2, 0x8882, 0x2dca, 0x8879,
+ 0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,
+ 0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,
+ 0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,
+ 0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
+ 0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,
+ 0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,
+ 0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
+ 0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
+ 0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
+ 0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,
+ 0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
+ 0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
+ 0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
+ 0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
+ 0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
+ 0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
+ 0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
+ 0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
+ 0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
+ 0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
+ 0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
+ 0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
+ 0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
+ 0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
+ 0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
+ 0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
+ 0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
+ 0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
+ 0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
+ 0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
+ 0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
+ 0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+ 0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
+ 0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
+ 0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
+ 0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
+ 0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
+ 0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+ 0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+ 0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+ 0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+ 0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+ 0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+ 0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+ 0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+ 0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+ 0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+ 0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+ 0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+ 0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+ 0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+ 0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+ 0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+ 0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+ 0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+ 0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+ 0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+ 0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+ 0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+ 0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+ 0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+ 0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+ 0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+ 0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+ 0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+ 0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+ 0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+ 0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+ 0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+ 0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+ 0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+ 0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+ 0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+ 0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+ 0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+ 0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+ 0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+ 0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+ 0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+ 0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+ 0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+ 0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+ 0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+ 0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+ 0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+ 0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+ 0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+ 0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+ 0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+ 0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+ 0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+ 0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+ 0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+ 0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+ 0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+ 0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+ 0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+ 0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+ 0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+ 0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+ 0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+ 0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+ 0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+ 0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+ 0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+ 0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+ 0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+ 0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+ 0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+ 0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+ 0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+ 0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+ 0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+ 0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+ 0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+ 0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+ 0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+ 0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+ 0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
+ 0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,
+ 0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,
+ 0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,
+ 0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,
+ 0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,
+ 0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,
+ 0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,
+ 0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,
+ 0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,
+ 0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,
+ 0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,
+ 0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,
+ 0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,
+ 0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,
+ 0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,
+ 0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,
+ 0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,
+ 0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,
+ 0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,
+ 0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,
+ 0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,
+ 0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,
+ 0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,
+ 0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,
+ 0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,
+ 0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,
+ 0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,
+ 0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,
+ 0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,
+ 0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,
+ 0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,
+ 0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,
+ 0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,
+ 0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,
+ 0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,
+ 0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,
+ 0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,
+ 0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,
+ 0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,
+ 0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,
+ 0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,
+ 0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,
+ 0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,
+ 0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,
+ 0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,
+ 0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,
+ 0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,
+ 0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,
+ 0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,
+ 0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,
+ 0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,
+ 0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,
+ 0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,
+ 0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,
+ 0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,
+ 0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,
+ 0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,
+ 0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,
+ 0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,
+ 0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,
+ 0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,
+ 0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,
+ 0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,
+ 0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,
+ 0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,
+ 0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,
+ 0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 0xf974,
+ 0x7fd4, 0xf96d, 0x7fd4, 0xf967, 0x7fd4, 0xf961, 0x7fd3, 0xf95b,
+ 0x7fd3, 0xf954, 0x7fd3, 0xf94e, 0x7fd2, 0xf948, 0x7fd2, 0xf941,
+ 0x7fd2, 0xf93b, 0x7fd1, 0xf935, 0x7fd1, 0xf92f, 0x7fd1, 0xf928,
+ 0x7fd0, 0xf922, 0x7fd0, 0xf91c, 0x7fd0, 0xf916, 0x7fcf, 0xf90f,
+ 0x7fcf, 0xf909, 0x7fcf, 0xf903, 0x7fce, 0xf8fc, 0x7fce, 0xf8f6,
+ 0x7fce, 0xf8f0, 0x7fcd, 0xf8ea, 0x7fcd, 0xf8e3, 0x7fcd, 0xf8dd,
+ 0x7fcc, 0xf8d7, 0x7fcc, 0xf8d0, 0x7fcb, 0xf8ca, 0x7fcb, 0xf8c4,
+ 0x7fcb, 0xf8be, 0x7fca, 0xf8b7, 0x7fca, 0xf8b1, 0x7fca, 0xf8ab,
+ 0x7fc9, 0xf8a5, 0x7fc9, 0xf89e, 0x7fc9, 0xf898, 0x7fc8, 0xf892,
+ 0x7fc8, 0xf88b, 0x7fc7, 0xf885, 0x7fc7, 0xf87f, 0x7fc7, 0xf879,
+ 0x7fc6, 0xf872, 0x7fc6, 0xf86c, 0x7fc6, 0xf866, 0x7fc5, 0xf860,
+ 0x7fc5, 0xf859, 0x7fc5, 0xf853, 0x7fc4, 0xf84d, 0x7fc4, 0xf846,
+ 0x7fc3, 0xf840, 0x7fc3, 0xf83a, 0x7fc3, 0xf834, 0x7fc2, 0xf82d,
+ 0x7fc2, 0xf827, 0x7fc1, 0xf821, 0x7fc1, 0xf81b, 0x7fc1, 0xf814,
+ 0x7fc0, 0xf80e, 0x7fc0, 0xf808, 0x7fc0, 0xf802, 0x7fbf, 0xf7fb,
+ 0x7fbf, 0xf7f5, 0x7fbe, 0xf7ef, 0x7fbe, 0xf7e8, 0x7fbe, 0xf7e2,
+ 0x7fbd, 0xf7dc, 0x7fbd, 0xf7d6, 0x7fbc, 0xf7cf, 0x7fbc, 0xf7c9,
+ 0x7fbc, 0xf7c3, 0x7fbb, 0xf7bd, 0x7fbb, 0xf7b6, 0x7fba, 0xf7b0,
+ 0x7fba, 0xf7aa, 0x7fb9, 0xf7a3, 0x7fb9, 0xf79d, 0x7fb9, 0xf797,
+ 0x7fb8, 0xf791, 0x7fb8, 0xf78a, 0x7fb7, 0xf784, 0x7fb7, 0xf77e,
+ 0x7fb7, 0xf778, 0x7fb6, 0xf771, 0x7fb6, 0xf76b, 0x7fb5, 0xf765,
+ 0x7fb5, 0xf75e, 0x7fb4, 0xf758, 0x7fb4, 0xf752, 0x7fb4, 0xf74c,
+ 0x7fb3, 0xf745, 0x7fb3, 0xf73f, 0x7fb2, 0xf739, 0x7fb2, 0xf733,
+ 0x7fb1, 0xf72c, 0x7fb1, 0xf726, 0x7fb1, 0xf720, 0x7fb0, 0xf71a,
+ 0x7fb0, 0xf713, 0x7faf, 0xf70d, 0x7faf, 0xf707, 0x7fae, 0xf700,
+ 0x7fae, 0xf6fa, 0x7fae, 0xf6f4, 0x7fad, 0xf6ee, 0x7fad, 0xf6e7,
+ 0x7fac, 0xf6e1, 0x7fac, 0xf6db, 0x7fab, 0xf6d5, 0x7fab, 0xf6ce,
+ 0x7faa, 0xf6c8, 0x7faa, 0xf6c2, 0x7fa9, 0xf6bc, 0x7fa9, 0xf6b5,
+ 0x7fa9, 0xf6af, 0x7fa8, 0xf6a9, 0x7fa8, 0xf6a2, 0x7fa7, 0xf69c,
+ 0x7fa7, 0xf696, 0x7fa6, 0xf690, 0x7fa6, 0xf689, 0x7fa5, 0xf683,
+ 0x7fa5, 0xf67d, 0x7fa4, 0xf677, 0x7fa4, 0xf670, 0x7fa3, 0xf66a,
+ 0x7fa3, 0xf664, 0x7fa3, 0xf65e, 0x7fa2, 0xf657, 0x7fa2, 0xf651,
+ 0x7fa1, 0xf64b, 0x7fa1, 0xf644, 0x7fa0, 0xf63e, 0x7fa0, 0xf638,
+ 0x7f9f, 0xf632, 0x7f9f, 0xf62b, 0x7f9e, 0xf625, 0x7f9e, 0xf61f,
+ 0x7f9d, 0xf619, 0x7f9d, 0xf612, 0x7f9c, 0xf60c, 0x7f9c, 0xf606,
+ 0x7f9b, 0xf600, 0x7f9b, 0xf5f9, 0x7f9a, 0xf5f3, 0x7f9a, 0xf5ed,
+ 0x7f99, 0xf5e7, 0x7f99, 0xf5e0, 0x7f98, 0xf5da, 0x7f98, 0xf5d4,
+ 0x7f97, 0xf5cd, 0x7f97, 0xf5c7, 0x7f96, 0xf5c1, 0x7f96, 0xf5bb,
+ 0x7f95, 0xf5b4, 0x7f95, 0xf5ae, 0x7f94, 0xf5a8, 0x7f94, 0xf5a2,
+ 0x7f93, 0xf59b, 0x7f93, 0xf595, 0x7f92, 0xf58f, 0x7f92, 0xf589,
+ 0x7f91, 0xf582, 0x7f91, 0xf57c, 0x7f90, 0xf576, 0x7f90, 0xf570,
+ 0x7f8f, 0xf569, 0x7f8f, 0xf563, 0x7f8e, 0xf55d, 0x7f8e, 0xf556,
+ 0x7f8d, 0xf550, 0x7f8d, 0xf54a, 0x7f8c, 0xf544, 0x7f8b, 0xf53d,
+ 0x7f8b, 0xf537, 0x7f8a, 0xf531, 0x7f8a, 0xf52b, 0x7f89, 0xf524,
+ 0x7f89, 0xf51e, 0x7f88, 0xf518, 0x7f88, 0xf512, 0x7f87, 0xf50b,
+ 0x7f87, 0xf505, 0x7f86, 0xf4ff, 0x7f86, 0xf4f9, 0x7f85, 0xf4f2,
+ 0x7f85, 0xf4ec, 0x7f84, 0xf4e6, 0x7f83, 0xf4e0, 0x7f83, 0xf4d9,
+ 0x7f82, 0xf4d3, 0x7f82, 0xf4cd, 0x7f81, 0xf4c6, 0x7f81, 0xf4c0,
+ 0x7f80, 0xf4ba, 0x7f80, 0xf4b4, 0x7f7f, 0xf4ad, 0x7f7e, 0xf4a7,
+ 0x7f7e, 0xf4a1, 0x7f7d, 0xf49b, 0x7f7d, 0xf494, 0x7f7c, 0xf48e,
+ 0x7f7c, 0xf488, 0x7f7b, 0xf482, 0x7f7b, 0xf47b, 0x7f7a, 0xf475,
+ 0x7f79, 0xf46f, 0x7f79, 0xf469, 0x7f78, 0xf462, 0x7f78, 0xf45c,
+ 0x7f77, 0xf456, 0x7f77, 0xf450, 0x7f76, 0xf449, 0x7f75, 0xf443,
+ 0x7f75, 0xf43d, 0x7f74, 0xf437, 0x7f74, 0xf430, 0x7f73, 0xf42a,
+ 0x7f72, 0xf424, 0x7f72, 0xf41e, 0x7f71, 0xf417, 0x7f71, 0xf411,
+ 0x7f70, 0xf40b, 0x7f70, 0xf405, 0x7f6f, 0xf3fe, 0x7f6e, 0xf3f8,
+ 0x7f6e, 0xf3f2, 0x7f6d, 0xf3ec, 0x7f6d, 0xf3e5, 0x7f6c, 0xf3df,
+ 0x7f6b, 0xf3d9, 0x7f6b, 0xf3d2, 0x7f6a, 0xf3cc, 0x7f6a, 0xf3c6,
+ 0x7f69, 0xf3c0, 0x7f68, 0xf3b9, 0x7f68, 0xf3b3, 0x7f67, 0xf3ad,
+ 0x7f67, 0xf3a7, 0x7f66, 0xf3a0, 0x7f65, 0xf39a, 0x7f65, 0xf394,
+ 0x7f64, 0xf38e, 0x7f64, 0xf387, 0x7f63, 0xf381, 0x7f62, 0xf37b,
+ 0x7f62, 0xf375, 0x7f61, 0xf36e, 0x7f60, 0xf368, 0x7f60, 0xf362,
+ 0x7f5f, 0xf35c, 0x7f5f, 0xf355, 0x7f5e, 0xf34f, 0x7f5d, 0xf349,
+ 0x7f5d, 0xf343, 0x7f5c, 0xf33c, 0x7f5b, 0xf336, 0x7f5b, 0xf330,
+ 0x7f5a, 0xf32a, 0x7f5a, 0xf323, 0x7f59, 0xf31d, 0x7f58, 0xf317,
+ 0x7f58, 0xf311, 0x7f57, 0xf30a, 0x7f56, 0xf304, 0x7f56, 0xf2fe,
+ 0x7f55, 0xf2f8, 0x7f55, 0xf2f1, 0x7f54, 0xf2eb, 0x7f53, 0xf2e5,
+ 0x7f53, 0xf2df, 0x7f52, 0xf2d8, 0x7f51, 0xf2d2, 0x7f51, 0xf2cc,
+ 0x7f50, 0xf2c6, 0x7f4f, 0xf2bf, 0x7f4f, 0xf2b9, 0x7f4e, 0xf2b3,
+ 0x7f4d, 0xf2ad, 0x7f4d, 0xf2a6, 0x7f4c, 0xf2a0, 0x7f4b, 0xf29a,
+ 0x7f4b, 0xf294, 0x7f4a, 0xf28d, 0x7f49, 0xf287, 0x7f49, 0xf281,
+ 0x7f48, 0xf27b, 0x7f47, 0xf274, 0x7f47, 0xf26e, 0x7f46, 0xf268,
+ 0x7f45, 0xf262, 0x7f45, 0xf25b, 0x7f44, 0xf255, 0x7f43, 0xf24f,
+ 0x7f43, 0xf249, 0x7f42, 0xf242, 0x7f41, 0xf23c, 0x7f41, 0xf236,
+ 0x7f40, 0xf230, 0x7f3f, 0xf229, 0x7f3f, 0xf223, 0x7f3e, 0xf21d,
+ 0x7f3d, 0xf217, 0x7f3d, 0xf210, 0x7f3c, 0xf20a, 0x7f3b, 0xf204,
+ 0x7f3b, 0xf1fe, 0x7f3a, 0xf1f7, 0x7f39, 0xf1f1, 0x7f39, 0xf1eb,
+ 0x7f38, 0xf1e5, 0x7f37, 0xf1de, 0x7f36, 0xf1d8, 0x7f36, 0xf1d2,
+ 0x7f35, 0xf1cc, 0x7f34, 0xf1c6, 0x7f34, 0xf1bf, 0x7f33, 0xf1b9,
+ 0x7f32, 0xf1b3, 0x7f32, 0xf1ad, 0x7f31, 0xf1a6, 0x7f30, 0xf1a0,
+ 0x7f2f, 0xf19a, 0x7f2f, 0xf194, 0x7f2e, 0xf18d, 0x7f2d, 0xf187,
+ 0x7f2d, 0xf181, 0x7f2c, 0xf17b, 0x7f2b, 0xf174, 0x7f2a, 0xf16e,
+ 0x7f2a, 0xf168, 0x7f29, 0xf162, 0x7f28, 0xf15b, 0x7f28, 0xf155,
+ 0x7f27, 0xf14f, 0x7f26, 0xf149, 0x7f25, 0xf142, 0x7f25, 0xf13c,
+ 0x7f24, 0xf136, 0x7f23, 0xf130, 0x7f23, 0xf129, 0x7f22, 0xf123,
+ 0x7f21, 0xf11d, 0x7f20, 0xf117, 0x7f20, 0xf110, 0x7f1f, 0xf10a,
+ 0x7f1e, 0xf104, 0x7f1d, 0xf0fe, 0x7f1d, 0xf0f8, 0x7f1c, 0xf0f1,
+ 0x7f1b, 0xf0eb, 0x7f1a, 0xf0e5, 0x7f1a, 0xf0df, 0x7f19, 0xf0d8,
+ 0x7f18, 0xf0d2, 0x7f17, 0xf0cc, 0x7f17, 0xf0c6, 0x7f16, 0xf0bf,
+ 0x7f15, 0xf0b9, 0x7f14, 0xf0b3, 0x7f14, 0xf0ad, 0x7f13, 0xf0a6,
+ 0x7f12, 0xf0a0, 0x7f11, 0xf09a, 0x7f11, 0xf094, 0x7f10, 0xf08d,
+ 0x7f0f, 0xf087, 0x7f0e, 0xf081, 0x7f0e, 0xf07b, 0x7f0d, 0xf075,
+ 0x7f0c, 0xf06e, 0x7f0b, 0xf068, 0x7f0b, 0xf062, 0x7f0a, 0xf05c,
+ 0x7f09, 0xf055, 0x7f08, 0xf04f, 0x7f08, 0xf049, 0x7f07, 0xf043,
+ 0x7f06, 0xf03c, 0x7f05, 0xf036, 0x7f04, 0xf030, 0x7f04, 0xf02a,
+ 0x7f03, 0xf023, 0x7f02, 0xf01d, 0x7f01, 0xf017, 0x7f01, 0xf011,
+ 0x7f00, 0xf00b, 0x7eff, 0xf004, 0x7efe, 0xeffe, 0x7efd, 0xeff8,
+ 0x7efd, 0xeff2, 0x7efc, 0xefeb, 0x7efb, 0xefe5, 0x7efa, 0xefdf,
+ 0x7ef9, 0xefd9, 0x7ef9, 0xefd2, 0x7ef8, 0xefcc, 0x7ef7, 0xefc6,
+ 0x7ef6, 0xefc0, 0x7ef5, 0xefb9, 0x7ef5, 0xefb3, 0x7ef4, 0xefad,
+ 0x7ef3, 0xefa7, 0x7ef2, 0xefa1, 0x7ef1, 0xef9a, 0x7ef1, 0xef94,
+ 0x7ef0, 0xef8e, 0x7eef, 0xef88, 0x7eee, 0xef81, 0x7eed, 0xef7b,
+ 0x7eed, 0xef75, 0x7eec, 0xef6f, 0x7eeb, 0xef68, 0x7eea, 0xef62,
+ 0x7ee9, 0xef5c, 0x7ee9, 0xef56, 0x7ee8, 0xef50, 0x7ee7, 0xef49,
+ 0x7ee6, 0xef43, 0x7ee5, 0xef3d, 0x7ee4, 0xef37, 0x7ee4, 0xef30,
+ 0x7ee3, 0xef2a, 0x7ee2, 0xef24, 0x7ee1, 0xef1e, 0x7ee0, 0xef18,
+ 0x7edf, 0xef11, 0x7edf, 0xef0b, 0x7ede, 0xef05, 0x7edd, 0xeeff,
+ 0x7edc, 0xeef8, 0x7edb, 0xeef2, 0x7eda, 0xeeec, 0x7eda, 0xeee6,
+ 0x7ed9, 0xeedf, 0x7ed8, 0xeed9, 0x7ed7, 0xeed3, 0x7ed6, 0xeecd,
+ 0x7ed5, 0xeec7, 0x7ed5, 0xeec0, 0x7ed4, 0xeeba, 0x7ed3, 0xeeb4,
+ 0x7ed2, 0xeeae, 0x7ed1, 0xeea7, 0x7ed0, 0xeea1, 0x7ecf, 0xee9b,
+ 0x7ecf, 0xee95, 0x7ece, 0xee8f, 0x7ecd, 0xee88, 0x7ecc, 0xee82,
+ 0x7ecb, 0xee7c, 0x7eca, 0xee76, 0x7ec9, 0xee6f, 0x7ec9, 0xee69,
+ 0x7ec8, 0xee63, 0x7ec7, 0xee5d, 0x7ec6, 0xee57, 0x7ec5, 0xee50,
+ 0x7ec4, 0xee4a, 0x7ec3, 0xee44, 0x7ec3, 0xee3e, 0x7ec2, 0xee37,
+ 0x7ec1, 0xee31, 0x7ec0, 0xee2b, 0x7ebf, 0xee25, 0x7ebe, 0xee1f,
+ 0x7ebd, 0xee18, 0x7ebc, 0xee12, 0x7ebb, 0xee0c, 0x7ebb, 0xee06,
+ 0x7eba, 0xedff, 0x7eb9, 0xedf9, 0x7eb8, 0xedf3, 0x7eb7, 0xeded,
+ 0x7eb6, 0xede7, 0x7eb5, 0xede0, 0x7eb4, 0xedda, 0x7eb4, 0xedd4,
+ 0x7eb3, 0xedce, 0x7eb2, 0xedc7, 0x7eb1, 0xedc1, 0x7eb0, 0xedbb,
+ 0x7eaf, 0xedb5, 0x7eae, 0xedaf, 0x7ead, 0xeda8, 0x7eac, 0xeda2,
+ 0x7eab, 0xed9c, 0x7eab, 0xed96, 0x7eaa, 0xed8f, 0x7ea9, 0xed89,
+ 0x7ea8, 0xed83, 0x7ea7, 0xed7d, 0x7ea6, 0xed77, 0x7ea5, 0xed70,
+ 0x7ea4, 0xed6a, 0x7ea3, 0xed64, 0x7ea2, 0xed5e, 0x7ea1, 0xed58,
+ 0x7ea1, 0xed51, 0x7ea0, 0xed4b, 0x7e9f, 0xed45, 0x7e9e, 0xed3f,
+ 0x7e9d, 0xed38, 0x7e9c, 0xed32, 0x7e9b, 0xed2c, 0x7e9a, 0xed26,
+ 0x7e99, 0xed20, 0x7e98, 0xed19, 0x7e97, 0xed13, 0x7e96, 0xed0d,
+ 0x7e95, 0xed07, 0x7e94, 0xed01, 0x7e94, 0xecfa, 0x7e93, 0xecf4,
+ 0x7e92, 0xecee, 0x7e91, 0xece8, 0x7e90, 0xece1, 0x7e8f, 0xecdb,
+ 0x7e8e, 0xecd5, 0x7e8d, 0xeccf, 0x7e8c, 0xecc9, 0x7e8b, 0xecc2,
+ 0x7e8a, 0xecbc, 0x7e89, 0xecb6, 0x7e88, 0xecb0, 0x7e87, 0xecaa,
+ 0x7e86, 0xeca3, 0x7e85, 0xec9d, 0x7e84, 0xec97, 0x7e84, 0xec91,
+ 0x7e83, 0xec8a, 0x7e82, 0xec84, 0x7e81, 0xec7e, 0x7e80, 0xec78,
+ 0x7e7f, 0xec72, 0x7e7e, 0xec6b, 0x7e7d, 0xec65, 0x7e7c, 0xec5f,
+ 0x7e7b, 0xec59, 0x7e7a, 0xec53, 0x7e79, 0xec4c, 0x7e78, 0xec46,
+ 0x7e77, 0xec40, 0x7e76, 0xec3a, 0x7e75, 0xec34, 0x7e74, 0xec2d,
+ 0x7e73, 0xec27, 0x7e72, 0xec21, 0x7e71, 0xec1b, 0x7e70, 0xec15,
+ 0x7e6f, 0xec0e, 0x7e6e, 0xec08, 0x7e6d, 0xec02, 0x7e6c, 0xebfc,
+ 0x7e6b, 0xebf5, 0x7e6a, 0xebef, 0x7e69, 0xebe9, 0x7e68, 0xebe3,
+ 0x7e67, 0xebdd, 0x7e66, 0xebd6, 0x7e65, 0xebd0, 0x7e64, 0xebca,
+ 0x7e63, 0xebc4, 0x7e62, 0xebbe, 0x7e61, 0xebb7, 0x7e60, 0xebb1,
+ 0x7e5f, 0xebab, 0x7e5e, 0xeba5, 0x7e5d, 0xeb9f, 0x7e5c, 0xeb98,
+ 0x7e5b, 0xeb92, 0x7e5a, 0xeb8c, 0x7e59, 0xeb86, 0x7e58, 0xeb80,
+ 0x7e57, 0xeb79, 0x7e56, 0xeb73, 0x7e55, 0xeb6d, 0x7e54, 0xeb67,
+ 0x7e53, 0xeb61, 0x7e52, 0xeb5a, 0x7e51, 0xeb54, 0x7e50, 0xeb4e,
+ 0x7e4f, 0xeb48, 0x7e4e, 0xeb42, 0x7e4d, 0xeb3b, 0x7e4c, 0xeb35,
+ 0x7e4b, 0xeb2f, 0x7e4a, 0xeb29, 0x7e49, 0xeb23, 0x7e48, 0xeb1c,
+ 0x7e47, 0xeb16, 0x7e46, 0xeb10, 0x7e45, 0xeb0a, 0x7e44, 0xeb04,
+ 0x7e43, 0xeafd, 0x7e42, 0xeaf7, 0x7e41, 0xeaf1, 0x7e40, 0xeaeb,
+ 0x7e3f, 0xeae5, 0x7e3e, 0xeade, 0x7e3d, 0xead8, 0x7e3c, 0xead2,
+ 0x7e3b, 0xeacc, 0x7e3a, 0xeac6, 0x7e39, 0xeabf, 0x7e38, 0xeab9,
+ 0x7e37, 0xeab3, 0x7e35, 0xeaad, 0x7e34, 0xeaa7, 0x7e33, 0xeaa0,
+ 0x7e32, 0xea9a, 0x7e31, 0xea94, 0x7e30, 0xea8e, 0x7e2f, 0xea88,
+ 0x7e2e, 0xea81, 0x7e2d, 0xea7b, 0x7e2c, 0xea75, 0x7e2b, 0xea6f,
+ 0x7e2a, 0xea69, 0x7e29, 0xea63, 0x7e28, 0xea5c, 0x7e27, 0xea56,
+ 0x7e26, 0xea50, 0x7e25, 0xea4a, 0x7e24, 0xea44, 0x7e22, 0xea3d,
+ 0x7e21, 0xea37, 0x7e20, 0xea31, 0x7e1f, 0xea2b, 0x7e1e, 0xea25,
+ 0x7e1d, 0xea1e, 0x7e1c, 0xea18, 0x7e1b, 0xea12, 0x7e1a, 0xea0c,
+ 0x7e19, 0xea06, 0x7e18, 0xe9ff, 0x7e17, 0xe9f9, 0x7e16, 0xe9f3,
+ 0x7e14, 0xe9ed, 0x7e13, 0xe9e7, 0x7e12, 0xe9e1, 0x7e11, 0xe9da,
+ 0x7e10, 0xe9d4, 0x7e0f, 0xe9ce, 0x7e0e, 0xe9c8, 0x7e0d, 0xe9c2,
+ 0x7e0c, 0xe9bb, 0x7e0b, 0xe9b5, 0x7e0a, 0xe9af, 0x7e08, 0xe9a9,
+ 0x7e07, 0xe9a3, 0x7e06, 0xe99c, 0x7e05, 0xe996, 0x7e04, 0xe990,
+ 0x7e03, 0xe98a, 0x7e02, 0xe984, 0x7e01, 0xe97e, 0x7e00, 0xe977,
+ 0x7dff, 0xe971, 0x7dfd, 0xe96b, 0x7dfc, 0xe965, 0x7dfb, 0xe95f,
+ 0x7dfa, 0xe958, 0x7df9, 0xe952, 0x7df8, 0xe94c, 0x7df7, 0xe946,
+ 0x7df6, 0xe940, 0x7df5, 0xe93a, 0x7df3, 0xe933, 0x7df2, 0xe92d,
+ 0x7df1, 0xe927, 0x7df0, 0xe921, 0x7def, 0xe91b, 0x7dee, 0xe914,
+ 0x7ded, 0xe90e, 0x7dec, 0xe908, 0x7dea, 0xe902, 0x7de9, 0xe8fc,
+ 0x7de8, 0xe8f6, 0x7de7, 0xe8ef, 0x7de6, 0xe8e9, 0x7de5, 0xe8e3,
+ 0x7de4, 0xe8dd, 0x7de2, 0xe8d7, 0x7de1, 0xe8d0, 0x7de0, 0xe8ca,
+ 0x7ddf, 0xe8c4, 0x7dde, 0xe8be, 0x7ddd, 0xe8b8, 0x7ddc, 0xe8b2,
+ 0x7dda, 0xe8ab, 0x7dd9, 0xe8a5, 0x7dd8, 0xe89f, 0x7dd7, 0xe899,
+ 0x7dd6, 0xe893, 0x7dd5, 0xe88c, 0x7dd4, 0xe886, 0x7dd2, 0xe880,
+ 0x7dd1, 0xe87a, 0x7dd0, 0xe874, 0x7dcf, 0xe86e, 0x7dce, 0xe867,
+ 0x7dcd, 0xe861, 0x7dcc, 0xe85b, 0x7dca, 0xe855, 0x7dc9, 0xe84f,
+ 0x7dc8, 0xe849, 0x7dc7, 0xe842, 0x7dc6, 0xe83c, 0x7dc5, 0xe836,
+ 0x7dc3, 0xe830, 0x7dc2, 0xe82a, 0x7dc1, 0xe823, 0x7dc0, 0xe81d,
+ 0x7dbf, 0xe817, 0x7dbd, 0xe811, 0x7dbc, 0xe80b, 0x7dbb, 0xe805,
+ 0x7dba, 0xe7fe, 0x7db9, 0xe7f8, 0x7db8, 0xe7f2, 0x7db6, 0xe7ec,
+ 0x7db5, 0xe7e6, 0x7db4, 0xe7e0, 0x7db3, 0xe7d9, 0x7db2, 0xe7d3,
+ 0x7db0, 0xe7cd, 0x7daf, 0xe7c7, 0x7dae, 0xe7c1, 0x7dad, 0xe7bb,
+ 0x7dac, 0xe7b4, 0x7dab, 0xe7ae, 0x7da9, 0xe7a8, 0x7da8, 0xe7a2,
+ 0x7da7, 0xe79c, 0x7da6, 0xe796, 0x7da5, 0xe78f, 0x7da3, 0xe789,
+ 0x7da2, 0xe783, 0x7da1, 0xe77d, 0x7da0, 0xe777, 0x7d9f, 0xe771,
+ 0x7d9d, 0xe76a, 0x7d9c, 0xe764, 0x7d9b, 0xe75e, 0x7d9a, 0xe758,
+ 0x7d98, 0xe752, 0x7d97, 0xe74c, 0x7d96, 0xe745, 0x7d95, 0xe73f,
+ 0x7d94, 0xe739, 0x7d92, 0xe733, 0x7d91, 0xe72d, 0x7d90, 0xe727,
+ 0x7d8f, 0xe720, 0x7d8e, 0xe71a, 0x7d8c, 0xe714, 0x7d8b, 0xe70e,
+ 0x7d8a, 0xe708, 0x7d89, 0xe702, 0x7d87, 0xe6fb, 0x7d86, 0xe6f5,
+ 0x7d85, 0xe6ef, 0x7d84, 0xe6e9, 0x7d82, 0xe6e3, 0x7d81, 0xe6dd,
+ 0x7d80, 0xe6d6, 0x7d7f, 0xe6d0, 0x7d7e, 0xe6ca, 0x7d7c, 0xe6c4,
+ 0x7d7b, 0xe6be, 0x7d7a, 0xe6b8, 0x7d79, 0xe6b2, 0x7d77, 0xe6ab,
+ 0x7d76, 0xe6a5, 0x7d75, 0xe69f, 0x7d74, 0xe699, 0x7d72, 0xe693,
+ 0x7d71, 0xe68d, 0x7d70, 0xe686, 0x7d6f, 0xe680, 0x7d6d, 0xe67a,
+ 0x7d6c, 0xe674, 0x7d6b, 0xe66e, 0x7d6a, 0xe668, 0x7d68, 0xe661,
+ 0x7d67, 0xe65b, 0x7d66, 0xe655, 0x7d65, 0xe64f, 0x7d63, 0xe649,
+ 0x7d62, 0xe643, 0x7d61, 0xe63d, 0x7d60, 0xe636, 0x7d5e, 0xe630,
+ 0x7d5d, 0xe62a, 0x7d5c, 0xe624, 0x7d5a, 0xe61e, 0x7d59, 0xe618,
+ 0x7d58, 0xe611, 0x7d57, 0xe60b, 0x7d55, 0xe605, 0x7d54, 0xe5ff,
+ 0x7d53, 0xe5f9, 0x7d52, 0xe5f3, 0x7d50, 0xe5ed, 0x7d4f, 0xe5e6,
+ 0x7d4e, 0xe5e0, 0x7d4c, 0xe5da, 0x7d4b, 0xe5d4, 0x7d4a, 0xe5ce,
+ 0x7d49, 0xe5c8, 0x7d47, 0xe5c2, 0x7d46, 0xe5bb, 0x7d45, 0xe5b5,
+ 0x7d43, 0xe5af, 0x7d42, 0xe5a9, 0x7d41, 0xe5a3, 0x7d3f, 0xe59d,
+ 0x7d3e, 0xe596, 0x7d3d, 0xe590, 0x7d3c, 0xe58a, 0x7d3a, 0xe584,
+ 0x7d39, 0xe57e, 0x7d38, 0xe578, 0x7d36, 0xe572, 0x7d35, 0xe56b,
+ 0x7d34, 0xe565, 0x7d32, 0xe55f, 0x7d31, 0xe559, 0x7d30, 0xe553,
+ 0x7d2f, 0xe54d, 0x7d2d, 0xe547, 0x7d2c, 0xe540, 0x7d2b, 0xe53a,
+ 0x7d29, 0xe534, 0x7d28, 0xe52e, 0x7d27, 0xe528, 0x7d25, 0xe522,
+ 0x7d24, 0xe51c, 0x7d23, 0xe515, 0x7d21, 0xe50f, 0x7d20, 0xe509,
+ 0x7d1f, 0xe503, 0x7d1d, 0xe4fd, 0x7d1c, 0xe4f7, 0x7d1b, 0xe4f1,
+ 0x7d19, 0xe4ea, 0x7d18, 0xe4e4, 0x7d17, 0xe4de, 0x7d15, 0xe4d8,
+ 0x7d14, 0xe4d2, 0x7d13, 0xe4cc, 0x7d11, 0xe4c6, 0x7d10, 0xe4bf,
+ 0x7d0f, 0xe4b9, 0x7d0d, 0xe4b3, 0x7d0c, 0xe4ad, 0x7d0b, 0xe4a7,
+ 0x7d09, 0xe4a1, 0x7d08, 0xe49b, 0x7d07, 0xe494, 0x7d05, 0xe48e,
+ 0x7d04, 0xe488, 0x7d03, 0xe482, 0x7d01, 0xe47c, 0x7d00, 0xe476,
+ 0x7cff, 0xe470, 0x7cfd, 0xe46a, 0x7cfc, 0xe463, 0x7cfb, 0xe45d,
+ 0x7cf9, 0xe457, 0x7cf8, 0xe451, 0x7cf6, 0xe44b, 0x7cf5, 0xe445,
+ 0x7cf4, 0xe43f, 0x7cf2, 0xe438, 0x7cf1, 0xe432, 0x7cf0, 0xe42c,
+ 0x7cee, 0xe426, 0x7ced, 0xe420, 0x7cec, 0xe41a, 0x7cea, 0xe414,
+ 0x7ce9, 0xe40e, 0x7ce7, 0xe407, 0x7ce6, 0xe401, 0x7ce5, 0xe3fb,
+ 0x7ce3, 0xe3f5, 0x7ce2, 0xe3ef, 0x7ce1, 0xe3e9, 0x7cdf, 0xe3e3,
+ 0x7cde, 0xe3dc, 0x7cdc, 0xe3d6, 0x7cdb, 0xe3d0, 0x7cda, 0xe3ca,
+ 0x7cd8, 0xe3c4, 0x7cd7, 0xe3be, 0x7cd5, 0xe3b8, 0x7cd4, 0xe3b2,
+ 0x7cd3, 0xe3ab, 0x7cd1, 0xe3a5, 0x7cd0, 0xe39f, 0x7ccf, 0xe399,
+ 0x7ccd, 0xe393, 0x7ccc, 0xe38d, 0x7cca, 0xe387, 0x7cc9, 0xe381,
+ 0x7cc8, 0xe37a, 0x7cc6, 0xe374, 0x7cc5, 0xe36e, 0x7cc3, 0xe368,
+ 0x7cc2, 0xe362, 0x7cc1, 0xe35c, 0x7cbf, 0xe356, 0x7cbe, 0xe350,
+ 0x7cbc, 0xe349, 0x7cbb, 0xe343, 0x7cb9, 0xe33d, 0x7cb8, 0xe337,
+ 0x7cb7, 0xe331, 0x7cb5, 0xe32b, 0x7cb4, 0xe325, 0x7cb2, 0xe31f,
+ 0x7cb1, 0xe318, 0x7cb0, 0xe312, 0x7cae, 0xe30c, 0x7cad, 0xe306,
+ 0x7cab, 0xe300, 0x7caa, 0xe2fa, 0x7ca8, 0xe2f4, 0x7ca7, 0xe2ee,
+ 0x7ca6, 0xe2e8, 0x7ca4, 0xe2e1, 0x7ca3, 0xe2db, 0x7ca1, 0xe2d5,
+ 0x7ca0, 0xe2cf, 0x7c9e, 0xe2c9, 0x7c9d, 0xe2c3, 0x7c9c, 0xe2bd,
+ 0x7c9a, 0xe2b7, 0x7c99, 0xe2b0, 0x7c97, 0xe2aa, 0x7c96, 0xe2a4,
+ 0x7c94, 0xe29e, 0x7c93, 0xe298, 0x7c91, 0xe292, 0x7c90, 0xe28c,
+ 0x7c8f, 0xe286, 0x7c8d, 0xe280, 0x7c8c, 0xe279, 0x7c8a, 0xe273,
+ 0x7c89, 0xe26d, 0x7c87, 0xe267, 0x7c86, 0xe261, 0x7c84, 0xe25b,
+ 0x7c83, 0xe255, 0x7c82, 0xe24f, 0x7c80, 0xe249, 0x7c7f, 0xe242,
+ 0x7c7d, 0xe23c, 0x7c7c, 0xe236, 0x7c7a, 0xe230, 0x7c79, 0xe22a,
+ 0x7c77, 0xe224, 0x7c76, 0xe21e, 0x7c74, 0xe218, 0x7c73, 0xe212,
+ 0x7c71, 0xe20b, 0x7c70, 0xe205, 0x7c6e, 0xe1ff, 0x7c6d, 0xe1f9,
+ 0x7c6c, 0xe1f3, 0x7c6a, 0xe1ed, 0x7c69, 0xe1e7, 0x7c67, 0xe1e1,
+ 0x7c66, 0xe1db, 0x7c64, 0xe1d4, 0x7c63, 0xe1ce, 0x7c61, 0xe1c8,
+ 0x7c60, 0xe1c2, 0x7c5e, 0xe1bc, 0x7c5d, 0xe1b6, 0x7c5b, 0xe1b0,
+ 0x7c5a, 0xe1aa, 0x7c58, 0xe1a4, 0x7c57, 0xe19e, 0x7c55, 0xe197,
+ 0x7c54, 0xe191, 0x7c52, 0xe18b, 0x7c51, 0xe185, 0x7c4f, 0xe17f,
+ 0x7c4e, 0xe179, 0x7c4c, 0xe173, 0x7c4b, 0xe16d, 0x7c49, 0xe167,
+ 0x7c48, 0xe160, 0x7c46, 0xe15a, 0x7c45, 0xe154, 0x7c43, 0xe14e,
+ 0x7c42, 0xe148, 0x7c40, 0xe142, 0x7c3f, 0xe13c, 0x7c3d, 0xe136,
+ 0x7c3c, 0xe130, 0x7c3a, 0xe12a, 0x7c39, 0xe123, 0x7c37, 0xe11d,
+ 0x7c36, 0xe117, 0x7c34, 0xe111, 0x7c33, 0xe10b, 0x7c31, 0xe105,
+ 0x7c30, 0xe0ff, 0x7c2e, 0xe0f9, 0x7c2d, 0xe0f3, 0x7c2b, 0xe0ed,
+ 0x7c29, 0xe0e7, 0x7c28, 0xe0e0, 0x7c26, 0xe0da, 0x7c25, 0xe0d4,
+ 0x7c23, 0xe0ce, 0x7c22, 0xe0c8, 0x7c20, 0xe0c2, 0x7c1f, 0xe0bc,
+ 0x7c1d, 0xe0b6, 0x7c1c, 0xe0b0, 0x7c1a, 0xe0aa, 0x7c19, 0xe0a3,
+ 0x7c17, 0xe09d, 0x7c16, 0xe097, 0x7c14, 0xe091, 0x7c12, 0xe08b,
+ 0x7c11, 0xe085, 0x7c0f, 0xe07f, 0x7c0e, 0xe079, 0x7c0c, 0xe073,
+ 0x7c0b, 0xe06d, 0x7c09, 0xe067, 0x7c08, 0xe061, 0x7c06, 0xe05a,
+ 0x7c05, 0xe054, 0x7c03, 0xe04e, 0x7c01, 0xe048, 0x7c00, 0xe042,
+ 0x7bfe, 0xe03c, 0x7bfd, 0xe036, 0x7bfb, 0xe030, 0x7bfa, 0xe02a,
+ 0x7bf8, 0xe024, 0x7bf6, 0xe01e, 0x7bf5, 0xe017, 0x7bf3, 0xe011,
+ 0x7bf2, 0xe00b, 0x7bf0, 0xe005, 0x7bef, 0xdfff, 0x7bed, 0xdff9,
+ 0x7beb, 0xdff3, 0x7bea, 0xdfed, 0x7be8, 0xdfe7, 0x7be7, 0xdfe1,
+ 0x7be5, 0xdfdb, 0x7be4, 0xdfd5, 0x7be2, 0xdfce, 0x7be0, 0xdfc8,
+ 0x7bdf, 0xdfc2, 0x7bdd, 0xdfbc, 0x7bdc, 0xdfb6, 0x7bda, 0xdfb0,
+ 0x7bd9, 0xdfaa, 0x7bd7, 0xdfa4, 0x7bd5, 0xdf9e, 0x7bd4, 0xdf98,
+ 0x7bd2, 0xdf92, 0x7bd1, 0xdf8c, 0x7bcf, 0xdf86, 0x7bcd, 0xdf7f,
+ 0x7bcc, 0xdf79, 0x7bca, 0xdf73, 0x7bc9, 0xdf6d, 0x7bc7, 0xdf67,
+ 0x7bc5, 0xdf61, 0x7bc4, 0xdf5b, 0x7bc2, 0xdf55, 0x7bc1, 0xdf4f,
+ 0x7bbf, 0xdf49, 0x7bbd, 0xdf43, 0x7bbc, 0xdf3d, 0x7bba, 0xdf37,
+ 0x7bb9, 0xdf30, 0x7bb7, 0xdf2a, 0x7bb5, 0xdf24, 0x7bb4, 0xdf1e,
+ 0x7bb2, 0xdf18, 0x7bb0, 0xdf12, 0x7baf, 0xdf0c, 0x7bad, 0xdf06,
+ 0x7bac, 0xdf00, 0x7baa, 0xdefa, 0x7ba8, 0xdef4, 0x7ba7, 0xdeee,
+ 0x7ba5, 0xdee8, 0x7ba3, 0xdee2, 0x7ba2, 0xdedb, 0x7ba0, 0xded5,
+ 0x7b9f, 0xdecf, 0x7b9d, 0xdec9, 0x7b9b, 0xdec3, 0x7b9a, 0xdebd,
+ 0x7b98, 0xdeb7, 0x7b96, 0xdeb1, 0x7b95, 0xdeab, 0x7b93, 0xdea5,
+ 0x7b92, 0xde9f, 0x7b90, 0xde99, 0x7b8e, 0xde93, 0x7b8d, 0xde8d,
+ 0x7b8b, 0xde87, 0x7b89, 0xde80, 0x7b88, 0xde7a, 0x7b86, 0xde74,
+ 0x7b84, 0xde6e, 0x7b83, 0xde68, 0x7b81, 0xde62, 0x7b7f, 0xde5c,
+ 0x7b7e, 0xde56, 0x7b7c, 0xde50, 0x7b7a, 0xde4a, 0x7b79, 0xde44,
+ 0x7b77, 0xde3e, 0x7b76, 0xde38, 0x7b74, 0xde32, 0x7b72, 0xde2c,
+ 0x7b71, 0xde26, 0x7b6f, 0xde1f, 0x7b6d, 0xde19, 0x7b6c, 0xde13,
+ 0x7b6a, 0xde0d, 0x7b68, 0xde07, 0x7b67, 0xde01, 0x7b65, 0xddfb,
+ 0x7b63, 0xddf5, 0x7b62, 0xddef, 0x7b60, 0xdde9, 0x7b5e, 0xdde3,
+ 0x7b5d, 0xdddd, 0x7b5b, 0xddd7, 0x7b59, 0xddd1, 0x7b57, 0xddcb,
+ 0x7b56, 0xddc5, 0x7b54, 0xddbf, 0x7b52, 0xddb9, 0x7b51, 0xddb2,
+ 0x7b4f, 0xddac, 0x7b4d, 0xdda6, 0x7b4c, 0xdda0, 0x7b4a, 0xdd9a,
+ 0x7b48, 0xdd94, 0x7b47, 0xdd8e, 0x7b45, 0xdd88, 0x7b43, 0xdd82,
+ 0x7b42, 0xdd7c, 0x7b40, 0xdd76, 0x7b3e, 0xdd70, 0x7b3c, 0xdd6a,
+ 0x7b3b, 0xdd64, 0x7b39, 0xdd5e, 0x7b37, 0xdd58, 0x7b36, 0xdd52,
+ 0x7b34, 0xdd4c, 0x7b32, 0xdd46, 0x7b31, 0xdd40, 0x7b2f, 0xdd39,
+ 0x7b2d, 0xdd33, 0x7b2b, 0xdd2d, 0x7b2a, 0xdd27, 0x7b28, 0xdd21,
+ 0x7b26, 0xdd1b, 0x7b25, 0xdd15, 0x7b23, 0xdd0f, 0x7b21, 0xdd09,
+ 0x7b1f, 0xdd03, 0x7b1e, 0xdcfd, 0x7b1c, 0xdcf7, 0x7b1a, 0xdcf1,
+ 0x7b19, 0xdceb, 0x7b17, 0xdce5, 0x7b15, 0xdcdf, 0x7b13, 0xdcd9,
+ 0x7b12, 0xdcd3, 0x7b10, 0xdccd, 0x7b0e, 0xdcc7, 0x7b0c, 0xdcc1,
+ 0x7b0b, 0xdcbb, 0x7b09, 0xdcb5, 0x7b07, 0xdcae, 0x7b06, 0xdca8,
+ 0x7b04, 0xdca2, 0x7b02, 0xdc9c, 0x7b00, 0xdc96, 0x7aff, 0xdc90,
+ 0x7afd, 0xdc8a, 0x7afb, 0xdc84, 0x7af9, 0xdc7e, 0x7af8, 0xdc78,
+ 0x7af6, 0xdc72, 0x7af4, 0xdc6c, 0x7af2, 0xdc66, 0x7af1, 0xdc60,
+ 0x7aef, 0xdc5a, 0x7aed, 0xdc54, 0x7aeb, 0xdc4e, 0x7aea, 0xdc48,
+ 0x7ae8, 0xdc42, 0x7ae6, 0xdc3c, 0x7ae4, 0xdc36, 0x7ae3, 0xdc30,
+ 0x7ae1, 0xdc2a, 0x7adf, 0xdc24, 0x7add, 0xdc1e, 0x7adc, 0xdc18,
+ 0x7ada, 0xdc12, 0x7ad8, 0xdc0c, 0x7ad6, 0xdc06, 0x7ad5, 0xdbff,
+ 0x7ad3, 0xdbf9, 0x7ad1, 0xdbf3, 0x7acf, 0xdbed, 0x7acd, 0xdbe7,
+ 0x7acc, 0xdbe1, 0x7aca, 0xdbdb, 0x7ac8, 0xdbd5, 0x7ac6, 0xdbcf,
+ 0x7ac5, 0xdbc9, 0x7ac3, 0xdbc3, 0x7ac1, 0xdbbd, 0x7abf, 0xdbb7,
+ 0x7abd, 0xdbb1, 0x7abc, 0xdbab, 0x7aba, 0xdba5, 0x7ab8, 0xdb9f,
+ 0x7ab6, 0xdb99, 0x7ab5, 0xdb93, 0x7ab3, 0xdb8d, 0x7ab1, 0xdb87,
+ 0x7aaf, 0xdb81, 0x7aad, 0xdb7b, 0x7aac, 0xdb75, 0x7aaa, 0xdb6f,
+ 0x7aa8, 0xdb69, 0x7aa6, 0xdb63, 0x7aa4, 0xdb5d, 0x7aa3, 0xdb57,
+ 0x7aa1, 0xdb51, 0x7a9f, 0xdb4b, 0x7a9d, 0xdb45, 0x7a9b, 0xdb3f,
+ 0x7a9a, 0xdb39, 0x7a98, 0xdb33, 0x7a96, 0xdb2d, 0x7a94, 0xdb27,
+ 0x7a92, 0xdb21, 0x7a91, 0xdb1b, 0x7a8f, 0xdb15, 0x7a8d, 0xdb0f,
+ 0x7a8b, 0xdb09, 0x7a89, 0xdb03, 0x7a87, 0xdafd, 0x7a86, 0xdaf7,
+ 0x7a84, 0xdaf1, 0x7a82, 0xdaea, 0x7a80, 0xdae4, 0x7a7e, 0xdade,
+ 0x7a7d, 0xdad8, 0x7a7b, 0xdad2, 0x7a79, 0xdacc, 0x7a77, 0xdac6,
+ 0x7a75, 0xdac0, 0x7a73, 0xdaba, 0x7a72, 0xdab4, 0x7a70, 0xdaae,
+ 0x7a6e, 0xdaa8, 0x7a6c, 0xdaa2, 0x7a6a, 0xda9c, 0x7a68, 0xda96,
+ 0x7a67, 0xda90, 0x7a65, 0xda8a, 0x7a63, 0xda84, 0x7a61, 0xda7e,
+ 0x7a5f, 0xda78, 0x7a5d, 0xda72, 0x7a5c, 0xda6c, 0x7a5a, 0xda66,
+ 0x7a58, 0xda60, 0x7a56, 0xda5a, 0x7a54, 0xda54, 0x7a52, 0xda4e,
+ 0x7a50, 0xda48, 0x7a4f, 0xda42, 0x7a4d, 0xda3c, 0x7a4b, 0xda36,
+ 0x7a49, 0xda30, 0x7a47, 0xda2a, 0x7a45, 0xda24, 0x7a43, 0xda1e,
+ 0x7a42, 0xda18, 0x7a40, 0xda12, 0x7a3e, 0xda0c, 0x7a3c, 0xda06,
+ 0x7a3a, 0xda00, 0x7a38, 0xd9fa, 0x7a36, 0xd9f4, 0x7a35, 0xd9ee,
+ 0x7a33, 0xd9e8, 0x7a31, 0xd9e2, 0x7a2f, 0xd9dc, 0x7a2d, 0xd9d6,
+ 0x7a2b, 0xd9d0, 0x7a29, 0xd9ca, 0x7a27, 0xd9c4, 0x7a26, 0xd9be,
+ 0x7a24, 0xd9b8, 0x7a22, 0xd9b2, 0x7a20, 0xd9ac, 0x7a1e, 0xd9a6,
+ 0x7a1c, 0xd9a0, 0x7a1a, 0xd99a, 0x7a18, 0xd994, 0x7a16, 0xd98e,
+ 0x7a15, 0xd988, 0x7a13, 0xd982, 0x7a11, 0xd97c, 0x7a0f, 0xd976,
+ 0x7a0d, 0xd970, 0x7a0b, 0xd96a, 0x7a09, 0xd964, 0x7a07, 0xd95e,
+ 0x7a05, 0xd958, 0x7a04, 0xd952, 0x7a02, 0xd94c, 0x7a00, 0xd946,
+ 0x79fe, 0xd940, 0x79fc, 0xd93a, 0x79fa, 0xd934, 0x79f8, 0xd92e,
+ 0x79f6, 0xd928, 0x79f4, 0xd922, 0x79f2, 0xd91c, 0x79f0, 0xd917,
+ 0x79ef, 0xd911, 0x79ed, 0xd90b, 0x79eb, 0xd905, 0x79e9, 0xd8ff,
+ 0x79e7, 0xd8f9, 0x79e5, 0xd8f3, 0x79e3, 0xd8ed, 0x79e1, 0xd8e7,
+ 0x79df, 0xd8e1, 0x79dd, 0xd8db, 0x79db, 0xd8d5, 0x79d9, 0xd8cf,
+ 0x79d8, 0xd8c9, 0x79d6, 0xd8c3, 0x79d4, 0xd8bd, 0x79d2, 0xd8b7,
+ 0x79d0, 0xd8b1, 0x79ce, 0xd8ab, 0x79cc, 0xd8a5, 0x79ca, 0xd89f,
+ 0x79c8, 0xd899, 0x79c6, 0xd893, 0x79c4, 0xd88d, 0x79c2, 0xd887,
+ 0x79c0, 0xd881, 0x79be, 0xd87b, 0x79bc, 0xd875, 0x79bb, 0xd86f,
+ 0x79b9, 0xd869, 0x79b7, 0xd863, 0x79b5, 0xd85d, 0x79b3, 0xd857,
+ 0x79b1, 0xd851, 0x79af, 0xd84b, 0x79ad, 0xd845, 0x79ab, 0xd83f,
+ 0x79a9, 0xd839, 0x79a7, 0xd833, 0x79a5, 0xd82d, 0x79a3, 0xd827,
+ 0x79a1, 0xd821, 0x799f, 0xd81b, 0x799d, 0xd815, 0x799b, 0xd80f,
+ 0x7999, 0xd80a, 0x7997, 0xd804, 0x7995, 0xd7fe, 0x7993, 0xd7f8,
+ 0x7992, 0xd7f2, 0x7990, 0xd7ec, 0x798e, 0xd7e6, 0x798c, 0xd7e0,
+ 0x798a, 0xd7da, 0x7988, 0xd7d4, 0x7986, 0xd7ce, 0x7984, 0xd7c8,
+ 0x7982, 0xd7c2, 0x7980, 0xd7bc, 0x797e, 0xd7b6, 0x797c, 0xd7b0,
+ 0x797a, 0xd7aa, 0x7978, 0xd7a4, 0x7976, 0xd79e, 0x7974, 0xd798,
+ 0x7972, 0xd792, 0x7970, 0xd78c, 0x796e, 0xd786, 0x796c, 0xd780,
+ 0x796a, 0xd77a, 0x7968, 0xd774, 0x7966, 0xd76e, 0x7964, 0xd768,
+ 0x7962, 0xd763, 0x7960, 0xd75d, 0x795e, 0xd757, 0x795c, 0xd751,
+ 0x795a, 0xd74b, 0x7958, 0xd745, 0x7956, 0xd73f, 0x7954, 0xd739,
+ 0x7952, 0xd733, 0x7950, 0xd72d, 0x794e, 0xd727, 0x794c, 0xd721,
+ 0x794a, 0xd71b, 0x7948, 0xd715, 0x7946, 0xd70f, 0x7944, 0xd709,
+ 0x7942, 0xd703, 0x7940, 0xd6fd, 0x793e, 0xd6f7, 0x793c, 0xd6f1,
+ 0x793a, 0xd6eb, 0x7938, 0xd6e5, 0x7936, 0xd6e0, 0x7934, 0xd6da,
+ 0x7932, 0xd6d4, 0x7930, 0xd6ce, 0x792e, 0xd6c8, 0x792c, 0xd6c2,
+ 0x792a, 0xd6bc, 0x7928, 0xd6b6, 0x7926, 0xd6b0, 0x7924, 0xd6aa,
+ 0x7922, 0xd6a4, 0x7920, 0xd69e, 0x791e, 0xd698, 0x791c, 0xd692,
+ 0x7919, 0xd68c, 0x7917, 0xd686, 0x7915, 0xd680, 0x7913, 0xd67a,
+ 0x7911, 0xd675, 0x790f, 0xd66f, 0x790d, 0xd669, 0x790b, 0xd663,
+ 0x7909, 0xd65d, 0x7907, 0xd657, 0x7905, 0xd651, 0x7903, 0xd64b,
+ 0x7901, 0xd645, 0x78ff, 0xd63f, 0x78fd, 0xd639, 0x78fb, 0xd633,
+ 0x78f9, 0xd62d, 0x78f7, 0xd627, 0x78f5, 0xd621, 0x78f3, 0xd61b,
+ 0x78f1, 0xd615, 0x78ee, 0xd610, 0x78ec, 0xd60a, 0x78ea, 0xd604,
+ 0x78e8, 0xd5fe, 0x78e6, 0xd5f8, 0x78e4, 0xd5f2, 0x78e2, 0xd5ec,
+ 0x78e0, 0xd5e6, 0x78de, 0xd5e0, 0x78dc, 0xd5da, 0x78da, 0xd5d4,
+ 0x78d8, 0xd5ce, 0x78d6, 0xd5c8, 0x78d4, 0xd5c2, 0x78d2, 0xd5bc,
+ 0x78cf, 0xd5b7, 0x78cd, 0xd5b1, 0x78cb, 0xd5ab, 0x78c9, 0xd5a5,
+ 0x78c7, 0xd59f, 0x78c5, 0xd599, 0x78c3, 0xd593, 0x78c1, 0xd58d,
+ 0x78bf, 0xd587, 0x78bd, 0xd581, 0x78bb, 0xd57b, 0x78b9, 0xd575,
+ 0x78b6, 0xd56f, 0x78b4, 0xd569, 0x78b2, 0xd564, 0x78b0, 0xd55e,
+ 0x78ae, 0xd558, 0x78ac, 0xd552, 0x78aa, 0xd54c, 0x78a8, 0xd546,
+ 0x78a6, 0xd540, 0x78a4, 0xd53a, 0x78a2, 0xd534, 0x789f, 0xd52e,
+ 0x789d, 0xd528, 0x789b, 0xd522, 0x7899, 0xd51c, 0x7897, 0xd517,
+ 0x7895, 0xd511, 0x7893, 0xd50b, 0x7891, 0xd505, 0x788f, 0xd4ff,
+ 0x788c, 0xd4f9, 0x788a, 0xd4f3, 0x7888, 0xd4ed, 0x7886, 0xd4e7,
+ 0x7884, 0xd4e1, 0x7882, 0xd4db, 0x7880, 0xd4d5, 0x787e, 0xd4d0,
+ 0x787c, 0xd4ca, 0x7879, 0xd4c4, 0x7877, 0xd4be, 0x7875, 0xd4b8,
+ 0x7873, 0xd4b2, 0x7871, 0xd4ac, 0x786f, 0xd4a6, 0x786d, 0xd4a0,
+ 0x786b, 0xd49a, 0x7868, 0xd494, 0x7866, 0xd48f, 0x7864, 0xd489,
+ 0x7862, 0xd483, 0x7860, 0xd47d, 0x785e, 0xd477, 0x785c, 0xd471,
+ 0x7859, 0xd46b, 0x7857, 0xd465, 0x7855, 0xd45f, 0x7853, 0xd459,
+ 0x7851, 0xd453, 0x784f, 0xd44e, 0x784d, 0xd448, 0x784a, 0xd442,
+ 0x7848, 0xd43c, 0x7846, 0xd436, 0x7844, 0xd430, 0x7842, 0xd42a,
+ 0x7840, 0xd424, 0x783e, 0xd41e, 0x783b, 0xd418, 0x7839, 0xd412,
+ 0x7837, 0xd40d, 0x7835, 0xd407, 0x7833, 0xd401, 0x7831, 0xd3fb,
+ 0x782e, 0xd3f5, 0x782c, 0xd3ef, 0x782a, 0xd3e9, 0x7828, 0xd3e3,
+ 0x7826, 0xd3dd, 0x7824, 0xd3d7, 0x7821, 0xd3d2, 0x781f, 0xd3cc,
+ 0x781d, 0xd3c6, 0x781b, 0xd3c0, 0x7819, 0xd3ba, 0x7817, 0xd3b4,
+ 0x7814, 0xd3ae, 0x7812, 0xd3a8, 0x7810, 0xd3a2, 0x780e, 0xd39d,
+ 0x780c, 0xd397, 0x780a, 0xd391, 0x7807, 0xd38b, 0x7805, 0xd385,
+ 0x7803, 0xd37f, 0x7801, 0xd379, 0x77ff, 0xd373, 0x77fc, 0xd36d,
+ 0x77fa, 0xd368, 0x77f8, 0xd362, 0x77f6, 0xd35c, 0x77f4, 0xd356,
+ 0x77f1, 0xd350, 0x77ef, 0xd34a, 0x77ed, 0xd344, 0x77eb, 0xd33e,
+ 0x77e9, 0xd338, 0x77e6, 0xd333, 0x77e4, 0xd32d, 0x77e2, 0xd327,
+ 0x77e0, 0xd321, 0x77de, 0xd31b, 0x77db, 0xd315, 0x77d9, 0xd30f,
+ 0x77d7, 0xd309, 0x77d5, 0xd303, 0x77d3, 0xd2fe, 0x77d0, 0xd2f8,
+ 0x77ce, 0xd2f2, 0x77cc, 0xd2ec, 0x77ca, 0xd2e6, 0x77c8, 0xd2e0,
+ 0x77c5, 0xd2da, 0x77c3, 0xd2d4, 0x77c1, 0xd2cf, 0x77bf, 0xd2c9,
+ 0x77bc, 0xd2c3, 0x77ba, 0xd2bd, 0x77b8, 0xd2b7, 0x77b6, 0xd2b1,
+ 0x77b4, 0xd2ab, 0x77b1, 0xd2a5, 0x77af, 0xd2a0, 0x77ad, 0xd29a,
+ 0x77ab, 0xd294, 0x77a8, 0xd28e, 0x77a6, 0xd288, 0x77a4, 0xd282,
+ 0x77a2, 0xd27c, 0x77a0, 0xd276, 0x779d, 0xd271, 0x779b, 0xd26b,
+ 0x7799, 0xd265, 0x7797, 0xd25f, 0x7794, 0xd259, 0x7792, 0xd253,
+ 0x7790, 0xd24d, 0x778e, 0xd247, 0x778b, 0xd242, 0x7789, 0xd23c,
+ 0x7787, 0xd236, 0x7785, 0xd230, 0x7782, 0xd22a, 0x7780, 0xd224,
+ 0x777e, 0xd21e, 0x777c, 0xd219, 0x7779, 0xd213, 0x7777, 0xd20d,
+ 0x7775, 0xd207, 0x7773, 0xd201, 0x7770, 0xd1fb, 0x776e, 0xd1f5,
+ 0x776c, 0xd1ef, 0x776a, 0xd1ea, 0x7767, 0xd1e4, 0x7765, 0xd1de,
+ 0x7763, 0xd1d8, 0x7760, 0xd1d2, 0x775e, 0xd1cc, 0x775c, 0xd1c6,
+ 0x775a, 0xd1c1, 0x7757, 0xd1bb, 0x7755, 0xd1b5, 0x7753, 0xd1af,
+ 0x7751, 0xd1a9, 0x774e, 0xd1a3, 0x774c, 0xd19d, 0x774a, 0xd198,
+ 0x7747, 0xd192, 0x7745, 0xd18c, 0x7743, 0xd186, 0x7741, 0xd180,
+ 0x773e, 0xd17a, 0x773c, 0xd174, 0x773a, 0xd16f, 0x7738, 0xd169,
+ 0x7735, 0xd163, 0x7733, 0xd15d, 0x7731, 0xd157, 0x772e, 0xd151,
+ 0x772c, 0xd14b, 0x772a, 0xd146, 0x7727, 0xd140, 0x7725, 0xd13a,
+ 0x7723, 0xd134, 0x7721, 0xd12e, 0x771e, 0xd128, 0x771c, 0xd123,
+ 0x771a, 0xd11d, 0x7717, 0xd117, 0x7715, 0xd111, 0x7713, 0xd10b,
+ 0x7710, 0xd105, 0x770e, 0xd0ff, 0x770c, 0xd0fa, 0x770a, 0xd0f4,
+ 0x7707, 0xd0ee, 0x7705, 0xd0e8, 0x7703, 0xd0e2, 0x7700, 0xd0dc,
+ 0x76fe, 0xd0d7, 0x76fc, 0xd0d1, 0x76f9, 0xd0cb, 0x76f7, 0xd0c5,
+ 0x76f5, 0xd0bf, 0x76f2, 0xd0b9, 0x76f0, 0xd0b4, 0x76ee, 0xd0ae,
+ 0x76eb, 0xd0a8, 0x76e9, 0xd0a2, 0x76e7, 0xd09c, 0x76e4, 0xd096,
+ 0x76e2, 0xd091, 0x76e0, 0xd08b, 0x76dd, 0xd085, 0x76db, 0xd07f,
+ 0x76d9, 0xd079, 0x76d6, 0xd073, 0x76d4, 0xd06e, 0x76d2, 0xd068,
+ 0x76cf, 0xd062, 0x76cd, 0xd05c, 0x76cb, 0xd056, 0x76c8, 0xd050,
+ 0x76c6, 0xd04b, 0x76c4, 0xd045, 0x76c1, 0xd03f, 0x76bf, 0xd039,
+ 0x76bd, 0xd033, 0x76ba, 0xd02d, 0x76b8, 0xd028, 0x76b6, 0xd022,
+ 0x76b3, 0xd01c, 0x76b1, 0xd016, 0x76af, 0xd010, 0x76ac, 0xd00a,
+ 0x76aa, 0xd005, 0x76a8, 0xcfff, 0x76a5, 0xcff9, 0x76a3, 0xcff3,
+ 0x76a0, 0xcfed, 0x769e, 0xcfe7, 0x769c, 0xcfe2, 0x7699, 0xcfdc,
+ 0x7697, 0xcfd6, 0x7695, 0xcfd0, 0x7692, 0xcfca, 0x7690, 0xcfc5,
+ 0x768e, 0xcfbf, 0x768b, 0xcfb9, 0x7689, 0xcfb3, 0x7686, 0xcfad,
+ 0x7684, 0xcfa7, 0x7682, 0xcfa2, 0x767f, 0xcf9c, 0x767d, 0xcf96,
+ 0x767b, 0xcf90, 0x7678, 0xcf8a, 0x7676, 0xcf85, 0x7673, 0xcf7f,
+ 0x7671, 0xcf79, 0x766f, 0xcf73, 0x766c, 0xcf6d, 0x766a, 0xcf67,
+ 0x7668, 0xcf62, 0x7665, 0xcf5c, 0x7663, 0xcf56, 0x7660, 0xcf50,
+ 0x765e, 0xcf4a, 0x765c, 0xcf45, 0x7659, 0xcf3f, 0x7657, 0xcf39,
+ 0x7654, 0xcf33, 0x7652, 0xcf2d, 0x7650, 0xcf28, 0x764d, 0xcf22,
+ 0x764b, 0xcf1c, 0x7648, 0xcf16, 0x7646, 0xcf10, 0x7644, 0xcf0b,
+ 0x7641, 0xcf05, 0x763f, 0xceff, 0x763c, 0xcef9, 0x763a, 0xcef3,
+ 0x7638, 0xceee, 0x7635, 0xcee8, 0x7633, 0xcee2, 0x7630, 0xcedc,
+ 0x762e, 0xced6, 0x762b, 0xced1, 0x7629, 0xcecb, 0x7627, 0xcec5,
+ 0x7624, 0xcebf, 0x7622, 0xceb9, 0x761f, 0xceb4, 0x761d, 0xceae,
+ 0x761b, 0xcea8, 0x7618, 0xcea2, 0x7616, 0xce9c, 0x7613, 0xce97,
+ 0x7611, 0xce91, 0x760e, 0xce8b, 0x760c, 0xce85, 0x760a, 0xce7f,
+ 0x7607, 0xce7a, 0x7605, 0xce74, 0x7602, 0xce6e, 0x7600, 0xce68,
+ 0x75fd, 0xce62, 0x75fb, 0xce5d, 0x75f9, 0xce57, 0x75f6, 0xce51,
+ 0x75f4, 0xce4b, 0x75f1, 0xce45, 0x75ef, 0xce40, 0x75ec, 0xce3a,
+ 0x75ea, 0xce34, 0x75e7, 0xce2e, 0x75e5, 0xce28, 0x75e3, 0xce23,
+ 0x75e0, 0xce1d, 0x75de, 0xce17, 0x75db, 0xce11, 0x75d9, 0xce0c,
+ 0x75d6, 0xce06, 0x75d4, 0xce00, 0x75d1, 0xcdfa, 0x75cf, 0xcdf4,
+ 0x75cc, 0xcdef, 0x75ca, 0xcde9, 0x75c8, 0xcde3, 0x75c5, 0xcddd,
+ 0x75c3, 0xcdd8, 0x75c0, 0xcdd2, 0x75be, 0xcdcc, 0x75bb, 0xcdc6,
+ 0x75b9, 0xcdc0, 0x75b6, 0xcdbb, 0x75b4, 0xcdb5, 0x75b1, 0xcdaf,
+ 0x75af, 0xcda9, 0x75ac, 0xcda3, 0x75aa, 0xcd9e, 0x75a7, 0xcd98,
+ 0x75a5, 0xcd92, 0x75a3, 0xcd8c, 0x75a0, 0xcd87, 0x759e, 0xcd81,
+ 0x759b, 0xcd7b, 0x7599, 0xcd75, 0x7596, 0xcd70, 0x7594, 0xcd6a,
+ 0x7591, 0xcd64, 0x758f, 0xcd5e, 0x758c, 0xcd58, 0x758a, 0xcd53,
+ 0x7587, 0xcd4d, 0x7585, 0xcd47, 0x7582, 0xcd41, 0x7580, 0xcd3c,
+ 0x757d, 0xcd36, 0x757b, 0xcd30, 0x7578, 0xcd2a, 0x7576, 0xcd25,
+ 0x7573, 0xcd1f, 0x7571, 0xcd19, 0x756e, 0xcd13, 0x756c, 0xcd0d,
+ 0x7569, 0xcd08, 0x7567, 0xcd02, 0x7564, 0xccfc, 0x7562, 0xccf6,
+ 0x755f, 0xccf1, 0x755d, 0xcceb, 0x755a, 0xcce5, 0x7558, 0xccdf,
+ 0x7555, 0xccda, 0x7553, 0xccd4, 0x7550, 0xccce, 0x754e, 0xccc8,
+ 0x754b, 0xccc3, 0x7549, 0xccbd, 0x7546, 0xccb7, 0x7544, 0xccb1,
+ 0x7541, 0xccac, 0x753f, 0xcca6, 0x753c, 0xcca0, 0x753a, 0xcc9a,
+ 0x7537, 0xcc95, 0x7535, 0xcc8f, 0x7532, 0xcc89, 0x752f, 0xcc83,
+ 0x752d, 0xcc7e, 0x752a, 0xcc78, 0x7528, 0xcc72, 0x7525, 0xcc6c,
+ 0x7523, 0xcc67, 0x7520, 0xcc61, 0x751e, 0xcc5b, 0x751b, 0xcc55,
+ 0x7519, 0xcc50, 0x7516, 0xcc4a, 0x7514, 0xcc44, 0x7511, 0xcc3e,
+ 0x750f, 0xcc39, 0x750c, 0xcc33, 0x7509, 0xcc2d, 0x7507, 0xcc27,
+ 0x7504, 0xcc22, 0x7502, 0xcc1c, 0x74ff, 0xcc16, 0x74fd, 0xcc10,
+ 0x74fa, 0xcc0b, 0x74f8, 0xcc05, 0x74f5, 0xcbff, 0x74f2, 0xcbf9,
+ 0x74f0, 0xcbf4, 0x74ed, 0xcbee, 0x74eb, 0xcbe8, 0x74e8, 0xcbe2,
+ 0x74e6, 0xcbdd, 0x74e3, 0xcbd7, 0x74e1, 0xcbd1, 0x74de, 0xcbcb,
+ 0x74db, 0xcbc6, 0x74d9, 0xcbc0, 0x74d6, 0xcbba, 0x74d4, 0xcbb5,
+ 0x74d1, 0xcbaf, 0x74cf, 0xcba9, 0x74cc, 0xcba3, 0x74c9, 0xcb9e,
+ 0x74c7, 0xcb98, 0x74c4, 0xcb92, 0x74c2, 0xcb8c, 0x74bf, 0xcb87,
+ 0x74bd, 0xcb81, 0x74ba, 0xcb7b, 0x74b7, 0xcb75, 0x74b5, 0xcb70,
+ 0x74b2, 0xcb6a, 0x74b0, 0xcb64, 0x74ad, 0xcb5f, 0x74ab, 0xcb59,
+ 0x74a8, 0xcb53, 0x74a5, 0xcb4d, 0x74a3, 0xcb48, 0x74a0, 0xcb42,
+ 0x749e, 0xcb3c, 0x749b, 0xcb36, 0x7498, 0xcb31, 0x7496, 0xcb2b,
+ 0x7493, 0xcb25, 0x7491, 0xcb20, 0x748e, 0xcb1a, 0x748b, 0xcb14,
+ 0x7489, 0xcb0e, 0x7486, 0xcb09, 0x7484, 0xcb03, 0x7481, 0xcafd,
+ 0x747e, 0xcaf8, 0x747c, 0xcaf2, 0x7479, 0xcaec, 0x7477, 0xcae6,
+ 0x7474, 0xcae1, 0x7471, 0xcadb, 0x746f, 0xcad5, 0x746c, 0xcad0,
+ 0x746a, 0xcaca, 0x7467, 0xcac4, 0x7464, 0xcabe, 0x7462, 0xcab9,
+ 0x745f, 0xcab3, 0x745c, 0xcaad, 0x745a, 0xcaa8, 0x7457, 0xcaa2,
+ 0x7455, 0xca9c, 0x7452, 0xca96, 0x744f, 0xca91, 0x744d, 0xca8b,
+ 0x744a, 0xca85, 0x7448, 0xca80, 0x7445, 0xca7a, 0x7442, 0xca74,
+ 0x7440, 0xca6e, 0x743d, 0xca69, 0x743a, 0xca63, 0x7438, 0xca5d,
+ 0x7435, 0xca58, 0x7432, 0xca52, 0x7430, 0xca4c, 0x742d, 0xca46,
+ 0x742b, 0xca41, 0x7428, 0xca3b, 0x7425, 0xca35, 0x7423, 0xca30,
+ 0x7420, 0xca2a, 0x741d, 0xca24, 0x741b, 0xca1f, 0x7418, 0xca19,
+ 0x7415, 0xca13, 0x7413, 0xca0d, 0x7410, 0xca08, 0x740d, 0xca02,
+ 0x740b, 0xc9fc, 0x7408, 0xc9f7, 0x7406, 0xc9f1, 0x7403, 0xc9eb,
+ 0x7400, 0xc9e6, 0x73fe, 0xc9e0, 0x73fb, 0xc9da, 0x73f8, 0xc9d5,
+ 0x73f6, 0xc9cf, 0x73f3, 0xc9c9, 0x73f0, 0xc9c3, 0x73ee, 0xc9be,
+ 0x73eb, 0xc9b8, 0x73e8, 0xc9b2, 0x73e6, 0xc9ad, 0x73e3, 0xc9a7,
+ 0x73e0, 0xc9a1, 0x73de, 0xc99c, 0x73db, 0xc996, 0x73d8, 0xc990,
+ 0x73d6, 0xc98b, 0x73d3, 0xc985, 0x73d0, 0xc97f, 0x73ce, 0xc97a,
+ 0x73cb, 0xc974, 0x73c8, 0xc96e, 0x73c6, 0xc968, 0x73c3, 0xc963,
+ 0x73c0, 0xc95d, 0x73bd, 0xc957, 0x73bb, 0xc952, 0x73b8, 0xc94c,
+ 0x73b5, 0xc946, 0x73b3, 0xc941, 0x73b0, 0xc93b, 0x73ad, 0xc935,
+ 0x73ab, 0xc930, 0x73a8, 0xc92a, 0x73a5, 0xc924, 0x73a3, 0xc91f,
+ 0x73a0, 0xc919, 0x739d, 0xc913, 0x739b, 0xc90e, 0x7398, 0xc908,
+ 0x7395, 0xc902, 0x7392, 0xc8fd, 0x7390, 0xc8f7, 0x738d, 0xc8f1,
+ 0x738a, 0xc8ec, 0x7388, 0xc8e6, 0x7385, 0xc8e0, 0x7382, 0xc8db,
+ 0x737f, 0xc8d5, 0x737d, 0xc8cf, 0x737a, 0xc8ca, 0x7377, 0xc8c4,
+ 0x7375, 0xc8be, 0x7372, 0xc8b9, 0x736f, 0xc8b3, 0x736c, 0xc8ad,
+ 0x736a, 0xc8a8, 0x7367, 0xc8a2, 0x7364, 0xc89c, 0x7362, 0xc897,
+ 0x735f, 0xc891, 0x735c, 0xc88b, 0x7359, 0xc886, 0x7357, 0xc880,
+ 0x7354, 0xc87a, 0x7351, 0xc875, 0x734f, 0xc86f, 0x734c, 0xc869,
+ 0x7349, 0xc864, 0x7346, 0xc85e, 0x7344, 0xc858, 0x7341, 0xc853,
+ 0x733e, 0xc84d, 0x733b, 0xc847, 0x7339, 0xc842, 0x7336, 0xc83c,
+ 0x7333, 0xc836, 0x7330, 0xc831, 0x732e, 0xc82b, 0x732b, 0xc825,
+ 0x7328, 0xc820, 0x7326, 0xc81a, 0x7323, 0xc814, 0x7320, 0xc80f,
+ 0x731d, 0xc809, 0x731b, 0xc803, 0x7318, 0xc7fe, 0x7315, 0xc7f8,
+ 0x7312, 0xc7f3, 0x7310, 0xc7ed, 0x730d, 0xc7e7, 0x730a, 0xc7e2,
+ 0x7307, 0xc7dc, 0x7305, 0xc7d6, 0x7302, 0xc7d1, 0x72ff, 0xc7cb,
+ 0x72fc, 0xc7c5, 0x72f9, 0xc7c0, 0x72f7, 0xc7ba, 0x72f4, 0xc7b4,
+ 0x72f1, 0xc7af, 0x72ee, 0xc7a9, 0x72ec, 0xc7a3, 0x72e9, 0xc79e,
+ 0x72e6, 0xc798, 0x72e3, 0xc793, 0x72e1, 0xc78d, 0x72de, 0xc787,
+ 0x72db, 0xc782, 0x72d8, 0xc77c, 0x72d5, 0xc776, 0x72d3, 0xc771,
+ 0x72d0, 0xc76b, 0x72cd, 0xc765, 0x72ca, 0xc760, 0x72c8, 0xc75a,
+ 0x72c5, 0xc755, 0x72c2, 0xc74f, 0x72bf, 0xc749, 0x72bc, 0xc744,
+ 0x72ba, 0xc73e, 0x72b7, 0xc738, 0x72b4, 0xc733, 0x72b1, 0xc72d,
+ 0x72af, 0xc728, 0x72ac, 0xc722, 0x72a9, 0xc71c, 0x72a6, 0xc717,
+ 0x72a3, 0xc711, 0x72a1, 0xc70b, 0x729e, 0xc706, 0x729b, 0xc700,
+ 0x7298, 0xc6fa, 0x7295, 0xc6f5, 0x7293, 0xc6ef, 0x7290, 0xc6ea,
+ 0x728d, 0xc6e4, 0x728a, 0xc6de, 0x7287, 0xc6d9, 0x7285, 0xc6d3,
+ 0x7282, 0xc6ce, 0x727f, 0xc6c8, 0x727c, 0xc6c2, 0x7279, 0xc6bd,
+ 0x7276, 0xc6b7, 0x7274, 0xc6b1, 0x7271, 0xc6ac, 0x726e, 0xc6a6,
+ 0x726b, 0xc6a1, 0x7268, 0xc69b, 0x7266, 0xc695, 0x7263, 0xc690,
+ 0x7260, 0xc68a, 0x725d, 0xc684, 0x725a, 0xc67f, 0x7257, 0xc679,
+ 0x7255, 0xc674, 0x7252, 0xc66e, 0x724f, 0xc668, 0x724c, 0xc663,
+ 0x7249, 0xc65d, 0x7247, 0xc658, 0x7244, 0xc652, 0x7241, 0xc64c,
+ 0x723e, 0xc647, 0x723b, 0xc641, 0x7238, 0xc63c, 0x7236, 0xc636,
+ 0x7233, 0xc630, 0x7230, 0xc62b, 0x722d, 0xc625, 0x722a, 0xc620,
+ 0x7227, 0xc61a, 0x7224, 0xc614, 0x7222, 0xc60f, 0x721f, 0xc609,
+ 0x721c, 0xc603, 0x7219, 0xc5fe, 0x7216, 0xc5f8, 0x7213, 0xc5f3,
+ 0x7211, 0xc5ed, 0x720e, 0xc5e7, 0x720b, 0xc5e2, 0x7208, 0xc5dc,
+ 0x7205, 0xc5d7, 0x7202, 0xc5d1, 0x71ff, 0xc5cc, 0x71fd, 0xc5c6,
+ 0x71fa, 0xc5c0, 0x71f7, 0xc5bb, 0x71f4, 0xc5b5, 0x71f1, 0xc5b0,
+ 0x71ee, 0xc5aa, 0x71eb, 0xc5a4, 0x71e9, 0xc59f, 0x71e6, 0xc599,
+ 0x71e3, 0xc594, 0x71e0, 0xc58e, 0x71dd, 0xc588, 0x71da, 0xc583,
+ 0x71d7, 0xc57d, 0x71d4, 0xc578, 0x71d2, 0xc572, 0x71cf, 0xc56c,
+ 0x71cc, 0xc567, 0x71c9, 0xc561, 0x71c6, 0xc55c, 0x71c3, 0xc556,
+ 0x71c0, 0xc551, 0x71bd, 0xc54b, 0x71bb, 0xc545, 0x71b8, 0xc540,
+ 0x71b5, 0xc53a, 0x71b2, 0xc535, 0x71af, 0xc52f, 0x71ac, 0xc529,
+ 0x71a9, 0xc524, 0x71a6, 0xc51e, 0x71a3, 0xc519, 0x71a1, 0xc513,
+ 0x719e, 0xc50e, 0x719b, 0xc508, 0x7198, 0xc502, 0x7195, 0xc4fd,
+ 0x7192, 0xc4f7, 0x718f, 0xc4f2, 0x718c, 0xc4ec, 0x7189, 0xc4e7,
+ 0x7186, 0xc4e1, 0x7184, 0xc4db, 0x7181, 0xc4d6, 0x717e, 0xc4d0,
+ 0x717b, 0xc4cb, 0x7178, 0xc4c5, 0x7175, 0xc4c0, 0x7172, 0xc4ba,
+ 0x716f, 0xc4b4, 0x716c, 0xc4af, 0x7169, 0xc4a9, 0x7167, 0xc4a4,
+ 0x7164, 0xc49e, 0x7161, 0xc499, 0x715e, 0xc493, 0x715b, 0xc48d,
+ 0x7158, 0xc488, 0x7155, 0xc482, 0x7152, 0xc47d, 0x714f, 0xc477,
+ 0x714c, 0xc472, 0x7149, 0xc46c, 0x7146, 0xc467, 0x7143, 0xc461,
+ 0x7141, 0xc45b, 0x713e, 0xc456, 0x713b, 0xc450, 0x7138, 0xc44b,
+ 0x7135, 0xc445, 0x7132, 0xc440, 0x712f, 0xc43a, 0x712c, 0xc434,
+ 0x7129, 0xc42f, 0x7126, 0xc429, 0x7123, 0xc424, 0x7120, 0xc41e,
+ 0x711d, 0xc419, 0x711a, 0xc413, 0x7117, 0xc40e, 0x7114, 0xc408,
+ 0x7112, 0xc403, 0x710f, 0xc3fd, 0x710c, 0xc3f7, 0x7109, 0xc3f2,
+ 0x7106, 0xc3ec, 0x7103, 0xc3e7, 0x7100, 0xc3e1, 0x70fd, 0xc3dc,
+ 0x70fa, 0xc3d6, 0x70f7, 0xc3d1, 0x70f4, 0xc3cb, 0x70f1, 0xc3c5,
+ 0x70ee, 0xc3c0, 0x70eb, 0xc3ba, 0x70e8, 0xc3b5, 0x70e5, 0xc3af,
+ 0x70e2, 0xc3aa, 0x70df, 0xc3a4, 0x70dc, 0xc39f, 0x70d9, 0xc399,
+ 0x70d6, 0xc394, 0x70d3, 0xc38e, 0x70d1, 0xc389, 0x70ce, 0xc383,
+ 0x70cb, 0xc37d, 0x70c8, 0xc378, 0x70c5, 0xc372, 0x70c2, 0xc36d,
+ 0x70bf, 0xc367, 0x70bc, 0xc362, 0x70b9, 0xc35c, 0x70b6, 0xc357,
+ 0x70b3, 0xc351, 0x70b0, 0xc34c, 0x70ad, 0xc346, 0x70aa, 0xc341,
+ 0x70a7, 0xc33b, 0x70a4, 0xc336, 0x70a1, 0xc330, 0x709e, 0xc32a,
+ 0x709b, 0xc325, 0x7098, 0xc31f, 0x7095, 0xc31a, 0x7092, 0xc314,
+ 0x708f, 0xc30f, 0x708c, 0xc309, 0x7089, 0xc304, 0x7086, 0xc2fe,
+ 0x7083, 0xc2f9, 0x7080, 0xc2f3, 0x707d, 0xc2ee, 0x707a, 0xc2e8,
+ 0x7077, 0xc2e3, 0x7074, 0xc2dd, 0x7071, 0xc2d8, 0x706e, 0xc2d2,
+ 0x706b, 0xc2cd, 0x7068, 0xc2c7, 0x7065, 0xc2c2, 0x7062, 0xc2bc,
+ 0x705f, 0xc2b7, 0x705c, 0xc2b1, 0x7059, 0xc2ab, 0x7056, 0xc2a6,
+ 0x7053, 0xc2a0, 0x7050, 0xc29b, 0x704d, 0xc295, 0x704a, 0xc290,
+ 0x7047, 0xc28a, 0x7044, 0xc285, 0x7041, 0xc27f, 0x703e, 0xc27a,
+ 0x703b, 0xc274, 0x7038, 0xc26f, 0x7035, 0xc269, 0x7032, 0xc264,
+ 0x702f, 0xc25e, 0x702c, 0xc259, 0x7029, 0xc253, 0x7026, 0xc24e,
+ 0x7023, 0xc248, 0x7020, 0xc243, 0x701d, 0xc23d, 0x7019, 0xc238,
+ 0x7016, 0xc232, 0x7013, 0xc22d, 0x7010, 0xc227, 0x700d, 0xc222,
+ 0x700a, 0xc21c, 0x7007, 0xc217, 0x7004, 0xc211, 0x7001, 0xc20c,
+ 0x6ffe, 0xc206, 0x6ffb, 0xc201, 0x6ff8, 0xc1fb, 0x6ff5, 0xc1f6,
+ 0x6ff2, 0xc1f0, 0x6fef, 0xc1eb, 0x6fec, 0xc1e5, 0x6fe9, 0xc1e0,
+ 0x6fe6, 0xc1da, 0x6fe3, 0xc1d5, 0x6fe0, 0xc1cf, 0x6fdd, 0xc1ca,
+ 0x6fda, 0xc1c4, 0x6fd6, 0xc1bf, 0x6fd3, 0xc1b9, 0x6fd0, 0xc1b4,
+ 0x6fcd, 0xc1ae, 0x6fca, 0xc1a9, 0x6fc7, 0xc1a3, 0x6fc4, 0xc19e,
+ 0x6fc1, 0xc198, 0x6fbe, 0xc193, 0x6fbb, 0xc18d, 0x6fb8, 0xc188,
+ 0x6fb5, 0xc183, 0x6fb2, 0xc17d, 0x6faf, 0xc178, 0x6fac, 0xc172,
+ 0x6fa9, 0xc16d, 0x6fa5, 0xc167, 0x6fa2, 0xc162, 0x6f9f, 0xc15c,
+ 0x6f9c, 0xc157, 0x6f99, 0xc151, 0x6f96, 0xc14c, 0x6f93, 0xc146,
+ 0x6f90, 0xc141, 0x6f8d, 0xc13b, 0x6f8a, 0xc136, 0x6f87, 0xc130,
+ 0x6f84, 0xc12b, 0x6f81, 0xc125, 0x6f7d, 0xc120, 0x6f7a, 0xc11a,
+ 0x6f77, 0xc115, 0x6f74, 0xc10f, 0x6f71, 0xc10a, 0x6f6e, 0xc105,
+ 0x6f6b, 0xc0ff, 0x6f68, 0xc0fa, 0x6f65, 0xc0f4, 0x6f62, 0xc0ef,
+ 0x6f5f, 0xc0e9, 0x6f5b, 0xc0e4, 0x6f58, 0xc0de, 0x6f55, 0xc0d9,
+ 0x6f52, 0xc0d3, 0x6f4f, 0xc0ce, 0x6f4c, 0xc0c8, 0x6f49, 0xc0c3,
+ 0x6f46, 0xc0bd, 0x6f43, 0xc0b8, 0x6f3f, 0xc0b3, 0x6f3c, 0xc0ad,
+ 0x6f39, 0xc0a8, 0x6f36, 0xc0a2, 0x6f33, 0xc09d, 0x6f30, 0xc097,
+ 0x6f2d, 0xc092, 0x6f2a, 0xc08c, 0x6f27, 0xc087, 0x6f23, 0xc081,
+ 0x6f20, 0xc07c, 0x6f1d, 0xc077, 0x6f1a, 0xc071, 0x6f17, 0xc06c,
+ 0x6f14, 0xc066, 0x6f11, 0xc061, 0x6f0e, 0xc05b, 0x6f0b, 0xc056,
+ 0x6f07, 0xc050, 0x6f04, 0xc04b, 0x6f01, 0xc045, 0x6efe, 0xc040,
+ 0x6efb, 0xc03b, 0x6ef8, 0xc035, 0x6ef5, 0xc030, 0x6ef1, 0xc02a,
+ 0x6eee, 0xc025, 0x6eeb, 0xc01f, 0x6ee8, 0xc01a, 0x6ee5, 0xc014,
+ 0x6ee2, 0xc00f, 0x6edf, 0xc00a, 0x6edc, 0xc004, 0x6ed8, 0xbfff,
+ 0x6ed5, 0xbff9, 0x6ed2, 0xbff4, 0x6ecf, 0xbfee, 0x6ecc, 0xbfe9,
+ 0x6ec9, 0xbfe3, 0x6ec6, 0xbfde, 0x6ec2, 0xbfd9, 0x6ebf, 0xbfd3,
+ 0x6ebc, 0xbfce, 0x6eb9, 0xbfc8, 0x6eb6, 0xbfc3, 0x6eb3, 0xbfbd,
+ 0x6eaf, 0xbfb8, 0x6eac, 0xbfb3, 0x6ea9, 0xbfad, 0x6ea6, 0xbfa8,
+ 0x6ea3, 0xbfa2, 0x6ea0, 0xbf9d, 0x6e9c, 0xbf97, 0x6e99, 0xbf92,
+ 0x6e96, 0xbf8d, 0x6e93, 0xbf87, 0x6e90, 0xbf82, 0x6e8d, 0xbf7c,
+ 0x6e89, 0xbf77, 0x6e86, 0xbf71, 0x6e83, 0xbf6c, 0x6e80, 0xbf67,
+ 0x6e7d, 0xbf61, 0x6e7a, 0xbf5c, 0x6e76, 0xbf56, 0x6e73, 0xbf51,
+ 0x6e70, 0xbf4b, 0x6e6d, 0xbf46, 0x6e6a, 0xbf41, 0x6e67, 0xbf3b,
+ 0x6e63, 0xbf36, 0x6e60, 0xbf30, 0x6e5d, 0xbf2b, 0x6e5a, 0xbf26,
+ 0x6e57, 0xbf20, 0x6e53, 0xbf1b, 0x6e50, 0xbf15, 0x6e4d, 0xbf10,
+ 0x6e4a, 0xbf0a, 0x6e47, 0xbf05, 0x6e44, 0xbf00, 0x6e40, 0xbefa,
+ 0x6e3d, 0xbef5, 0x6e3a, 0xbeef, 0x6e37, 0xbeea, 0x6e34, 0xbee5,
+ 0x6e30, 0xbedf, 0x6e2d, 0xbeda, 0x6e2a, 0xbed4, 0x6e27, 0xbecf,
+ 0x6e24, 0xbeca, 0x6e20, 0xbec4, 0x6e1d, 0xbebf, 0x6e1a, 0xbeb9,
+ 0x6e17, 0xbeb4, 0x6e14, 0xbeae, 0x6e10, 0xbea9, 0x6e0d, 0xbea4,
+ 0x6e0a, 0xbe9e, 0x6e07, 0xbe99, 0x6e04, 0xbe93, 0x6e00, 0xbe8e,
+ 0x6dfd, 0xbe89, 0x6dfa, 0xbe83, 0x6df7, 0xbe7e, 0x6df3, 0xbe78,
+ 0x6df0, 0xbe73, 0x6ded, 0xbe6e, 0x6dea, 0xbe68, 0x6de7, 0xbe63,
+ 0x6de3, 0xbe5e, 0x6de0, 0xbe58, 0x6ddd, 0xbe53, 0x6dda, 0xbe4d,
+ 0x6dd6, 0xbe48, 0x6dd3, 0xbe43, 0x6dd0, 0xbe3d, 0x6dcd, 0xbe38,
+ 0x6dca, 0xbe32, 0x6dc6, 0xbe2d, 0x6dc3, 0xbe28, 0x6dc0, 0xbe22,
+ 0x6dbd, 0xbe1d, 0x6db9, 0xbe17, 0x6db6, 0xbe12, 0x6db3, 0xbe0d,
+ 0x6db0, 0xbe07, 0x6dac, 0xbe02, 0x6da9, 0xbdfd, 0x6da6, 0xbdf7,
+ 0x6da3, 0xbdf2, 0x6d9f, 0xbdec, 0x6d9c, 0xbde7, 0x6d99, 0xbde2,
+ 0x6d96, 0xbddc, 0x6d92, 0xbdd7, 0x6d8f, 0xbdd1, 0x6d8c, 0xbdcc,
+ 0x6d89, 0xbdc7, 0x6d85, 0xbdc1, 0x6d82, 0xbdbc, 0x6d7f, 0xbdb7,
+ 0x6d7c, 0xbdb1, 0x6d78, 0xbdac, 0x6d75, 0xbda6, 0x6d72, 0xbda1,
+ 0x6d6f, 0xbd9c, 0x6d6b, 0xbd96, 0x6d68, 0xbd91, 0x6d65, 0xbd8c,
+ 0x6d62, 0xbd86, 0x6d5e, 0xbd81, 0x6d5b, 0xbd7c, 0x6d58, 0xbd76,
+ 0x6d55, 0xbd71, 0x6d51, 0xbd6b, 0x6d4e, 0xbd66, 0x6d4b, 0xbd61,
+ 0x6d48, 0xbd5b, 0x6d44, 0xbd56, 0x6d41, 0xbd51, 0x6d3e, 0xbd4b,
+ 0x6d3a, 0xbd46, 0x6d37, 0xbd40, 0x6d34, 0xbd3b, 0x6d31, 0xbd36,
+ 0x6d2d, 0xbd30, 0x6d2a, 0xbd2b, 0x6d27, 0xbd26, 0x6d23, 0xbd20,
+ 0x6d20, 0xbd1b, 0x6d1d, 0xbd16, 0x6d1a, 0xbd10, 0x6d16, 0xbd0b,
+ 0x6d13, 0xbd06, 0x6d10, 0xbd00, 0x6d0c, 0xbcfb, 0x6d09, 0xbcf5,
+ 0x6d06, 0xbcf0, 0x6d03, 0xbceb, 0x6cff, 0xbce5, 0x6cfc, 0xbce0,
+ 0x6cf9, 0xbcdb, 0x6cf5, 0xbcd5, 0x6cf2, 0xbcd0, 0x6cef, 0xbccb,
+ 0x6cec, 0xbcc5, 0x6ce8, 0xbcc0, 0x6ce5, 0xbcbb, 0x6ce2, 0xbcb5,
+ 0x6cde, 0xbcb0, 0x6cdb, 0xbcab, 0x6cd8, 0xbca5, 0x6cd4, 0xbca0,
+ 0x6cd1, 0xbc9b, 0x6cce, 0xbc95, 0x6cca, 0xbc90, 0x6cc7, 0xbc8b,
+ 0x6cc4, 0xbc85, 0x6cc1, 0xbc80, 0x6cbd, 0xbc7b, 0x6cba, 0xbc75,
+ 0x6cb7, 0xbc70, 0x6cb3, 0xbc6b, 0x6cb0, 0xbc65, 0x6cad, 0xbc60,
+ 0x6ca9, 0xbc5b, 0x6ca6, 0xbc55, 0x6ca3, 0xbc50, 0x6c9f, 0xbc4b,
+ 0x6c9c, 0xbc45, 0x6c99, 0xbc40, 0x6c95, 0xbc3b, 0x6c92, 0xbc35,
+ 0x6c8f, 0xbc30, 0x6c8b, 0xbc2b, 0x6c88, 0xbc25, 0x6c85, 0xbc20,
+ 0x6c81, 0xbc1b, 0x6c7e, 0xbc15, 0x6c7b, 0xbc10, 0x6c77, 0xbc0b,
+ 0x6c74, 0xbc05, 0x6c71, 0xbc00, 0x6c6d, 0xbbfb, 0x6c6a, 0xbbf5,
+ 0x6c67, 0xbbf0, 0x6c63, 0xbbeb, 0x6c60, 0xbbe5, 0x6c5d, 0xbbe0,
+ 0x6c59, 0xbbdb, 0x6c56, 0xbbd5, 0x6c53, 0xbbd0, 0x6c4f, 0xbbcb,
+ 0x6c4c, 0xbbc5, 0x6c49, 0xbbc0, 0x6c45, 0xbbbb, 0x6c42, 0xbbb5,
+ 0x6c3f, 0xbbb0, 0x6c3b, 0xbbab, 0x6c38, 0xbba6, 0x6c34, 0xbba0,
+ 0x6c31, 0xbb9b, 0x6c2e, 0xbb96, 0x6c2a, 0xbb90, 0x6c27, 0xbb8b,
+ 0x6c24, 0xbb86, 0x6c20, 0xbb80, 0x6c1d, 0xbb7b, 0x6c1a, 0xbb76,
+ 0x6c16, 0xbb70, 0x6c13, 0xbb6b, 0x6c0f, 0xbb66, 0x6c0c, 0xbb61,
+ 0x6c09, 0xbb5b, 0x6c05, 0xbb56, 0x6c02, 0xbb51, 0x6bff, 0xbb4b,
+ 0x6bfb, 0xbb46, 0x6bf8, 0xbb41, 0x6bf5, 0xbb3b, 0x6bf1, 0xbb36,
+ 0x6bee, 0xbb31, 0x6bea, 0xbb2c, 0x6be7, 0xbb26, 0x6be4, 0xbb21,
+ 0x6be0, 0xbb1c, 0x6bdd, 0xbb16, 0x6bd9, 0xbb11, 0x6bd6, 0xbb0c,
+ 0x6bd3, 0xbb06, 0x6bcf, 0xbb01, 0x6bcc, 0xbafc, 0x6bc9, 0xbaf7,
+ 0x6bc5, 0xbaf1, 0x6bc2, 0xbaec, 0x6bbe, 0xbae7, 0x6bbb, 0xbae1,
+ 0x6bb8, 0xbadc, 0x6bb4, 0xbad7, 0x6bb1, 0xbad2, 0x6bad, 0xbacc,
+ 0x6baa, 0xbac7, 0x6ba7, 0xbac2, 0x6ba3, 0xbabc, 0x6ba0, 0xbab7,
+ 0x6b9c, 0xbab2, 0x6b99, 0xbaad, 0x6b96, 0xbaa7, 0x6b92, 0xbaa2,
+ 0x6b8f, 0xba9d, 0x6b8b, 0xba97, 0x6b88, 0xba92, 0x6b85, 0xba8d,
+ 0x6b81, 0xba88, 0x6b7e, 0xba82, 0x6b7a, 0xba7d, 0x6b77, 0xba78,
+ 0x6b73, 0xba73, 0x6b70, 0xba6d, 0x6b6d, 0xba68, 0x6b69, 0xba63,
+ 0x6b66, 0xba5d, 0x6b62, 0xba58, 0x6b5f, 0xba53, 0x6b5c, 0xba4e,
+ 0x6b58, 0xba48, 0x6b55, 0xba43, 0x6b51, 0xba3e, 0x6b4e, 0xba39,
+ 0x6b4a, 0xba33, 0x6b47, 0xba2e, 0x6b44, 0xba29, 0x6b40, 0xba23,
+ 0x6b3d, 0xba1e, 0x6b39, 0xba19, 0x6b36, 0xba14, 0x6b32, 0xba0e,
+ 0x6b2f, 0xba09, 0x6b2c, 0xba04, 0x6b28, 0xb9ff, 0x6b25, 0xb9f9,
+ 0x6b21, 0xb9f4, 0x6b1e, 0xb9ef, 0x6b1a, 0xb9ea, 0x6b17, 0xb9e4,
+ 0x6b13, 0xb9df, 0x6b10, 0xb9da, 0x6b0d, 0xb9d5, 0x6b09, 0xb9cf,
+ 0x6b06, 0xb9ca, 0x6b02, 0xb9c5, 0x6aff, 0xb9c0, 0x6afb, 0xb9ba,
+ 0x6af8, 0xb9b5, 0x6af4, 0xb9b0, 0x6af1, 0xb9ab, 0x6aee, 0xb9a5,
+ 0x6aea, 0xb9a0, 0x6ae7, 0xb99b, 0x6ae3, 0xb996, 0x6ae0, 0xb990,
+ 0x6adc, 0xb98b, 0x6ad9, 0xb986, 0x6ad5, 0xb981, 0x6ad2, 0xb97b,
+ 0x6ace, 0xb976, 0x6acb, 0xb971, 0x6ac8, 0xb96c, 0x6ac4, 0xb966,
+ 0x6ac1, 0xb961, 0x6abd, 0xb95c, 0x6aba, 0xb957, 0x6ab6, 0xb951,
+ 0x6ab3, 0xb94c, 0x6aaf, 0xb947, 0x6aac, 0xb942, 0x6aa8, 0xb93c,
+ 0x6aa5, 0xb937, 0x6aa1, 0xb932, 0x6a9e, 0xb92d, 0x6a9a, 0xb928,
+ 0x6a97, 0xb922, 0x6a93, 0xb91d, 0x6a90, 0xb918, 0x6a8c, 0xb913,
+ 0x6a89, 0xb90d, 0x6a86, 0xb908, 0x6a82, 0xb903, 0x6a7f, 0xb8fe,
+ 0x6a7b, 0xb8f8, 0x6a78, 0xb8f3, 0x6a74, 0xb8ee, 0x6a71, 0xb8e9,
+ 0x6a6d, 0xb8e4, 0x6a6a, 0xb8de, 0x6a66, 0xb8d9, 0x6a63, 0xb8d4,
+ 0x6a5f, 0xb8cf, 0x6a5c, 0xb8c9, 0x6a58, 0xb8c4, 0x6a55, 0xb8bf,
+ 0x6a51, 0xb8ba, 0x6a4e, 0xb8b5, 0x6a4a, 0xb8af, 0x6a47, 0xb8aa,
+ 0x6a43, 0xb8a5, 0x6a40, 0xb8a0, 0x6a3c, 0xb89b, 0x6a39, 0xb895,
+ 0x6a35, 0xb890, 0x6a32, 0xb88b, 0x6a2e, 0xb886, 0x6a2b, 0xb880,
+ 0x6a27, 0xb87b, 0x6a24, 0xb876, 0x6a20, 0xb871, 0x6a1d, 0xb86c,
+ 0x6a19, 0xb866, 0x6a16, 0xb861, 0x6a12, 0xb85c, 0x6a0e, 0xb857,
+ 0x6a0b, 0xb852, 0x6a07, 0xb84c, 0x6a04, 0xb847, 0x6a00, 0xb842,
+ 0x69fd, 0xb83d, 0x69f9, 0xb838, 0x69f6, 0xb832, 0x69f2, 0xb82d,
+ 0x69ef, 0xb828, 0x69eb, 0xb823, 0x69e8, 0xb81e, 0x69e4, 0xb818,
+ 0x69e1, 0xb813, 0x69dd, 0xb80e, 0x69da, 0xb809, 0x69d6, 0xb804,
+ 0x69d3, 0xb7fe, 0x69cf, 0xb7f9, 0x69cb, 0xb7f4, 0x69c8, 0xb7ef,
+ 0x69c4, 0xb7ea, 0x69c1, 0xb7e4, 0x69bd, 0xb7df, 0x69ba, 0xb7da,
+ 0x69b6, 0xb7d5, 0x69b3, 0xb7d0, 0x69af, 0xb7ca, 0x69ac, 0xb7c5,
+ 0x69a8, 0xb7c0, 0x69a5, 0xb7bb, 0x69a1, 0xb7b6, 0x699d, 0xb7b1,
+ 0x699a, 0xb7ab, 0x6996, 0xb7a6, 0x6993, 0xb7a1, 0x698f, 0xb79c,
+ 0x698c, 0xb797, 0x6988, 0xb791, 0x6985, 0xb78c, 0x6981, 0xb787,
+ 0x697d, 0xb782, 0x697a, 0xb77d, 0x6976, 0xb778, 0x6973, 0xb772,
+ 0x696f, 0xb76d, 0x696c, 0xb768, 0x6968, 0xb763, 0x6964, 0xb75e,
+ 0x6961, 0xb758, 0x695d, 0xb753, 0x695a, 0xb74e, 0x6956, 0xb749,
+ 0x6953, 0xb744, 0x694f, 0xb73f, 0x694b, 0xb739, 0x6948, 0xb734,
+ 0x6944, 0xb72f, 0x6941, 0xb72a, 0x693d, 0xb725, 0x693a, 0xb720,
+ 0x6936, 0xb71a, 0x6932, 0xb715, 0x692f, 0xb710, 0x692b, 0xb70b,
+ 0x6928, 0xb706, 0x6924, 0xb701, 0x6921, 0xb6fb, 0x691d, 0xb6f6,
+ 0x6919, 0xb6f1, 0x6916, 0xb6ec, 0x6912, 0xb6e7, 0x690f, 0xb6e2,
+ 0x690b, 0xb6dd, 0x6907, 0xb6d7, 0x6904, 0xb6d2, 0x6900, 0xb6cd,
+ 0x68fd, 0xb6c8, 0x68f9, 0xb6c3, 0x68f5, 0xb6be, 0x68f2, 0xb6b8,
+ 0x68ee, 0xb6b3, 0x68eb, 0xb6ae, 0x68e7, 0xb6a9, 0x68e3, 0xb6a4,
+ 0x68e0, 0xb69f, 0x68dc, 0xb69a, 0x68d9, 0xb694, 0x68d5, 0xb68f,
+ 0x68d1, 0xb68a, 0x68ce, 0xb685, 0x68ca, 0xb680, 0x68c7, 0xb67b,
+ 0x68c3, 0xb676, 0x68bf, 0xb670, 0x68bc, 0xb66b, 0x68b8, 0xb666,
+ 0x68b5, 0xb661, 0x68b1, 0xb65c, 0x68ad, 0xb657, 0x68aa, 0xb652,
+ 0x68a6, 0xb64c, 0x68a3, 0xb647, 0x689f, 0xb642, 0x689b, 0xb63d,
+ 0x6898, 0xb638, 0x6894, 0xb633, 0x6890, 0xb62e, 0x688d, 0xb628,
+ 0x6889, 0xb623, 0x6886, 0xb61e, 0x6882, 0xb619, 0x687e, 0xb614,
+ 0x687b, 0xb60f, 0x6877, 0xb60a, 0x6873, 0xb605, 0x6870, 0xb5ff,
+ 0x686c, 0xb5fa, 0x6868, 0xb5f5, 0x6865, 0xb5f0, 0x6861, 0xb5eb,
+ 0x685e, 0xb5e6, 0x685a, 0xb5e1, 0x6856, 0xb5dc, 0x6853, 0xb5d6,
+ 0x684f, 0xb5d1, 0x684b, 0xb5cc, 0x6848, 0xb5c7, 0x6844, 0xb5c2,
+ 0x6840, 0xb5bd, 0x683d, 0xb5b8, 0x6839, 0xb5b3, 0x6835, 0xb5ae,
+ 0x6832, 0xb5a8, 0x682e, 0xb5a3, 0x682b, 0xb59e, 0x6827, 0xb599,
+ 0x6823, 0xb594, 0x6820, 0xb58f, 0x681c, 0xb58a, 0x6818, 0xb585,
+ 0x6815, 0xb57f, 0x6811, 0xb57a, 0x680d, 0xb575, 0x680a, 0xb570,
+ 0x6806, 0xb56b, 0x6802, 0xb566, 0x67ff, 0xb561, 0x67fb, 0xb55c,
+ 0x67f7, 0xb557, 0x67f4, 0xb552, 0x67f0, 0xb54c, 0x67ec, 0xb547,
+ 0x67e9, 0xb542, 0x67e5, 0xb53d, 0x67e1, 0xb538, 0x67de, 0xb533,
+ 0x67da, 0xb52e, 0x67d6, 0xb529, 0x67d3, 0xb524, 0x67cf, 0xb51f,
+ 0x67cb, 0xb519, 0x67c8, 0xb514, 0x67c4, 0xb50f, 0x67c0, 0xb50a,
+ 0x67bd, 0xb505, 0x67b9, 0xb500, 0x67b5, 0xb4fb, 0x67b2, 0xb4f6,
+ 0x67ae, 0xb4f1, 0x67aa, 0xb4ec, 0x67a6, 0xb4e7, 0x67a3, 0xb4e1,
+ 0x679f, 0xb4dc, 0x679b, 0xb4d7, 0x6798, 0xb4d2, 0x6794, 0xb4cd,
+ 0x6790, 0xb4c8, 0x678d, 0xb4c3, 0x6789, 0xb4be, 0x6785, 0xb4b9,
+ 0x6782, 0xb4b4, 0x677e, 0xb4af, 0x677a, 0xb4aa, 0x6776, 0xb4a4,
+ 0x6773, 0xb49f, 0x676f, 0xb49a, 0x676b, 0xb495, 0x6768, 0xb490,
+ 0x6764, 0xb48b, 0x6760, 0xb486, 0x675d, 0xb481, 0x6759, 0xb47c,
+ 0x6755, 0xb477, 0x6751, 0xb472, 0x674e, 0xb46d, 0x674a, 0xb468,
+ 0x6746, 0xb462, 0x6743, 0xb45d, 0x673f, 0xb458, 0x673b, 0xb453,
+ 0x6737, 0xb44e, 0x6734, 0xb449, 0x6730, 0xb444, 0x672c, 0xb43f,
+ 0x6729, 0xb43a, 0x6725, 0xb435, 0x6721, 0xb430, 0x671d, 0xb42b,
+ 0x671a, 0xb426, 0x6716, 0xb421, 0x6712, 0xb41c, 0x670e, 0xb417,
+ 0x670b, 0xb411, 0x6707, 0xb40c, 0x6703, 0xb407, 0x6700, 0xb402,
+ 0x66fc, 0xb3fd, 0x66f8, 0xb3f8, 0x66f4, 0xb3f3, 0x66f1, 0xb3ee,
+ 0x66ed, 0xb3e9, 0x66e9, 0xb3e4, 0x66e5, 0xb3df, 0x66e2, 0xb3da,
+ 0x66de, 0xb3d5, 0x66da, 0xb3d0, 0x66d6, 0xb3cb, 0x66d3, 0xb3c6,
+ 0x66cf, 0xb3c1, 0x66cb, 0xb3bc, 0x66c8, 0xb3b7, 0x66c4, 0xb3b1,
+ 0x66c0, 0xb3ac, 0x66bc, 0xb3a7, 0x66b9, 0xb3a2, 0x66b5, 0xb39d,
+ 0x66b1, 0xb398, 0x66ad, 0xb393, 0x66aa, 0xb38e, 0x66a6, 0xb389,
+ 0x66a2, 0xb384, 0x669e, 0xb37f, 0x669b, 0xb37a, 0x6697, 0xb375,
+ 0x6693, 0xb370, 0x668f, 0xb36b, 0x668b, 0xb366, 0x6688, 0xb361,
+ 0x6684, 0xb35c, 0x6680, 0xb357, 0x667c, 0xb352, 0x6679, 0xb34d,
+ 0x6675, 0xb348, 0x6671, 0xb343, 0x666d, 0xb33e, 0x666a, 0xb339,
+ 0x6666, 0xb334, 0x6662, 0xb32f, 0x665e, 0xb32a, 0x665b, 0xb325,
+ 0x6657, 0xb31f, 0x6653, 0xb31a, 0x664f, 0xb315, 0x664b, 0xb310,
+ 0x6648, 0xb30b, 0x6644, 0xb306, 0x6640, 0xb301, 0x663c, 0xb2fc,
+ 0x6639, 0xb2f7, 0x6635, 0xb2f2, 0x6631, 0xb2ed, 0x662d, 0xb2e8,
+ 0x6629, 0xb2e3, 0x6626, 0xb2de, 0x6622, 0xb2d9, 0x661e, 0xb2d4,
+ 0x661a, 0xb2cf, 0x6616, 0xb2ca, 0x6613, 0xb2c5, 0x660f, 0xb2c0,
+ 0x660b, 0xb2bb, 0x6607, 0xb2b6, 0x6603, 0xb2b1, 0x6600, 0xb2ac,
+ 0x65fc, 0xb2a7, 0x65f8, 0xb2a2, 0x65f4, 0xb29d, 0x65f0, 0xb298,
+ 0x65ed, 0xb293, 0x65e9, 0xb28e, 0x65e5, 0xb289, 0x65e1, 0xb284,
+ 0x65dd, 0xb27f, 0x65da, 0xb27a, 0x65d6, 0xb275, 0x65d2, 0xb270,
+ 0x65ce, 0xb26b, 0x65ca, 0xb266, 0x65c7, 0xb261, 0x65c3, 0xb25c,
+ 0x65bf, 0xb257, 0x65bb, 0xb252, 0x65b7, 0xb24d, 0x65b4, 0xb248,
+ 0x65b0, 0xb243, 0x65ac, 0xb23e, 0x65a8, 0xb239, 0x65a4, 0xb234,
+ 0x65a0, 0xb22f, 0x659d, 0xb22a, 0x6599, 0xb225, 0x6595, 0xb220,
+ 0x6591, 0xb21b, 0x658d, 0xb216, 0x658a, 0xb211, 0x6586, 0xb20c,
+ 0x6582, 0xb207, 0x657e, 0xb202, 0x657a, 0xb1fd, 0x6576, 0xb1f8,
+ 0x6573, 0xb1f3, 0x656f, 0xb1ee, 0x656b, 0xb1e9, 0x6567, 0xb1e4,
+ 0x6563, 0xb1df, 0x655f, 0xb1da, 0x655c, 0xb1d6, 0x6558, 0xb1d1,
+ 0x6554, 0xb1cc, 0x6550, 0xb1c7, 0x654c, 0xb1c2, 0x6548, 0xb1bd,
+ 0x6545, 0xb1b8, 0x6541, 0xb1b3, 0x653d, 0xb1ae, 0x6539, 0xb1a9,
+ 0x6535, 0xb1a4, 0x6531, 0xb19f, 0x652d, 0xb19a, 0x652a, 0xb195,
+ 0x6526, 0xb190, 0x6522, 0xb18b, 0x651e, 0xb186, 0x651a, 0xb181,
+ 0x6516, 0xb17c, 0x6513, 0xb177, 0x650f, 0xb172, 0x650b, 0xb16d,
+ 0x6507, 0xb168, 0x6503, 0xb163, 0x64ff, 0xb15e, 0x64fb, 0xb159,
+ 0x64f7, 0xb154, 0x64f4, 0xb14f, 0x64f0, 0xb14a, 0x64ec, 0xb146,
+ 0x64e8, 0xb141, 0x64e4, 0xb13c, 0x64e0, 0xb137, 0x64dc, 0xb132,
+ 0x64d9, 0xb12d, 0x64d5, 0xb128, 0x64d1, 0xb123, 0x64cd, 0xb11e,
+ 0x64c9, 0xb119, 0x64c5, 0xb114, 0x64c1, 0xb10f, 0x64bd, 0xb10a,
+ 0x64ba, 0xb105, 0x64b6, 0xb100, 0x64b2, 0xb0fb, 0x64ae, 0xb0f6,
+ 0x64aa, 0xb0f1, 0x64a6, 0xb0ec, 0x64a2, 0xb0e8, 0x649e, 0xb0e3,
+ 0x649b, 0xb0de, 0x6497, 0xb0d9, 0x6493, 0xb0d4, 0x648f, 0xb0cf,
+ 0x648b, 0xb0ca, 0x6487, 0xb0c5, 0x6483, 0xb0c0, 0x647f, 0xb0bb,
+ 0x647b, 0xb0b6, 0x6478, 0xb0b1, 0x6474, 0xb0ac, 0x6470, 0xb0a7,
+ 0x646c, 0xb0a2, 0x6468, 0xb09e, 0x6464, 0xb099, 0x6460, 0xb094,
+ 0x645c, 0xb08f, 0x6458, 0xb08a, 0x6454, 0xb085, 0x6451, 0xb080,
+ 0x644d, 0xb07b, 0x6449, 0xb076, 0x6445, 0xb071, 0x6441, 0xb06c,
+ 0x643d, 0xb067, 0x6439, 0xb062, 0x6435, 0xb05e, 0x6431, 0xb059,
+ 0x642d, 0xb054, 0x6429, 0xb04f, 0x6426, 0xb04a, 0x6422, 0xb045,
+ 0x641e, 0xb040, 0x641a, 0xb03b, 0x6416, 0xb036, 0x6412, 0xb031,
+ 0x640e, 0xb02c, 0x640a, 0xb027, 0x6406, 0xb023, 0x6402, 0xb01e,
+ 0x63fe, 0xb019, 0x63fa, 0xb014, 0x63f7, 0xb00f, 0x63f3, 0xb00a,
+ 0x63ef, 0xb005, 0x63eb, 0xb000, 0x63e7, 0xaffb, 0x63e3, 0xaff6,
+ 0x63df, 0xaff1, 0x63db, 0xafed, 0x63d7, 0xafe8, 0x63d3, 0xafe3,
+ 0x63cf, 0xafde, 0x63cb, 0xafd9, 0x63c7, 0xafd4, 0x63c3, 0xafcf,
+ 0x63c0, 0xafca, 0x63bc, 0xafc5, 0x63b8, 0xafc1, 0x63b4, 0xafbc,
+ 0x63b0, 0xafb7, 0x63ac, 0xafb2, 0x63a8, 0xafad, 0x63a4, 0xafa8,
+ 0x63a0, 0xafa3, 0x639c, 0xaf9e, 0x6398, 0xaf99, 0x6394, 0xaf94,
+ 0x6390, 0xaf90, 0x638c, 0xaf8b, 0x6388, 0xaf86, 0x6384, 0xaf81,
+ 0x6380, 0xaf7c, 0x637c, 0xaf77, 0x6378, 0xaf72, 0x6375, 0xaf6d,
+ 0x6371, 0xaf69, 0x636d, 0xaf64, 0x6369, 0xaf5f, 0x6365, 0xaf5a,
+ 0x6361, 0xaf55, 0x635d, 0xaf50, 0x6359, 0xaf4b, 0x6355, 0xaf46,
+ 0x6351, 0xaf41, 0x634d, 0xaf3d, 0x6349, 0xaf38, 0x6345, 0xaf33,
+ 0x6341, 0xaf2e, 0x633d, 0xaf29, 0x6339, 0xaf24, 0x6335, 0xaf1f,
+ 0x6331, 0xaf1b, 0x632d, 0xaf16, 0x6329, 0xaf11, 0x6325, 0xaf0c,
+ 0x6321, 0xaf07, 0x631d, 0xaf02, 0x6319, 0xaefd, 0x6315, 0xaef8,
+ 0x6311, 0xaef4, 0x630d, 0xaeef, 0x6309, 0xaeea, 0x6305, 0xaee5,
+ 0x6301, 0xaee0, 0x62fd, 0xaedb, 0x62f9, 0xaed6, 0x62f5, 0xaed2,
+ 0x62f2, 0xaecd, 0x62ee, 0xaec8, 0x62ea, 0xaec3, 0x62e6, 0xaebe,
+ 0x62e2, 0xaeb9, 0x62de, 0xaeb4, 0x62da, 0xaeb0, 0x62d6, 0xaeab,
+ 0x62d2, 0xaea6, 0x62ce, 0xaea1, 0x62ca, 0xae9c, 0x62c6, 0xae97,
+ 0x62c2, 0xae92, 0x62be, 0xae8e, 0x62ba, 0xae89, 0x62b6, 0xae84,
+ 0x62b2, 0xae7f, 0x62ae, 0xae7a, 0x62aa, 0xae75, 0x62a6, 0xae71,
+ 0x62a2, 0xae6c, 0x629e, 0xae67, 0x629a, 0xae62, 0x6296, 0xae5d,
+ 0x6292, 0xae58, 0x628e, 0xae54, 0x628a, 0xae4f, 0x6286, 0xae4a,
+ 0x6282, 0xae45, 0x627e, 0xae40, 0x627a, 0xae3b, 0x6275, 0xae37,
+ 0x6271, 0xae32, 0x626d, 0xae2d, 0x6269, 0xae28, 0x6265, 0xae23,
+ 0x6261, 0xae1e, 0x625d, 0xae1a, 0x6259, 0xae15, 0x6255, 0xae10,
+ 0x6251, 0xae0b, 0x624d, 0xae06, 0x6249, 0xae01, 0x6245, 0xadfd,
+ 0x6241, 0xadf8, 0x623d, 0xadf3, 0x6239, 0xadee, 0x6235, 0xade9,
+ 0x6231, 0xade4, 0x622d, 0xade0, 0x6229, 0xaddb, 0x6225, 0xadd6,
+ 0x6221, 0xadd1, 0x621d, 0xadcc, 0x6219, 0xadc8, 0x6215, 0xadc3,
+ 0x6211, 0xadbe, 0x620d, 0xadb9, 0x6209, 0xadb4, 0x6205, 0xadaf,
+ 0x6201, 0xadab, 0x61fd, 0xada6, 0x61f9, 0xada1, 0x61f5, 0xad9c,
+ 0x61f1, 0xad97, 0x61ec, 0xad93, 0x61e8, 0xad8e, 0x61e4, 0xad89,
+ 0x61e0, 0xad84, 0x61dc, 0xad7f, 0x61d8, 0xad7b, 0x61d4, 0xad76,
+ 0x61d0, 0xad71, 0x61cc, 0xad6c, 0x61c8, 0xad67, 0x61c4, 0xad63,
+ 0x61c0, 0xad5e, 0x61bc, 0xad59, 0x61b8, 0xad54, 0x61b4, 0xad4f,
+ 0x61b0, 0xad4b, 0x61ac, 0xad46, 0x61a8, 0xad41, 0x61a3, 0xad3c,
+ 0x619f, 0xad37, 0x619b, 0xad33, 0x6197, 0xad2e, 0x6193, 0xad29,
+ 0x618f, 0xad24, 0x618b, 0xad1f, 0x6187, 0xad1b, 0x6183, 0xad16,
+ 0x617f, 0xad11, 0x617b, 0xad0c, 0x6177, 0xad08, 0x6173, 0xad03,
+ 0x616f, 0xacfe, 0x616b, 0xacf9, 0x6166, 0xacf4, 0x6162, 0xacf0,
+ 0x615e, 0xaceb, 0x615a, 0xace6, 0x6156, 0xace1, 0x6152, 0xacdd,
+ 0x614e, 0xacd8, 0x614a, 0xacd3, 0x6146, 0xacce, 0x6142, 0xacc9,
+ 0x613e, 0xacc5, 0x613a, 0xacc0, 0x6135, 0xacbb, 0x6131, 0xacb6,
+ 0x612d, 0xacb2, 0x6129, 0xacad, 0x6125, 0xaca8, 0x6121, 0xaca3,
+ 0x611d, 0xac9e, 0x6119, 0xac9a, 0x6115, 0xac95, 0x6111, 0xac90,
+ 0x610d, 0xac8b, 0x6108, 0xac87, 0x6104, 0xac82, 0x6100, 0xac7d,
+ 0x60fc, 0xac78, 0x60f8, 0xac74, 0x60f4, 0xac6f, 0x60f0, 0xac6a,
+ 0x60ec, 0xac65, 0x60e8, 0xac61, 0x60e4, 0xac5c, 0x60df, 0xac57,
+ 0x60db, 0xac52, 0x60d7, 0xac4e, 0x60d3, 0xac49, 0x60cf, 0xac44,
+ 0x60cb, 0xac3f, 0x60c7, 0xac3b, 0x60c3, 0xac36, 0x60bf, 0xac31,
+ 0x60ba, 0xac2c, 0x60b6, 0xac28, 0x60b2, 0xac23, 0x60ae, 0xac1e,
+ 0x60aa, 0xac19, 0x60a6, 0xac15, 0x60a2, 0xac10, 0x609e, 0xac0b,
+ 0x6099, 0xac06, 0x6095, 0xac02, 0x6091, 0xabfd, 0x608d, 0xabf8,
+ 0x6089, 0xabf3, 0x6085, 0xabef, 0x6081, 0xabea, 0x607d, 0xabe5,
+ 0x6078, 0xabe0, 0x6074, 0xabdc, 0x6070, 0xabd7, 0x606c, 0xabd2,
+ 0x6068, 0xabcd, 0x6064, 0xabc9, 0x6060, 0xabc4, 0x605c, 0xabbf,
+ 0x6057, 0xabbb, 0x6053, 0xabb6, 0x604f, 0xabb1, 0x604b, 0xabac,
+ 0x6047, 0xaba8, 0x6043, 0xaba3, 0x603f, 0xab9e, 0x603a, 0xab99,
+ 0x6036, 0xab95, 0x6032, 0xab90, 0x602e, 0xab8b, 0x602a, 0xab87,
+ 0x6026, 0xab82, 0x6022, 0xab7d, 0x601d, 0xab78, 0x6019, 0xab74,
+ 0x6015, 0xab6f, 0x6011, 0xab6a, 0x600d, 0xab66, 0x6009, 0xab61,
+ 0x6004, 0xab5c, 0x6000, 0xab57, 0x5ffc, 0xab53, 0x5ff8, 0xab4e,
+ 0x5ff4, 0xab49, 0x5ff0, 0xab45, 0x5fec, 0xab40, 0x5fe7, 0xab3b,
+ 0x5fe3, 0xab36, 0x5fdf, 0xab32, 0x5fdb, 0xab2d, 0x5fd7, 0xab28,
+ 0x5fd3, 0xab24, 0x5fce, 0xab1f, 0x5fca, 0xab1a, 0x5fc6, 0xab16,
+ 0x5fc2, 0xab11, 0x5fbe, 0xab0c, 0x5fba, 0xab07, 0x5fb5, 0xab03,
+ 0x5fb1, 0xaafe, 0x5fad, 0xaaf9, 0x5fa9, 0xaaf5, 0x5fa5, 0xaaf0,
+ 0x5fa0, 0xaaeb, 0x5f9c, 0xaae7, 0x5f98, 0xaae2, 0x5f94, 0xaadd,
+ 0x5f90, 0xaad8, 0x5f8c, 0xaad4, 0x5f87, 0xaacf, 0x5f83, 0xaaca,
+ 0x5f7f, 0xaac6, 0x5f7b, 0xaac1, 0x5f77, 0xaabc, 0x5f72, 0xaab8,
+ 0x5f6e, 0xaab3, 0x5f6a, 0xaaae, 0x5f66, 0xaaaa, 0x5f62, 0xaaa5,
+ 0x5f5e, 0xaaa0, 0x5f59, 0xaa9c, 0x5f55, 0xaa97, 0x5f51, 0xaa92,
+ 0x5f4d, 0xaa8e, 0x5f49, 0xaa89, 0x5f44, 0xaa84, 0x5f40, 0xaa7f,
+ 0x5f3c, 0xaa7b, 0x5f38, 0xaa76, 0x5f34, 0xaa71, 0x5f2f, 0xaa6d,
+ 0x5f2b, 0xaa68, 0x5f27, 0xaa63, 0x5f23, 0xaa5f, 0x5f1f, 0xaa5a,
+ 0x5f1a, 0xaa55, 0x5f16, 0xaa51, 0x5f12, 0xaa4c, 0x5f0e, 0xaa47,
+ 0x5f0a, 0xaa43, 0x5f05, 0xaa3e, 0x5f01, 0xaa39, 0x5efd, 0xaa35,
+ 0x5ef9, 0xaa30, 0x5ef5, 0xaa2b, 0x5ef0, 0xaa27, 0x5eec, 0xaa22,
+ 0x5ee8, 0xaa1d, 0x5ee4, 0xaa19, 0x5edf, 0xaa14, 0x5edb, 0xaa10,
+ 0x5ed7, 0xaa0b, 0x5ed3, 0xaa06, 0x5ecf, 0xaa02, 0x5eca, 0xa9fd,
+ 0x5ec6, 0xa9f8, 0x5ec2, 0xa9f4, 0x5ebe, 0xa9ef, 0x5eb9, 0xa9ea,
+ 0x5eb5, 0xa9e6, 0x5eb1, 0xa9e1, 0x5ead, 0xa9dc, 0x5ea9, 0xa9d8,
+ 0x5ea4, 0xa9d3, 0x5ea0, 0xa9ce, 0x5e9c, 0xa9ca, 0x5e98, 0xa9c5,
+ 0x5e93, 0xa9c0, 0x5e8f, 0xa9bc, 0x5e8b, 0xa9b7, 0x5e87, 0xa9b3,
+ 0x5e82, 0xa9ae, 0x5e7e, 0xa9a9, 0x5e7a, 0xa9a5, 0x5e76, 0xa9a0,
+ 0x5e71, 0xa99b, 0x5e6d, 0xa997, 0x5e69, 0xa992, 0x5e65, 0xa98d,
+ 0x5e60, 0xa989, 0x5e5c, 0xa984, 0x5e58, 0xa980, 0x5e54, 0xa97b,
+ 0x5e50, 0xa976, 0x5e4b, 0xa972, 0x5e47, 0xa96d, 0x5e43, 0xa968,
+ 0x5e3f, 0xa964, 0x5e3a, 0xa95f, 0x5e36, 0xa95b, 0x5e32, 0xa956,
+ 0x5e2d, 0xa951, 0x5e29, 0xa94d, 0x5e25, 0xa948, 0x5e21, 0xa943,
+ 0x5e1c, 0xa93f, 0x5e18, 0xa93a, 0x5e14, 0xa936, 0x5e10, 0xa931,
+ 0x5e0b, 0xa92c, 0x5e07, 0xa928, 0x5e03, 0xa923, 0x5dff, 0xa91e,
+ 0x5dfa, 0xa91a, 0x5df6, 0xa915, 0x5df2, 0xa911, 0x5dee, 0xa90c,
+ 0x5de9, 0xa907, 0x5de5, 0xa903, 0x5de1, 0xa8fe, 0x5ddc, 0xa8fa,
+ 0x5dd8, 0xa8f5, 0x5dd4, 0xa8f0, 0x5dd0, 0xa8ec, 0x5dcb, 0xa8e7,
+ 0x5dc7, 0xa8e3, 0x5dc3, 0xa8de, 0x5dbf, 0xa8d9, 0x5dba, 0xa8d5,
+ 0x5db6, 0xa8d0, 0x5db2, 0xa8cc, 0x5dad, 0xa8c7, 0x5da9, 0xa8c2,
+ 0x5da5, 0xa8be, 0x5da1, 0xa8b9, 0x5d9c, 0xa8b5, 0x5d98, 0xa8b0,
+ 0x5d94, 0xa8ab, 0x5d8f, 0xa8a7, 0x5d8b, 0xa8a2, 0x5d87, 0xa89e,
+ 0x5d83, 0xa899, 0x5d7e, 0xa894, 0x5d7a, 0xa890, 0x5d76, 0xa88b,
+ 0x5d71, 0xa887, 0x5d6d, 0xa882, 0x5d69, 0xa87d, 0x5d65, 0xa879,
+ 0x5d60, 0xa874, 0x5d5c, 0xa870, 0x5d58, 0xa86b, 0x5d53, 0xa867,
+ 0x5d4f, 0xa862, 0x5d4b, 0xa85d, 0x5d46, 0xa859, 0x5d42, 0xa854,
+ 0x5d3e, 0xa850, 0x5d3a, 0xa84b, 0x5d35, 0xa847, 0x5d31, 0xa842,
+ 0x5d2d, 0xa83d, 0x5d28, 0xa839, 0x5d24, 0xa834, 0x5d20, 0xa830,
+ 0x5d1b, 0xa82b, 0x5d17, 0xa827, 0x5d13, 0xa822, 0x5d0e, 0xa81d,
+ 0x5d0a, 0xa819, 0x5d06, 0xa814, 0x5d01, 0xa810, 0x5cfd, 0xa80b,
+ 0x5cf9, 0xa807, 0x5cf5, 0xa802, 0x5cf0, 0xa7fd, 0x5cec, 0xa7f9,
+ 0x5ce8, 0xa7f4, 0x5ce3, 0xa7f0, 0x5cdf, 0xa7eb, 0x5cdb, 0xa7e7,
+ 0x5cd6, 0xa7e2, 0x5cd2, 0xa7de, 0x5cce, 0xa7d9, 0x5cc9, 0xa7d4,
+ 0x5cc5, 0xa7d0, 0x5cc1, 0xa7cb, 0x5cbc, 0xa7c7, 0x5cb8, 0xa7c2,
+ 0x5cb4, 0xa7be, 0x5caf, 0xa7b9, 0x5cab, 0xa7b5, 0x5ca7, 0xa7b0,
+ 0x5ca2, 0xa7ab, 0x5c9e, 0xa7a7, 0x5c9a, 0xa7a2, 0x5c95, 0xa79e,
+ 0x5c91, 0xa799, 0x5c8d, 0xa795, 0x5c88, 0xa790, 0x5c84, 0xa78c,
+ 0x5c80, 0xa787, 0x5c7b, 0xa783, 0x5c77, 0xa77e, 0x5c73, 0xa779,
+ 0x5c6e, 0xa775, 0x5c6a, 0xa770, 0x5c66, 0xa76c, 0x5c61, 0xa767,
+ 0x5c5d, 0xa763, 0x5c58, 0xa75e, 0x5c54, 0xa75a, 0x5c50, 0xa755,
+ 0x5c4b, 0xa751, 0x5c47, 0xa74c, 0x5c43, 0xa748, 0x5c3e, 0xa743,
+ 0x5c3a, 0xa73f, 0x5c36, 0xa73a, 0x5c31, 0xa735, 0x5c2d, 0xa731,
+ 0x5c29, 0xa72c, 0x5c24, 0xa728, 0x5c20, 0xa723, 0x5c1b, 0xa71f,
+ 0x5c17, 0xa71a, 0x5c13, 0xa716, 0x5c0e, 0xa711, 0x5c0a, 0xa70d,
+ 0x5c06, 0xa708, 0x5c01, 0xa704, 0x5bfd, 0xa6ff, 0x5bf9, 0xa6fb,
+ 0x5bf4, 0xa6f6, 0x5bf0, 0xa6f2, 0x5beb, 0xa6ed, 0x5be7, 0xa6e9,
+ 0x5be3, 0xa6e4, 0x5bde, 0xa6e0, 0x5bda, 0xa6db, 0x5bd6, 0xa6d7,
+ 0x5bd1, 0xa6d2, 0x5bcd, 0xa6ce, 0x5bc8, 0xa6c9, 0x5bc4, 0xa6c5,
+ 0x5bc0, 0xa6c0, 0x5bbb, 0xa6bc, 0x5bb7, 0xa6b7, 0x5bb2, 0xa6b3,
+ 0x5bae, 0xa6ae, 0x5baa, 0xa6aa, 0x5ba5, 0xa6a5, 0x5ba1, 0xa6a1,
+ 0x5b9d, 0xa69c, 0x5b98, 0xa698, 0x5b94, 0xa693, 0x5b8f, 0xa68f,
+ 0x5b8b, 0xa68a, 0x5b87, 0xa686, 0x5b82, 0xa681, 0x5b7e, 0xa67d,
+ 0x5b79, 0xa678, 0x5b75, 0xa674, 0x5b71, 0xa66f, 0x5b6c, 0xa66b,
+ 0x5b68, 0xa666, 0x5b63, 0xa662, 0x5b5f, 0xa65d, 0x5b5b, 0xa659,
+ 0x5b56, 0xa654, 0x5b52, 0xa650, 0x5b4d, 0xa64b, 0x5b49, 0xa647,
+ 0x5b45, 0xa642, 0x5b40, 0xa63e, 0x5b3c, 0xa639, 0x5b37, 0xa635,
+ 0x5b33, 0xa630, 0x5b2f, 0xa62c, 0x5b2a, 0xa627, 0x5b26, 0xa623,
+ 0x5b21, 0xa61f, 0x5b1d, 0xa61a, 0x5b19, 0xa616, 0x5b14, 0xa611,
+ 0x5b10, 0xa60d, 0x5b0b, 0xa608, 0x5b07, 0xa604, 0x5b02, 0xa5ff,
+ 0x5afe, 0xa5fb, 0x5afa, 0xa5f6, 0x5af5, 0xa5f2, 0x5af1, 0xa5ed,
+ 0x5aec, 0xa5e9, 0x5ae8, 0xa5e4, 0x5ae4, 0xa5e0, 0x5adf, 0xa5dc,
+ 0x5adb, 0xa5d7, 0x5ad6, 0xa5d3, 0x5ad2, 0xa5ce, 0x5acd, 0xa5ca,
+ 0x5ac9, 0xa5c5, 0x5ac5, 0xa5c1, 0x5ac0, 0xa5bc, 0x5abc, 0xa5b8,
+ 0x5ab7, 0xa5b3, 0x5ab3, 0xa5af, 0x5aae, 0xa5aa, 0x5aaa, 0xa5a6,
+ 0x5aa5, 0xa5a2, 0x5aa1, 0xa59d, 0x5a9d, 0xa599, 0x5a98, 0xa594,
+ 0x5a94, 0xa590, 0x5a8f, 0xa58b, 0x5a8b, 0xa587, 0x5a86, 0xa582,
+ 0x5a82, 0xa57e, 0x5a7e, 0xa57a, 0x5a79, 0xa575, 0x5a75, 0xa571,
+ 0x5a70, 0xa56c, 0x5a6c, 0xa568, 0x5a67, 0xa563, 0x5a63, 0xa55f,
+ 0x5a5e, 0xa55b, 0x5a5a, 0xa556, 0x5a56, 0xa552, 0x5a51, 0xa54d,
+ 0x5a4d, 0xa549, 0x5a48, 0xa544, 0x5a44, 0xa540, 0x5a3f, 0xa53b,
+ 0x5a3b, 0xa537, 0x5a36, 0xa533, 0x5a32, 0xa52e, 0x5a2d, 0xa52a,
+ 0x5a29, 0xa525, 0x5a24, 0xa521, 0x5a20, 0xa51c, 0x5a1c, 0xa518,
+ 0x5a17, 0xa514, 0x5a13, 0xa50f, 0x5a0e, 0xa50b, 0x5a0a, 0xa506,
+ 0x5a05, 0xa502, 0x5a01, 0xa4fe, 0x59fc, 0xa4f9, 0x59f8, 0xa4f5,
+ 0x59f3, 0xa4f0, 0x59ef, 0xa4ec, 0x59ea, 0xa4e7, 0x59e6, 0xa4e3,
+ 0x59e1, 0xa4df, 0x59dd, 0xa4da, 0x59d9, 0xa4d6, 0x59d4, 0xa4d1,
+ 0x59d0, 0xa4cd, 0x59cb, 0xa4c9, 0x59c7, 0xa4c4, 0x59c2, 0xa4c0,
+ 0x59be, 0xa4bb, 0x59b9, 0xa4b7, 0x59b5, 0xa4b3, 0x59b0, 0xa4ae,
+ 0x59ac, 0xa4aa, 0x59a7, 0xa4a5, 0x59a3, 0xa4a1, 0x599e, 0xa49d,
+ 0x599a, 0xa498, 0x5995, 0xa494, 0x5991, 0xa48f, 0x598c, 0xa48b,
+ 0x5988, 0xa487, 0x5983, 0xa482, 0x597f, 0xa47e, 0x597a, 0xa479,
+ 0x5976, 0xa475, 0x5971, 0xa471, 0x596d, 0xa46c, 0x5968, 0xa468,
+ 0x5964, 0xa463, 0x595f, 0xa45f, 0x595b, 0xa45b, 0x5956, 0xa456,
+ 0x5952, 0xa452, 0x594d, 0xa44e, 0x5949, 0xa449, 0x5944, 0xa445,
+ 0x5940, 0xa440, 0x593b, 0xa43c, 0x5937, 0xa438, 0x5932, 0xa433,
+ 0x592e, 0xa42f, 0x5929, 0xa42a, 0x5925, 0xa426, 0x5920, 0xa422,
+ 0x591c, 0xa41d, 0x5917, 0xa419, 0x5913, 0xa415, 0x590e, 0xa410,
+ 0x590a, 0xa40c, 0x5905, 0xa407, 0x5901, 0xa403, 0x58fc, 0xa3ff,
+ 0x58f8, 0xa3fa, 0x58f3, 0xa3f6, 0x58ef, 0xa3f2, 0x58ea, 0xa3ed,
+ 0x58e6, 0xa3e9, 0x58e1, 0xa3e5, 0x58dd, 0xa3e0, 0x58d8, 0xa3dc,
+ 0x58d4, 0xa3d7, 0x58cf, 0xa3d3, 0x58cb, 0xa3cf, 0x58c6, 0xa3ca,
+ 0x58c1, 0xa3c6, 0x58bd, 0xa3c2, 0x58b8, 0xa3bd, 0x58b4, 0xa3b9,
+ 0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,
+ 0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,
+ 0x588b, 0xa392, 0x5887, 0xa38d, 0x5882, 0xa389, 0x587d, 0xa385,
+ 0x5879, 0xa380, 0x5874, 0xa37c, 0x5870, 0xa378, 0x586b, 0xa373,
+ 0x5867, 0xa36f, 0x5862, 0xa36b, 0x585e, 0xa366, 0x5859, 0xa362,
+ 0x5855, 0xa35e, 0x5850, 0xa359, 0x584b, 0xa355, 0x5847, 0xa351,
+ 0x5842, 0xa34c, 0x583e, 0xa348, 0x5839, 0xa344, 0x5835, 0xa33f,
+ 0x5830, 0xa33b, 0x582c, 0xa337, 0x5827, 0xa332, 0x5822, 0xa32e,
+ 0x581e, 0xa32a, 0x5819, 0xa325, 0x5815, 0xa321, 0x5810, 0xa31d,
+ 0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,
+ 0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,
+ 0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,
+ 0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,
+ 0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,
+ 0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,
+ 0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,
+ 0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,
+ 0x5779, 0xa28f, 0x5775, 0xa28a, 0x5770, 0xa286, 0x576c, 0xa282,
+ 0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,
+ 0x5755, 0xa26c, 0x5750, 0xa268, 0x574b, 0xa264, 0x5747, 0xa25f,
+ 0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,
+ 0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,
+ 0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,
+ 0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,
+ 0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,
+ 0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,
+ 0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,
+ 0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,
+ 0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,
+ 0x569c, 0xa1c1, 0x5698, 0xa1bd, 0x5693, 0xa1b9, 0x568e, 0xa1b5,
+ 0x568a, 0xa1b0, 0x5685, 0xa1ac, 0x5680, 0xa1a8, 0x567c, 0xa1a4,
+ 0x5677, 0xa1a0, 0x5673, 0xa19b, 0x566e, 0xa197, 0x5669, 0xa193,
+ 0x5665, 0xa18f, 0x5660, 0xa18a, 0x565b, 0xa186, 0x5657, 0xa182,
+ 0x5652, 0xa17e, 0x564d, 0xa179, 0x5649, 0xa175, 0x5644, 0xa171,
+ 0x5640, 0xa16d, 0x563b, 0xa168, 0x5636, 0xa164, 0x5632, 0xa160,
+ 0x562d, 0xa15c, 0x5628, 0xa157, 0x5624, 0xa153, 0x561f, 0xa14f,
+ 0x561a, 0xa14b, 0x5616, 0xa147, 0x5611, 0xa142, 0x560c, 0xa13e,
+ 0x5608, 0xa13a, 0x5603, 0xa136, 0x55fe, 0xa131, 0x55fa, 0xa12d,
+ 0x55f5, 0xa129, 0x55f0, 0xa125, 0x55ec, 0xa121, 0x55e7, 0xa11c,
+ 0x55e3, 0xa118, 0x55de, 0xa114, 0x55d9, 0xa110, 0x55d5, 0xa10b,
+ 0x55d0, 0xa107, 0x55cb, 0xa103, 0x55c7, 0xa0ff, 0x55c2, 0xa0fb,
+ 0x55bd, 0xa0f6, 0x55b9, 0xa0f2, 0x55b4, 0xa0ee, 0x55af, 0xa0ea,
+ 0x55ab, 0xa0e6, 0x55a6, 0xa0e1, 0x55a1, 0xa0dd, 0x559d, 0xa0d9,
+ 0x5598, 0xa0d5, 0x5593, 0xa0d1, 0x558f, 0xa0cc, 0x558a, 0xa0c8,
+ 0x5585, 0xa0c4, 0x5581, 0xa0c0, 0x557c, 0xa0bc, 0x5577, 0xa0b7,
+ 0x5572, 0xa0b3, 0x556e, 0xa0af, 0x5569, 0xa0ab, 0x5564, 0xa0a7,
+ 0x5560, 0xa0a2, 0x555b, 0xa09e, 0x5556, 0xa09a, 0x5552, 0xa096,
+ 0x554d, 0xa092, 0x5548, 0xa08e, 0x5544, 0xa089, 0x553f, 0xa085,
+ 0x553a, 0xa081, 0x5536, 0xa07d, 0x5531, 0xa079, 0x552c, 0xa074,
+ 0x5528, 0xa070, 0x5523, 0xa06c, 0x551e, 0xa068, 0x5519, 0xa064,
+ 0x5515, 0xa060, 0x5510, 0xa05b, 0x550b, 0xa057, 0x5507, 0xa053,
+ 0x5502, 0xa04f, 0x54fd, 0xa04b, 0x54f9, 0xa046, 0x54f4, 0xa042,
+ 0x54ef, 0xa03e, 0x54ea, 0xa03a, 0x54e6, 0xa036, 0x54e1, 0xa032,
+ 0x54dc, 0xa02d, 0x54d8, 0xa029, 0x54d3, 0xa025, 0x54ce, 0xa021,
+ 0x54ca, 0xa01d, 0x54c5, 0xa019, 0x54c0, 0xa014, 0x54bb, 0xa010,
+ 0x54b7, 0xa00c, 0x54b2, 0xa008, 0x54ad, 0xa004, 0x54a9, 0xa000,
+ 0x54a4, 0x9ffc, 0x549f, 0x9ff7, 0x549a, 0x9ff3, 0x5496, 0x9fef,
+ 0x5491, 0x9feb, 0x548c, 0x9fe7, 0x5488, 0x9fe3, 0x5483, 0x9fde,
+ 0x547e, 0x9fda, 0x5479, 0x9fd6, 0x5475, 0x9fd2, 0x5470, 0x9fce,
+ 0x546b, 0x9fca, 0x5467, 0x9fc6, 0x5462, 0x9fc1, 0x545d, 0x9fbd,
+ 0x5458, 0x9fb9, 0x5454, 0x9fb5, 0x544f, 0x9fb1, 0x544a, 0x9fad,
+ 0x5445, 0x9fa9, 0x5441, 0x9fa4, 0x543c, 0x9fa0, 0x5437, 0x9f9c,
+ 0x5433, 0x9f98, 0x542e, 0x9f94, 0x5429, 0x9f90, 0x5424, 0x9f8c,
+ 0x5420, 0x9f88, 0x541b, 0x9f83, 0x5416, 0x9f7f, 0x5411, 0x9f7b,
+ 0x540d, 0x9f77, 0x5408, 0x9f73, 0x5403, 0x9f6f, 0x53fe, 0x9f6b,
+ 0x53fa, 0x9f67, 0x53f5, 0x9f62, 0x53f0, 0x9f5e, 0x53eb, 0x9f5a,
+ 0x53e7, 0x9f56, 0x53e2, 0x9f52, 0x53dd, 0x9f4e, 0x53d8, 0x9f4a,
+ 0x53d4, 0x9f46, 0x53cf, 0x9f41, 0x53ca, 0x9f3d, 0x53c5, 0x9f39,
+ 0x53c1, 0x9f35, 0x53bc, 0x9f31, 0x53b7, 0x9f2d, 0x53b2, 0x9f29,
+ 0x53ae, 0x9f25, 0x53a9, 0x9f21, 0x53a4, 0x9f1c, 0x539f, 0x9f18,
+ 0x539b, 0x9f14, 0x5396, 0x9f10, 0x5391, 0x9f0c, 0x538c, 0x9f08,
+ 0x5388, 0x9f04, 0x5383, 0x9f00, 0x537e, 0x9efc, 0x5379, 0x9ef8,
+ 0x5375, 0x9ef3, 0x5370, 0x9eef, 0x536b, 0x9eeb, 0x5366, 0x9ee7,
+ 0x5362, 0x9ee3, 0x535d, 0x9edf, 0x5358, 0x9edb, 0x5353, 0x9ed7,
+ 0x534e, 0x9ed3, 0x534a, 0x9ecf, 0x5345, 0x9ecb, 0x5340, 0x9ec6,
+ 0x533b, 0x9ec2, 0x5337, 0x9ebe, 0x5332, 0x9eba, 0x532d, 0x9eb6,
+ 0x5328, 0x9eb2, 0x5323, 0x9eae, 0x531f, 0x9eaa, 0x531a, 0x9ea6,
+ 0x5315, 0x9ea2, 0x5310, 0x9e9e, 0x530c, 0x9e9a, 0x5307, 0x9e95,
+ 0x5302, 0x9e91, 0x52fd, 0x9e8d, 0x52f8, 0x9e89, 0x52f4, 0x9e85,
+ 0x52ef, 0x9e81, 0x52ea, 0x9e7d, 0x52e5, 0x9e79, 0x52e1, 0x9e75,
+ 0x52dc, 0x9e71, 0x52d7, 0x9e6d, 0x52d2, 0x9e69, 0x52cd, 0x9e65,
+ 0x52c9, 0x9e61, 0x52c4, 0x9e5d, 0x52bf, 0x9e58, 0x52ba, 0x9e54,
+ 0x52b5, 0x9e50, 0x52b1, 0x9e4c, 0x52ac, 0x9e48, 0x52a7, 0x9e44,
+ 0x52a2, 0x9e40, 0x529d, 0x9e3c, 0x5299, 0x9e38, 0x5294, 0x9e34,
+ 0x528f, 0x9e30, 0x528a, 0x9e2c, 0x5285, 0x9e28, 0x5281, 0x9e24,
+ 0x527c, 0x9e20, 0x5277, 0x9e1c, 0x5272, 0x9e18, 0x526d, 0x9e14,
+ 0x5269, 0x9e0f, 0x5264, 0x9e0b, 0x525f, 0x9e07, 0x525a, 0x9e03,
+ 0x5255, 0x9dff, 0x5251, 0x9dfb, 0x524c, 0x9df7, 0x5247, 0x9df3,
+ 0x5242, 0x9def, 0x523d, 0x9deb, 0x5238, 0x9de7, 0x5234, 0x9de3,
+ 0x522f, 0x9ddf, 0x522a, 0x9ddb, 0x5225, 0x9dd7, 0x5220, 0x9dd3,
+ 0x521c, 0x9dcf, 0x5217, 0x9dcb, 0x5212, 0x9dc7, 0x520d, 0x9dc3,
+ 0x5208, 0x9dbf, 0x5203, 0x9dbb, 0x51ff, 0x9db7, 0x51fa, 0x9db3,
+ 0x51f5, 0x9daf, 0x51f0, 0x9dab, 0x51eb, 0x9da7, 0x51e6, 0x9da3,
+ 0x51e2, 0x9d9f, 0x51dd, 0x9d9b, 0x51d8, 0x9d97, 0x51d3, 0x9d93,
+ 0x51ce, 0x9d8f, 0x51c9, 0x9d8b, 0x51c5, 0x9d86, 0x51c0, 0x9d82,
+ 0x51bb, 0x9d7e, 0x51b6, 0x9d7a, 0x51b1, 0x9d76, 0x51ac, 0x9d72,
+ 0x51a8, 0x9d6e, 0x51a3, 0x9d6a, 0x519e, 0x9d66, 0x5199, 0x9d62,
+ 0x5194, 0x9d5e, 0x518f, 0x9d5a, 0x518b, 0x9d56, 0x5186, 0x9d52,
+ 0x5181, 0x9d4e, 0x517c, 0x9d4a, 0x5177, 0x9d46, 0x5172, 0x9d42,
+ 0x516e, 0x9d3e, 0x5169, 0x9d3a, 0x5164, 0x9d36, 0x515f, 0x9d32,
+ 0x515a, 0x9d2e, 0x5155, 0x9d2a, 0x5150, 0x9d26, 0x514c, 0x9d22,
+ 0x5147, 0x9d1e, 0x5142, 0x9d1a, 0x513d, 0x9d16, 0x5138, 0x9d12,
+ 0x5133, 0x9d0e, 0x512e, 0x9d0b, 0x512a, 0x9d07, 0x5125, 0x9d03,
+ 0x5120, 0x9cff, 0x511b, 0x9cfb, 0x5116, 0x9cf7, 0x5111, 0x9cf3,
+ 0x510c, 0x9cef, 0x5108, 0x9ceb, 0x5103, 0x9ce7, 0x50fe, 0x9ce3,
+ 0x50f9, 0x9cdf, 0x50f4, 0x9cdb, 0x50ef, 0x9cd7, 0x50ea, 0x9cd3,
+ 0x50e5, 0x9ccf, 0x50e1, 0x9ccb, 0x50dc, 0x9cc7, 0x50d7, 0x9cc3,
+ 0x50d2, 0x9cbf, 0x50cd, 0x9cbb, 0x50c8, 0x9cb7, 0x50c3, 0x9cb3,
+ 0x50bf, 0x9caf, 0x50ba, 0x9cab, 0x50b5, 0x9ca7, 0x50b0, 0x9ca3,
+ 0x50ab, 0x9c9f, 0x50a6, 0x9c9b, 0x50a1, 0x9c97, 0x509c, 0x9c93,
+ 0x5097, 0x9c8f, 0x5093, 0x9c8b, 0x508e, 0x9c88, 0x5089, 0x9c84,
+ 0x5084, 0x9c80, 0x507f, 0x9c7c, 0x507a, 0x9c78, 0x5075, 0x9c74,
+ 0x5070, 0x9c70, 0x506c, 0x9c6c, 0x5067, 0x9c68, 0x5062, 0x9c64,
+ 0x505d, 0x9c60, 0x5058, 0x9c5c, 0x5053, 0x9c58, 0x504e, 0x9c54,
+ 0x5049, 0x9c50, 0x5044, 0x9c4c, 0x503f, 0x9c48, 0x503b, 0x9c44,
+ 0x5036, 0x9c40, 0x5031, 0x9c3d, 0x502c, 0x9c39, 0x5027, 0x9c35,
+ 0x5022, 0x9c31, 0x501d, 0x9c2d, 0x5018, 0x9c29, 0x5013, 0x9c25,
+ 0x500f, 0x9c21, 0x500a, 0x9c1d, 0x5005, 0x9c19, 0x5000, 0x9c15,
+ 0x4ffb, 0x9c11, 0x4ff6, 0x9c0d, 0x4ff1, 0x9c09, 0x4fec, 0x9c06,
+ 0x4fe7, 0x9c02, 0x4fe2, 0x9bfe, 0x4fdd, 0x9bfa, 0x4fd9, 0x9bf6,
+ 0x4fd4, 0x9bf2, 0x4fcf, 0x9bee, 0x4fca, 0x9bea, 0x4fc5, 0x9be6,
+ 0x4fc0, 0x9be2, 0x4fbb, 0x9bde, 0x4fb6, 0x9bda, 0x4fb1, 0x9bd7,
+ 0x4fac, 0x9bd3, 0x4fa7, 0x9bcf, 0x4fa2, 0x9bcb, 0x4f9e, 0x9bc7,
+ 0x4f99, 0x9bc3, 0x4f94, 0x9bbf, 0x4f8f, 0x9bbb, 0x4f8a, 0x9bb7,
+ 0x4f85, 0x9bb3, 0x4f80, 0x9baf, 0x4f7b, 0x9bac, 0x4f76, 0x9ba8,
+ 0x4f71, 0x9ba4, 0x4f6c, 0x9ba0, 0x4f67, 0x9b9c, 0x4f62, 0x9b98,
+ 0x4f5e, 0x9b94, 0x4f59, 0x9b90, 0x4f54, 0x9b8c, 0x4f4f, 0x9b88,
+ 0x4f4a, 0x9b85, 0x4f45, 0x9b81, 0x4f40, 0x9b7d, 0x4f3b, 0x9b79,
+ 0x4f36, 0x9b75, 0x4f31, 0x9b71, 0x4f2c, 0x9b6d, 0x4f27, 0x9b69,
+ 0x4f22, 0x9b65, 0x4f1d, 0x9b62, 0x4f18, 0x9b5e, 0x4f14, 0x9b5a,
+ 0x4f0f, 0x9b56, 0x4f0a, 0x9b52, 0x4f05, 0x9b4e, 0x4f00, 0x9b4a,
+ 0x4efb, 0x9b46, 0x4ef6, 0x9b43, 0x4ef1, 0x9b3f, 0x4eec, 0x9b3b,
+ 0x4ee7, 0x9b37, 0x4ee2, 0x9b33, 0x4edd, 0x9b2f, 0x4ed8, 0x9b2b,
+ 0x4ed3, 0x9b27, 0x4ece, 0x9b24, 0x4ec9, 0x9b20, 0x4ec4, 0x9b1c,
+ 0x4ebf, 0x9b18, 0x4eba, 0x9b14, 0x4eb6, 0x9b10, 0x4eb1, 0x9b0c,
+ 0x4eac, 0x9b09, 0x4ea7, 0x9b05, 0x4ea2, 0x9b01, 0x4e9d, 0x9afd,
+ 0x4e98, 0x9af9, 0x4e93, 0x9af5, 0x4e8e, 0x9af1, 0x4e89, 0x9aed,
+ 0x4e84, 0x9aea, 0x4e7f, 0x9ae6, 0x4e7a, 0x9ae2, 0x4e75, 0x9ade,
+ 0x4e70, 0x9ada, 0x4e6b, 0x9ad6, 0x4e66, 0x9ad3, 0x4e61, 0x9acf,
+ 0x4e5c, 0x9acb, 0x4e57, 0x9ac7, 0x4e52, 0x9ac3, 0x4e4d, 0x9abf,
+ 0x4e48, 0x9abb, 0x4e43, 0x9ab8, 0x4e3e, 0x9ab4, 0x4e39, 0x9ab0,
+ 0x4e34, 0x9aac, 0x4e2f, 0x9aa8, 0x4e2a, 0x9aa4, 0x4e26, 0x9aa1,
+ 0x4e21, 0x9a9d, 0x4e1c, 0x9a99, 0x4e17, 0x9a95, 0x4e12, 0x9a91,
+ 0x4e0d, 0x9a8d, 0x4e08, 0x9a8a, 0x4e03, 0x9a86, 0x4dfe, 0x9a82,
+ 0x4df9, 0x9a7e, 0x4df4, 0x9a7a, 0x4def, 0x9a76, 0x4dea, 0x9a73,
+ 0x4de5, 0x9a6f, 0x4de0, 0x9a6b, 0x4ddb, 0x9a67, 0x4dd6, 0x9a63,
+ 0x4dd1, 0x9a60, 0x4dcc, 0x9a5c, 0x4dc7, 0x9a58, 0x4dc2, 0x9a54,
+ 0x4dbd, 0x9a50, 0x4db8, 0x9a4c, 0x4db3, 0x9a49, 0x4dae, 0x9a45,
+ 0x4da9, 0x9a41, 0x4da4, 0x9a3d, 0x4d9f, 0x9a39, 0x4d9a, 0x9a36,
+ 0x4d95, 0x9a32, 0x4d90, 0x9a2e, 0x4d8b, 0x9a2a, 0x4d86, 0x9a26,
+ 0x4d81, 0x9a23, 0x4d7c, 0x9a1f, 0x4d77, 0x9a1b, 0x4d72, 0x9a17,
+ 0x4d6d, 0x9a13, 0x4d68, 0x9a10, 0x4d63, 0x9a0c, 0x4d5e, 0x9a08,
+ 0x4d59, 0x9a04, 0x4d54, 0x9a00, 0x4d4f, 0x99fd, 0x4d4a, 0x99f9,
+ 0x4d45, 0x99f5, 0x4d40, 0x99f1, 0x4d3b, 0x99ed, 0x4d36, 0x99ea,
+ 0x4d31, 0x99e6, 0x4d2c, 0x99e2, 0x4d27, 0x99de, 0x4d22, 0x99da,
+ 0x4d1d, 0x99d7, 0x4d18, 0x99d3, 0x4d13, 0x99cf, 0x4d0e, 0x99cb,
+ 0x4d09, 0x99c7, 0x4d04, 0x99c4, 0x4cff, 0x99c0, 0x4cfa, 0x99bc,
+ 0x4cf5, 0x99b8, 0x4cf0, 0x99b5, 0x4ceb, 0x99b1, 0x4ce6, 0x99ad,
+ 0x4ce1, 0x99a9, 0x4cdb, 0x99a5, 0x4cd6, 0x99a2, 0x4cd1, 0x999e,
+ 0x4ccc, 0x999a, 0x4cc7, 0x9996, 0x4cc2, 0x9993, 0x4cbd, 0x998f,
+ 0x4cb8, 0x998b, 0x4cb3, 0x9987, 0x4cae, 0x9984, 0x4ca9, 0x9980,
+ 0x4ca4, 0x997c, 0x4c9f, 0x9978, 0x4c9a, 0x9975, 0x4c95, 0x9971,
+ 0x4c90, 0x996d, 0x4c8b, 0x9969, 0x4c86, 0x9965, 0x4c81, 0x9962,
+ 0x4c7c, 0x995e, 0x4c77, 0x995a, 0x4c72, 0x9956, 0x4c6d, 0x9953,
+ 0x4c68, 0x994f, 0x4c63, 0x994b, 0x4c5e, 0x9947, 0x4c59, 0x9944,
+ 0x4c54, 0x9940, 0x4c4f, 0x993c, 0x4c49, 0x9938, 0x4c44, 0x9935,
+ 0x4c3f, 0x9931, 0x4c3a, 0x992d, 0x4c35, 0x992a, 0x4c30, 0x9926,
+ 0x4c2b, 0x9922, 0x4c26, 0x991e, 0x4c21, 0x991b, 0x4c1c, 0x9917,
+ 0x4c17, 0x9913, 0x4c12, 0x990f, 0x4c0d, 0x990c, 0x4c08, 0x9908,
+ 0x4c03, 0x9904, 0x4bfe, 0x9900, 0x4bf9, 0x98fd, 0x4bf4, 0x98f9,
+ 0x4bef, 0x98f5, 0x4be9, 0x98f2, 0x4be4, 0x98ee, 0x4bdf, 0x98ea,
+ 0x4bda, 0x98e6, 0x4bd5, 0x98e3, 0x4bd0, 0x98df, 0x4bcb, 0x98db,
+ 0x4bc6, 0x98d7, 0x4bc1, 0x98d4, 0x4bbc, 0x98d0, 0x4bb7, 0x98cc,
+ 0x4bb2, 0x98c9, 0x4bad, 0x98c5, 0x4ba8, 0x98c1, 0x4ba3, 0x98bd,
+ 0x4b9e, 0x98ba, 0x4b98, 0x98b6, 0x4b93, 0x98b2, 0x4b8e, 0x98af,
+ 0x4b89, 0x98ab, 0x4b84, 0x98a7, 0x4b7f, 0x98a3, 0x4b7a, 0x98a0,
+ 0x4b75, 0x989c, 0x4b70, 0x9898, 0x4b6b, 0x9895, 0x4b66, 0x9891,
+ 0x4b61, 0x988d, 0x4b5c, 0x988a, 0x4b56, 0x9886, 0x4b51, 0x9882,
+ 0x4b4c, 0x987e, 0x4b47, 0x987b, 0x4b42, 0x9877, 0x4b3d, 0x9873,
+ 0x4b38, 0x9870, 0x4b33, 0x986c, 0x4b2e, 0x9868, 0x4b29, 0x9865,
+ 0x4b24, 0x9861, 0x4b1f, 0x985d, 0x4b19, 0x985a, 0x4b14, 0x9856,
+ 0x4b0f, 0x9852, 0x4b0a, 0x984e, 0x4b05, 0x984b, 0x4b00, 0x9847,
+ 0x4afb, 0x9843, 0x4af6, 0x9840, 0x4af1, 0x983c, 0x4aec, 0x9838,
+ 0x4ae7, 0x9835, 0x4ae1, 0x9831, 0x4adc, 0x982d, 0x4ad7, 0x982a,
+ 0x4ad2, 0x9826, 0x4acd, 0x9822, 0x4ac8, 0x981f, 0x4ac3, 0x981b,
+ 0x4abe, 0x9817, 0x4ab9, 0x9814, 0x4ab4, 0x9810, 0x4aae, 0x980c,
+ 0x4aa9, 0x9809, 0x4aa4, 0x9805, 0x4a9f, 0x9801, 0x4a9a, 0x97fe,
+ 0x4a95, 0x97fa, 0x4a90, 0x97f6, 0x4a8b, 0x97f3, 0x4a86, 0x97ef,
+ 0x4a81, 0x97eb, 0x4a7b, 0x97e8, 0x4a76, 0x97e4, 0x4a71, 0x97e0,
+ 0x4a6c, 0x97dd, 0x4a67, 0x97d9, 0x4a62, 0x97d5, 0x4a5d, 0x97d2,
+ 0x4a58, 0x97ce, 0x4a52, 0x97cb, 0x4a4d, 0x97c7, 0x4a48, 0x97c3,
+ 0x4a43, 0x97c0, 0x4a3e, 0x97bc, 0x4a39, 0x97b8, 0x4a34, 0x97b5,
+ 0x4a2f, 0x97b1, 0x4a2a, 0x97ad, 0x4a24, 0x97aa, 0x4a1f, 0x97a6,
+ 0x4a1a, 0x97a2, 0x4a15, 0x979f, 0x4a10, 0x979b, 0x4a0b, 0x9798,
+ 0x4a06, 0x9794, 0x4a01, 0x9790, 0x49fb, 0x978d, 0x49f6, 0x9789,
+ 0x49f1, 0x9785, 0x49ec, 0x9782, 0x49e7, 0x977e, 0x49e2, 0x977a,
+ 0x49dd, 0x9777, 0x49d8, 0x9773, 0x49d2, 0x9770, 0x49cd, 0x976c,
+ 0x49c8, 0x9768, 0x49c3, 0x9765, 0x49be, 0x9761, 0x49b9, 0x975d,
+ 0x49b4, 0x975a, 0x49ae, 0x9756, 0x49a9, 0x9753, 0x49a4, 0x974f,
+ 0x499f, 0x974b, 0x499a, 0x9748, 0x4995, 0x9744, 0x4990, 0x9741,
+ 0x498a, 0x973d, 0x4985, 0x9739, 0x4980, 0x9736, 0x497b, 0x9732,
+ 0x4976, 0x972f, 0x4971, 0x972b, 0x496c, 0x9727, 0x4966, 0x9724,
+ 0x4961, 0x9720, 0x495c, 0x971d, 0x4957, 0x9719, 0x4952, 0x9715,
+ 0x494d, 0x9712, 0x4948, 0x970e, 0x4942, 0x970b, 0x493d, 0x9707,
+ 0x4938, 0x9703, 0x4933, 0x9700, 0x492e, 0x96fc, 0x4929, 0x96f9,
+ 0x4923, 0x96f5, 0x491e, 0x96f1, 0x4919, 0x96ee, 0x4914, 0x96ea,
+ 0x490f, 0x96e7, 0x490a, 0x96e3, 0x4905, 0x96df, 0x48ff, 0x96dc,
+ 0x48fa, 0x96d8, 0x48f5, 0x96d5, 0x48f0, 0x96d1, 0x48eb, 0x96ce,
+ 0x48e6, 0x96ca, 0x48e0, 0x96c6, 0x48db, 0x96c3, 0x48d6, 0x96bf,
+ 0x48d1, 0x96bc, 0x48cc, 0x96b8, 0x48c7, 0x96b5, 0x48c1, 0x96b1,
+ 0x48bc, 0x96ad, 0x48b7, 0x96aa, 0x48b2, 0x96a6, 0x48ad, 0x96a3,
+ 0x48a8, 0x969f, 0x48a2, 0x969c, 0x489d, 0x9698, 0x4898, 0x9694,
+ 0x4893, 0x9691, 0x488e, 0x968d, 0x4888, 0x968a, 0x4883, 0x9686,
+ 0x487e, 0x9683, 0x4879, 0x967f, 0x4874, 0x967b, 0x486f, 0x9678,
+ 0x4869, 0x9674, 0x4864, 0x9671, 0x485f, 0x966d, 0x485a, 0x966a,
+ 0x4855, 0x9666, 0x484f, 0x9663, 0x484a, 0x965f, 0x4845, 0x965b,
+ 0x4840, 0x9658, 0x483b, 0x9654, 0x4836, 0x9651, 0x4830, 0x964d,
+ 0x482b, 0x964a, 0x4826, 0x9646, 0x4821, 0x9643, 0x481c, 0x963f,
+ 0x4816, 0x963c, 0x4811, 0x9638, 0x480c, 0x9635, 0x4807, 0x9631,
+ 0x4802, 0x962d, 0x47fc, 0x962a, 0x47f7, 0x9626, 0x47f2, 0x9623,
+ 0x47ed, 0x961f, 0x47e8, 0x961c, 0x47e2, 0x9618, 0x47dd, 0x9615,
+ 0x47d8, 0x9611, 0x47d3, 0x960e, 0x47ce, 0x960a, 0x47c8, 0x9607,
+ 0x47c3, 0x9603, 0x47be, 0x9600, 0x47b9, 0x95fc, 0x47b4, 0x95f9,
+ 0x47ae, 0x95f5, 0x47a9, 0x95f2, 0x47a4, 0x95ee, 0x479f, 0x95ea,
+ 0x479a, 0x95e7, 0x4794, 0x95e3, 0x478f, 0x95e0, 0x478a, 0x95dc,
+ 0x4785, 0x95d9, 0x4780, 0x95d5, 0x477a, 0x95d2, 0x4775, 0x95ce,
+ 0x4770, 0x95cb, 0x476b, 0x95c7, 0x4765, 0x95c4, 0x4760, 0x95c0,
+ 0x475b, 0x95bd, 0x4756, 0x95b9, 0x4751, 0x95b6, 0x474b, 0x95b2,
+ 0x4746, 0x95af, 0x4741, 0x95ab, 0x473c, 0x95a8, 0x4737, 0x95a4,
+ 0x4731, 0x95a1, 0x472c, 0x959d, 0x4727, 0x959a, 0x4722, 0x9596,
+ 0x471c, 0x9593, 0x4717, 0x958f, 0x4712, 0x958c, 0x470d, 0x9588,
+ 0x4708, 0x9585, 0x4702, 0x9581, 0x46fd, 0x957e, 0x46f8, 0x957a,
+ 0x46f3, 0x9577, 0x46ed, 0x9574, 0x46e8, 0x9570, 0x46e3, 0x956d,
+ 0x46de, 0x9569, 0x46d8, 0x9566, 0x46d3, 0x9562, 0x46ce, 0x955f,
+ 0x46c9, 0x955b, 0x46c4, 0x9558, 0x46be, 0x9554, 0x46b9, 0x9551,
+ 0x46b4, 0x954d, 0x46af, 0x954a, 0x46a9, 0x9546, 0x46a4, 0x9543,
+ 0x469f, 0x953f, 0x469a, 0x953c, 0x4694, 0x9538, 0x468f, 0x9535,
+ 0x468a, 0x9532, 0x4685, 0x952e, 0x467f, 0x952b, 0x467a, 0x9527,
+ 0x4675, 0x9524, 0x4670, 0x9520, 0x466a, 0x951d, 0x4665, 0x9519,
+ 0x4660, 0x9516, 0x465b, 0x9512, 0x4655, 0x950f, 0x4650, 0x950c,
+ 0x464b, 0x9508, 0x4646, 0x9505, 0x4640, 0x9501, 0x463b, 0x94fe,
+ 0x4636, 0x94fa, 0x4631, 0x94f7, 0x462b, 0x94f3, 0x4626, 0x94f0,
+ 0x4621, 0x94ed, 0x461c, 0x94e9, 0x4616, 0x94e6, 0x4611, 0x94e2,
+ 0x460c, 0x94df, 0x4607, 0x94db, 0x4601, 0x94d8, 0x45fc, 0x94d4,
+ 0x45f7, 0x94d1, 0x45f2, 0x94ce, 0x45ec, 0x94ca, 0x45e7, 0x94c7,
+ 0x45e2, 0x94c3, 0x45dd, 0x94c0, 0x45d7, 0x94bc, 0x45d2, 0x94b9,
+ 0x45cd, 0x94b6, 0x45c7, 0x94b2, 0x45c2, 0x94af, 0x45bd, 0x94ab,
+ 0x45b8, 0x94a8, 0x45b2, 0x94a4, 0x45ad, 0x94a1, 0x45a8, 0x949e,
+ 0x45a3, 0x949a, 0x459d, 0x9497, 0x4598, 0x9493, 0x4593, 0x9490,
+ 0x458d, 0x948d, 0x4588, 0x9489, 0x4583, 0x9486, 0x457e, 0x9482,
+ 0x4578, 0x947f, 0x4573, 0x947b, 0x456e, 0x9478, 0x4569, 0x9475,
+ 0x4563, 0x9471, 0x455e, 0x946e, 0x4559, 0x946a, 0x4553, 0x9467,
+ 0x454e, 0x9464, 0x4549, 0x9460, 0x4544, 0x945d, 0x453e, 0x9459,
+ 0x4539, 0x9456, 0x4534, 0x9453, 0x452e, 0x944f, 0x4529, 0x944c,
+ 0x4524, 0x9448, 0x451f, 0x9445, 0x4519, 0x9442, 0x4514, 0x943e,
+ 0x450f, 0x943b, 0x4509, 0x9437, 0x4504, 0x9434, 0x44ff, 0x9431,
+ 0x44fa, 0x942d, 0x44f4, 0x942a, 0x44ef, 0x9427, 0x44ea, 0x9423,
+ 0x44e4, 0x9420, 0x44df, 0x941c, 0x44da, 0x9419, 0x44d4, 0x9416,
+ 0x44cf, 0x9412, 0x44ca, 0x940f, 0x44c5, 0x940b, 0x44bf, 0x9408,
+ 0x44ba, 0x9405, 0x44b5, 0x9401, 0x44af, 0x93fe, 0x44aa, 0x93fb,
+ 0x44a5, 0x93f7, 0x449f, 0x93f4, 0x449a, 0x93f1, 0x4495, 0x93ed,
+ 0x4490, 0x93ea, 0x448a, 0x93e6, 0x4485, 0x93e3, 0x4480, 0x93e0,
+ 0x447a, 0x93dc, 0x4475, 0x93d9, 0x4470, 0x93d6, 0x446a, 0x93d2,
+ 0x4465, 0x93cf, 0x4460, 0x93cc, 0x445a, 0x93c8, 0x4455, 0x93c5,
+ 0x4450, 0x93c1, 0x444b, 0x93be, 0x4445, 0x93bb, 0x4440, 0x93b7,
+ 0x443b, 0x93b4, 0x4435, 0x93b1, 0x4430, 0x93ad, 0x442b, 0x93aa,
+ 0x4425, 0x93a7, 0x4420, 0x93a3, 0x441b, 0x93a0, 0x4415, 0x939d,
+ 0x4410, 0x9399, 0x440b, 0x9396, 0x4405, 0x9393, 0x4400, 0x938f,
+ 0x43fb, 0x938c, 0x43f5, 0x9389, 0x43f0, 0x9385, 0x43eb, 0x9382,
+ 0x43e5, 0x937f, 0x43e0, 0x937b, 0x43db, 0x9378, 0x43d5, 0x9375,
+ 0x43d0, 0x9371, 0x43cb, 0x936e, 0x43c5, 0x936b, 0x43c0, 0x9367,
+ 0x43bb, 0x9364, 0x43b5, 0x9361, 0x43b0, 0x935d, 0x43ab, 0x935a,
+ 0x43a5, 0x9357, 0x43a0, 0x9353, 0x439b, 0x9350, 0x4395, 0x934d,
+ 0x4390, 0x9349, 0x438b, 0x9346, 0x4385, 0x9343, 0x4380, 0x933f,
+ 0x437b, 0x933c, 0x4375, 0x9339, 0x4370, 0x9336, 0x436b, 0x9332,
+ 0x4365, 0x932f, 0x4360, 0x932c, 0x435b, 0x9328, 0x4355, 0x9325,
+ 0x4350, 0x9322, 0x434b, 0x931e, 0x4345, 0x931b, 0x4340, 0x9318,
+ 0x433b, 0x9314, 0x4335, 0x9311, 0x4330, 0x930e, 0x432b, 0x930b,
+ 0x4325, 0x9307, 0x4320, 0x9304, 0x431b, 0x9301, 0x4315, 0x92fd,
+ 0x4310, 0x92fa, 0x430b, 0x92f7, 0x4305, 0x92f4, 0x4300, 0x92f0,
+ 0x42fa, 0x92ed, 0x42f5, 0x92ea, 0x42f0, 0x92e6, 0x42ea, 0x92e3,
+ 0x42e5, 0x92e0, 0x42e0, 0x92dd, 0x42da, 0x92d9, 0x42d5, 0x92d6,
+ 0x42d0, 0x92d3, 0x42ca, 0x92cf, 0x42c5, 0x92cc, 0x42c0, 0x92c9,
+ 0x42ba, 0x92c6, 0x42b5, 0x92c2, 0x42af, 0x92bf, 0x42aa, 0x92bc,
+ 0x42a5, 0x92b8, 0x429f, 0x92b5, 0x429a, 0x92b2, 0x4295, 0x92af,
+ 0x428f, 0x92ab, 0x428a, 0x92a8, 0x4284, 0x92a5, 0x427f, 0x92a2,
+ 0x427a, 0x929e, 0x4274, 0x929b, 0x426f, 0x9298, 0x426a, 0x9295,
+ 0x4264, 0x9291, 0x425f, 0x928e, 0x425a, 0x928b, 0x4254, 0x9288,
+ 0x424f, 0x9284, 0x4249, 0x9281, 0x4244, 0x927e, 0x423f, 0x927b,
+ 0x4239, 0x9277, 0x4234, 0x9274, 0x422f, 0x9271, 0x4229, 0x926e,
+ 0x4224, 0x926a, 0x421e, 0x9267, 0x4219, 0x9264, 0x4214, 0x9261,
+ 0x420e, 0x925d, 0x4209, 0x925a, 0x4203, 0x9257, 0x41fe, 0x9254,
+ 0x41f9, 0x9250, 0x41f3, 0x924d, 0x41ee, 0x924a, 0x41e9, 0x9247,
+ 0x41e3, 0x9243, 0x41de, 0x9240, 0x41d8, 0x923d, 0x41d3, 0x923a,
+ 0x41ce, 0x9236, 0x41c8, 0x9233, 0x41c3, 0x9230, 0x41bd, 0x922d,
+ 0x41b8, 0x922a, 0x41b3, 0x9226, 0x41ad, 0x9223, 0x41a8, 0x9220,
+ 0x41a2, 0x921d, 0x419d, 0x9219, 0x4198, 0x9216, 0x4192, 0x9213,
+ 0x418d, 0x9210, 0x4188, 0x920d, 0x4182, 0x9209, 0x417d, 0x9206,
+ 0x4177, 0x9203, 0x4172, 0x9200, 0x416d, 0x91fc, 0x4167, 0x91f9,
+ 0x4162, 0x91f6, 0x415c, 0x91f3, 0x4157, 0x91f0, 0x4152, 0x91ec,
+ 0x414c, 0x91e9, 0x4147, 0x91e6, 0x4141, 0x91e3, 0x413c, 0x91e0,
+ 0x4136, 0x91dc, 0x4131, 0x91d9, 0x412c, 0x91d6, 0x4126, 0x91d3,
+ 0x4121, 0x91d0, 0x411b, 0x91cc, 0x4116, 0x91c9, 0x4111, 0x91c6,
+ 0x410b, 0x91c3, 0x4106, 0x91c0, 0x4100, 0x91bc, 0x40fb, 0x91b9,
+ 0x40f6, 0x91b6, 0x40f0, 0x91b3, 0x40eb, 0x91b0, 0x40e5, 0x91ad,
+ 0x40e0, 0x91a9, 0x40da, 0x91a6, 0x40d5, 0x91a3, 0x40d0, 0x91a0,
+ 0x40ca, 0x919d, 0x40c5, 0x9199, 0x40bf, 0x9196, 0x40ba, 0x9193,
+ 0x40b5, 0x9190, 0x40af, 0x918d, 0x40aa, 0x918a, 0x40a4, 0x9186,
+ 0x409f, 0x9183, 0x4099, 0x9180, 0x4094, 0x917d, 0x408f, 0x917a,
+ 0x4089, 0x9177, 0x4084, 0x9173, 0x407e, 0x9170, 0x4079, 0x916d,
+ 0x4073, 0x916a, 0x406e, 0x9167, 0x4069, 0x9164, 0x4063, 0x9160,
+ 0x405e, 0x915d, 0x4058, 0x915a, 0x4053, 0x9157, 0x404d, 0x9154,
+ 0x4048, 0x9151, 0x4043, 0x914d, 0x403d, 0x914a, 0x4038, 0x9147,
+ 0x4032, 0x9144, 0x402d, 0x9141, 0x4027, 0x913e, 0x4022, 0x913a,
+ 0x401d, 0x9137, 0x4017, 0x9134, 0x4012, 0x9131, 0x400c, 0x912e,
+ 0x4007, 0x912b, 0x4001, 0x9128, 0x3ffc, 0x9124, 0x3ff6, 0x9121,
+ 0x3ff1, 0x911e, 0x3fec, 0x911b, 0x3fe6, 0x9118, 0x3fe1, 0x9115,
+ 0x3fdb, 0x9112, 0x3fd6, 0x910f, 0x3fd0, 0x910b, 0x3fcb, 0x9108,
+ 0x3fc5, 0x9105, 0x3fc0, 0x9102, 0x3fbb, 0x90ff, 0x3fb5, 0x90fc,
+ 0x3fb0, 0x90f9, 0x3faa, 0x90f5, 0x3fa5, 0x90f2, 0x3f9f, 0x90ef,
+ 0x3f9a, 0x90ec, 0x3f94, 0x90e9, 0x3f8f, 0x90e6, 0x3f89, 0x90e3,
+ 0x3f84, 0x90e0, 0x3f7f, 0x90dd, 0x3f79, 0x90d9, 0x3f74, 0x90d6,
+ 0x3f6e, 0x90d3, 0x3f69, 0x90d0, 0x3f63, 0x90cd, 0x3f5e, 0x90ca,
+ 0x3f58, 0x90c7, 0x3f53, 0x90c4, 0x3f4d, 0x90c1, 0x3f48, 0x90bd,
+ 0x3f43, 0x90ba, 0x3f3d, 0x90b7, 0x3f38, 0x90b4, 0x3f32, 0x90b1,
+ 0x3f2d, 0x90ae, 0x3f27, 0x90ab, 0x3f22, 0x90a8, 0x3f1c, 0x90a5,
+ 0x3f17, 0x90a1, 0x3f11, 0x909e, 0x3f0c, 0x909b, 0x3f06, 0x9098,
+ 0x3f01, 0x9095, 0x3efb, 0x9092, 0x3ef6, 0x908f, 0x3ef1, 0x908c,
+ 0x3eeb, 0x9089, 0x3ee6, 0x9086, 0x3ee0, 0x9083, 0x3edb, 0x907f,
+ 0x3ed5, 0x907c, 0x3ed0, 0x9079, 0x3eca, 0x9076, 0x3ec5, 0x9073,
+ 0x3ebf, 0x9070, 0x3eba, 0x906d, 0x3eb4, 0x906a, 0x3eaf, 0x9067,
+ 0x3ea9, 0x9064, 0x3ea4, 0x9061, 0x3e9e, 0x905e, 0x3e99, 0x905b,
+ 0x3e93, 0x9057, 0x3e8e, 0x9054, 0x3e88, 0x9051, 0x3e83, 0x904e,
+ 0x3e7d, 0x904b, 0x3e78, 0x9048, 0x3e73, 0x9045, 0x3e6d, 0x9042,
+ 0x3e68, 0x903f, 0x3e62, 0x903c, 0x3e5d, 0x9039, 0x3e57, 0x9036,
+ 0x3e52, 0x9033, 0x3e4c, 0x9030, 0x3e47, 0x902d, 0x3e41, 0x902a,
+ 0x3e3c, 0x9026, 0x3e36, 0x9023, 0x3e31, 0x9020, 0x3e2b, 0x901d,
+ 0x3e26, 0x901a, 0x3e20, 0x9017, 0x3e1b, 0x9014, 0x3e15, 0x9011,
+ 0x3e10, 0x900e, 0x3e0a, 0x900b, 0x3e05, 0x9008, 0x3dff, 0x9005,
+ 0x3dfa, 0x9002, 0x3df4, 0x8fff, 0x3def, 0x8ffc, 0x3de9, 0x8ff9,
+ 0x3de4, 0x8ff6, 0x3dde, 0x8ff3, 0x3dd9, 0x8ff0, 0x3dd3, 0x8fed,
+ 0x3dce, 0x8fea, 0x3dc8, 0x8fe7, 0x3dc3, 0x8fe3, 0x3dbd, 0x8fe0,
+ 0x3db8, 0x8fdd, 0x3db2, 0x8fda, 0x3dad, 0x8fd7, 0x3da7, 0x8fd4,
+ 0x3da2, 0x8fd1, 0x3d9c, 0x8fce, 0x3d97, 0x8fcb, 0x3d91, 0x8fc8,
+ 0x3d8c, 0x8fc5, 0x3d86, 0x8fc2, 0x3d81, 0x8fbf, 0x3d7b, 0x8fbc,
+ 0x3d76, 0x8fb9, 0x3d70, 0x8fb6, 0x3d6b, 0x8fb3, 0x3d65, 0x8fb0,
+ 0x3d60, 0x8fad, 0x3d5a, 0x8faa, 0x3d55, 0x8fa7, 0x3d4f, 0x8fa4,
+ 0x3d49, 0x8fa1, 0x3d44, 0x8f9e, 0x3d3e, 0x8f9b, 0x3d39, 0x8f98,
+ 0x3d33, 0x8f95, 0x3d2e, 0x8f92, 0x3d28, 0x8f8f, 0x3d23, 0x8f8c,
+ 0x3d1d, 0x8f89, 0x3d18, 0x8f86, 0x3d12, 0x8f83, 0x3d0d, 0x8f80,
+ 0x3d07, 0x8f7d, 0x3d02, 0x8f7a, 0x3cfc, 0x8f77, 0x3cf7, 0x8f74,
+ 0x3cf1, 0x8f71, 0x3cec, 0x8f6e, 0x3ce6, 0x8f6b, 0x3ce1, 0x8f68,
+ 0x3cdb, 0x8f65, 0x3cd6, 0x8f62, 0x3cd0, 0x8f5f, 0x3cca, 0x8f5c,
+ 0x3cc5, 0x8f59, 0x3cbf, 0x8f56, 0x3cba, 0x8f53, 0x3cb4, 0x8f50,
+ 0x3caf, 0x8f4d, 0x3ca9, 0x8f4a, 0x3ca4, 0x8f47, 0x3c9e, 0x8f44,
+ 0x3c99, 0x8f41, 0x3c93, 0x8f3e, 0x3c8e, 0x8f3b, 0x3c88, 0x8f38,
+ 0x3c83, 0x8f35, 0x3c7d, 0x8f32, 0x3c77, 0x8f2f, 0x3c72, 0x8f2d,
+ 0x3c6c, 0x8f2a, 0x3c67, 0x8f27, 0x3c61, 0x8f24, 0x3c5c, 0x8f21,
+ 0x3c56, 0x8f1e, 0x3c51, 0x8f1b, 0x3c4b, 0x8f18, 0x3c46, 0x8f15,
+ 0x3c40, 0x8f12, 0x3c3b, 0x8f0f, 0x3c35, 0x8f0c, 0x3c2f, 0x8f09,
+ 0x3c2a, 0x8f06, 0x3c24, 0x8f03, 0x3c1f, 0x8f00, 0x3c19, 0x8efd,
+ 0x3c14, 0x8efa, 0x3c0e, 0x8ef7, 0x3c09, 0x8ef4, 0x3c03, 0x8ef1,
+ 0x3bfd, 0x8eee, 0x3bf8, 0x8eec, 0x3bf2, 0x8ee9, 0x3bed, 0x8ee6,
+ 0x3be7, 0x8ee3, 0x3be2, 0x8ee0, 0x3bdc, 0x8edd, 0x3bd7, 0x8eda,
+ 0x3bd1, 0x8ed7, 0x3bcc, 0x8ed4, 0x3bc6, 0x8ed1, 0x3bc0, 0x8ece,
+ 0x3bbb, 0x8ecb, 0x3bb5, 0x8ec8, 0x3bb0, 0x8ec5, 0x3baa, 0x8ec2,
+ 0x3ba5, 0x8ebf, 0x3b9f, 0x8ebd, 0x3b99, 0x8eba, 0x3b94, 0x8eb7,
+ 0x3b8e, 0x8eb4, 0x3b89, 0x8eb1, 0x3b83, 0x8eae, 0x3b7e, 0x8eab,
+ 0x3b78, 0x8ea8, 0x3b73, 0x8ea5, 0x3b6d, 0x8ea2, 0x3b67, 0x8e9f,
+ 0x3b62, 0x8e9c, 0x3b5c, 0x8e99, 0x3b57, 0x8e97, 0x3b51, 0x8e94,
+ 0x3b4c, 0x8e91, 0x3b46, 0x8e8e, 0x3b40, 0x8e8b, 0x3b3b, 0x8e88,
+ 0x3b35, 0x8e85, 0x3b30, 0x8e82, 0x3b2a, 0x8e7f, 0x3b25, 0x8e7c,
+ 0x3b1f, 0x8e7a, 0x3b19, 0x8e77, 0x3b14, 0x8e74, 0x3b0e, 0x8e71,
+ 0x3b09, 0x8e6e, 0x3b03, 0x8e6b, 0x3afe, 0x8e68, 0x3af8, 0x8e65,
+ 0x3af2, 0x8e62, 0x3aed, 0x8e5f, 0x3ae7, 0x8e5d, 0x3ae2, 0x8e5a,
+ 0x3adc, 0x8e57, 0x3ad7, 0x8e54, 0x3ad1, 0x8e51, 0x3acb, 0x8e4e,
+ 0x3ac6, 0x8e4b, 0x3ac0, 0x8e48, 0x3abb, 0x8e45, 0x3ab5, 0x8e43,
+ 0x3aaf, 0x8e40, 0x3aaa, 0x8e3d, 0x3aa4, 0x8e3a, 0x3a9f, 0x8e37,
+ 0x3a99, 0x8e34, 0x3a94, 0x8e31, 0x3a8e, 0x8e2e, 0x3a88, 0x8e2c,
+ 0x3a83, 0x8e29, 0x3a7d, 0x8e26, 0x3a78, 0x8e23, 0x3a72, 0x8e20,
+ 0x3a6c, 0x8e1d, 0x3a67, 0x8e1a, 0x3a61, 0x8e17, 0x3a5c, 0x8e15,
+ 0x3a56, 0x8e12, 0x3a50, 0x8e0f, 0x3a4b, 0x8e0c, 0x3a45, 0x8e09,
+ 0x3a40, 0x8e06, 0x3a3a, 0x8e03, 0x3a34, 0x8e01, 0x3a2f, 0x8dfe,
+ 0x3a29, 0x8dfb, 0x3a24, 0x8df8, 0x3a1e, 0x8df5, 0x3a19, 0x8df2,
+ 0x3a13, 0x8def, 0x3a0d, 0x8ded, 0x3a08, 0x8dea, 0x3a02, 0x8de7,
+ 0x39fd, 0x8de4, 0x39f7, 0x8de1, 0x39f1, 0x8dde, 0x39ec, 0x8ddc,
+ 0x39e6, 0x8dd9, 0x39e0, 0x8dd6, 0x39db, 0x8dd3, 0x39d5, 0x8dd0,
+ 0x39d0, 0x8dcd, 0x39ca, 0x8dca, 0x39c4, 0x8dc8, 0x39bf, 0x8dc5,
+ 0x39b9, 0x8dc2, 0x39b4, 0x8dbf, 0x39ae, 0x8dbc, 0x39a8, 0x8db9,
+ 0x39a3, 0x8db7, 0x399d, 0x8db4, 0x3998, 0x8db1, 0x3992, 0x8dae,
+ 0x398c, 0x8dab, 0x3987, 0x8da9, 0x3981, 0x8da6, 0x397c, 0x8da3,
+ 0x3976, 0x8da0, 0x3970, 0x8d9d, 0x396b, 0x8d9a, 0x3965, 0x8d98,
+ 0x395f, 0x8d95, 0x395a, 0x8d92, 0x3954, 0x8d8f, 0x394f, 0x8d8c,
+ 0x3949, 0x8d8a, 0x3943, 0x8d87, 0x393e, 0x8d84, 0x3938, 0x8d81,
+ 0x3932, 0x8d7e, 0x392d, 0x8d7b, 0x3927, 0x8d79, 0x3922, 0x8d76,
+ 0x391c, 0x8d73, 0x3916, 0x8d70, 0x3911, 0x8d6d, 0x390b, 0x8d6b,
+ 0x3906, 0x8d68, 0x3900, 0x8d65, 0x38fa, 0x8d62, 0x38f5, 0x8d5f,
+ 0x38ef, 0x8d5d, 0x38e9, 0x8d5a, 0x38e4, 0x8d57, 0x38de, 0x8d54,
+ 0x38d8, 0x8d51, 0x38d3, 0x8d4f, 0x38cd, 0x8d4c, 0x38c8, 0x8d49,
+ 0x38c2, 0x8d46, 0x38bc, 0x8d44, 0x38b7, 0x8d41, 0x38b1, 0x8d3e,
+ 0x38ab, 0x8d3b, 0x38a6, 0x8d38, 0x38a0, 0x8d36, 0x389b, 0x8d33,
+ 0x3895, 0x8d30, 0x388f, 0x8d2d, 0x388a, 0x8d2b, 0x3884, 0x8d28,
+ 0x387e, 0x8d25, 0x3879, 0x8d22, 0x3873, 0x8d1f, 0x386d, 0x8d1d,
+ 0x3868, 0x8d1a, 0x3862, 0x8d17, 0x385d, 0x8d14, 0x3857, 0x8d12,
+ 0x3851, 0x8d0f, 0x384c, 0x8d0c, 0x3846, 0x8d09, 0x3840, 0x8d07,
+ 0x383b, 0x8d04, 0x3835, 0x8d01, 0x382f, 0x8cfe, 0x382a, 0x8cfb,
+ 0x3824, 0x8cf9, 0x381e, 0x8cf6, 0x3819, 0x8cf3, 0x3813, 0x8cf0,
+ 0x380d, 0x8cee, 0x3808, 0x8ceb, 0x3802, 0x8ce8, 0x37fd, 0x8ce5,
+ 0x37f7, 0x8ce3, 0x37f1, 0x8ce0, 0x37ec, 0x8cdd, 0x37e6, 0x8cda,
+ 0x37e0, 0x8cd8, 0x37db, 0x8cd5, 0x37d5, 0x8cd2, 0x37cf, 0x8cd0,
+ 0x37ca, 0x8ccd, 0x37c4, 0x8cca, 0x37be, 0x8cc7, 0x37b9, 0x8cc5,
+ 0x37b3, 0x8cc2, 0x37ad, 0x8cbf, 0x37a8, 0x8cbc, 0x37a2, 0x8cba,
+ 0x379c, 0x8cb7, 0x3797, 0x8cb4, 0x3791, 0x8cb1, 0x378b, 0x8caf,
+ 0x3786, 0x8cac, 0x3780, 0x8ca9, 0x377a, 0x8ca7, 0x3775, 0x8ca4,
+ 0x376f, 0x8ca1, 0x3769, 0x8c9e, 0x3764, 0x8c9c, 0x375e, 0x8c99,
+ 0x3758, 0x8c96, 0x3753, 0x8c94, 0x374d, 0x8c91, 0x3747, 0x8c8e,
+ 0x3742, 0x8c8b, 0x373c, 0x8c89, 0x3736, 0x8c86, 0x3731, 0x8c83,
+ 0x372b, 0x8c81, 0x3725, 0x8c7e, 0x3720, 0x8c7b, 0x371a, 0x8c78,
+ 0x3714, 0x8c76, 0x370f, 0x8c73, 0x3709, 0x8c70, 0x3703, 0x8c6e,
+ 0x36fe, 0x8c6b, 0x36f8, 0x8c68, 0x36f2, 0x8c65, 0x36ed, 0x8c63,
+ 0x36e7, 0x8c60, 0x36e1, 0x8c5d, 0x36dc, 0x8c5b, 0x36d6, 0x8c58,
+ 0x36d0, 0x8c55, 0x36cb, 0x8c53, 0x36c5, 0x8c50, 0x36bf, 0x8c4d,
+ 0x36ba, 0x8c4b, 0x36b4, 0x8c48, 0x36ae, 0x8c45, 0x36a9, 0x8c43,
+ 0x36a3, 0x8c40, 0x369d, 0x8c3d, 0x3698, 0x8c3a, 0x3692, 0x8c38,
+ 0x368c, 0x8c35, 0x3686, 0x8c32, 0x3681, 0x8c30, 0x367b, 0x8c2d,
+ 0x3675, 0x8c2a, 0x3670, 0x8c28, 0x366a, 0x8c25, 0x3664, 0x8c22,
+ 0x365f, 0x8c20, 0x3659, 0x8c1d, 0x3653, 0x8c1a, 0x364e, 0x8c18,
+ 0x3648, 0x8c15, 0x3642, 0x8c12, 0x363d, 0x8c10, 0x3637, 0x8c0d,
+ 0x3631, 0x8c0a, 0x362b, 0x8c08, 0x3626, 0x8c05, 0x3620, 0x8c02,
+ 0x361a, 0x8c00, 0x3615, 0x8bfd, 0x360f, 0x8bfa, 0x3609, 0x8bf8,
+ 0x3604, 0x8bf5, 0x35fe, 0x8bf3, 0x35f8, 0x8bf0, 0x35f3, 0x8bed,
+ 0x35ed, 0x8beb, 0x35e7, 0x8be8, 0x35e1, 0x8be5, 0x35dc, 0x8be3,
+ 0x35d6, 0x8be0, 0x35d0, 0x8bdd, 0x35cb, 0x8bdb, 0x35c5, 0x8bd8,
+ 0x35bf, 0x8bd5, 0x35ba, 0x8bd3, 0x35b4, 0x8bd0, 0x35ae, 0x8bce,
+ 0x35a8, 0x8bcb, 0x35a3, 0x8bc8, 0x359d, 0x8bc6, 0x3597, 0x8bc3,
+ 0x3592, 0x8bc0, 0x358c, 0x8bbe, 0x3586, 0x8bbb, 0x3580, 0x8bb8,
+ 0x357b, 0x8bb6, 0x3575, 0x8bb3, 0x356f, 0x8bb1, 0x356a, 0x8bae,
+ 0x3564, 0x8bab, 0x355e, 0x8ba9, 0x3558, 0x8ba6, 0x3553, 0x8ba4,
+ 0x354d, 0x8ba1, 0x3547, 0x8b9e, 0x3542, 0x8b9c, 0x353c, 0x8b99,
+ 0x3536, 0x8b96, 0x3530, 0x8b94, 0x352b, 0x8b91, 0x3525, 0x8b8f,
+ 0x351f, 0x8b8c, 0x351a, 0x8b89, 0x3514, 0x8b87, 0x350e, 0x8b84,
+ 0x3508, 0x8b82, 0x3503, 0x8b7f, 0x34fd, 0x8b7c, 0x34f7, 0x8b7a,
+ 0x34f2, 0x8b77, 0x34ec, 0x8b75, 0x34e6, 0x8b72, 0x34e0, 0x8b6f,
+ 0x34db, 0x8b6d, 0x34d5, 0x8b6a, 0x34cf, 0x8b68, 0x34ca, 0x8b65,
+ 0x34c4, 0x8b62, 0x34be, 0x8b60, 0x34b8, 0x8b5d, 0x34b3, 0x8b5b,
+ 0x34ad, 0x8b58, 0x34a7, 0x8b55, 0x34a1, 0x8b53, 0x349c, 0x8b50,
+ 0x3496, 0x8b4e, 0x3490, 0x8b4b, 0x348b, 0x8b49, 0x3485, 0x8b46,
+ 0x347f, 0x8b43, 0x3479, 0x8b41, 0x3474, 0x8b3e, 0x346e, 0x8b3c,
+ 0x3468, 0x8b39, 0x3462, 0x8b37, 0x345d, 0x8b34, 0x3457, 0x8b31,
+ 0x3451, 0x8b2f, 0x344b, 0x8b2c, 0x3446, 0x8b2a, 0x3440, 0x8b27,
+ 0x343a, 0x8b25, 0x3435, 0x8b22, 0x342f, 0x8b1f, 0x3429, 0x8b1d,
+ 0x3423, 0x8b1a, 0x341e, 0x8b18, 0x3418, 0x8b15, 0x3412, 0x8b13,
+ 0x340c, 0x8b10, 0x3407, 0x8b0e, 0x3401, 0x8b0b, 0x33fb, 0x8b08,
+ 0x33f5, 0x8b06, 0x33f0, 0x8b03, 0x33ea, 0x8b01, 0x33e4, 0x8afe,
+ 0x33de, 0x8afc, 0x33d9, 0x8af9, 0x33d3, 0x8af7, 0x33cd, 0x8af4,
+ 0x33c7, 0x8af1, 0x33c2, 0x8aef, 0x33bc, 0x8aec, 0x33b6, 0x8aea,
+ 0x33b0, 0x8ae7, 0x33ab, 0x8ae5, 0x33a5, 0x8ae2, 0x339f, 0x8ae0,
+ 0x3399, 0x8add, 0x3394, 0x8adb, 0x338e, 0x8ad8, 0x3388, 0x8ad6,
+ 0x3382, 0x8ad3, 0x337d, 0x8ad1, 0x3377, 0x8ace, 0x3371, 0x8acb,
+ 0x336b, 0x8ac9, 0x3366, 0x8ac6, 0x3360, 0x8ac4, 0x335a, 0x8ac1,
+ 0x3354, 0x8abf, 0x334f, 0x8abc, 0x3349, 0x8aba, 0x3343, 0x8ab7,
+ 0x333d, 0x8ab5, 0x3338, 0x8ab2, 0x3332, 0x8ab0, 0x332c, 0x8aad,
+ 0x3326, 0x8aab, 0x3321, 0x8aa8, 0x331b, 0x8aa6, 0x3315, 0x8aa3,
+ 0x330f, 0x8aa1, 0x330a, 0x8a9e, 0x3304, 0x8a9c, 0x32fe, 0x8a99,
+ 0x32f8, 0x8a97, 0x32f3, 0x8a94, 0x32ed, 0x8a92, 0x32e7, 0x8a8f,
+ 0x32e1, 0x8a8d, 0x32db, 0x8a8a, 0x32d6, 0x8a88, 0x32d0, 0x8a85,
+ 0x32ca, 0x8a83, 0x32c4, 0x8a80, 0x32bf, 0x8a7e, 0x32b9, 0x8a7b,
+ 0x32b3, 0x8a79, 0x32ad, 0x8a76, 0x32a8, 0x8a74, 0x32a2, 0x8a71,
+ 0x329c, 0x8a6f, 0x3296, 0x8a6c, 0x3290, 0x8a6a, 0x328b, 0x8a67,
+ 0x3285, 0x8a65, 0x327f, 0x8a62, 0x3279, 0x8a60, 0x3274, 0x8a5d,
+ 0x326e, 0x8a5b, 0x3268, 0x8a59, 0x3262, 0x8a56, 0x325d, 0x8a54,
+ 0x3257, 0x8a51, 0x3251, 0x8a4f, 0x324b, 0x8a4c, 0x3245, 0x8a4a,
+ 0x3240, 0x8a47, 0x323a, 0x8a45, 0x3234, 0x8a42, 0x322e, 0x8a40,
+ 0x3228, 0x8a3d, 0x3223, 0x8a3b, 0x321d, 0x8a38, 0x3217, 0x8a36,
+ 0x3211, 0x8a34, 0x320c, 0x8a31, 0x3206, 0x8a2f, 0x3200, 0x8a2c,
+ 0x31fa, 0x8a2a, 0x31f4, 0x8a27, 0x31ef, 0x8a25, 0x31e9, 0x8a22,
+ 0x31e3, 0x8a20, 0x31dd, 0x8a1d, 0x31d8, 0x8a1b, 0x31d2, 0x8a19,
+ 0x31cc, 0x8a16, 0x31c6, 0x8a14, 0x31c0, 0x8a11, 0x31bb, 0x8a0f,
+ 0x31b5, 0x8a0c, 0x31af, 0x8a0a, 0x31a9, 0x8a07, 0x31a3, 0x8a05,
+ 0x319e, 0x8a03, 0x3198, 0x8a00, 0x3192, 0x89fe, 0x318c, 0x89fb,
+ 0x3186, 0x89f9, 0x3181, 0x89f6, 0x317b, 0x89f4, 0x3175, 0x89f2,
+ 0x316f, 0x89ef, 0x3169, 0x89ed, 0x3164, 0x89ea, 0x315e, 0x89e8,
+ 0x3158, 0x89e5, 0x3152, 0x89e3, 0x314c, 0x89e1, 0x3147, 0x89de,
+ 0x3141, 0x89dc, 0x313b, 0x89d9, 0x3135, 0x89d7, 0x312f, 0x89d5,
+ 0x312a, 0x89d2, 0x3124, 0x89d0, 0x311e, 0x89cd, 0x3118, 0x89cb,
+ 0x3112, 0x89c8, 0x310d, 0x89c6, 0x3107, 0x89c4, 0x3101, 0x89c1,
+ 0x30fb, 0x89bf, 0x30f5, 0x89bc, 0x30f0, 0x89ba, 0x30ea, 0x89b8,
+ 0x30e4, 0x89b5, 0x30de, 0x89b3, 0x30d8, 0x89b0, 0x30d3, 0x89ae,
+ 0x30cd, 0x89ac, 0x30c7, 0x89a9, 0x30c1, 0x89a7, 0x30bb, 0x89a4,
+ 0x30b6, 0x89a2, 0x30b0, 0x89a0, 0x30aa, 0x899d, 0x30a4, 0x899b,
+ 0x309e, 0x8998, 0x3099, 0x8996, 0x3093, 0x8994, 0x308d, 0x8991,
+ 0x3087, 0x898f, 0x3081, 0x898d, 0x307b, 0x898a, 0x3076, 0x8988,
+ 0x3070, 0x8985, 0x306a, 0x8983, 0x3064, 0x8981, 0x305e, 0x897e,
+ 0x3059, 0x897c, 0x3053, 0x897a, 0x304d, 0x8977, 0x3047, 0x8975,
+ 0x3041, 0x8972, 0x303b, 0x8970, 0x3036, 0x896e, 0x3030, 0x896b,
+ 0x302a, 0x8969, 0x3024, 0x8967, 0x301e, 0x8964, 0x3019, 0x8962,
+ 0x3013, 0x8960, 0x300d, 0x895d, 0x3007, 0x895b, 0x3001, 0x8958,
+ 0x2ffb, 0x8956, 0x2ff6, 0x8954, 0x2ff0, 0x8951, 0x2fea, 0x894f,
+ 0x2fe4, 0x894d, 0x2fde, 0x894a, 0x2fd8, 0x8948, 0x2fd3, 0x8946,
+ 0x2fcd, 0x8943, 0x2fc7, 0x8941, 0x2fc1, 0x893f, 0x2fbb, 0x893c,
+ 0x2fb5, 0x893a, 0x2fb0, 0x8938, 0x2faa, 0x8935, 0x2fa4, 0x8933,
+ 0x2f9e, 0x8931, 0x2f98, 0x892e, 0x2f92, 0x892c, 0x2f8d, 0x892a,
+ 0x2f87, 0x8927, 0x2f81, 0x8925, 0x2f7b, 0x8923, 0x2f75, 0x8920,
+ 0x2f6f, 0x891e, 0x2f6a, 0x891c, 0x2f64, 0x8919, 0x2f5e, 0x8917,
+ 0x2f58, 0x8915, 0x2f52, 0x8912, 0x2f4c, 0x8910, 0x2f47, 0x890e,
+ 0x2f41, 0x890b, 0x2f3b, 0x8909, 0x2f35, 0x8907, 0x2f2f, 0x8904,
+ 0x2f29, 0x8902, 0x2f24, 0x8900, 0x2f1e, 0x88fd, 0x2f18, 0x88fb,
+ 0x2f12, 0x88f9, 0x2f0c, 0x88f6, 0x2f06, 0x88f4, 0x2f01, 0x88f2,
+ 0x2efb, 0x88f0, 0x2ef5, 0x88ed, 0x2eef, 0x88eb, 0x2ee9, 0x88e9,
+ 0x2ee3, 0x88e6, 0x2edd, 0x88e4, 0x2ed8, 0x88e2, 0x2ed2, 0x88df,
+ 0x2ecc, 0x88dd, 0x2ec6, 0x88db, 0x2ec0, 0x88d9, 0x2eba, 0x88d6,
+ 0x2eb5, 0x88d4, 0x2eaf, 0x88d2, 0x2ea9, 0x88cf, 0x2ea3, 0x88cd,
+ 0x2e9d, 0x88cb, 0x2e97, 0x88c8, 0x2e91, 0x88c6, 0x2e8c, 0x88c4,
+ 0x2e86, 0x88c2, 0x2e80, 0x88bf, 0x2e7a, 0x88bd, 0x2e74, 0x88bb,
+ 0x2e6e, 0x88b9, 0x2e68, 0x88b6, 0x2e63, 0x88b4, 0x2e5d, 0x88b2,
+ 0x2e57, 0x88af, 0x2e51, 0x88ad, 0x2e4b, 0x88ab, 0x2e45, 0x88a9,
+ 0x2e3f, 0x88a6, 0x2e3a, 0x88a4, 0x2e34, 0x88a2, 0x2e2e, 0x88a0,
+ 0x2e28, 0x889d, 0x2e22, 0x889b, 0x2e1c, 0x8899, 0x2e16, 0x8896,
+ 0x2e11, 0x8894, 0x2e0b, 0x8892, 0x2e05, 0x8890, 0x2dff, 0x888d,
+ 0x2df9, 0x888b, 0x2df3, 0x8889, 0x2ded, 0x8887, 0x2de7, 0x8884,
+ 0x2de2, 0x8882, 0x2ddc, 0x8880, 0x2dd6, 0x887e, 0x2dd0, 0x887b,
+ 0x2dca, 0x8879, 0x2dc4, 0x8877, 0x2dbe, 0x8875, 0x2db9, 0x8872,
+ 0x2db3, 0x8870, 0x2dad, 0x886e, 0x2da7, 0x886c, 0x2da1, 0x8869,
+ 0x2d9b, 0x8867, 0x2d95, 0x8865, 0x2d8f, 0x8863, 0x2d8a, 0x8860,
+ 0x2d84, 0x885e, 0x2d7e, 0x885c, 0x2d78, 0x885a, 0x2d72, 0x8858,
+ 0x2d6c, 0x8855, 0x2d66, 0x8853, 0x2d60, 0x8851, 0x2d5b, 0x884f,
+ 0x2d55, 0x884c, 0x2d4f, 0x884a, 0x2d49, 0x8848, 0x2d43, 0x8846,
+ 0x2d3d, 0x8844, 0x2d37, 0x8841, 0x2d31, 0x883f, 0x2d2c, 0x883d,
+ 0x2d26, 0x883b, 0x2d20, 0x8838, 0x2d1a, 0x8836, 0x2d14, 0x8834,
+ 0x2d0e, 0x8832, 0x2d08, 0x8830, 0x2d02, 0x882d, 0x2cfd, 0x882b,
+ 0x2cf7, 0x8829, 0x2cf1, 0x8827, 0x2ceb, 0x8825, 0x2ce5, 0x8822,
+ 0x2cdf, 0x8820, 0x2cd9, 0x881e, 0x2cd3, 0x881c, 0x2ccd, 0x881a,
+ 0x2cc8, 0x8817, 0x2cc2, 0x8815, 0x2cbc, 0x8813, 0x2cb6, 0x8811,
+ 0x2cb0, 0x880f, 0x2caa, 0x880c, 0x2ca4, 0x880a, 0x2c9e, 0x8808,
+ 0x2c98, 0x8806, 0x2c93, 0x8804, 0x2c8d, 0x8801, 0x2c87, 0x87ff,
+ 0x2c81, 0x87fd, 0x2c7b, 0x87fb, 0x2c75, 0x87f9, 0x2c6f, 0x87f6,
+ 0x2c69, 0x87f4, 0x2c63, 0x87f2, 0x2c5e, 0x87f0, 0x2c58, 0x87ee,
+ 0x2c52, 0x87ec, 0x2c4c, 0x87e9, 0x2c46, 0x87e7, 0x2c40, 0x87e5,
+ 0x2c3a, 0x87e3, 0x2c34, 0x87e1, 0x2c2e, 0x87df, 0x2c29, 0x87dc,
+ 0x2c23, 0x87da, 0x2c1d, 0x87d8, 0x2c17, 0x87d6, 0x2c11, 0x87d4,
+ 0x2c0b, 0x87d2, 0x2c05, 0x87cf, 0x2bff, 0x87cd, 0x2bf9, 0x87cb,
+ 0x2bf3, 0x87c9, 0x2bee, 0x87c7, 0x2be8, 0x87c5, 0x2be2, 0x87c2,
+ 0x2bdc, 0x87c0, 0x2bd6, 0x87be, 0x2bd0, 0x87bc, 0x2bca, 0x87ba,
+ 0x2bc4, 0x87b8, 0x2bbe, 0x87b6, 0x2bb8, 0x87b3, 0x2bb2, 0x87b1,
+ 0x2bad, 0x87af, 0x2ba7, 0x87ad, 0x2ba1, 0x87ab, 0x2b9b, 0x87a9,
+ 0x2b95, 0x87a7, 0x2b8f, 0x87a4, 0x2b89, 0x87a2, 0x2b83, 0x87a0,
+ 0x2b7d, 0x879e, 0x2b77, 0x879c, 0x2b71, 0x879a, 0x2b6c, 0x8798,
+ 0x2b66, 0x8795, 0x2b60, 0x8793, 0x2b5a, 0x8791, 0x2b54, 0x878f,
+ 0x2b4e, 0x878d, 0x2b48, 0x878b, 0x2b42, 0x8789, 0x2b3c, 0x8787,
+ 0x2b36, 0x8784, 0x2b30, 0x8782, 0x2b2b, 0x8780, 0x2b25, 0x877e,
+ 0x2b1f, 0x877c, 0x2b19, 0x877a, 0x2b13, 0x8778, 0x2b0d, 0x8776,
+ 0x2b07, 0x8774, 0x2b01, 0x8771, 0x2afb, 0x876f, 0x2af5, 0x876d,
+ 0x2aef, 0x876b, 0x2ae9, 0x8769, 0x2ae4, 0x8767, 0x2ade, 0x8765,
+ 0x2ad8, 0x8763, 0x2ad2, 0x8761, 0x2acc, 0x875e, 0x2ac6, 0x875c,
+ 0x2ac0, 0x875a, 0x2aba, 0x8758, 0x2ab4, 0x8756, 0x2aae, 0x8754,
+ 0x2aa8, 0x8752, 0x2aa2, 0x8750, 0x2a9c, 0x874e, 0x2a97, 0x874c,
+ 0x2a91, 0x874a, 0x2a8b, 0x8747, 0x2a85, 0x8745, 0x2a7f, 0x8743,
+ 0x2a79, 0x8741, 0x2a73, 0x873f, 0x2a6d, 0x873d, 0x2a67, 0x873b,
+ 0x2a61, 0x8739, 0x2a5b, 0x8737, 0x2a55, 0x8735, 0x2a4f, 0x8733,
+ 0x2a49, 0x8731, 0x2a44, 0x872e, 0x2a3e, 0x872c, 0x2a38, 0x872a,
+ 0x2a32, 0x8728, 0x2a2c, 0x8726, 0x2a26, 0x8724, 0x2a20, 0x8722,
+ 0x2a1a, 0x8720, 0x2a14, 0x871e, 0x2a0e, 0x871c, 0x2a08, 0x871a,
+ 0x2a02, 0x8718, 0x29fc, 0x8716, 0x29f6, 0x8714, 0x29f0, 0x8712,
+ 0x29eb, 0x870f, 0x29e5, 0x870d, 0x29df, 0x870b, 0x29d9, 0x8709,
+ 0x29d3, 0x8707, 0x29cd, 0x8705, 0x29c7, 0x8703, 0x29c1, 0x8701,
+ 0x29bb, 0x86ff, 0x29b5, 0x86fd, 0x29af, 0x86fb, 0x29a9, 0x86f9,
+ 0x29a3, 0x86f7, 0x299d, 0x86f5, 0x2997, 0x86f3, 0x2991, 0x86f1,
+ 0x298b, 0x86ef, 0x2986, 0x86ed, 0x2980, 0x86eb, 0x297a, 0x86e9,
+ 0x2974, 0x86e7, 0x296e, 0x86e4, 0x2968, 0x86e2, 0x2962, 0x86e0,
+ 0x295c, 0x86de, 0x2956, 0x86dc, 0x2950, 0x86da, 0x294a, 0x86d8,
+ 0x2944, 0x86d6, 0x293e, 0x86d4, 0x2938, 0x86d2, 0x2932, 0x86d0,
+ 0x292c, 0x86ce, 0x2926, 0x86cc, 0x2920, 0x86ca, 0x291b, 0x86c8,
+ 0x2915, 0x86c6, 0x290f, 0x86c4, 0x2909, 0x86c2, 0x2903, 0x86c0,
+ 0x28fd, 0x86be, 0x28f7, 0x86bc, 0x28f1, 0x86ba, 0x28eb, 0x86b8,
+ 0x28e5, 0x86b6, 0x28df, 0x86b4, 0x28d9, 0x86b2, 0x28d3, 0x86b0,
+ 0x28cd, 0x86ae, 0x28c7, 0x86ac, 0x28c1, 0x86aa, 0x28bb, 0x86a8,
+ 0x28b5, 0x86a6, 0x28af, 0x86a4, 0x28a9, 0x86a2, 0x28a3, 0x86a0,
+ 0x289d, 0x869e, 0x2898, 0x869c, 0x2892, 0x869a, 0x288c, 0x8698,
+ 0x2886, 0x8696, 0x2880, 0x8694, 0x287a, 0x8692, 0x2874, 0x8690,
+ 0x286e, 0x868e, 0x2868, 0x868c, 0x2862, 0x868a, 0x285c, 0x8688,
+ 0x2856, 0x8686, 0x2850, 0x8684, 0x284a, 0x8682, 0x2844, 0x8680,
+ 0x283e, 0x867e, 0x2838, 0x867c, 0x2832, 0x867a, 0x282c, 0x8678,
+ 0x2826, 0x8676, 0x2820, 0x8674, 0x281a, 0x8672, 0x2814, 0x8670,
+ 0x280e, 0x866e, 0x2808, 0x866d, 0x2802, 0x866b, 0x27fc, 0x8669,
+ 0x27f6, 0x8667, 0x27f1, 0x8665, 0x27eb, 0x8663, 0x27e5, 0x8661,
+ 0x27df, 0x865f, 0x27d9, 0x865d, 0x27d3, 0x865b, 0x27cd, 0x8659,
+ 0x27c7, 0x8657, 0x27c1, 0x8655, 0x27bb, 0x8653, 0x27b5, 0x8651,
+ 0x27af, 0x864f, 0x27a9, 0x864d, 0x27a3, 0x864b, 0x279d, 0x8649,
+ 0x2797, 0x8647, 0x2791, 0x8645, 0x278b, 0x8644, 0x2785, 0x8642,
+ 0x277f, 0x8640, 0x2779, 0x863e, 0x2773, 0x863c, 0x276d, 0x863a,
+ 0x2767, 0x8638, 0x2761, 0x8636, 0x275b, 0x8634, 0x2755, 0x8632,
+ 0x274f, 0x8630, 0x2749, 0x862e, 0x2743, 0x862c, 0x273d, 0x862a,
+ 0x2737, 0x8628, 0x2731, 0x8627, 0x272b, 0x8625, 0x2725, 0x8623,
+ 0x271f, 0x8621, 0x2719, 0x861f, 0x2713, 0x861d, 0x270d, 0x861b,
+ 0x2707, 0x8619, 0x2701, 0x8617, 0x26fb, 0x8615, 0x26f5, 0x8613,
+ 0x26ef, 0x8611, 0x26e9, 0x8610, 0x26e4, 0x860e, 0x26de, 0x860c,
+ 0x26d8, 0x860a, 0x26d2, 0x8608, 0x26cc, 0x8606, 0x26c6, 0x8604,
+ 0x26c0, 0x8602, 0x26ba, 0x8600, 0x26b4, 0x85fe, 0x26ae, 0x85fc,
+ 0x26a8, 0x85fb, 0x26a2, 0x85f9, 0x269c, 0x85f7, 0x2696, 0x85f5,
+ 0x2690, 0x85f3, 0x268a, 0x85f1, 0x2684, 0x85ef, 0x267e, 0x85ed,
+ 0x2678, 0x85eb, 0x2672, 0x85ea, 0x266c, 0x85e8, 0x2666, 0x85e6,
+ 0x2660, 0x85e4, 0x265a, 0x85e2, 0x2654, 0x85e0, 0x264e, 0x85de,
+ 0x2648, 0x85dc, 0x2642, 0x85da, 0x263c, 0x85d9, 0x2636, 0x85d7,
+ 0x2630, 0x85d5, 0x262a, 0x85d3, 0x2624, 0x85d1, 0x261e, 0x85cf,
+ 0x2618, 0x85cd, 0x2612, 0x85cb, 0x260c, 0x85ca, 0x2606, 0x85c8,
+ 0x2600, 0x85c6, 0x25fa, 0x85c4, 0x25f4, 0x85c2, 0x25ee, 0x85c0,
+ 0x25e8, 0x85be, 0x25e2, 0x85bd, 0x25dc, 0x85bb, 0x25d6, 0x85b9,
+ 0x25d0, 0x85b7, 0x25ca, 0x85b5, 0x25c4, 0x85b3, 0x25be, 0x85b1,
+ 0x25b8, 0x85b0, 0x25b2, 0x85ae, 0x25ac, 0x85ac, 0x25a6, 0x85aa,
+ 0x25a0, 0x85a8, 0x259a, 0x85a6, 0x2594, 0x85a4, 0x258e, 0x85a3,
+ 0x2588, 0x85a1, 0x2582, 0x859f, 0x257c, 0x859d, 0x2576, 0x859b,
+ 0x2570, 0x8599, 0x256a, 0x8598, 0x2564, 0x8596, 0x255e, 0x8594,
+ 0x2558, 0x8592, 0x2552, 0x8590, 0x254c, 0x858e, 0x2546, 0x858d,
+ 0x2540, 0x858b, 0x253a, 0x8589, 0x2534, 0x8587, 0x252e, 0x8585,
+ 0x2528, 0x8583, 0x2522, 0x8582, 0x251c, 0x8580, 0x2516, 0x857e,
+ 0x250f, 0x857c, 0x2509, 0x857a, 0x2503, 0x8579, 0x24fd, 0x8577,
+ 0x24f7, 0x8575, 0x24f1, 0x8573, 0x24eb, 0x8571, 0x24e5, 0x856f,
+ 0x24df, 0x856e, 0x24d9, 0x856c, 0x24d3, 0x856a, 0x24cd, 0x8568,
+ 0x24c7, 0x8566, 0x24c1, 0x8565, 0x24bb, 0x8563, 0x24b5, 0x8561,
+ 0x24af, 0x855f, 0x24a9, 0x855d, 0x24a3, 0x855c, 0x249d, 0x855a,
+ 0x2497, 0x8558, 0x2491, 0x8556, 0x248b, 0x8554, 0x2485, 0x8553,
+ 0x247f, 0x8551, 0x2479, 0x854f, 0x2473, 0x854d, 0x246d, 0x854b,
+ 0x2467, 0x854a, 0x2461, 0x8548, 0x245b, 0x8546, 0x2455, 0x8544,
+ 0x244f, 0x8543, 0x2449, 0x8541, 0x2443, 0x853f, 0x243d, 0x853d,
+ 0x2437, 0x853b, 0x2431, 0x853a, 0x242b, 0x8538, 0x2425, 0x8536,
+ 0x241f, 0x8534, 0x2419, 0x8533, 0x2413, 0x8531, 0x240d, 0x852f,
+ 0x2407, 0x852d, 0x2401, 0x852b, 0x23fa, 0x852a, 0x23f4, 0x8528,
+ 0x23ee, 0x8526, 0x23e8, 0x8524, 0x23e2, 0x8523, 0x23dc, 0x8521,
+ 0x23d6, 0x851f, 0x23d0, 0x851d, 0x23ca, 0x851c, 0x23c4, 0x851a,
+ 0x23be, 0x8518, 0x23b8, 0x8516, 0x23b2, 0x8515, 0x23ac, 0x8513,
+ 0x23a6, 0x8511, 0x23a0, 0x850f, 0x239a, 0x850e, 0x2394, 0x850c,
+ 0x238e, 0x850a, 0x2388, 0x8508, 0x2382, 0x8507, 0x237c, 0x8505,
+ 0x2376, 0x8503, 0x2370, 0x8501, 0x236a, 0x8500, 0x2364, 0x84fe,
+ 0x235e, 0x84fc, 0x2358, 0x84fa, 0x2352, 0x84f9, 0x234b, 0x84f7,
+ 0x2345, 0x84f5, 0x233f, 0x84f4, 0x2339, 0x84f2, 0x2333, 0x84f0,
+ 0x232d, 0x84ee, 0x2327, 0x84ed, 0x2321, 0x84eb, 0x231b, 0x84e9,
+ 0x2315, 0x84e7, 0x230f, 0x84e6, 0x2309, 0x84e4, 0x2303, 0x84e2,
+ 0x22fd, 0x84e1, 0x22f7, 0x84df, 0x22f1, 0x84dd, 0x22eb, 0x84db,
+ 0x22e5, 0x84da, 0x22df, 0x84d8, 0x22d9, 0x84d6, 0x22d3, 0x84d5,
+ 0x22cd, 0x84d3, 0x22c7, 0x84d1, 0x22c0, 0x84cf, 0x22ba, 0x84ce,
+ 0x22b4, 0x84cc, 0x22ae, 0x84ca, 0x22a8, 0x84c9, 0x22a2, 0x84c7,
+ 0x229c, 0x84c5, 0x2296, 0x84c4, 0x2290, 0x84c2, 0x228a, 0x84c0,
+ 0x2284, 0x84be, 0x227e, 0x84bd, 0x2278, 0x84bb, 0x2272, 0x84b9,
+ 0x226c, 0x84b8, 0x2266, 0x84b6, 0x2260, 0x84b4, 0x225a, 0x84b3,
+ 0x2254, 0x84b1, 0x224e, 0x84af, 0x2247, 0x84ae, 0x2241, 0x84ac,
+ 0x223b, 0x84aa, 0x2235, 0x84a9, 0x222f, 0x84a7, 0x2229, 0x84a5,
+ 0x2223, 0x84a3, 0x221d, 0x84a2, 0x2217, 0x84a0, 0x2211, 0x849e,
+ 0x220b, 0x849d, 0x2205, 0x849b, 0x21ff, 0x8499, 0x21f9, 0x8498,
+ 0x21f3, 0x8496, 0x21ed, 0x8494, 0x21e7, 0x8493, 0x21e1, 0x8491,
+ 0x21da, 0x848f, 0x21d4, 0x848e, 0x21ce, 0x848c, 0x21c8, 0x848a,
+ 0x21c2, 0x8489, 0x21bc, 0x8487, 0x21b6, 0x8486, 0x21b0, 0x8484,
+ 0x21aa, 0x8482, 0x21a4, 0x8481, 0x219e, 0x847f, 0x2198, 0x847d,
+ 0x2192, 0x847c, 0x218c, 0x847a, 0x2186, 0x8478, 0x2180, 0x8477,
+ 0x2179, 0x8475, 0x2173, 0x8473, 0x216d, 0x8472, 0x2167, 0x8470,
+ 0x2161, 0x846e, 0x215b, 0x846d, 0x2155, 0x846b, 0x214f, 0x846a,
+ 0x2149, 0x8468, 0x2143, 0x8466, 0x213d, 0x8465, 0x2137, 0x8463,
+ 0x2131, 0x8461, 0x212b, 0x8460, 0x2125, 0x845e, 0x211e, 0x845d,
+ 0x2118, 0x845b, 0x2112, 0x8459, 0x210c, 0x8458, 0x2106, 0x8456,
+ 0x2100, 0x8454, 0x20fa, 0x8453, 0x20f4, 0x8451, 0x20ee, 0x8450,
+ 0x20e8, 0x844e, 0x20e2, 0x844c, 0x20dc, 0x844b, 0x20d6, 0x8449,
+ 0x20d0, 0x8447, 0x20c9, 0x8446, 0x20c3, 0x8444, 0x20bd, 0x8443,
+ 0x20b7, 0x8441, 0x20b1, 0x843f, 0x20ab, 0x843e, 0x20a5, 0x843c,
+ 0x209f, 0x843b, 0x2099, 0x8439, 0x2093, 0x8437, 0x208d, 0x8436,
+ 0x2087, 0x8434, 0x2081, 0x8433, 0x207a, 0x8431, 0x2074, 0x842f,
+ 0x206e, 0x842e, 0x2068, 0x842c, 0x2062, 0x842b, 0x205c, 0x8429,
+ 0x2056, 0x8427, 0x2050, 0x8426, 0x204a, 0x8424, 0x2044, 0x8423,
+ 0x203e, 0x8421, 0x2038, 0x8420, 0x2032, 0x841e, 0x202b, 0x841c,
+ 0x2025, 0x841b, 0x201f, 0x8419, 0x2019, 0x8418, 0x2013, 0x8416,
+ 0x200d, 0x8415, 0x2007, 0x8413, 0x2001, 0x8411, 0x1ffb, 0x8410,
+ 0x1ff5, 0x840e, 0x1fef, 0x840d, 0x1fe9, 0x840b, 0x1fe2, 0x840a,
+ 0x1fdc, 0x8408, 0x1fd6, 0x8406, 0x1fd0, 0x8405, 0x1fca, 0x8403,
+ 0x1fc4, 0x8402, 0x1fbe, 0x8400, 0x1fb8, 0x83ff, 0x1fb2, 0x83fd,
+ 0x1fac, 0x83fb, 0x1fa6, 0x83fa, 0x1f9f, 0x83f8, 0x1f99, 0x83f7,
+ 0x1f93, 0x83f5, 0x1f8d, 0x83f4, 0x1f87, 0x83f2, 0x1f81, 0x83f1,
+ 0x1f7b, 0x83ef, 0x1f75, 0x83ee, 0x1f6f, 0x83ec, 0x1f69, 0x83ea,
+ 0x1f63, 0x83e9, 0x1f5d, 0x83e7, 0x1f56, 0x83e6, 0x1f50, 0x83e4,
+ 0x1f4a, 0x83e3, 0x1f44, 0x83e1, 0x1f3e, 0x83e0, 0x1f38, 0x83de,
+ 0x1f32, 0x83dd, 0x1f2c, 0x83db, 0x1f26, 0x83da, 0x1f20, 0x83d8,
+ 0x1f19, 0x83d7, 0x1f13, 0x83d5, 0x1f0d, 0x83d3, 0x1f07, 0x83d2,
+ 0x1f01, 0x83d0, 0x1efb, 0x83cf, 0x1ef5, 0x83cd, 0x1eef, 0x83cc,
+ 0x1ee9, 0x83ca, 0x1ee3, 0x83c9, 0x1edd, 0x83c7, 0x1ed6, 0x83c6,
+ 0x1ed0, 0x83c4, 0x1eca, 0x83c3, 0x1ec4, 0x83c1, 0x1ebe, 0x83c0,
+ 0x1eb8, 0x83be, 0x1eb2, 0x83bd, 0x1eac, 0x83bb, 0x1ea6, 0x83ba,
+ 0x1ea0, 0x83b8, 0x1e99, 0x83b7, 0x1e93, 0x83b5, 0x1e8d, 0x83b4,
+ 0x1e87, 0x83b2, 0x1e81, 0x83b1, 0x1e7b, 0x83af, 0x1e75, 0x83ae,
+ 0x1e6f, 0x83ac, 0x1e69, 0x83ab, 0x1e62, 0x83a9, 0x1e5c, 0x83a8,
+ 0x1e56, 0x83a6, 0x1e50, 0x83a5, 0x1e4a, 0x83a3, 0x1e44, 0x83a2,
+ 0x1e3e, 0x83a0, 0x1e38, 0x839f, 0x1e32, 0x839d, 0x1e2c, 0x839c,
+ 0x1e25, 0x839a, 0x1e1f, 0x8399, 0x1e19, 0x8397, 0x1e13, 0x8396,
+ 0x1e0d, 0x8394, 0x1e07, 0x8393, 0x1e01, 0x8392, 0x1dfb, 0x8390,
+ 0x1df5, 0x838f, 0x1dee, 0x838d, 0x1de8, 0x838c, 0x1de2, 0x838a,
+ 0x1ddc, 0x8389, 0x1dd6, 0x8387, 0x1dd0, 0x8386, 0x1dca, 0x8384,
+ 0x1dc4, 0x8383, 0x1dbe, 0x8381, 0x1db7, 0x8380, 0x1db1, 0x837e,
+ 0x1dab, 0x837d, 0x1da5, 0x837c, 0x1d9f, 0x837a, 0x1d99, 0x8379,
+ 0x1d93, 0x8377, 0x1d8d, 0x8376, 0x1d87, 0x8374, 0x1d80, 0x8373,
+ 0x1d7a, 0x8371, 0x1d74, 0x8370, 0x1d6e, 0x836f, 0x1d68, 0x836d,
+ 0x1d62, 0x836c, 0x1d5c, 0x836a, 0x1d56, 0x8369, 0x1d50, 0x8367,
+ 0x1d49, 0x8366, 0x1d43, 0x8364, 0x1d3d, 0x8363, 0x1d37, 0x8362,
+ 0x1d31, 0x8360, 0x1d2b, 0x835f, 0x1d25, 0x835d, 0x1d1f, 0x835c,
+ 0x1d18, 0x835a, 0x1d12, 0x8359, 0x1d0c, 0x8358, 0x1d06, 0x8356,
+ 0x1d00, 0x8355, 0x1cfa, 0x8353, 0x1cf4, 0x8352, 0x1cee, 0x8350,
+ 0x1ce8, 0x834f, 0x1ce1, 0x834e, 0x1cdb, 0x834c, 0x1cd5, 0x834b,
+ 0x1ccf, 0x8349, 0x1cc9, 0x8348, 0x1cc3, 0x8347, 0x1cbd, 0x8345,
+ 0x1cb7, 0x8344, 0x1cb0, 0x8342, 0x1caa, 0x8341, 0x1ca4, 0x833f,
+ 0x1c9e, 0x833e, 0x1c98, 0x833d, 0x1c92, 0x833b, 0x1c8c, 0x833a,
+ 0x1c86, 0x8338, 0x1c7f, 0x8337, 0x1c79, 0x8336, 0x1c73, 0x8334,
+ 0x1c6d, 0x8333, 0x1c67, 0x8331, 0x1c61, 0x8330, 0x1c5b, 0x832f,
+ 0x1c55, 0x832d, 0x1c4e, 0x832c, 0x1c48, 0x832b, 0x1c42, 0x8329,
+ 0x1c3c, 0x8328, 0x1c36, 0x8326, 0x1c30, 0x8325, 0x1c2a, 0x8324,
+ 0x1c24, 0x8322, 0x1c1d, 0x8321, 0x1c17, 0x831f, 0x1c11, 0x831e,
+ 0x1c0b, 0x831d, 0x1c05, 0x831b, 0x1bff, 0x831a, 0x1bf9, 0x8319,
+ 0x1bf2, 0x8317, 0x1bec, 0x8316, 0x1be6, 0x8314, 0x1be0, 0x8313,
+ 0x1bda, 0x8312, 0x1bd4, 0x8310, 0x1bce, 0x830f, 0x1bc8, 0x830e,
+ 0x1bc1, 0x830c, 0x1bbb, 0x830b, 0x1bb5, 0x830a, 0x1baf, 0x8308,
+ 0x1ba9, 0x8307, 0x1ba3, 0x8305, 0x1b9d, 0x8304, 0x1b96, 0x8303,
+ 0x1b90, 0x8301, 0x1b8a, 0x8300, 0x1b84, 0x82ff, 0x1b7e, 0x82fd,
+ 0x1b78, 0x82fc, 0x1b72, 0x82fb, 0x1b6c, 0x82f9, 0x1b65, 0x82f8,
+ 0x1b5f, 0x82f7, 0x1b59, 0x82f5, 0x1b53, 0x82f4, 0x1b4d, 0x82f3,
+ 0x1b47, 0x82f1, 0x1b41, 0x82f0, 0x1b3a, 0x82ef, 0x1b34, 0x82ed,
+ 0x1b2e, 0x82ec, 0x1b28, 0x82eb, 0x1b22, 0x82e9, 0x1b1c, 0x82e8,
+ 0x1b16, 0x82e7, 0x1b0f, 0x82e5, 0x1b09, 0x82e4, 0x1b03, 0x82e3,
+ 0x1afd, 0x82e1, 0x1af7, 0x82e0, 0x1af1, 0x82df, 0x1aeb, 0x82dd,
+ 0x1ae4, 0x82dc, 0x1ade, 0x82db, 0x1ad8, 0x82d9, 0x1ad2, 0x82d8,
+ 0x1acc, 0x82d7, 0x1ac6, 0x82d5, 0x1ac0, 0x82d4, 0x1ab9, 0x82d3,
+ 0x1ab3, 0x82d1, 0x1aad, 0x82d0, 0x1aa7, 0x82cf, 0x1aa1, 0x82ce,
+ 0x1a9b, 0x82cc, 0x1a95, 0x82cb, 0x1a8e, 0x82ca, 0x1a88, 0x82c8,
+ 0x1a82, 0x82c7, 0x1a7c, 0x82c6, 0x1a76, 0x82c4, 0x1a70, 0x82c3,
+ 0x1a6a, 0x82c2, 0x1a63, 0x82c1, 0x1a5d, 0x82bf, 0x1a57, 0x82be,
+ 0x1a51, 0x82bd, 0x1a4b, 0x82bb, 0x1a45, 0x82ba, 0x1a3e, 0x82b9,
+ 0x1a38, 0x82b7, 0x1a32, 0x82b6, 0x1a2c, 0x82b5, 0x1a26, 0x82b4,
+ 0x1a20, 0x82b2, 0x1a1a, 0x82b1, 0x1a13, 0x82b0, 0x1a0d, 0x82ae,
+ 0x1a07, 0x82ad, 0x1a01, 0x82ac, 0x19fb, 0x82ab, 0x19f5, 0x82a9,
+ 0x19ef, 0x82a8, 0x19e8, 0x82a7, 0x19e2, 0x82a6, 0x19dc, 0x82a4,
+ 0x19d6, 0x82a3, 0x19d0, 0x82a2, 0x19ca, 0x82a0, 0x19c3, 0x829f,
+ 0x19bd, 0x829e, 0x19b7, 0x829d, 0x19b1, 0x829b, 0x19ab, 0x829a,
+ 0x19a5, 0x8299, 0x199f, 0x8298, 0x1998, 0x8296, 0x1992, 0x8295,
+ 0x198c, 0x8294, 0x1986, 0x8293, 0x1980, 0x8291, 0x197a, 0x8290,
+ 0x1973, 0x828f, 0x196d, 0x828e, 0x1967, 0x828c, 0x1961, 0x828b,
+ 0x195b, 0x828a, 0x1955, 0x8289, 0x194e, 0x8287, 0x1948, 0x8286,
+ 0x1942, 0x8285, 0x193c, 0x8284, 0x1936, 0x8282, 0x1930, 0x8281,
+ 0x192a, 0x8280, 0x1923, 0x827f, 0x191d, 0x827e, 0x1917, 0x827c,
+ 0x1911, 0x827b, 0x190b, 0x827a, 0x1905, 0x8279, 0x18fe, 0x8277,
+ 0x18f8, 0x8276, 0x18f2, 0x8275, 0x18ec, 0x8274, 0x18e6, 0x8272,
+ 0x18e0, 0x8271, 0x18d9, 0x8270, 0x18d3, 0x826f, 0x18cd, 0x826e,
+ 0x18c7, 0x826c, 0x18c1, 0x826b, 0x18bb, 0x826a, 0x18b4, 0x8269,
+ 0x18ae, 0x8268, 0x18a8, 0x8266, 0x18a2, 0x8265, 0x189c, 0x8264,
+ 0x1896, 0x8263, 0x188f, 0x8261, 0x1889, 0x8260, 0x1883, 0x825f,
+ 0x187d, 0x825e, 0x1877, 0x825d, 0x1871, 0x825b, 0x186a, 0x825a,
+ 0x1864, 0x8259, 0x185e, 0x8258, 0x1858, 0x8257, 0x1852, 0x8255,
+ 0x184c, 0x8254, 0x1845, 0x8253, 0x183f, 0x8252, 0x1839, 0x8251,
+ 0x1833, 0x8250, 0x182d, 0x824e, 0x1827, 0x824d, 0x1820, 0x824c,
+ 0x181a, 0x824b, 0x1814, 0x824a, 0x180e, 0x8248, 0x1808, 0x8247,
+ 0x1802, 0x8246, 0x17fb, 0x8245, 0x17f5, 0x8244, 0x17ef, 0x8243,
+ 0x17e9, 0x8241, 0x17e3, 0x8240, 0x17dd, 0x823f, 0x17d6, 0x823e,
+ 0x17d0, 0x823d, 0x17ca, 0x823b, 0x17c4, 0x823a, 0x17be, 0x8239,
+ 0x17b7, 0x8238, 0x17b1, 0x8237, 0x17ab, 0x8236, 0x17a5, 0x8234,
+ 0x179f, 0x8233, 0x1799, 0x8232, 0x1792, 0x8231, 0x178c, 0x8230,
+ 0x1786, 0x822f, 0x1780, 0x822e, 0x177a, 0x822c, 0x1774, 0x822b,
+ 0x176d, 0x822a, 0x1767, 0x8229, 0x1761, 0x8228, 0x175b, 0x8227,
+ 0x1755, 0x8226, 0x174e, 0x8224, 0x1748, 0x8223, 0x1742, 0x8222,
+ 0x173c, 0x8221, 0x1736, 0x8220, 0x1730, 0x821f, 0x1729, 0x821e,
+ 0x1723, 0x821c, 0x171d, 0x821b, 0x1717, 0x821a, 0x1711, 0x8219,
+ 0x170a, 0x8218, 0x1704, 0x8217, 0x16fe, 0x8216, 0x16f8, 0x8214,
+ 0x16f2, 0x8213, 0x16ec, 0x8212, 0x16e5, 0x8211, 0x16df, 0x8210,
+ 0x16d9, 0x820f, 0x16d3, 0x820e, 0x16cd, 0x820d, 0x16c6, 0x820b,
+ 0x16c0, 0x820a, 0x16ba, 0x8209, 0x16b4, 0x8208, 0x16ae, 0x8207,
+ 0x16a8, 0x8206, 0x16a1, 0x8205, 0x169b, 0x8204, 0x1695, 0x8203,
+ 0x168f, 0x8201, 0x1689, 0x8200, 0x1682, 0x81ff, 0x167c, 0x81fe,
+ 0x1676, 0x81fd, 0x1670, 0x81fc, 0x166a, 0x81fb, 0x1664, 0x81fa,
+ 0x165d, 0x81f9, 0x1657, 0x81f8, 0x1651, 0x81f6, 0x164b, 0x81f5,
+ 0x1645, 0x81f4, 0x163e, 0x81f3, 0x1638, 0x81f2, 0x1632, 0x81f1,
+ 0x162c, 0x81f0, 0x1626, 0x81ef, 0x161f, 0x81ee, 0x1619, 0x81ed,
+ 0x1613, 0x81ec, 0x160d, 0x81ea, 0x1607, 0x81e9, 0x1601, 0x81e8,
+ 0x15fa, 0x81e7, 0x15f4, 0x81e6, 0x15ee, 0x81e5, 0x15e8, 0x81e4,
+ 0x15e2, 0x81e3, 0x15db, 0x81e2, 0x15d5, 0x81e1, 0x15cf, 0x81e0,
+ 0x15c9, 0x81df, 0x15c3, 0x81de, 0x15bc, 0x81dc, 0x15b6, 0x81db,
+ 0x15b0, 0x81da, 0x15aa, 0x81d9, 0x15a4, 0x81d8, 0x159d, 0x81d7,
+ 0x1597, 0x81d6, 0x1591, 0x81d5, 0x158b, 0x81d4, 0x1585, 0x81d3,
+ 0x157f, 0x81d2, 0x1578, 0x81d1, 0x1572, 0x81d0, 0x156c, 0x81cf,
+ 0x1566, 0x81ce, 0x1560, 0x81cd, 0x1559, 0x81cc, 0x1553, 0x81cb,
+ 0x154d, 0x81c9, 0x1547, 0x81c8, 0x1541, 0x81c7, 0x153a, 0x81c6,
+ 0x1534, 0x81c5, 0x152e, 0x81c4, 0x1528, 0x81c3, 0x1522, 0x81c2,
+ 0x151b, 0x81c1, 0x1515, 0x81c0, 0x150f, 0x81bf, 0x1509, 0x81be,
+ 0x1503, 0x81bd, 0x14fc, 0x81bc, 0x14f6, 0x81bb, 0x14f0, 0x81ba,
+ 0x14ea, 0x81b9, 0x14e4, 0x81b8, 0x14dd, 0x81b7, 0x14d7, 0x81b6,
+ 0x14d1, 0x81b5, 0x14cb, 0x81b4, 0x14c5, 0x81b3, 0x14be, 0x81b2,
+ 0x14b8, 0x81b1, 0x14b2, 0x81b0, 0x14ac, 0x81af, 0x14a6, 0x81ae,
+ 0x149f, 0x81ad, 0x1499, 0x81ac, 0x1493, 0x81ab, 0x148d, 0x81aa,
+ 0x1487, 0x81a9, 0x1480, 0x81a8, 0x147a, 0x81a7, 0x1474, 0x81a6,
+ 0x146e, 0x81a5, 0x1468, 0x81a4, 0x1461, 0x81a3, 0x145b, 0x81a2,
+ 0x1455, 0x81a1, 0x144f, 0x81a0, 0x1449, 0x819f, 0x1442, 0x819e,
+ 0x143c, 0x819d, 0x1436, 0x819c, 0x1430, 0x819b, 0x142a, 0x819a,
+ 0x1423, 0x8199, 0x141d, 0x8198, 0x1417, 0x8197, 0x1411, 0x8196,
+ 0x140b, 0x8195, 0x1404, 0x8194, 0x13fe, 0x8193, 0x13f8, 0x8192,
+ 0x13f2, 0x8191, 0x13eb, 0x8190, 0x13e5, 0x818f, 0x13df, 0x818e,
+ 0x13d9, 0x818d, 0x13d3, 0x818c, 0x13cc, 0x818b, 0x13c6, 0x818a,
+ 0x13c0, 0x8189, 0x13ba, 0x8188, 0x13b4, 0x8187, 0x13ad, 0x8186,
+ 0x13a7, 0x8185, 0x13a1, 0x8184, 0x139b, 0x8183, 0x1395, 0x8182,
+ 0x138e, 0x8181, 0x1388, 0x8180, 0x1382, 0x817f, 0x137c, 0x817e,
+ 0x1376, 0x817d, 0x136f, 0x817c, 0x1369, 0x817c, 0x1363, 0x817b,
+ 0x135d, 0x817a, 0x1356, 0x8179, 0x1350, 0x8178, 0x134a, 0x8177,
+ 0x1344, 0x8176, 0x133e, 0x8175, 0x1337, 0x8174, 0x1331, 0x8173,
+ 0x132b, 0x8172, 0x1325, 0x8171, 0x131f, 0x8170, 0x1318, 0x816f,
+ 0x1312, 0x816e, 0x130c, 0x816d, 0x1306, 0x816c, 0x12ff, 0x816c,
+ 0x12f9, 0x816b, 0x12f3, 0x816a, 0x12ed, 0x8169, 0x12e7, 0x8168,
+ 0x12e0, 0x8167, 0x12da, 0x8166, 0x12d4, 0x8165, 0x12ce, 0x8164,
+ 0x12c8, 0x8163, 0x12c1, 0x8162, 0x12bb, 0x8161, 0x12b5, 0x8160,
+ 0x12af, 0x815f, 0x12a8, 0x815f, 0x12a2, 0x815e, 0x129c, 0x815d,
+ 0x1296, 0x815c, 0x1290, 0x815b, 0x1289, 0x815a, 0x1283, 0x8159,
+ 0x127d, 0x8158, 0x1277, 0x8157, 0x1271, 0x8156, 0x126a, 0x8155,
+ 0x1264, 0x8155, 0x125e, 0x8154, 0x1258, 0x8153, 0x1251, 0x8152,
+ 0x124b, 0x8151, 0x1245, 0x8150, 0x123f, 0x814f, 0x1239, 0x814e,
+ 0x1232, 0x814d, 0x122c, 0x814c, 0x1226, 0x814c, 0x1220, 0x814b,
+ 0x1219, 0x814a, 0x1213, 0x8149, 0x120d, 0x8148, 0x1207, 0x8147,
+ 0x1201, 0x8146, 0x11fa, 0x8145, 0x11f4, 0x8145, 0x11ee, 0x8144,
+ 0x11e8, 0x8143, 0x11e1, 0x8142, 0x11db, 0x8141, 0x11d5, 0x8140,
+ 0x11cf, 0x813f, 0x11c9, 0x813e, 0x11c2, 0x813d, 0x11bc, 0x813d,
+ 0x11b6, 0x813c, 0x11b0, 0x813b, 0x11a9, 0x813a, 0x11a3, 0x8139,
+ 0x119d, 0x8138, 0x1197, 0x8137, 0x1191, 0x8137, 0x118a, 0x8136,
+ 0x1184, 0x8135, 0x117e, 0x8134, 0x1178, 0x8133, 0x1171, 0x8132,
+ 0x116b, 0x8131, 0x1165, 0x8131, 0x115f, 0x8130, 0x1159, 0x812f,
+ 0x1152, 0x812e, 0x114c, 0x812d, 0x1146, 0x812c, 0x1140, 0x812b,
+ 0x1139, 0x812b, 0x1133, 0x812a, 0x112d, 0x8129, 0x1127, 0x8128,
+ 0x1121, 0x8127, 0x111a, 0x8126, 0x1114, 0x8126, 0x110e, 0x8125,
+ 0x1108, 0x8124, 0x1101, 0x8123, 0x10fb, 0x8122, 0x10f5, 0x8121,
+ 0x10ef, 0x8121, 0x10e8, 0x8120, 0x10e2, 0x811f, 0x10dc, 0x811e,
+ 0x10d6, 0x811d, 0x10d0, 0x811c, 0x10c9, 0x811c, 0x10c3, 0x811b,
+ 0x10bd, 0x811a, 0x10b7, 0x8119, 0x10b0, 0x8118, 0x10aa, 0x8117,
+ 0x10a4, 0x8117, 0x109e, 0x8116, 0x1098, 0x8115, 0x1091, 0x8114,
+ 0x108b, 0x8113, 0x1085, 0x8113, 0x107f, 0x8112, 0x1078, 0x8111,
+ 0x1072, 0x8110, 0x106c, 0x810f, 0x1066, 0x810f, 0x105f, 0x810e,
+ 0x1059, 0x810d, 0x1053, 0x810c, 0x104d, 0x810b, 0x1047, 0x810b,
+ 0x1040, 0x810a, 0x103a, 0x8109, 0x1034, 0x8108, 0x102e, 0x8107,
+ 0x1027, 0x8107, 0x1021, 0x8106, 0x101b, 0x8105, 0x1015, 0x8104,
+ 0x100e, 0x8103, 0x1008, 0x8103, 0x1002, 0x8102, 0xffc, 0x8101,
+ 0xff5, 0x8100, 0xfef, 0x80ff, 0xfe9, 0x80ff, 0xfe3, 0x80fe,
+ 0xfdd, 0x80fd, 0xfd6, 0x80fc, 0xfd0, 0x80fc, 0xfca, 0x80fb,
+ 0xfc4, 0x80fa, 0xfbd, 0x80f9, 0xfb7, 0x80f8, 0xfb1, 0x80f8,
+ 0xfab, 0x80f7, 0xfa4, 0x80f6, 0xf9e, 0x80f5, 0xf98, 0x80f5,
+ 0xf92, 0x80f4, 0xf8b, 0x80f3, 0xf85, 0x80f2, 0xf7f, 0x80f2,
+ 0xf79, 0x80f1, 0xf73, 0x80f0, 0xf6c, 0x80ef, 0xf66, 0x80ef,
+ 0xf60, 0x80ee, 0xf5a, 0x80ed, 0xf53, 0x80ec, 0xf4d, 0x80ec,
+ 0xf47, 0x80eb, 0xf41, 0x80ea, 0xf3a, 0x80e9, 0xf34, 0x80e9,
+ 0xf2e, 0x80e8, 0xf28, 0x80e7, 0xf21, 0x80e6, 0xf1b, 0x80e6,
+ 0xf15, 0x80e5, 0xf0f, 0x80e4, 0xf08, 0x80e3, 0xf02, 0x80e3,
+ 0xefc, 0x80e2, 0xef6, 0x80e1, 0xef0, 0x80e0, 0xee9, 0x80e0,
+ 0xee3, 0x80df, 0xedd, 0x80de, 0xed7, 0x80dd, 0xed0, 0x80dd,
+ 0xeca, 0x80dc, 0xec4, 0x80db, 0xebe, 0x80db, 0xeb7, 0x80da,
+ 0xeb1, 0x80d9, 0xeab, 0x80d8, 0xea5, 0x80d8, 0xe9e, 0x80d7,
+ 0xe98, 0x80d6, 0xe92, 0x80d6, 0xe8c, 0x80d5, 0xe85, 0x80d4,
+ 0xe7f, 0x80d3, 0xe79, 0x80d3, 0xe73, 0x80d2, 0xe6c, 0x80d1,
+ 0xe66, 0x80d1, 0xe60, 0x80d0, 0xe5a, 0x80cf, 0xe53, 0x80ce,
+ 0xe4d, 0x80ce, 0xe47, 0x80cd, 0xe41, 0x80cc, 0xe3a, 0x80cc,
+ 0xe34, 0x80cb, 0xe2e, 0x80ca, 0xe28, 0x80ca, 0xe22, 0x80c9,
+ 0xe1b, 0x80c8, 0xe15, 0x80c7, 0xe0f, 0x80c7, 0xe09, 0x80c6,
+ 0xe02, 0x80c5, 0xdfc, 0x80c5, 0xdf6, 0x80c4, 0xdf0, 0x80c3,
+ 0xde9, 0x80c3, 0xde3, 0x80c2, 0xddd, 0x80c1, 0xdd7, 0x80c1,
+ 0xdd0, 0x80c0, 0xdca, 0x80bf, 0xdc4, 0x80bf, 0xdbe, 0x80be,
+ 0xdb7, 0x80bd, 0xdb1, 0x80bd, 0xdab, 0x80bc, 0xda5, 0x80bb,
+ 0xd9e, 0x80bb, 0xd98, 0x80ba, 0xd92, 0x80b9, 0xd8c, 0x80b9,
+ 0xd85, 0x80b8, 0xd7f, 0x80b7, 0xd79, 0x80b7, 0xd73, 0x80b6,
+ 0xd6c, 0x80b5, 0xd66, 0x80b5, 0xd60, 0x80b4, 0xd5a, 0x80b3,
+ 0xd53, 0x80b3, 0xd4d, 0x80b2, 0xd47, 0x80b1, 0xd41, 0x80b1,
+ 0xd3a, 0x80b0, 0xd34, 0x80af, 0xd2e, 0x80af, 0xd28, 0x80ae,
+ 0xd21, 0x80ad, 0xd1b, 0x80ad, 0xd15, 0x80ac, 0xd0f, 0x80ab,
+ 0xd08, 0x80ab, 0xd02, 0x80aa, 0xcfc, 0x80aa, 0xcf6, 0x80a9,
+ 0xcef, 0x80a8, 0xce9, 0x80a8, 0xce3, 0x80a7, 0xcdd, 0x80a6,
+ 0xcd6, 0x80a6, 0xcd0, 0x80a5, 0xcca, 0x80a5, 0xcc4, 0x80a4,
+ 0xcbd, 0x80a3, 0xcb7, 0x80a3, 0xcb1, 0x80a2, 0xcab, 0x80a1,
+ 0xca4, 0x80a1, 0xc9e, 0x80a0, 0xc98, 0x80a0, 0xc92, 0x809f,
+ 0xc8b, 0x809e, 0xc85, 0x809e, 0xc7f, 0x809d, 0xc79, 0x809c,
+ 0xc72, 0x809c, 0xc6c, 0x809b, 0xc66, 0x809b, 0xc60, 0x809a,
+ 0xc59, 0x8099, 0xc53, 0x8099, 0xc4d, 0x8098, 0xc47, 0x8098,
+ 0xc40, 0x8097, 0xc3a, 0x8096, 0xc34, 0x8096, 0xc2e, 0x8095,
+ 0xc27, 0x8095, 0xc21, 0x8094, 0xc1b, 0x8093, 0xc14, 0x8093,
+ 0xc0e, 0x8092, 0xc08, 0x8092, 0xc02, 0x8091, 0xbfb, 0x8090,
+ 0xbf5, 0x8090, 0xbef, 0x808f, 0xbe9, 0x808f, 0xbe2, 0x808e,
+ 0xbdc, 0x808e, 0xbd6, 0x808d, 0xbd0, 0x808c, 0xbc9, 0x808c,
+ 0xbc3, 0x808b, 0xbbd, 0x808b, 0xbb7, 0x808a, 0xbb0, 0x8089,
+ 0xbaa, 0x8089, 0xba4, 0x8088, 0xb9e, 0x8088, 0xb97, 0x8087,
+ 0xb91, 0x8087, 0xb8b, 0x8086, 0xb85, 0x8085, 0xb7e, 0x8085,
+ 0xb78, 0x8084, 0xb72, 0x8084, 0xb6c, 0x8083, 0xb65, 0x8083,
+ 0xb5f, 0x8082, 0xb59, 0x8082, 0xb53, 0x8081, 0xb4c, 0x8080,
+ 0xb46, 0x8080, 0xb40, 0x807f, 0xb3a, 0x807f, 0xb33, 0x807e,
+ 0xb2d, 0x807e, 0xb27, 0x807d, 0xb20, 0x807d, 0xb1a, 0x807c,
+ 0xb14, 0x807b, 0xb0e, 0x807b, 0xb07, 0x807a, 0xb01, 0x807a,
+ 0xafb, 0x8079, 0xaf5, 0x8079, 0xaee, 0x8078, 0xae8, 0x8078,
+ 0xae2, 0x8077, 0xadc, 0x8077, 0xad5, 0x8076, 0xacf, 0x8076,
+ 0xac9, 0x8075, 0xac3, 0x8075, 0xabc, 0x8074, 0xab6, 0x8073,
+ 0xab0, 0x8073, 0xaaa, 0x8072, 0xaa3, 0x8072, 0xa9d, 0x8071,
+ 0xa97, 0x8071, 0xa90, 0x8070, 0xa8a, 0x8070, 0xa84, 0x806f,
+ 0xa7e, 0x806f, 0xa77, 0x806e, 0xa71, 0x806e, 0xa6b, 0x806d,
+ 0xa65, 0x806d, 0xa5e, 0x806c, 0xa58, 0x806c, 0xa52, 0x806b,
+ 0xa4c, 0x806b, 0xa45, 0x806a, 0xa3f, 0x806a, 0xa39, 0x8069,
+ 0xa33, 0x8069, 0xa2c, 0x8068, 0xa26, 0x8068, 0xa20, 0x8067,
+ 0xa19, 0x8067, 0xa13, 0x8066, 0xa0d, 0x8066, 0xa07, 0x8065,
+ 0xa00, 0x8065, 0x9fa, 0x8064, 0x9f4, 0x8064, 0x9ee, 0x8063,
+ 0x9e7, 0x8063, 0x9e1, 0x8062, 0x9db, 0x8062, 0x9d5, 0x8061,
+ 0x9ce, 0x8061, 0x9c8, 0x8060, 0x9c2, 0x8060, 0x9bc, 0x805f,
+ 0x9b5, 0x805f, 0x9af, 0x805e, 0x9a9, 0x805e, 0x9a2, 0x805d,
+ 0x99c, 0x805d, 0x996, 0x805d, 0x990, 0x805c, 0x989, 0x805c,
+ 0x983, 0x805b, 0x97d, 0x805b, 0x977, 0x805a, 0x970, 0x805a,
+ 0x96a, 0x8059, 0x964, 0x8059, 0x95e, 0x8058, 0x957, 0x8058,
+ 0x951, 0x8057, 0x94b, 0x8057, 0x944, 0x8057, 0x93e, 0x8056,
+ 0x938, 0x8056, 0x932, 0x8055, 0x92b, 0x8055, 0x925, 0x8054,
+ 0x91f, 0x8054, 0x919, 0x8053, 0x912, 0x8053, 0x90c, 0x8052,
+ 0x906, 0x8052, 0x900, 0x8052, 0x8f9, 0x8051, 0x8f3, 0x8051,
+ 0x8ed, 0x8050, 0x8e6, 0x8050, 0x8e0, 0x804f, 0x8da, 0x804f,
+ 0x8d4, 0x804f, 0x8cd, 0x804e, 0x8c7, 0x804e, 0x8c1, 0x804d,
+ 0x8bb, 0x804d, 0x8b4, 0x804c, 0x8ae, 0x804c, 0x8a8, 0x804c,
+ 0x8a2, 0x804b, 0x89b, 0x804b, 0x895, 0x804a, 0x88f, 0x804a,
+ 0x888, 0x8049, 0x882, 0x8049, 0x87c, 0x8049, 0x876, 0x8048,
+ 0x86f, 0x8048, 0x869, 0x8047, 0x863, 0x8047, 0x85d, 0x8047,
+ 0x856, 0x8046, 0x850, 0x8046, 0x84a, 0x8045, 0x843, 0x8045,
+ 0x83d, 0x8044, 0x837, 0x8044, 0x831, 0x8044, 0x82a, 0x8043,
+ 0x824, 0x8043, 0x81e, 0x8042, 0x818, 0x8042, 0x811, 0x8042,
+ 0x80b, 0x8041, 0x805, 0x8041, 0x7fe, 0x8040, 0x7f8, 0x8040,
+ 0x7f2, 0x8040, 0x7ec, 0x803f, 0x7e5, 0x803f, 0x7df, 0x803f,
+ 0x7d9, 0x803e, 0x7d3, 0x803e, 0x7cc, 0x803d, 0x7c6, 0x803d,
+ 0x7c0, 0x803d, 0x7ba, 0x803c, 0x7b3, 0x803c, 0x7ad, 0x803b,
+ 0x7a7, 0x803b, 0x7a0, 0x803b, 0x79a, 0x803a, 0x794, 0x803a,
+ 0x78e, 0x803a, 0x787, 0x8039, 0x781, 0x8039, 0x77b, 0x8039,
+ 0x775, 0x8038, 0x76e, 0x8038, 0x768, 0x8037, 0x762, 0x8037,
+ 0x75b, 0x8037, 0x755, 0x8036, 0x74f, 0x8036, 0x749, 0x8036,
+ 0x742, 0x8035, 0x73c, 0x8035, 0x736, 0x8035, 0x730, 0x8034,
+ 0x729, 0x8034, 0x723, 0x8033, 0x71d, 0x8033, 0x716, 0x8033,
+ 0x710, 0x8032, 0x70a, 0x8032, 0x704, 0x8032, 0x6fd, 0x8031,
+ 0x6f7, 0x8031, 0x6f1, 0x8031, 0x6ea, 0x8030, 0x6e4, 0x8030,
+ 0x6de, 0x8030, 0x6d8, 0x802f, 0x6d1, 0x802f, 0x6cb, 0x802f,
+ 0x6c5, 0x802e, 0x6bf, 0x802e, 0x6b8, 0x802e, 0x6b2, 0x802d,
+ 0x6ac, 0x802d, 0x6a5, 0x802d, 0x69f, 0x802c, 0x699, 0x802c,
+ 0x693, 0x802c, 0x68c, 0x802b, 0x686, 0x802b, 0x680, 0x802b,
+ 0x67a, 0x802a, 0x673, 0x802a, 0x66d, 0x802a, 0x667, 0x802a,
+ 0x660, 0x8029, 0x65a, 0x8029, 0x654, 0x8029, 0x64e, 0x8028,
+ 0x647, 0x8028, 0x641, 0x8028, 0x63b, 0x8027, 0x635, 0x8027,
+ 0x62e, 0x8027, 0x628, 0x8026, 0x622, 0x8026, 0x61b, 0x8026,
+ 0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,
+ 0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,
+ 0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,
+ 0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,
+ 0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,
+ 0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,
+ 0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,
+ 0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,
+ 0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,
+ 0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,
+ 0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,
+ 0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,
+ 0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,
+ 0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,
+ 0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,
+ 0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,
+ 0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,
+ 0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,
+ 0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,
+ 0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,
+ 0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,
+ 0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,
+ 0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,
+ 0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,
+ 0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,
+ 0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,
+ 0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,
+ 0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,
+ 0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,
+ 0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,
+ 0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,
+ 0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,
+ 0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,
+ 0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,
+ 0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,
+ 0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,
+ 0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,
+ 0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,
+ 0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,
+ 0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,
+ 0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,
+ 0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,
+ 0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,
+ 0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,
+ 0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,
+ 0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,
+ 0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,
+ 0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,
+ 0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,
+ 0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,
+ 0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,
+ 0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,
+ 0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,
+ 0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,
+ 0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,
+ 0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,
+ 0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,
+ 0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,
+ 0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,
+ 0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,
+ 0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,
+ 0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,
+};
+
+
+/**
+* \par
+* cosFactor tables are generated using the formula : cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+* \par
+* C command to generate the table
+*
+* for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* }
+* \par
+* where N is the number of factors to generate and c is pi/(2*N)
+* \par
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.
+
+*/
+
+static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
+ 0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+ 0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+ 0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+ 0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+ 0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+ 0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+ 0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+ 0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+ 0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+ 0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+ 0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+ 0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+ 0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+ 0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+ 0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+ 0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+ 0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+ 0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+ 0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+ 0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+ 0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+ 0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+ 0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+ 0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+ 0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+ 0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+ 0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+ 0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+ 0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+ 0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+ 0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+ 0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+ 0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+ 0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+ 0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+ 0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+ 0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+ 0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+ 0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+ 0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+ 0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+ 0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+ 0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+ 0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+ 0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+ 0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+ 0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+ 0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+ 0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+ 0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+ 0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+ 0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+ 0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+ 0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+ 0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+ 0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+ 0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+ 0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+ 0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+ 0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+ 0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+ 0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+ 0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+ 0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+ 0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+ 0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+ 0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+ 0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+ 0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+ 0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+ 0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+ 0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+ 0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+ 0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+ 0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+ 0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+ 0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+ 0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+ 0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+ 0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+ 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+ 0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+ 0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+ 0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+ 0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+ 0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+ 0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+ 0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+ 0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+ 0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+ 0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+ 0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+ 0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+ 0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+ 0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+ 0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+ 0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+ 0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+ 0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+ 0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
+ 0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
+ 0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
+ 0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
+ 0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
+ 0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
+ 0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
+ 0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
+ 0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
+ 0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
+ 0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,
+ 0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,
+ 0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,
+ 0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,
+ 0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,
+ 0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,
+ 0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,
+ 0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,
+ 0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,
+ 0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,
+ 0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,
+ 0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,
+ 0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,
+ 0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,
+ 0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,
+ 0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,
+ 0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,
+ 0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,
+ 0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,
+ 0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,
+ 0x7986, 0x797e, 0x7976, 0x796e, 0x7966, 0x795e, 0x7956, 0x794e,
+ 0x7946, 0x793e, 0x7936, 0x792e, 0x7926, 0x791e, 0x7915, 0x790d,
+ 0x7905, 0x78fd, 0x78f5, 0x78ec, 0x78e4, 0x78dc, 0x78d4, 0x78cb,
+ 0x78c3, 0x78bb, 0x78b2, 0x78aa, 0x78a2, 0x7899, 0x7891, 0x7888,
+ 0x7880, 0x7877, 0x786f, 0x7866, 0x785e, 0x7855, 0x784d, 0x7844,
+ 0x783b, 0x7833, 0x782a, 0x7821, 0x7819, 0x7810, 0x7807, 0x77ff,
+ 0x77f6, 0x77ed, 0x77e4, 0x77db, 0x77d3, 0x77ca, 0x77c1, 0x77b8,
+ 0x77af, 0x77a6, 0x779d, 0x7794, 0x778b, 0x7782, 0x7779, 0x7770,
+ 0x7767, 0x775e, 0x7755, 0x774c, 0x7743, 0x773a, 0x7731, 0x7727,
+ 0x771e, 0x7715, 0x770c, 0x7703, 0x76f9, 0x76f0, 0x76e7, 0x76dd,
+ 0x76d4, 0x76cb, 0x76c1, 0x76b8, 0x76af, 0x76a5, 0x769c, 0x7692,
+ 0x7689, 0x767f, 0x7676, 0x766c, 0x7663, 0x7659, 0x7650, 0x7646,
+ 0x763c, 0x7633, 0x7629, 0x761f, 0x7616, 0x760c, 0x7602, 0x75f9,
+ 0x75ef, 0x75e5, 0x75db, 0x75d1, 0x75c8, 0x75be, 0x75b4, 0x75aa,
+ 0x75a0, 0x7596, 0x758c, 0x7582, 0x7578, 0x756e, 0x7564, 0x755a,
+ 0x7550, 0x7546, 0x753c, 0x7532, 0x7528, 0x751e, 0x7514, 0x7509,
+ 0x74ff, 0x74f5, 0x74eb, 0x74e1, 0x74d6, 0x74cc, 0x74c2, 0x74b7,
+ 0x74ad, 0x74a3, 0x7498, 0x748e, 0x7484, 0x7479, 0x746f, 0x7464,
+ 0x745a, 0x744f, 0x7445, 0x743a, 0x7430, 0x7425, 0x741b, 0x7410,
+ 0x7406, 0x73fb, 0x73f0, 0x73e6, 0x73db, 0x73d0, 0x73c6, 0x73bb,
+ 0x73b0, 0x73a5, 0x739b, 0x7390, 0x7385, 0x737a, 0x736f, 0x7364,
+ 0x7359, 0x734f, 0x7344, 0x7339, 0x732e, 0x7323, 0x7318, 0x730d,
+ 0x7302, 0x72f7, 0x72ec, 0x72e1, 0x72d5, 0x72ca, 0x72bf, 0x72b4,
+ 0x72a9, 0x729e, 0x7293, 0x7287, 0x727c, 0x7271, 0x7266, 0x725a,
+ 0x724f, 0x7244, 0x7238, 0x722d, 0x7222, 0x7216, 0x720b, 0x71ff,
+ 0x71f4, 0x71e9, 0x71dd, 0x71d2, 0x71c6, 0x71bb, 0x71af, 0x71a3,
+ 0x7198, 0x718c, 0x7181, 0x7175, 0x7169, 0x715e, 0x7152, 0x7146,
+ 0x713b, 0x712f, 0x7123, 0x7117, 0x710c, 0x7100, 0x70f4, 0x70e8,
+ 0x70dc, 0x70d1, 0x70c5, 0x70b9, 0x70ad, 0x70a1, 0x7095, 0x7089,
+ 0x707d, 0x7071, 0x7065, 0x7059, 0x704d, 0x7041, 0x7035, 0x7029,
+ 0x701d, 0x7010, 0x7004, 0x6ff8, 0x6fec, 0x6fe0, 0x6fd3, 0x6fc7,
+ 0x6fbb, 0x6faf, 0x6fa2, 0x6f96, 0x6f8a, 0x6f7d, 0x6f71, 0x6f65,
+ 0x6f58, 0x6f4c, 0x6f3f, 0x6f33, 0x6f27, 0x6f1a, 0x6f0e, 0x6f01,
+ 0x6ef5, 0x6ee8, 0x6edc, 0x6ecf, 0x6ec2, 0x6eb6, 0x6ea9, 0x6e9c,
+ 0x6e90, 0x6e83, 0x6e76, 0x6e6a, 0x6e5d, 0x6e50, 0x6e44, 0x6e37,
+ 0x6e2a, 0x6e1d, 0x6e10, 0x6e04, 0x6df7, 0x6dea, 0x6ddd, 0x6dd0,
+ 0x6dc3, 0x6db6, 0x6da9, 0x6d9c, 0x6d8f, 0x6d82, 0x6d75, 0x6d68,
+ 0x6d5b, 0x6d4e, 0x6d41, 0x6d34, 0x6d27, 0x6d1a, 0x6d0c, 0x6cff,
+ 0x6cf2, 0x6ce5, 0x6cd8, 0x6cca, 0x6cbd, 0x6cb0, 0x6ca3, 0x6c95,
+ 0x6c88, 0x6c7b, 0x6c6d, 0x6c60, 0x6c53, 0x6c45, 0x6c38, 0x6c2a,
+ 0x6c1d, 0x6c0f, 0x6c02, 0x6bf5, 0x6be7, 0x6bd9, 0x6bcc, 0x6bbe,
+ 0x6bb1, 0x6ba3, 0x6b96, 0x6b88, 0x6b7a, 0x6b6d, 0x6b5f, 0x6b51,
+ 0x6b44, 0x6b36, 0x6b28, 0x6b1a, 0x6b0d, 0x6aff, 0x6af1, 0x6ae3,
+ 0x6ad5, 0x6ac8, 0x6aba, 0x6aac, 0x6a9e, 0x6a90, 0x6a82, 0x6a74,
+ 0x6a66, 0x6a58, 0x6a4a, 0x6a3c, 0x6a2e, 0x6a20, 0x6a12, 0x6a04,
+ 0x69f6, 0x69e8, 0x69da, 0x69cb, 0x69bd, 0x69af, 0x69a1, 0x6993,
+ 0x6985, 0x6976, 0x6968, 0x695a, 0x694b, 0x693d, 0x692f, 0x6921,
+ 0x6912, 0x6904, 0x68f5, 0x68e7, 0x68d9, 0x68ca, 0x68bc, 0x68ad,
+ 0x689f, 0x6890, 0x6882, 0x6873, 0x6865, 0x6856, 0x6848, 0x6839,
+ 0x682b, 0x681c, 0x680d, 0x67ff, 0x67f0, 0x67e1, 0x67d3, 0x67c4,
+ 0x67b5, 0x67a6, 0x6798, 0x6789, 0x677a, 0x676b, 0x675d, 0x674e,
+ 0x673f, 0x6730, 0x6721, 0x6712, 0x6703, 0x66f4, 0x66e5, 0x66d6,
+ 0x66c8, 0x66b9, 0x66aa, 0x669b, 0x668b, 0x667c, 0x666d, 0x665e,
+ 0x664f, 0x6640, 0x6631, 0x6622, 0x6613, 0x6603, 0x65f4, 0x65e5,
+ 0x65d6, 0x65c7, 0x65b7, 0x65a8, 0x6599, 0x658a, 0x657a, 0x656b,
+ 0x655c, 0x654c, 0x653d, 0x652d, 0x651e, 0x650f, 0x64ff, 0x64f0,
+ 0x64e0, 0x64d1, 0x64c1, 0x64b2, 0x64a2, 0x6493, 0x6483, 0x6474,
+ 0x6464, 0x6454, 0x6445, 0x6435, 0x6426, 0x6416, 0x6406, 0x63f7,
+ 0x63e7, 0x63d7, 0x63c7, 0x63b8, 0x63a8, 0x6398, 0x6388, 0x6378,
+ 0x6369, 0x6359, 0x6349, 0x6339, 0x6329, 0x6319, 0x6309, 0x62f9,
+ 0x62ea, 0x62da, 0x62ca, 0x62ba, 0x62aa, 0x629a, 0x628a, 0x627a,
+ 0x6269, 0x6259, 0x6249, 0x6239, 0x6229, 0x6219, 0x6209, 0x61f9,
+ 0x61e8, 0x61d8, 0x61c8, 0x61b8, 0x61a8, 0x6197, 0x6187, 0x6177,
+ 0x6166, 0x6156, 0x6146, 0x6135, 0x6125, 0x6115, 0x6104, 0x60f4,
+ 0x60e4, 0x60d3, 0x60c3, 0x60b2, 0x60a2, 0x6091, 0x6081, 0x6070,
+ 0x6060, 0x604f, 0x603f, 0x602e, 0x601d, 0x600d, 0x5ffc, 0x5fec,
+ 0x5fdb, 0x5fca, 0x5fba, 0x5fa9, 0x5f98, 0x5f87, 0x5f77, 0x5f66,
+ 0x5f55, 0x5f44, 0x5f34, 0x5f23, 0x5f12, 0x5f01, 0x5ef0, 0x5edf,
+ 0x5ecf, 0x5ebe, 0x5ead, 0x5e9c, 0x5e8b, 0x5e7a, 0x5e69, 0x5e58,
+ 0x5e47, 0x5e36, 0x5e25, 0x5e14, 0x5e03, 0x5df2, 0x5de1, 0x5dd0,
+ 0x5dbf, 0x5dad, 0x5d9c, 0x5d8b, 0x5d7a, 0x5d69, 0x5d58, 0x5d46,
+ 0x5d35, 0x5d24, 0x5d13, 0x5d01, 0x5cf0, 0x5cdf, 0x5cce, 0x5cbc,
+ 0x5cab, 0x5c9a, 0x5c88, 0x5c77, 0x5c66, 0x5c54, 0x5c43, 0x5c31,
+ 0x5c20, 0x5c0e, 0x5bfd, 0x5beb, 0x5bda, 0x5bc8, 0x5bb7, 0x5ba5,
+ 0x5b94, 0x5b82, 0x5b71, 0x5b5f, 0x5b4d, 0x5b3c, 0x5b2a, 0x5b19,
+ 0x5b07, 0x5af5, 0x5ae4, 0x5ad2, 0x5ac0, 0x5aae, 0x5a9d, 0x5a8b,
+ 0x5a79, 0x5a67, 0x5a56, 0x5a44, 0x5a32, 0x5a20, 0x5a0e, 0x59fc,
+ 0x59ea, 0x59d9, 0x59c7, 0x59b5, 0x59a3, 0x5991, 0x597f, 0x596d,
+ 0x595b, 0x5949, 0x5937, 0x5925, 0x5913, 0x5901, 0x58ef, 0x58dd,
+ 0x58cb, 0x58b8, 0x58a6, 0x5894, 0x5882, 0x5870, 0x585e, 0x584b,
+ 0x5839, 0x5827, 0x5815, 0x5803, 0x57f0, 0x57de, 0x57cc, 0x57b9,
+ 0x57a7, 0x5795, 0x5783, 0x5770, 0x575e, 0x574b, 0x5739, 0x5727,
+ 0x5714, 0x5702, 0x56ef, 0x56dd, 0x56ca, 0x56b8, 0x56a5, 0x5693,
+ 0x5680, 0x566e, 0x565b, 0x5649, 0x5636, 0x5624, 0x5611, 0x55fe,
+ 0x55ec, 0x55d9, 0x55c7, 0x55b4, 0x55a1, 0x558f, 0x557c, 0x5569,
+ 0x5556, 0x5544, 0x5531, 0x551e, 0x550b, 0x54f9, 0x54e6, 0x54d3,
+ 0x54c0, 0x54ad, 0x549a, 0x5488, 0x5475, 0x5462, 0x544f, 0x543c,
+ 0x5429, 0x5416, 0x5403, 0x53f0, 0x53dd, 0x53ca, 0x53b7, 0x53a4,
+ 0x5391, 0x537e, 0x536b, 0x5358, 0x5345, 0x5332, 0x531f, 0x530c,
+ 0x52f8, 0x52e5, 0x52d2, 0x52bf, 0x52ac, 0x5299, 0x5285, 0x5272,
+ 0x525f, 0x524c, 0x5238, 0x5225, 0x5212, 0x51ff, 0x51eb, 0x51d8,
+ 0x51c5, 0x51b1, 0x519e, 0x518b, 0x5177, 0x5164, 0x5150, 0x513d,
+ 0x512a, 0x5116, 0x5103, 0x50ef, 0x50dc, 0x50c8, 0x50b5, 0x50a1,
+ 0x508e, 0x507a, 0x5067, 0x5053, 0x503f, 0x502c, 0x5018, 0x5005,
+ 0x4ff1, 0x4fdd, 0x4fca, 0x4fb6, 0x4fa2, 0x4f8f, 0x4f7b, 0x4f67,
+ 0x4f54, 0x4f40, 0x4f2c, 0x4f18, 0x4f05, 0x4ef1, 0x4edd, 0x4ec9,
+ 0x4eb6, 0x4ea2, 0x4e8e, 0x4e7a, 0x4e66, 0x4e52, 0x4e3e, 0x4e2a,
+ 0x4e17, 0x4e03, 0x4def, 0x4ddb, 0x4dc7, 0x4db3, 0x4d9f, 0x4d8b,
+ 0x4d77, 0x4d63, 0x4d4f, 0x4d3b, 0x4d27, 0x4d13, 0x4cff, 0x4ceb,
+ 0x4cd6, 0x4cc2, 0x4cae, 0x4c9a, 0x4c86, 0x4c72, 0x4c5e, 0x4c49,
+ 0x4c35, 0x4c21, 0x4c0d, 0x4bf9, 0x4be4, 0x4bd0, 0x4bbc, 0x4ba8,
+ 0x4b93, 0x4b7f, 0x4b6b, 0x4b56, 0x4b42, 0x4b2e, 0x4b19, 0x4b05,
+ 0x4af1, 0x4adc, 0x4ac8, 0x4ab4, 0x4a9f, 0x4a8b, 0x4a76, 0x4a62,
+ 0x4a4d, 0x4a39, 0x4a24, 0x4a10, 0x49fb, 0x49e7, 0x49d2, 0x49be,
+ 0x49a9, 0x4995, 0x4980, 0x496c, 0x4957, 0x4942, 0x492e, 0x4919,
+ 0x4905, 0x48f0, 0x48db, 0x48c7, 0x48b2, 0x489d, 0x4888, 0x4874,
+ 0x485f, 0x484a, 0x4836, 0x4821, 0x480c, 0x47f7, 0x47e2, 0x47ce,
+ 0x47b9, 0x47a4, 0x478f, 0x477a, 0x4765, 0x4751, 0x473c, 0x4727,
+ 0x4712, 0x46fd, 0x46e8, 0x46d3, 0x46be, 0x46a9, 0x4694, 0x467f,
+ 0x466a, 0x4655, 0x4640, 0x462b, 0x4616, 0x4601, 0x45ec, 0x45d7,
+ 0x45c2, 0x45ad, 0x4598, 0x4583, 0x456e, 0x4559, 0x4544, 0x452e,
+ 0x4519, 0x4504, 0x44ef, 0x44da, 0x44c5, 0x44af, 0x449a, 0x4485,
+ 0x4470, 0x445a, 0x4445, 0x4430, 0x441b, 0x4405, 0x43f0, 0x43db,
+ 0x43c5, 0x43b0, 0x439b, 0x4385, 0x4370, 0x435b, 0x4345, 0x4330,
+ 0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
+ 0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
+ 0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
+ 0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
+ 0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
+ 0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
+ 0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
+ 0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
+ 0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
+ 0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
+ 0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
+ 0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
+ 0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
+ 0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
+ 0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
+ 0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
+ 0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
+ 0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
+ 0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
+ 0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
+ 0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
+ 0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
+ 0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
+ 0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
+ 0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
+ 0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
+ 0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
+ 0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
+ 0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
+ 0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
+ 0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
+ 0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
+ 0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+ 0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
+ 0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
+ 0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+ 0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
+ 0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
+ 0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
+ 0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
+ 0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
+ 0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
+ 0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
+ 0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
+ 0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
+ 0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
+ 0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
+ 0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
+ 0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
+ 0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
+ 0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+ 0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+ 0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+ 0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+ 0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+ 0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+ 0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+ 0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+ 0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+ 0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+ 0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+ 0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+ 0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+ 0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+ 0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+ 0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+ 0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+ 0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+ 0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+ 0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+ 0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+ 0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+ 0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+ 0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+ 0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+ 0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+ 0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+ 0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+ 0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+ 0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+ 0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+ 0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+ 0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+ 0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+ 0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+ 0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+ 0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+ 0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+ 0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+ 0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+ 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+ 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,
+ 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,
+ 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,
+ 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,
+ 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,
+ 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,
+ 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,
+ 0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,
+ 0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,
+ 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,
+ 0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,
+ 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,
+ 0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,
+ 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,
+ 0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,
+ 0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,
+ 0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,
+ 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,
+ 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,
+ 0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,
+ 0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,
+ 0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,
+ 0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
+ 0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,
+ 0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,
+ 0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,
+ 0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,
+ 0x7fd0, 0x7fd0, 0x7fcf, 0x7fcf, 0x7fcf, 0x7fce, 0x7fce, 0x7fce,
+ 0x7fcd, 0x7fcd, 0x7fcd, 0x7fcc, 0x7fcc, 0x7fcc, 0x7fcb, 0x7fcb,
+ 0x7fcb, 0x7fca, 0x7fca, 0x7fc9, 0x7fc9, 0x7fc9, 0x7fc8, 0x7fc8,
+ 0x7fc8, 0x7fc7, 0x7fc7, 0x7fc7, 0x7fc6, 0x7fc6, 0x7fc5, 0x7fc5,
+ 0x7fc5, 0x7fc4, 0x7fc4, 0x7fc4, 0x7fc3, 0x7fc3, 0x7fc2, 0x7fc2,
+ 0x7fc2, 0x7fc1, 0x7fc1, 0x7fc0, 0x7fc0, 0x7fc0, 0x7fbf, 0x7fbf,
+ 0x7fbf, 0x7fbe, 0x7fbe, 0x7fbd, 0x7fbd, 0x7fbd, 0x7fbc, 0x7fbc,
+ 0x7fbb, 0x7fbb, 0x7fbb, 0x7fba, 0x7fba, 0x7fb9, 0x7fb9, 0x7fb8,
+ 0x7fb8, 0x7fb8, 0x7fb7, 0x7fb7, 0x7fb6, 0x7fb6, 0x7fb6, 0x7fb5,
+ 0x7fb5, 0x7fb4, 0x7fb4, 0x7fb3, 0x7fb3, 0x7fb3, 0x7fb2, 0x7fb2,
+ 0x7fb1, 0x7fb1, 0x7fb0, 0x7fb0, 0x7faf, 0x7faf, 0x7faf, 0x7fae,
+ 0x7fae, 0x7fad, 0x7fad, 0x7fac, 0x7fac, 0x7fac, 0x7fab, 0x7fab,
+ 0x7faa, 0x7faa, 0x7fa9, 0x7fa9, 0x7fa8, 0x7fa8, 0x7fa7, 0x7fa7,
+ 0x7fa6, 0x7fa6, 0x7fa6, 0x7fa5, 0x7fa5, 0x7fa4, 0x7fa4, 0x7fa3,
+ 0x7fa3, 0x7fa2, 0x7fa2, 0x7fa1, 0x7fa1, 0x7fa0, 0x7fa0, 0x7f9f,
+ 0x7f9f, 0x7f9e, 0x7f9e, 0x7f9d, 0x7f9d, 0x7f9c, 0x7f9c, 0x7f9c,
+ 0x7f9b, 0x7f9b, 0x7f9a, 0x7f9a, 0x7f99, 0x7f99, 0x7f98, 0x7f98,
+ 0x7f97, 0x7f97, 0x7f96, 0x7f96, 0x7f95, 0x7f95, 0x7f94, 0x7f94,
+ 0x7f93, 0x7f92, 0x7f92, 0x7f91, 0x7f91, 0x7f90, 0x7f90, 0x7f8f,
+ 0x7f8f, 0x7f8e, 0x7f8e, 0x7f8d, 0x7f8d, 0x7f8c, 0x7f8c, 0x7f8b,
+ 0x7f8b, 0x7f8a, 0x7f8a, 0x7f89, 0x7f89, 0x7f88, 0x7f87, 0x7f87,
+ 0x7f86, 0x7f86, 0x7f85, 0x7f85, 0x7f84, 0x7f84, 0x7f83, 0x7f83,
+ 0x7f82, 0x7f81, 0x7f81, 0x7f80, 0x7f80, 0x7f7f, 0x7f7f, 0x7f7e,
+ 0x7f7e, 0x7f7d, 0x7f7c, 0x7f7c, 0x7f7b, 0x7f7b, 0x7f7a, 0x7f7a,
+ 0x7f79, 0x7f79, 0x7f78, 0x7f77, 0x7f77, 0x7f76, 0x7f76, 0x7f75,
+ 0x7f75, 0x7f74, 0x7f73, 0x7f73, 0x7f72, 0x7f72, 0x7f71, 0x7f70,
+ 0x7f70, 0x7f6f, 0x7f6f, 0x7f6e, 0x7f6d, 0x7f6d, 0x7f6c, 0x7f6c,
+ 0x7f6b, 0x7f6b, 0x7f6a, 0x7f69, 0x7f69, 0x7f68, 0x7f68, 0x7f67,
+ 0x7f66, 0x7f66, 0x7f65, 0x7f64, 0x7f64, 0x7f63, 0x7f63, 0x7f62,
+ 0x7f61, 0x7f61, 0x7f60, 0x7f60, 0x7f5f, 0x7f5e, 0x7f5e, 0x7f5d,
+ 0x7f5c, 0x7f5c, 0x7f5b, 0x7f5b, 0x7f5a, 0x7f59, 0x7f59, 0x7f58,
+ 0x7f57, 0x7f57, 0x7f56, 0x7f55, 0x7f55, 0x7f54, 0x7f54, 0x7f53,
+ 0x7f52, 0x7f52, 0x7f51, 0x7f50, 0x7f50, 0x7f4f, 0x7f4e, 0x7f4e,
+ 0x7f4d, 0x7f4c, 0x7f4c, 0x7f4b, 0x7f4a, 0x7f4a, 0x7f49, 0x7f48,
+ 0x7f48, 0x7f47, 0x7f46, 0x7f46, 0x7f45, 0x7f44, 0x7f44, 0x7f43,
+ 0x7f42, 0x7f42, 0x7f41, 0x7f40, 0x7f40, 0x7f3f, 0x7f3e, 0x7f3e,
+ 0x7f3d, 0x7f3c, 0x7f3c, 0x7f3b, 0x7f3a, 0x7f3a, 0x7f39, 0x7f38,
+ 0x7f37, 0x7f37, 0x7f36, 0x7f35, 0x7f35, 0x7f34, 0x7f33, 0x7f33,
+ 0x7f32, 0x7f31, 0x7f31, 0x7f30, 0x7f2f, 0x7f2e, 0x7f2e, 0x7f2d,
+ 0x7f2c, 0x7f2c, 0x7f2b, 0x7f2a, 0x7f29, 0x7f29, 0x7f28, 0x7f27,
+ 0x7f27, 0x7f26, 0x7f25, 0x7f24, 0x7f24, 0x7f23, 0x7f22, 0x7f21,
+ 0x7f21, 0x7f20, 0x7f1f, 0x7f1f, 0x7f1e, 0x7f1d, 0x7f1c, 0x7f1c,
+ 0x7f1b, 0x7f1a, 0x7f19, 0x7f19, 0x7f18, 0x7f17, 0x7f16, 0x7f16,
+ 0x7f15, 0x7f14, 0x7f13, 0x7f13, 0x7f12, 0x7f11, 0x7f10, 0x7f10,
+ 0x7f0f, 0x7f0e, 0x7f0d, 0x7f0d, 0x7f0c, 0x7f0b, 0x7f0a, 0x7f09,
+ 0x7f09, 0x7f08, 0x7f07, 0x7f06, 0x7f06, 0x7f05, 0x7f04, 0x7f03,
+ 0x7f02, 0x7f02, 0x7f01, 0x7f00, 0x7eff, 0x7eff, 0x7efe, 0x7efd,
+ 0x7efc, 0x7efb, 0x7efb, 0x7efa, 0x7ef9, 0x7ef8, 0x7ef7, 0x7ef7,
+ 0x7ef6, 0x7ef5, 0x7ef4, 0x7ef3, 0x7ef3, 0x7ef2, 0x7ef1, 0x7ef0,
+ 0x7eef, 0x7eef, 0x7eee, 0x7eed, 0x7eec, 0x7eeb, 0x7eeb, 0x7eea,
+ 0x7ee9, 0x7ee8, 0x7ee7, 0x7ee6, 0x7ee6, 0x7ee5, 0x7ee4, 0x7ee3,
+ 0x7ee2, 0x7ee2, 0x7ee1, 0x7ee0, 0x7edf, 0x7ede, 0x7edd, 0x7edd,
+ 0x7edc, 0x7edb, 0x7eda, 0x7ed9, 0x7ed8, 0x7ed8, 0x7ed7, 0x7ed6,
+ 0x7ed5, 0x7ed4, 0x7ed3, 0x7ed2, 0x7ed2, 0x7ed1, 0x7ed0, 0x7ecf,
+ 0x7ece, 0x7ecd, 0x7ecc, 0x7ecc, 0x7ecb, 0x7eca, 0x7ec9, 0x7ec8,
+ 0x7ec7, 0x7ec6, 0x7ec6, 0x7ec5, 0x7ec4, 0x7ec3, 0x7ec2, 0x7ec1,
+ 0x7ec0, 0x7ebf, 0x7ebf, 0x7ebe, 0x7ebd, 0x7ebc, 0x7ebb, 0x7eba,
+ 0x7eb9, 0x7eb8, 0x7eb8, 0x7eb7, 0x7eb6, 0x7eb5, 0x7eb4, 0x7eb3,
+ 0x7eb2, 0x7eb1, 0x7eb0, 0x7eaf, 0x7eaf, 0x7eae, 0x7ead, 0x7eac,
+ 0x7eab, 0x7eaa, 0x7ea9, 0x7ea8, 0x7ea7, 0x7ea6, 0x7ea6, 0x7ea5,
+ 0x7ea4, 0x7ea3, 0x7ea2, 0x7ea1, 0x7ea0, 0x7e9f, 0x7e9e, 0x7e9d,
+ 0x7e9c, 0x7e9b, 0x7e9b, 0x7e9a, 0x7e99, 0x7e98, 0x7e97, 0x7e96,
+ 0x7e95, 0x7e94, 0x7e93, 0x7e92, 0x7e91, 0x7e90, 0x7e8f, 0x7e8e,
+ 0x7e8d, 0x7e8d, 0x7e8c, 0x7e8b, 0x7e8a, 0x7e89, 0x7e88, 0x7e87,
+ 0x7e86, 0x7e85, 0x7e84, 0x7e83, 0x7e82, 0x7e81, 0x7e80, 0x7e7f,
+ 0x7e7e, 0x7e7d, 0x7e7c, 0x7e7b, 0x7e7a, 0x7e79, 0x7e78, 0x7e77,
+ 0x7e77, 0x7e76, 0x7e75, 0x7e74, 0x7e73, 0x7e72, 0x7e71, 0x7e70,
+ 0x7e6f, 0x7e6e, 0x7e6d, 0x7e6c, 0x7e6b, 0x7e6a, 0x7e69, 0x7e68,
+ 0x7e67, 0x7e66, 0x7e65, 0x7e64, 0x7e63, 0x7e62, 0x7e61, 0x7e60,
+ 0x7e5f, 0x7e5e, 0x7e5d, 0x7e5c, 0x7e5b, 0x7e5a, 0x7e59, 0x7e58,
+ 0x7e57, 0x7e56, 0x7e55, 0x7e54, 0x7e53, 0x7e52, 0x7e51, 0x7e50,
+ 0x7e4f, 0x7e4e, 0x7e4d, 0x7e4c, 0x7e4b, 0x7e4a, 0x7e49, 0x7e48,
+ 0x7e47, 0x7e46, 0x7e45, 0x7e43, 0x7e42, 0x7e41, 0x7e40, 0x7e3f,
+ 0x7e3e, 0x7e3d, 0x7e3c, 0x7e3b, 0x7e3a, 0x7e39, 0x7e38, 0x7e37,
+ 0x7e36, 0x7e35, 0x7e34, 0x7e33, 0x7e32, 0x7e31, 0x7e30, 0x7e2f,
+ 0x7e2e, 0x7e2d, 0x7e2b, 0x7e2a, 0x7e29, 0x7e28, 0x7e27, 0x7e26,
+ 0x7e25, 0x7e24, 0x7e23, 0x7e22, 0x7e21, 0x7e20, 0x7e1f, 0x7e1e,
+ 0x7e1d, 0x7e1b, 0x7e1a, 0x7e19, 0x7e18, 0x7e17, 0x7e16, 0x7e15,
+ 0x7e14, 0x7e13, 0x7e12, 0x7e11, 0x7e10, 0x7e0e, 0x7e0d, 0x7e0c,
+ 0x7e0b, 0x7e0a, 0x7e09, 0x7e08, 0x7e07, 0x7e06, 0x7e05, 0x7e04,
+ 0x7e02, 0x7e01, 0x7e00, 0x7dff, 0x7dfe, 0x7dfd, 0x7dfc, 0x7dfb,
+ 0x7dfa, 0x7df8, 0x7df7, 0x7df6, 0x7df5, 0x7df4, 0x7df3, 0x7df2,
+ 0x7df1, 0x7def, 0x7dee, 0x7ded, 0x7dec, 0x7deb, 0x7dea, 0x7de9,
+ 0x7de8, 0x7de6, 0x7de5, 0x7de4, 0x7de3, 0x7de2, 0x7de1, 0x7de0,
+ 0x7dde, 0x7ddd, 0x7ddc, 0x7ddb, 0x7dda, 0x7dd9, 0x7dd8, 0x7dd6,
+ 0x7dd5, 0x7dd4, 0x7dd3, 0x7dd2, 0x7dd1, 0x7dd0, 0x7dce, 0x7dcd,
+ 0x7dcc, 0x7dcb, 0x7dca, 0x7dc9, 0x7dc7, 0x7dc6, 0x7dc5, 0x7dc4,
+ 0x7dc3, 0x7dc2, 0x7dc0, 0x7dbf, 0x7dbe, 0x7dbd, 0x7dbc, 0x7dbb,
+ 0x7db9, 0x7db8, 0x7db7, 0x7db6, 0x7db5, 0x7db3, 0x7db2, 0x7db1,
+ 0x7db0, 0x7daf, 0x7dae, 0x7dac, 0x7dab, 0x7daa, 0x7da9, 0x7da8,
+ 0x7da6, 0x7da5, 0x7da4, 0x7da3, 0x7da2, 0x7da0, 0x7d9f, 0x7d9e,
+ 0x7d9d, 0x7d9c, 0x7d9a, 0x7d99, 0x7d98, 0x7d97, 0x7d95, 0x7d94,
+ 0x7d93, 0x7d92, 0x7d91, 0x7d8f, 0x7d8e, 0x7d8d, 0x7d8c, 0x7d8a,
+ 0x7d89, 0x7d88, 0x7d87, 0x7d86, 0x7d84, 0x7d83, 0x7d82, 0x7d81,
+ 0x7d7f, 0x7d7e, 0x7d7d, 0x7d7c, 0x7d7a, 0x7d79, 0x7d78, 0x7d77,
+ 0x7d75, 0x7d74, 0x7d73, 0x7d72, 0x7d70, 0x7d6f, 0x7d6e, 0x7d6d,
+ 0x7d6b, 0x7d6a, 0x7d69, 0x7d68, 0x7d66, 0x7d65, 0x7d64, 0x7d63,
+ 0x7d61, 0x7d60, 0x7d5f, 0x7d5e, 0x7d5c, 0x7d5b, 0x7d5a, 0x7d59,
+ 0x7d57, 0x7d56, 0x7d55, 0x7d53, 0x7d52, 0x7d51, 0x7d50, 0x7d4e,
+ 0x7d4d, 0x7d4c, 0x7d4a, 0x7d49, 0x7d48, 0x7d47, 0x7d45, 0x7d44,
+ 0x7d43, 0x7d41, 0x7d40, 0x7d3f, 0x7d3e, 0x7d3c, 0x7d3b, 0x7d3a,
+ 0x7d38, 0x7d37, 0x7d36, 0x7d34, 0x7d33, 0x7d32, 0x7d31, 0x7d2f,
+ 0x7d2e, 0x7d2d, 0x7d2b, 0x7d2a, 0x7d29, 0x7d27, 0x7d26, 0x7d25,
+ 0x7d23, 0x7d22, 0x7d21, 0x7d1f, 0x7d1e, 0x7d1d, 0x7d1b, 0x7d1a,
+ 0x7d19, 0x7d17, 0x7d16, 0x7d15, 0x7d13, 0x7d12, 0x7d11, 0x7d0f,
+ 0x7d0e, 0x7d0d, 0x7d0b, 0x7d0a, 0x7d09, 0x7d07, 0x7d06, 0x7d05,
+ 0x7d03, 0x7d02, 0x7d01, 0x7cff, 0x7cfe, 0x7cfd, 0x7cfb, 0x7cfa,
+ 0x7cf9, 0x7cf7, 0x7cf6, 0x7cf4, 0x7cf3, 0x7cf2, 0x7cf0, 0x7cef,
+ 0x7cee, 0x7cec, 0x7ceb, 0x7ce9, 0x7ce8, 0x7ce7, 0x7ce5, 0x7ce4,
+ 0x7ce3, 0x7ce1, 0x7ce0, 0x7cde, 0x7cdd, 0x7cdc, 0x7cda, 0x7cd9,
+ 0x7cd8, 0x7cd6, 0x7cd5, 0x7cd3, 0x7cd2, 0x7cd1, 0x7ccf, 0x7cce,
+ 0x7ccc, 0x7ccb, 0x7cca, 0x7cc8, 0x7cc7, 0x7cc5, 0x7cc4, 0x7cc3,
+ 0x7cc1, 0x7cc0, 0x7cbe, 0x7cbd, 0x7cbc, 0x7cba, 0x7cb9, 0x7cb7,
+ 0x7cb6, 0x7cb5, 0x7cb3, 0x7cb2, 0x7cb0, 0x7caf, 0x7cad, 0x7cac,
+ 0x7cab, 0x7ca9, 0x7ca8, 0x7ca6, 0x7ca5, 0x7ca3, 0x7ca2, 0x7ca1,
+ 0x7c9f, 0x7c9e, 0x7c9c, 0x7c9b, 0x7c99, 0x7c98, 0x7c97, 0x7c95,
+ 0x7c94, 0x7c92, 0x7c91, 0x7c8f, 0x7c8e, 0x7c8c, 0x7c8b, 0x7c8a,
+ 0x7c88, 0x7c87, 0x7c85, 0x7c84, 0x7c82, 0x7c81, 0x7c7f, 0x7c7e,
+ 0x7c7c, 0x7c7b, 0x7c79, 0x7c78, 0x7c77, 0x7c75, 0x7c74, 0x7c72,
+ 0x7c71, 0x7c6f, 0x7c6e, 0x7c6c, 0x7c6b, 0x7c69, 0x7c68, 0x7c66,
+ 0x7c65, 0x7c63, 0x7c62, 0x7c60, 0x7c5f, 0x7c5d, 0x7c5c, 0x7c5a,
+ 0x7c59, 0x7c58, 0x7c56, 0x7c55, 0x7c53, 0x7c52, 0x7c50, 0x7c4f,
+ 0x7c4d, 0x7c4c, 0x7c4a, 0x7c49, 0x7c47, 0x7c46, 0x7c44, 0x7c43,
+ 0x7c41, 0x7c3f, 0x7c3e, 0x7c3c, 0x7c3b, 0x7c39, 0x7c38, 0x7c36,
+ 0x7c35, 0x7c33, 0x7c32, 0x7c30, 0x7c2f, 0x7c2d, 0x7c2c, 0x7c2a,
+ 0x7c29, 0x7c27, 0x7c26, 0x7c24, 0x7c23, 0x7c21, 0x7c20, 0x7c1e,
+ 0x7c1c, 0x7c1b, 0x7c19, 0x7c18, 0x7c16, 0x7c15, 0x7c13, 0x7c12,
+ 0x7c10, 0x7c0f, 0x7c0d, 0x7c0b, 0x7c0a, 0x7c08, 0x7c07, 0x7c05,
+ 0x7c04, 0x7c02, 0x7c01, 0x7bff, 0x7bfd, 0x7bfc, 0x7bfa, 0x7bf9,
+ 0x7bf7, 0x7bf6, 0x7bf4, 0x7bf3, 0x7bf1, 0x7bef, 0x7bee, 0x7bec,
+ 0x7beb, 0x7be9, 0x7be8, 0x7be6, 0x7be4, 0x7be3, 0x7be1, 0x7be0,
+ 0x7bde, 0x7bdc, 0x7bdb, 0x7bd9, 0x7bd8, 0x7bd6, 0x7bd5, 0x7bd3,
+ 0x7bd1, 0x7bd0, 0x7bce, 0x7bcd, 0x7bcb, 0x7bc9, 0x7bc8, 0x7bc6,
+ 0x7bc5, 0x7bc3, 0x7bc1, 0x7bc0, 0x7bbe, 0x7bbd, 0x7bbb, 0x7bb9,
+ 0x7bb8, 0x7bb6, 0x7bb5, 0x7bb3, 0x7bb1, 0x7bb0, 0x7bae, 0x7bac,
+ 0x7bab, 0x7ba9, 0x7ba8, 0x7ba6, 0x7ba4, 0x7ba3, 0x7ba1, 0x7b9f,
+ 0x7b9e, 0x7b9c, 0x7b9b, 0x7b99, 0x7b97, 0x7b96, 0x7b94, 0x7b92,
+ 0x7b91, 0x7b8f, 0x7b8d, 0x7b8c, 0x7b8a, 0x7b89, 0x7b87, 0x7b85,
+ 0x7b84, 0x7b82, 0x7b80, 0x7b7f, 0x7b7d, 0x7b7b, 0x7b7a, 0x7b78,
+ 0x7b76, 0x7b75, 0x7b73, 0x7b71, 0x7b70, 0x7b6e, 0x7b6c, 0x7b6b,
+ 0x7b69, 0x7b67, 0x7b66, 0x7b64, 0x7b62, 0x7b61, 0x7b5f, 0x7b5d,
+ 0x7b5c, 0x7b5a, 0x7b58, 0x7b57, 0x7b55, 0x7b53, 0x7b52, 0x7b50,
+ 0x7b4e, 0x7b4d, 0x7b4b, 0x7b49, 0x7b47, 0x7b46, 0x7b44, 0x7b42,
+ 0x7b41, 0x7b3f, 0x7b3d, 0x7b3c, 0x7b3a, 0x7b38, 0x7b37, 0x7b35,
+ 0x7b33, 0x7b31, 0x7b30, 0x7b2e, 0x7b2c, 0x7b2b, 0x7b29, 0x7b27,
+ 0x7b25, 0x7b24, 0x7b22, 0x7b20, 0x7b1f, 0x7b1d, 0x7b1b, 0x7b19,
+ 0x7b18, 0x7b16, 0x7b14, 0x7b13, 0x7b11, 0x7b0f, 0x7b0d, 0x7b0c,
+ 0x7b0a, 0x7b08, 0x7b06, 0x7b05, 0x7b03, 0x7b01, 0x7aff, 0x7afe,
+ 0x7afc, 0x7afa, 0x7af8, 0x7af7, 0x7af5, 0x7af3, 0x7af2, 0x7af0,
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+ 0x7ae0, 0x7ade, 0x7adc, 0x7adb, 0x7ad9, 0x7ad7, 0x7ad5, 0x7ad4,
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+ 0x58f5, 0x58f1, 0x58ec, 0x58e8, 0x58e3, 0x58df, 0x58da, 0x58d6,
+ 0x58d1, 0x58cd, 0x58c8, 0x58c4, 0x58bf, 0x58bb, 0x58b6, 0x58b2,
+ 0x58ad, 0x58a9, 0x58a4, 0x589f, 0x589b, 0x5896, 0x5892, 0x588d,
+ 0x5889, 0x5884, 0x5880, 0x587b, 0x5877, 0x5872, 0x586e, 0x5869,
+ 0x5864, 0x5860, 0x585b, 0x5857, 0x5852, 0x584e, 0x5849, 0x5845,
+ 0x5840, 0x583c, 0x5837, 0x5832, 0x582e, 0x5829, 0x5825, 0x5820,
+ 0x581c, 0x5817, 0x5813, 0x580e, 0x5809, 0x5805, 0x5800, 0x57fc,
+ 0x57f7, 0x57f3, 0x57ee, 0x57e9, 0x57e5, 0x57e0, 0x57dc, 0x57d7,
+ 0x57d3, 0x57ce, 0x57c9, 0x57c5, 0x57c0, 0x57bc, 0x57b7, 0x57b3,
+ 0x57ae, 0x57a9, 0x57a5, 0x57a0, 0x579c, 0x5797, 0x5793, 0x578e,
+ 0x5789, 0x5785, 0x5780, 0x577c, 0x5777, 0x5772, 0x576e, 0x5769,
+ 0x5765, 0x5760, 0x575c, 0x5757, 0x5752, 0x574e, 0x5749, 0x5745,
+ 0x5740, 0x573b, 0x5737, 0x5732, 0x572e, 0x5729, 0x5724, 0x5720,
+ 0x571b, 0x5717, 0x5712, 0x570d, 0x5709, 0x5704, 0x56ff, 0x56fb,
+ 0x56f6, 0x56f2, 0x56ed, 0x56e8, 0x56e4, 0x56df, 0x56db, 0x56d6,
+ 0x56d1, 0x56cd, 0x56c8, 0x56c4, 0x56bf, 0x56ba, 0x56b6, 0x56b1,
+ 0x56ac, 0x56a8, 0x56a3, 0x569f, 0x569a, 0x5695, 0x5691, 0x568c,
+ 0x5687, 0x5683, 0x567e, 0x5679, 0x5675, 0x5670, 0x566c, 0x5667,
+ 0x5662, 0x565e, 0x5659, 0x5654, 0x5650, 0x564b, 0x5646, 0x5642,
+ 0x563d, 0x5639, 0x5634, 0x562f, 0x562b, 0x5626, 0x5621, 0x561d,
+ 0x5618, 0x5613, 0x560f, 0x560a, 0x5605, 0x5601, 0x55fc, 0x55f7,
+ 0x55f3, 0x55ee, 0x55ea, 0x55e5, 0x55e0, 0x55dc, 0x55d7, 0x55d2,
+ 0x55ce, 0x55c9, 0x55c4, 0x55c0, 0x55bb, 0x55b6, 0x55b2, 0x55ad,
+ 0x55a8, 0x55a4, 0x559f, 0x559a, 0x5596, 0x5591, 0x558c, 0x5588,
+ 0x5583, 0x557e, 0x5579, 0x5575, 0x5570, 0x556b, 0x5567, 0x5562,
+ 0x555d, 0x5559, 0x5554, 0x554f, 0x554b, 0x5546, 0x5541, 0x553d,
+ 0x5538, 0x5533, 0x552f, 0x552a, 0x5525, 0x5520, 0x551c, 0x5517,
+ 0x5512, 0x550e, 0x5509, 0x5504, 0x5500, 0x54fb, 0x54f6, 0x54f2,
+ 0x54ed, 0x54e8, 0x54e3, 0x54df, 0x54da, 0x54d5, 0x54d1, 0x54cc,
+ 0x54c7, 0x54c2, 0x54be, 0x54b9, 0x54b4, 0x54b0, 0x54ab, 0x54a6,
+ 0x54a2, 0x549d, 0x5498, 0x5493, 0x548f, 0x548a, 0x5485, 0x5480,
+ 0x547c, 0x5477, 0x5472, 0x546e, 0x5469, 0x5464, 0x545f, 0x545b,
+ 0x5456, 0x5451, 0x544d, 0x5448, 0x5443, 0x543e, 0x543a, 0x5435,
+ 0x5430, 0x542b, 0x5427, 0x5422, 0x541d, 0x5418, 0x5414, 0x540f,
+ 0x540a, 0x5406, 0x5401, 0x53fc, 0x53f7, 0x53f3, 0x53ee, 0x53e9,
+ 0x53e4, 0x53e0, 0x53db, 0x53d6, 0x53d1, 0x53cd, 0x53c8, 0x53c3,
+ 0x53be, 0x53ba, 0x53b5, 0x53b0, 0x53ab, 0x53a7, 0x53a2, 0x539d,
+ 0x5398, 0x5394, 0x538f, 0x538a, 0x5385, 0x5380, 0x537c, 0x5377,
+ 0x5372, 0x536d, 0x5369, 0x5364, 0x535f, 0x535a, 0x5356, 0x5351,
+ 0x534c, 0x5347, 0x5343, 0x533e, 0x5339, 0x5334, 0x532f, 0x532b,
+ 0x5326, 0x5321, 0x531c, 0x5318, 0x5313, 0x530e, 0x5309, 0x5304,
+ 0x5300, 0x52fb, 0x52f6, 0x52f1, 0x52ec, 0x52e8, 0x52e3, 0x52de,
+ 0x52d9, 0x52d5, 0x52d0, 0x52cb, 0x52c6, 0x52c1, 0x52bd, 0x52b8,
+ 0x52b3, 0x52ae, 0x52a9, 0x52a5, 0x52a0, 0x529b, 0x5296, 0x5291,
+ 0x528d, 0x5288, 0x5283, 0x527e, 0x5279, 0x5275, 0x5270, 0x526b,
+ 0x5266, 0x5261, 0x525d, 0x5258, 0x5253, 0x524e, 0x5249, 0x5244,
+ 0x5240, 0x523b, 0x5236, 0x5231, 0x522c, 0x5228, 0x5223, 0x521e,
+ 0x5219, 0x5214, 0x520f, 0x520b, 0x5206, 0x5201, 0x51fc, 0x51f7,
+ 0x51f3, 0x51ee, 0x51e9, 0x51e4, 0x51df, 0x51da, 0x51d6, 0x51d1,
+ 0x51cc, 0x51c7, 0x51c2, 0x51bd, 0x51b9, 0x51b4, 0x51af, 0x51aa,
+ 0x51a5, 0x51a0, 0x519c, 0x5197, 0x5192, 0x518d, 0x5188, 0x5183,
+ 0x517e, 0x517a, 0x5175, 0x5170, 0x516b, 0x5166, 0x5161, 0x515d,
+ 0x5158, 0x5153, 0x514e, 0x5149, 0x5144, 0x513f, 0x513b, 0x5136,
+ 0x5131, 0x512c, 0x5127, 0x5122, 0x511d, 0x5119, 0x5114, 0x510f,
+ 0x510a, 0x5105, 0x5100, 0x50fb, 0x50f7, 0x50f2, 0x50ed, 0x50e8,
+ 0x50e3, 0x50de, 0x50d9, 0x50d4, 0x50d0, 0x50cb, 0x50c6, 0x50c1,
+ 0x50bc, 0x50b7, 0x50b2, 0x50ad, 0x50a9, 0x50a4, 0x509f, 0x509a,
+ 0x5095, 0x5090, 0x508b, 0x5086, 0x5082, 0x507d, 0x5078, 0x5073,
+ 0x506e, 0x5069, 0x5064, 0x505f, 0x505a, 0x5056, 0x5051, 0x504c,
+ 0x5047, 0x5042, 0x503d, 0x5038, 0x5033, 0x502e, 0x5029, 0x5025,
+ 0x5020, 0x501b, 0x5016, 0x5011, 0x500c, 0x5007, 0x5002, 0x4ffd,
+ 0x4ff8, 0x4ff4, 0x4fef, 0x4fea, 0x4fe5, 0x4fe0, 0x4fdb, 0x4fd6,
+ 0x4fd1, 0x4fcc, 0x4fc7, 0x4fc2, 0x4fbe, 0x4fb9, 0x4fb4, 0x4faf,
+ 0x4faa, 0x4fa5, 0x4fa0, 0x4f9b, 0x4f96, 0x4f91, 0x4f8c, 0x4f87,
+ 0x4f82, 0x4f7e, 0x4f79, 0x4f74, 0x4f6f, 0x4f6a, 0x4f65, 0x4f60,
+ 0x4f5b, 0x4f56, 0x4f51, 0x4f4c, 0x4f47, 0x4f42, 0x4f3d, 0x4f39,
+ 0x4f34, 0x4f2f, 0x4f2a, 0x4f25, 0x4f20, 0x4f1b, 0x4f16, 0x4f11,
+ 0x4f0c, 0x4f07, 0x4f02, 0x4efd, 0x4ef8, 0x4ef3, 0x4eee, 0x4ee9,
+ 0x4ee5, 0x4ee0, 0x4edb, 0x4ed6, 0x4ed1, 0x4ecc, 0x4ec7, 0x4ec2,
+ 0x4ebd, 0x4eb8, 0x4eb3, 0x4eae, 0x4ea9, 0x4ea4, 0x4e9f, 0x4e9a,
+ 0x4e95, 0x4e90, 0x4e8b, 0x4e86, 0x4e81, 0x4e7c, 0x4e78, 0x4e73,
+ 0x4e6e, 0x4e69, 0x4e64, 0x4e5f, 0x4e5a, 0x4e55, 0x4e50, 0x4e4b,
+ 0x4e46, 0x4e41, 0x4e3c, 0x4e37, 0x4e32, 0x4e2d, 0x4e28, 0x4e23,
+ 0x4e1e, 0x4e19, 0x4e14, 0x4e0f, 0x4e0a, 0x4e05, 0x4e00, 0x4dfb,
+ 0x4df6, 0x4df1, 0x4dec, 0x4de7, 0x4de2, 0x4ddd, 0x4dd8, 0x4dd3,
+ 0x4dce, 0x4dc9, 0x4dc4, 0x4dbf, 0x4dba, 0x4db5, 0x4db0, 0x4dab,
+ 0x4da6, 0x4da1, 0x4d9c, 0x4d97, 0x4d92, 0x4d8d, 0x4d88, 0x4d83,
+ 0x4d7e, 0x4d79, 0x4d74, 0x4d6f, 0x4d6a, 0x4d65, 0x4d60, 0x4d5b,
+ 0x4d56, 0x4d51, 0x4d4c, 0x4d47, 0x4d42, 0x4d3d, 0x4d38, 0x4d33,
+ 0x4d2e, 0x4d29, 0x4d24, 0x4d1f, 0x4d1a, 0x4d15, 0x4d10, 0x4d0b,
+ 0x4d06, 0x4d01, 0x4cfc, 0x4cf7, 0x4cf2, 0x4ced, 0x4ce8, 0x4ce3,
+ 0x4cde, 0x4cd9, 0x4cd4, 0x4ccf, 0x4cca, 0x4cc5, 0x4cc0, 0x4cbb,
+ 0x4cb6, 0x4cb1, 0x4cac, 0x4ca7, 0x4ca2, 0x4c9d, 0x4c98, 0x4c93,
+ 0x4c8e, 0x4c88, 0x4c83, 0x4c7e, 0x4c79, 0x4c74, 0x4c6f, 0x4c6a,
+ 0x4c65, 0x4c60, 0x4c5b, 0x4c56, 0x4c51, 0x4c4c, 0x4c47, 0x4c42,
+ 0x4c3d, 0x4c38, 0x4c33, 0x4c2e, 0x4c29, 0x4c24, 0x4c1f, 0x4c1a,
+ 0x4c14, 0x4c0f, 0x4c0a, 0x4c05, 0x4c00, 0x4bfb, 0x4bf6, 0x4bf1,
+ 0x4bec, 0x4be7, 0x4be2, 0x4bdd, 0x4bd8, 0x4bd3, 0x4bce, 0x4bc9,
+ 0x4bc4, 0x4bbe, 0x4bb9, 0x4bb4, 0x4baf, 0x4baa, 0x4ba5, 0x4ba0,
+ 0x4b9b, 0x4b96, 0x4b91, 0x4b8c, 0x4b87, 0x4b82, 0x4b7d, 0x4b77,
+ 0x4b72, 0x4b6d, 0x4b68, 0x4b63, 0x4b5e, 0x4b59, 0x4b54, 0x4b4f,
+ 0x4b4a, 0x4b45, 0x4b40, 0x4b3b, 0x4b35, 0x4b30, 0x4b2b, 0x4b26,
+ 0x4b21, 0x4b1c, 0x4b17, 0x4b12, 0x4b0d, 0x4b08, 0x4b03, 0x4afd,
+ 0x4af8, 0x4af3, 0x4aee, 0x4ae9, 0x4ae4, 0x4adf, 0x4ada, 0x4ad5,
+ 0x4ad0, 0x4acb, 0x4ac5, 0x4ac0, 0x4abb, 0x4ab6, 0x4ab1, 0x4aac,
+ 0x4aa7, 0x4aa2, 0x4a9d, 0x4a97, 0x4a92, 0x4a8d, 0x4a88, 0x4a83,
+ 0x4a7e, 0x4a79, 0x4a74, 0x4a6f, 0x4a6a, 0x4a64, 0x4a5f, 0x4a5a,
+ 0x4a55, 0x4a50, 0x4a4b, 0x4a46, 0x4a41, 0x4a3b, 0x4a36, 0x4a31,
+ 0x4a2c, 0x4a27, 0x4a22, 0x4a1d, 0x4a18, 0x4a12, 0x4a0d, 0x4a08,
+ 0x4a03, 0x49fe, 0x49f9, 0x49f4, 0x49ef, 0x49e9, 0x49e4, 0x49df,
+ 0x49da, 0x49d5, 0x49d0, 0x49cb, 0x49c6, 0x49c0, 0x49bb, 0x49b6,
+ 0x49b1, 0x49ac, 0x49a7, 0x49a2, 0x499c, 0x4997, 0x4992, 0x498d,
+ 0x4988, 0x4983, 0x497e, 0x4978, 0x4973, 0x496e, 0x4969, 0x4964,
+ 0x495f, 0x495a, 0x4954, 0x494f, 0x494a, 0x4945, 0x4940, 0x493b,
+ 0x4936, 0x4930, 0x492b, 0x4926, 0x4921, 0x491c, 0x4917, 0x4911,
+ 0x490c, 0x4907, 0x4902, 0x48fd, 0x48f8, 0x48f2, 0x48ed, 0x48e8,
+ 0x48e3, 0x48de, 0x48d9, 0x48d3, 0x48ce, 0x48c9, 0x48c4, 0x48bf,
+ 0x48ba, 0x48b4, 0x48af, 0x48aa, 0x48a5, 0x48a0, 0x489b, 0x4895,
+ 0x4890, 0x488b, 0x4886, 0x4881, 0x487c, 0x4876, 0x4871, 0x486c,
+ 0x4867, 0x4862, 0x485c, 0x4857, 0x4852, 0x484d, 0x4848, 0x4843,
+ 0x483d, 0x4838, 0x4833, 0x482e, 0x4829, 0x4823, 0x481e, 0x4819,
+ 0x4814, 0x480f, 0x4809, 0x4804, 0x47ff, 0x47fa, 0x47f5, 0x47ef,
+ 0x47ea, 0x47e5, 0x47e0, 0x47db, 0x47d5, 0x47d0, 0x47cb, 0x47c6,
+ 0x47c1, 0x47bb, 0x47b6, 0x47b1, 0x47ac, 0x47a7, 0x47a1, 0x479c,
+ 0x4797, 0x4792, 0x478d, 0x4787, 0x4782, 0x477d, 0x4778, 0x4773,
+ 0x476d, 0x4768, 0x4763, 0x475e, 0x4758, 0x4753, 0x474e, 0x4749,
+ 0x4744, 0x473e, 0x4739, 0x4734, 0x472f, 0x4729, 0x4724, 0x471f,
+ 0x471a, 0x4715, 0x470f, 0x470a, 0x4705, 0x4700, 0x46fa, 0x46f5,
+ 0x46f0, 0x46eb, 0x46e6, 0x46e0, 0x46db, 0x46d6, 0x46d1, 0x46cb,
+ 0x46c6, 0x46c1, 0x46bc, 0x46b6, 0x46b1, 0x46ac, 0x46a7, 0x46a1,
+ 0x469c, 0x4697, 0x4692, 0x468d, 0x4687, 0x4682, 0x467d, 0x4678,
+ 0x4672, 0x466d, 0x4668, 0x4663, 0x465d, 0x4658, 0x4653, 0x464e,
+ 0x4648, 0x4643, 0x463e, 0x4639, 0x4633, 0x462e, 0x4629, 0x4624,
+ 0x461e, 0x4619, 0x4614, 0x460e, 0x4609, 0x4604, 0x45ff, 0x45f9,
+ 0x45f4, 0x45ef, 0x45ea, 0x45e4, 0x45df, 0x45da, 0x45d5, 0x45cf,
+ 0x45ca, 0x45c5, 0x45c0, 0x45ba, 0x45b5, 0x45b0, 0x45aa, 0x45a5,
+ 0x45a0, 0x459b, 0x4595, 0x4590, 0x458b, 0x4586, 0x4580, 0x457b,
+ 0x4576, 0x4570, 0x456b, 0x4566, 0x4561, 0x455b, 0x4556, 0x4551,
+ 0x454b, 0x4546, 0x4541, 0x453c, 0x4536, 0x4531, 0x452c, 0x4526,
+ 0x4521, 0x451c, 0x4517, 0x4511, 0x450c, 0x4507, 0x4501, 0x44fc,
+ 0x44f7, 0x44f2, 0x44ec, 0x44e7, 0x44e2, 0x44dc, 0x44d7, 0x44d2,
+ 0x44cd, 0x44c7, 0x44c2, 0x44bd, 0x44b7, 0x44b2, 0x44ad, 0x44a7,
+ 0x44a2, 0x449d, 0x4497, 0x4492, 0x448d, 0x4488, 0x4482, 0x447d,
+ 0x4478, 0x4472, 0x446d, 0x4468, 0x4462, 0x445d, 0x4458, 0x4452,
+ 0x444d, 0x4448, 0x4443, 0x443d, 0x4438, 0x4433, 0x442d, 0x4428,
+ 0x4423, 0x441d, 0x4418, 0x4413, 0x440d, 0x4408, 0x4403, 0x43fd,
+ 0x43f8, 0x43f3, 0x43ed, 0x43e8, 0x43e3, 0x43dd, 0x43d8, 0x43d3,
+ 0x43cd, 0x43c8, 0x43c3, 0x43bd, 0x43b8, 0x43b3, 0x43ad, 0x43a8,
+ 0x43a3, 0x439d, 0x4398, 0x4393, 0x438d, 0x4388, 0x4383, 0x437d,
+ 0x4378, 0x4373, 0x436d, 0x4368, 0x4363, 0x435d, 0x4358, 0x4353,
+ 0x434d, 0x4348, 0x4343, 0x433d, 0x4338, 0x4333, 0x432d, 0x4328,
+ 0x4323, 0x431d, 0x4318, 0x4313, 0x430d, 0x4308, 0x4302, 0x42fd,
+ 0x42f8, 0x42f2, 0x42ed, 0x42e8, 0x42e2, 0x42dd, 0x42d8, 0x42d2,
+ 0x42cd, 0x42c8, 0x42c2, 0x42bd, 0x42b7, 0x42b2, 0x42ad, 0x42a7,
+ 0x42a2, 0x429d, 0x4297, 0x4292, 0x428d, 0x4287, 0x4282, 0x427c,
+ 0x4277, 0x4272, 0x426c, 0x4267, 0x4262, 0x425c, 0x4257, 0x4251,
+ 0x424c, 0x4247, 0x4241, 0x423c, 0x4237, 0x4231, 0x422c, 0x4226,
+ 0x4221, 0x421c, 0x4216, 0x4211, 0x420c, 0x4206, 0x4201, 0x41fb,
+ 0x41f6, 0x41f1, 0x41eb, 0x41e6, 0x41e0, 0x41db, 0x41d6, 0x41d0,
+ 0x41cb, 0x41c6, 0x41c0, 0x41bb, 0x41b5, 0x41b0, 0x41ab, 0x41a5,
+ 0x41a0, 0x419a, 0x4195, 0x4190, 0x418a, 0x4185, 0x417f, 0x417a,
+ 0x4175, 0x416f, 0x416a, 0x4164, 0x415f, 0x415a, 0x4154, 0x414f,
+ 0x4149, 0x4144, 0x413f, 0x4139, 0x4134, 0x412e, 0x4129, 0x4124,
+ 0x411e, 0x4119, 0x4113, 0x410e, 0x4108, 0x4103, 0x40fe, 0x40f8,
+ 0x40f3, 0x40ed, 0x40e8, 0x40e3, 0x40dd, 0x40d8, 0x40d2, 0x40cd,
+ 0x40c8, 0x40c2, 0x40bd, 0x40b7, 0x40b2, 0x40ac, 0x40a7, 0x40a2,
+ 0x409c, 0x4097, 0x4091, 0x408c, 0x4086, 0x4081, 0x407c, 0x4076,
+ 0x4071, 0x406b, 0x4066, 0x4060, 0x405b, 0x4056, 0x4050, 0x404b,
+ 0x4045, 0x4040, 0x403a, 0x4035, 0x4030, 0x402a, 0x4025, 0x401f,
+ 0x401a, 0x4014, 0x400f, 0x4009, 0x4004, 0x3fff, 0x3ff9, 0x3ff4,
+ 0x3fee, 0x3fe9, 0x3fe3, 0x3fde, 0x3fd8, 0x3fd3, 0x3fce, 0x3fc8,
+ 0x3fc3, 0x3fbd, 0x3fb8, 0x3fb2, 0x3fad, 0x3fa7, 0x3fa2, 0x3f9d,
+ 0x3f97, 0x3f92, 0x3f8c, 0x3f87, 0x3f81, 0x3f7c, 0x3f76, 0x3f71,
+ 0x3f6b, 0x3f66, 0x3f61, 0x3f5b, 0x3f56, 0x3f50, 0x3f4b, 0x3f45,
+ 0x3f40, 0x3f3a, 0x3f35, 0x3f2f, 0x3f2a, 0x3f24, 0x3f1f, 0x3f1a,
+ 0x3f14, 0x3f0f, 0x3f09, 0x3f04, 0x3efe, 0x3ef9, 0x3ef3, 0x3eee,
+ 0x3ee8, 0x3ee3, 0x3edd, 0x3ed8, 0x3ed2, 0x3ecd, 0x3ec7, 0x3ec2,
+ 0x3ebd, 0x3eb7, 0x3eb2, 0x3eac, 0x3ea7, 0x3ea1, 0x3e9c, 0x3e96,
+ 0x3e91, 0x3e8b, 0x3e86, 0x3e80, 0x3e7b, 0x3e75, 0x3e70, 0x3e6a,
+ 0x3e65, 0x3e5f, 0x3e5a, 0x3e54, 0x3e4f, 0x3e49, 0x3e44, 0x3e3e,
+ 0x3e39, 0x3e33, 0x3e2e, 0x3e28, 0x3e23, 0x3e1d, 0x3e18, 0x3e12,
+ 0x3e0d, 0x3e07, 0x3e02, 0x3dfc, 0x3df7, 0x3df1, 0x3dec, 0x3de6,
+ 0x3de1, 0x3ddb, 0x3dd6, 0x3dd0, 0x3dcb, 0x3dc5, 0x3dc0, 0x3dba,
+ 0x3db5, 0x3daf, 0x3daa, 0x3da4, 0x3d9f, 0x3d99, 0x3d94, 0x3d8e,
+ 0x3d89, 0x3d83, 0x3d7e, 0x3d78, 0x3d73, 0x3d6d, 0x3d68, 0x3d62,
+ 0x3d5d, 0x3d57, 0x3d52, 0x3d4c, 0x3d47, 0x3d41, 0x3d3c, 0x3d36,
+ 0x3d31, 0x3d2b, 0x3d26, 0x3d20, 0x3d1b, 0x3d15, 0x3d10, 0x3d0a,
+ 0x3d04, 0x3cff, 0x3cf9, 0x3cf4, 0x3cee, 0x3ce9, 0x3ce3, 0x3cde,
+ 0x3cd8, 0x3cd3, 0x3ccd, 0x3cc8, 0x3cc2, 0x3cbd, 0x3cb7, 0x3cb2,
+ 0x3cac, 0x3ca7, 0x3ca1, 0x3c9b, 0x3c96, 0x3c90, 0x3c8b, 0x3c85,
+ 0x3c80, 0x3c7a, 0x3c75, 0x3c6f, 0x3c6a, 0x3c64, 0x3c5f, 0x3c59,
+ 0x3c53, 0x3c4e, 0x3c48, 0x3c43, 0x3c3d, 0x3c38, 0x3c32, 0x3c2d,
+ 0x3c27, 0x3c22, 0x3c1c, 0x3c16, 0x3c11, 0x3c0b, 0x3c06, 0x3c00,
+ 0x3bfb, 0x3bf5, 0x3bf0, 0x3bea, 0x3be5, 0x3bdf, 0x3bd9, 0x3bd4,
+ 0x3bce, 0x3bc9, 0x3bc3, 0x3bbe, 0x3bb8, 0x3bb3, 0x3bad, 0x3ba7,
+ 0x3ba2, 0x3b9c, 0x3b97, 0x3b91, 0x3b8c, 0x3b86, 0x3b80, 0x3b7b,
+ 0x3b75, 0x3b70, 0x3b6a, 0x3b65, 0x3b5f, 0x3b5a, 0x3b54, 0x3b4e,
+ 0x3b49, 0x3b43, 0x3b3e, 0x3b38, 0x3b33, 0x3b2d, 0x3b27, 0x3b22,
+ 0x3b1c, 0x3b17, 0x3b11, 0x3b0c, 0x3b06, 0x3b00, 0x3afb, 0x3af5,
+ 0x3af0, 0x3aea, 0x3ae4, 0x3adf, 0x3ad9, 0x3ad4, 0x3ace, 0x3ac9,
+ 0x3ac3, 0x3abd, 0x3ab8, 0x3ab2, 0x3aad, 0x3aa7, 0x3aa2, 0x3a9c,
+ 0x3a96, 0x3a91, 0x3a8b, 0x3a86, 0x3a80, 0x3a7a, 0x3a75, 0x3a6f,
+ 0x3a6a, 0x3a64, 0x3a5e, 0x3a59, 0x3a53, 0x3a4e, 0x3a48, 0x3a42,
+ 0x3a3d, 0x3a37, 0x3a32, 0x3a2c, 0x3a26, 0x3a21, 0x3a1b, 0x3a16,
+ 0x3a10, 0x3a0b, 0x3a05, 0x39ff, 0x39fa, 0x39f4, 0x39ee, 0x39e9,
+ 0x39e3, 0x39de, 0x39d8, 0x39d2, 0x39cd, 0x39c7, 0x39c2, 0x39bc,
+ 0x39b6, 0x39b1, 0x39ab, 0x39a6, 0x39a0, 0x399a, 0x3995, 0x398f,
+ 0x398a, 0x3984, 0x397e, 0x3979, 0x3973, 0x396d, 0x3968, 0x3962,
+ 0x395d, 0x3957, 0x3951, 0x394c, 0x3946, 0x3941, 0x393b, 0x3935,
+ 0x3930, 0x392a, 0x3924, 0x391f, 0x3919, 0x3914, 0x390e, 0x3908,
+ 0x3903, 0x38fd, 0x38f7, 0x38f2, 0x38ec, 0x38e7, 0x38e1, 0x38db,
+ 0x38d6, 0x38d0, 0x38ca, 0x38c5, 0x38bf, 0x38ba, 0x38b4, 0x38ae,
+ 0x38a9, 0x38a3, 0x389d, 0x3898, 0x3892, 0x388c, 0x3887, 0x3881,
+ 0x387c, 0x3876, 0x3870, 0x386b, 0x3865, 0x385f, 0x385a, 0x3854,
+ 0x384e, 0x3849, 0x3843, 0x383d, 0x3838, 0x3832, 0x382d, 0x3827,
+ 0x3821, 0x381c, 0x3816, 0x3810, 0x380b, 0x3805, 0x37ff, 0x37fa,
+ 0x37f4, 0x37ee, 0x37e9, 0x37e3, 0x37dd, 0x37d8, 0x37d2, 0x37cc,
+ 0x37c7, 0x37c1, 0x37bc, 0x37b6, 0x37b0, 0x37ab, 0x37a5, 0x379f,
+ 0x379a, 0x3794, 0x378e, 0x3789, 0x3783, 0x377d, 0x3778, 0x3772,
+ 0x376c, 0x3767, 0x3761, 0x375b, 0x3756, 0x3750, 0x374a, 0x3745,
+ 0x373f, 0x3739, 0x3734, 0x372e, 0x3728, 0x3723, 0x371d, 0x3717,
+ 0x3712, 0x370c, 0x3706, 0x3701, 0x36fb, 0x36f5, 0x36f0, 0x36ea,
+ 0x36e4, 0x36df, 0x36d9, 0x36d3, 0x36ce, 0x36c8, 0x36c2, 0x36bc,
+ 0x36b7, 0x36b1, 0x36ab, 0x36a6, 0x36a0, 0x369a, 0x3695, 0x368f,
+ 0x3689, 0x3684, 0x367e, 0x3678, 0x3673, 0x366d, 0x3667, 0x3662,
+ 0x365c, 0x3656, 0x3650, 0x364b, 0x3645, 0x363f, 0x363a, 0x3634,
+ 0x362e, 0x3629, 0x3623, 0x361d, 0x3618, 0x3612, 0x360c, 0x3606,
+ 0x3601, 0x35fb, 0x35f5, 0x35f0, 0x35ea, 0x35e4, 0x35df, 0x35d9,
+ 0x35d3, 0x35cd, 0x35c8, 0x35c2, 0x35bc, 0x35b7, 0x35b1, 0x35ab,
+ 0x35a6, 0x35a0, 0x359a, 0x3594, 0x358f, 0x3589, 0x3583, 0x357e,
+ 0x3578, 0x3572, 0x356c, 0x3567, 0x3561, 0x355b, 0x3556, 0x3550,
+ 0x354a, 0x3544, 0x353f, 0x3539, 0x3533, 0x352e, 0x3528, 0x3522,
+ 0x351c, 0x3517, 0x3511, 0x350b, 0x3506, 0x3500, 0x34fa, 0x34f4,
+ 0x34ef, 0x34e9, 0x34e3, 0x34de, 0x34d8, 0x34d2, 0x34cc, 0x34c7,
+ 0x34c1, 0x34bb, 0x34b6, 0x34b0, 0x34aa, 0x34a4, 0x349f, 0x3499,
+ 0x3493, 0x348d, 0x3488, 0x3482, 0x347c, 0x3476, 0x3471, 0x346b,
+ 0x3465, 0x3460, 0x345a, 0x3454, 0x344e, 0x3449, 0x3443, 0x343d,
+ 0x3437, 0x3432, 0x342c, 0x3426, 0x3420, 0x341b, 0x3415, 0x340f,
+ 0x340a, 0x3404, 0x33fe, 0x33f8, 0x33f3, 0x33ed, 0x33e7, 0x33e1,
+ 0x33dc, 0x33d6, 0x33d0, 0x33ca, 0x33c5, 0x33bf, 0x33b9, 0x33b3,
+ 0x33ae, 0x33a8, 0x33a2, 0x339c, 0x3397, 0x3391, 0x338b, 0x3385,
+ 0x3380, 0x337a, 0x3374, 0x336e, 0x3369, 0x3363, 0x335d, 0x3357,
+ 0x3352, 0x334c, 0x3346, 0x3340, 0x333b, 0x3335, 0x332f, 0x3329,
+ 0x3324, 0x331e, 0x3318, 0x3312, 0x330c, 0x3307, 0x3301, 0x32fb,
+ 0x32f5, 0x32f0, 0x32ea, 0x32e4, 0x32de, 0x32d9, 0x32d3, 0x32cd,
+ 0x32c7, 0x32c2, 0x32bc, 0x32b6, 0x32b0, 0x32aa, 0x32a5, 0x329f,
+ 0x3299, 0x3293, 0x328e, 0x3288, 0x3282, 0x327c, 0x3276, 0x3271,
+ 0x326b, 0x3265, 0x325f, 0x325a, 0x3254, 0x324e, 0x3248, 0x3243,
+ 0x323d, 0x3237, 0x3231, 0x322b, 0x3226, 0x3220, 0x321a, 0x3214,
+ 0x320e, 0x3209, 0x3203, 0x31fd, 0x31f7, 0x31f2, 0x31ec, 0x31e6,
+ 0x31e0, 0x31da, 0x31d5, 0x31cf, 0x31c9, 0x31c3, 0x31bd, 0x31b8,
+ 0x31b2, 0x31ac, 0x31a6, 0x31a1, 0x319b, 0x3195, 0x318f, 0x3189,
+ 0x3184, 0x317e, 0x3178, 0x3172, 0x316c, 0x3167, 0x3161, 0x315b,
+ 0x3155, 0x314f, 0x314a, 0x3144, 0x313e, 0x3138, 0x3132, 0x312d,
+ 0x3127, 0x3121, 0x311b, 0x3115, 0x3110, 0x310a, 0x3104, 0x30fe,
+ 0x30f8, 0x30f3, 0x30ed, 0x30e7, 0x30e1, 0x30db, 0x30d6, 0x30d0,
+ 0x30ca, 0x30c4, 0x30be, 0x30b8, 0x30b3, 0x30ad, 0x30a7, 0x30a1,
+ 0x309b, 0x3096, 0x3090, 0x308a, 0x3084, 0x307e, 0x3079, 0x3073,
+ 0x306d, 0x3067, 0x3061, 0x305b, 0x3056, 0x3050, 0x304a, 0x3044,
+ 0x303e, 0x3039, 0x3033, 0x302d, 0x3027, 0x3021, 0x301b, 0x3016,
+ 0x3010, 0x300a, 0x3004, 0x2ffe, 0x2ff8, 0x2ff3, 0x2fed, 0x2fe7,
+ 0x2fe1, 0x2fdb, 0x2fd6, 0x2fd0, 0x2fca, 0x2fc4, 0x2fbe, 0x2fb8,
+ 0x2fb3, 0x2fad, 0x2fa7, 0x2fa1, 0x2f9b, 0x2f95, 0x2f90, 0x2f8a,
+ 0x2f84, 0x2f7e, 0x2f78, 0x2f72, 0x2f6d, 0x2f67, 0x2f61, 0x2f5b,
+ 0x2f55, 0x2f4f, 0x2f4a, 0x2f44, 0x2f3e, 0x2f38, 0x2f32, 0x2f2c,
+ 0x2f27, 0x2f21, 0x2f1b, 0x2f15, 0x2f0f, 0x2f09, 0x2f03, 0x2efe,
+ 0x2ef8, 0x2ef2, 0x2eec, 0x2ee6, 0x2ee0, 0x2edb, 0x2ed5, 0x2ecf,
+ 0x2ec9, 0x2ec3, 0x2ebd, 0x2eb7, 0x2eb2, 0x2eac, 0x2ea6, 0x2ea0,
+ 0x2e9a, 0x2e94, 0x2e8e, 0x2e89, 0x2e83, 0x2e7d, 0x2e77, 0x2e71,
+ 0x2e6b, 0x2e65, 0x2e60, 0x2e5a, 0x2e54, 0x2e4e, 0x2e48, 0x2e42,
+ 0x2e3c, 0x2e37, 0x2e31, 0x2e2b, 0x2e25, 0x2e1f, 0x2e19, 0x2e13,
+ 0x2e0e, 0x2e08, 0x2e02, 0x2dfc, 0x2df6, 0x2df0, 0x2dea, 0x2de5,
+ 0x2ddf, 0x2dd9, 0x2dd3, 0x2dcd, 0x2dc7, 0x2dc1, 0x2dbb, 0x2db6,
+ 0x2db0, 0x2daa, 0x2da4, 0x2d9e, 0x2d98, 0x2d92, 0x2d8d, 0x2d87,
+ 0x2d81, 0x2d7b, 0x2d75, 0x2d6f, 0x2d69, 0x2d63, 0x2d5e, 0x2d58,
+ 0x2d52, 0x2d4c, 0x2d46, 0x2d40, 0x2d3a, 0x2d34, 0x2d2f, 0x2d29,
+ 0x2d23, 0x2d1d, 0x2d17, 0x2d11, 0x2d0b, 0x2d05, 0x2cff, 0x2cfa,
+ 0x2cf4, 0x2cee, 0x2ce8, 0x2ce2, 0x2cdc, 0x2cd6, 0x2cd0, 0x2ccb,
+ 0x2cc5, 0x2cbf, 0x2cb9, 0x2cb3, 0x2cad, 0x2ca7, 0x2ca1, 0x2c9b,
+ 0x2c96, 0x2c90, 0x2c8a, 0x2c84, 0x2c7e, 0x2c78, 0x2c72, 0x2c6c,
+ 0x2c66, 0x2c61, 0x2c5b, 0x2c55, 0x2c4f, 0x2c49, 0x2c43, 0x2c3d,
+ 0x2c37, 0x2c31, 0x2c2b, 0x2c26, 0x2c20, 0x2c1a, 0x2c14, 0x2c0e,
+ 0x2c08, 0x2c02, 0x2bfc, 0x2bf6, 0x2bf0, 0x2beb, 0x2be5, 0x2bdf,
+ 0x2bd9, 0x2bd3, 0x2bcd, 0x2bc7, 0x2bc1, 0x2bbb, 0x2bb5, 0x2bb0,
+ 0x2baa, 0x2ba4, 0x2b9e, 0x2b98, 0x2b92, 0x2b8c, 0x2b86, 0x2b80,
+ 0x2b7a, 0x2b74, 0x2b6f, 0x2b69, 0x2b63, 0x2b5d, 0x2b57, 0x2b51,
+ 0x2b4b, 0x2b45, 0x2b3f, 0x2b39, 0x2b33, 0x2b2d, 0x2b28, 0x2b22,
+ 0x2b1c, 0x2b16, 0x2b10, 0x2b0a, 0x2b04, 0x2afe, 0x2af8, 0x2af2,
+ 0x2aec, 0x2ae6, 0x2ae1, 0x2adb, 0x2ad5, 0x2acf, 0x2ac9, 0x2ac3,
+ 0x2abd, 0x2ab7, 0x2ab1, 0x2aab, 0x2aa5, 0x2a9f, 0x2a99, 0x2a94,
+ 0x2a8e, 0x2a88, 0x2a82, 0x2a7c, 0x2a76, 0x2a70, 0x2a6a, 0x2a64,
+ 0x2a5e, 0x2a58, 0x2a52, 0x2a4c, 0x2a47, 0x2a41, 0x2a3b, 0x2a35,
+ 0x2a2f, 0x2a29, 0x2a23, 0x2a1d, 0x2a17, 0x2a11, 0x2a0b, 0x2a05,
+ 0x29ff, 0x29f9, 0x29f3, 0x29ee, 0x29e8, 0x29e2, 0x29dc, 0x29d6,
+ 0x29d0, 0x29ca, 0x29c4, 0x29be, 0x29b8, 0x29b2, 0x29ac, 0x29a6,
+ 0x29a0, 0x299a, 0x2994, 0x298e, 0x2989, 0x2983, 0x297d, 0x2977,
+ 0x2971, 0x296b, 0x2965, 0x295f, 0x2959, 0x2953, 0x294d, 0x2947,
+ 0x2941, 0x293b, 0x2935, 0x292f, 0x2929, 0x2923, 0x291d, 0x2918,
+ 0x2912, 0x290c, 0x2906, 0x2900, 0x28fa, 0x28f4, 0x28ee, 0x28e8,
+ 0x28e2, 0x28dc, 0x28d6, 0x28d0, 0x28ca, 0x28c4, 0x28be, 0x28b8,
+ 0x28b2, 0x28ac, 0x28a6, 0x28a0, 0x289a, 0x2895, 0x288f, 0x2889,
+ 0x2883, 0x287d, 0x2877, 0x2871, 0x286b, 0x2865, 0x285f, 0x2859,
+ 0x2853, 0x284d, 0x2847, 0x2841, 0x283b, 0x2835, 0x282f, 0x2829,
+ 0x2823, 0x281d, 0x2817, 0x2811, 0x280b, 0x2805, 0x27ff, 0x27f9,
+ 0x27f3, 0x27ee, 0x27e8, 0x27e2, 0x27dc, 0x27d6, 0x27d0, 0x27ca,
+ 0x27c4, 0x27be, 0x27b8, 0x27b2, 0x27ac, 0x27a6, 0x27a0, 0x279a,
+ 0x2794, 0x278e, 0x2788, 0x2782, 0x277c, 0x2776, 0x2770, 0x276a,
+ 0x2764, 0x275e, 0x2758, 0x2752, 0x274c, 0x2746, 0x2740, 0x273a,
+ 0x2734, 0x272e, 0x2728, 0x2722, 0x271c, 0x2716, 0x2710, 0x270a,
+ 0x2704, 0x26fe, 0x26f8, 0x26f2, 0x26ec, 0x26e7, 0x26e1, 0x26db,
+ 0x26d5, 0x26cf, 0x26c9, 0x26c3, 0x26bd, 0x26b7, 0x26b1, 0x26ab,
+ 0x26a5, 0x269f, 0x2699, 0x2693, 0x268d, 0x2687, 0x2681, 0x267b,
+ 0x2675, 0x266f, 0x2669, 0x2663, 0x265d, 0x2657, 0x2651, 0x264b,
+ 0x2645, 0x263f, 0x2639, 0x2633, 0x262d, 0x2627, 0x2621, 0x261b,
+ 0x2615, 0x260f, 0x2609, 0x2603, 0x25fd, 0x25f7, 0x25f1, 0x25eb,
+ 0x25e5, 0x25df, 0x25d9, 0x25d3, 0x25cd, 0x25c7, 0x25c1, 0x25bb,
+ 0x25b5, 0x25af, 0x25a9, 0x25a3, 0x259d, 0x2597, 0x2591, 0x258b,
+ 0x2585, 0x257f, 0x2579, 0x2573, 0x256d, 0x2567, 0x2561, 0x255b,
+ 0x2555, 0x254f, 0x2549, 0x2543, 0x253d, 0x2537, 0x2531, 0x252b,
+ 0x2525, 0x251f, 0x2519, 0x2513, 0x250c, 0x2506, 0x2500, 0x24fa,
+ 0x24f4, 0x24ee, 0x24e8, 0x24e2, 0x24dc, 0x24d6, 0x24d0, 0x24ca,
+ 0x24c4, 0x24be, 0x24b8, 0x24b2, 0x24ac, 0x24a6, 0x24a0, 0x249a,
+ 0x2494, 0x248e, 0x2488, 0x2482, 0x247c, 0x2476, 0x2470, 0x246a,
+ 0x2464, 0x245e, 0x2458, 0x2452, 0x244c, 0x2446, 0x2440, 0x243a,
+ 0x2434, 0x242e, 0x2428, 0x2422, 0x241c, 0x2416, 0x2410, 0x240a,
+ 0x2404, 0x23fd, 0x23f7, 0x23f1, 0x23eb, 0x23e5, 0x23df, 0x23d9,
+ 0x23d3, 0x23cd, 0x23c7, 0x23c1, 0x23bb, 0x23b5, 0x23af, 0x23a9,
+ 0x23a3, 0x239d, 0x2397, 0x2391, 0x238b, 0x2385, 0x237f, 0x2379,
+ 0x2373, 0x236d, 0x2367, 0x2361, 0x235b, 0x2355, 0x234e, 0x2348,
+ 0x2342, 0x233c, 0x2336, 0x2330, 0x232a, 0x2324, 0x231e, 0x2318,
+ 0x2312, 0x230c, 0x2306, 0x2300, 0x22fa, 0x22f4, 0x22ee, 0x22e8,
+ 0x22e2, 0x22dc, 0x22d6, 0x22d0, 0x22ca, 0x22c4, 0x22bd, 0x22b7,
+ 0x22b1, 0x22ab, 0x22a5, 0x229f, 0x2299, 0x2293, 0x228d, 0x2287,
+ 0x2281, 0x227b, 0x2275, 0x226f, 0x2269, 0x2263, 0x225d, 0x2257,
+ 0x2251, 0x224a, 0x2244, 0x223e, 0x2238, 0x2232, 0x222c, 0x2226,
+ 0x2220, 0x221a, 0x2214, 0x220e, 0x2208, 0x2202, 0x21fc, 0x21f6,
+ 0x21f0, 0x21ea, 0x21e4, 0x21dd, 0x21d7, 0x21d1, 0x21cb, 0x21c5,
+ 0x21bf, 0x21b9, 0x21b3, 0x21ad, 0x21a7, 0x21a1, 0x219b, 0x2195,
+ 0x218f, 0x2189, 0x2183, 0x217c, 0x2176, 0x2170, 0x216a, 0x2164,
+ 0x215e, 0x2158, 0x2152, 0x214c, 0x2146, 0x2140, 0x213a, 0x2134,
+ 0x212e, 0x2128, 0x2121, 0x211b, 0x2115, 0x210f, 0x2109, 0x2103,
+ 0x20fd, 0x20f7, 0x20f1, 0x20eb, 0x20e5, 0x20df, 0x20d9, 0x20d3,
+ 0x20cc, 0x20c6, 0x20c0, 0x20ba, 0x20b4, 0x20ae, 0x20a8, 0x20a2,
+ 0x209c, 0x2096, 0x2090, 0x208a, 0x2084, 0x207e, 0x2077, 0x2071,
+ 0x206b, 0x2065, 0x205f, 0x2059, 0x2053, 0x204d, 0x2047, 0x2041,
+ 0x203b, 0x2035, 0x202e, 0x2028, 0x2022, 0x201c, 0x2016, 0x2010,
+ 0x200a, 0x2004, 0x1ffe, 0x1ff8, 0x1ff2, 0x1fec, 0x1fe5, 0x1fdf,
+ 0x1fd9, 0x1fd3, 0x1fcd, 0x1fc7, 0x1fc1, 0x1fbb, 0x1fb5, 0x1faf,
+ 0x1fa9, 0x1fa3, 0x1f9c, 0x1f96, 0x1f90, 0x1f8a, 0x1f84, 0x1f7e,
+ 0x1f78, 0x1f72, 0x1f6c, 0x1f66, 0x1f60, 0x1f59, 0x1f53, 0x1f4d,
+ 0x1f47, 0x1f41, 0x1f3b, 0x1f35, 0x1f2f, 0x1f29, 0x1f23, 0x1f1d,
+ 0x1f16, 0x1f10, 0x1f0a, 0x1f04, 0x1efe, 0x1ef8, 0x1ef2, 0x1eec,
+ 0x1ee6, 0x1ee0, 0x1ed9, 0x1ed3, 0x1ecd, 0x1ec7, 0x1ec1, 0x1ebb,
+ 0x1eb5, 0x1eaf, 0x1ea9, 0x1ea3, 0x1e9c, 0x1e96, 0x1e90, 0x1e8a,
+ 0x1e84, 0x1e7e, 0x1e78, 0x1e72, 0x1e6c, 0x1e66, 0x1e5f, 0x1e59,
+ 0x1e53, 0x1e4d, 0x1e47, 0x1e41, 0x1e3b, 0x1e35, 0x1e2f, 0x1e29,
+ 0x1e22, 0x1e1c, 0x1e16, 0x1e10, 0x1e0a, 0x1e04, 0x1dfe, 0x1df8,
+ 0x1df2, 0x1deb, 0x1de5, 0x1ddf, 0x1dd9, 0x1dd3, 0x1dcd, 0x1dc7,
+ 0x1dc1, 0x1dbb, 0x1db4, 0x1dae, 0x1da8, 0x1da2, 0x1d9c, 0x1d96,
+ 0x1d90, 0x1d8a, 0x1d84, 0x1d7d, 0x1d77, 0x1d71, 0x1d6b, 0x1d65,
+ 0x1d5f, 0x1d59, 0x1d53, 0x1d4c, 0x1d46, 0x1d40, 0x1d3a, 0x1d34,
+ 0x1d2e, 0x1d28, 0x1d22, 0x1d1c, 0x1d15, 0x1d0f, 0x1d09, 0x1d03,
+ 0x1cfd, 0x1cf7, 0x1cf1, 0x1ceb, 0x1ce4, 0x1cde, 0x1cd8, 0x1cd2,
+ 0x1ccc, 0x1cc6, 0x1cc0, 0x1cba, 0x1cb3, 0x1cad, 0x1ca7, 0x1ca1,
+ 0x1c9b, 0x1c95, 0x1c8f, 0x1c89, 0x1c83, 0x1c7c, 0x1c76, 0x1c70,
+ 0x1c6a, 0x1c64, 0x1c5e, 0x1c58, 0x1c51, 0x1c4b, 0x1c45, 0x1c3f,
+ 0x1c39, 0x1c33, 0x1c2d, 0x1c27, 0x1c20, 0x1c1a, 0x1c14, 0x1c0e,
+ 0x1c08, 0x1c02, 0x1bfc, 0x1bf6, 0x1bef, 0x1be9, 0x1be3, 0x1bdd,
+ 0x1bd7, 0x1bd1, 0x1bcb, 0x1bc4, 0x1bbe, 0x1bb8, 0x1bb2, 0x1bac,
+ 0x1ba6, 0x1ba0, 0x1b9a, 0x1b93, 0x1b8d, 0x1b87, 0x1b81, 0x1b7b,
+ 0x1b75, 0x1b6f, 0x1b68, 0x1b62, 0x1b5c, 0x1b56, 0x1b50, 0x1b4a,
+ 0x1b44, 0x1b3d, 0x1b37, 0x1b31, 0x1b2b, 0x1b25, 0x1b1f, 0x1b19,
+ 0x1b13, 0x1b0c, 0x1b06, 0x1b00, 0x1afa, 0x1af4, 0x1aee, 0x1ae8,
+ 0x1ae1, 0x1adb, 0x1ad5, 0x1acf, 0x1ac9, 0x1ac3, 0x1abd, 0x1ab6,
+ 0x1ab0, 0x1aaa, 0x1aa4, 0x1a9e, 0x1a98, 0x1a91, 0x1a8b, 0x1a85,
+ 0x1a7f, 0x1a79, 0x1a73, 0x1a6d, 0x1a66, 0x1a60, 0x1a5a, 0x1a54,
+ 0x1a4e, 0x1a48, 0x1a42, 0x1a3b, 0x1a35, 0x1a2f, 0x1a29, 0x1a23,
+ 0x1a1d, 0x1a17, 0x1a10, 0x1a0a, 0x1a04, 0x19fe, 0x19f8, 0x19f2,
+ 0x19eb, 0x19e5, 0x19df, 0x19d9, 0x19d3, 0x19cd, 0x19c7, 0x19c0,
+ 0x19ba, 0x19b4, 0x19ae, 0x19a8, 0x19a2, 0x199b, 0x1995, 0x198f,
+ 0x1989, 0x1983, 0x197d, 0x1977, 0x1970, 0x196a, 0x1964, 0x195e,
+ 0x1958, 0x1952, 0x194b, 0x1945, 0x193f, 0x1939, 0x1933, 0x192d,
+ 0x1926, 0x1920, 0x191a, 0x1914, 0x190e, 0x1908, 0x1901, 0x18fb,
+ 0x18f5, 0x18ef, 0x18e9, 0x18e3, 0x18dc, 0x18d6, 0x18d0, 0x18ca,
+ 0x18c4, 0x18be, 0x18b8, 0x18b1, 0x18ab, 0x18a5, 0x189f, 0x1899,
+ 0x1893, 0x188c, 0x1886, 0x1880, 0x187a, 0x1874, 0x186e, 0x1867,
+ 0x1861, 0x185b, 0x1855, 0x184f, 0x1848, 0x1842, 0x183c, 0x1836,
+ 0x1830, 0x182a, 0x1823, 0x181d, 0x1817, 0x1811, 0x180b, 0x1805,
+ 0x17fe, 0x17f8, 0x17f2, 0x17ec, 0x17e6, 0x17e0, 0x17d9, 0x17d3,
+ 0x17cd, 0x17c7, 0x17c1, 0x17bb, 0x17b4, 0x17ae, 0x17a8, 0x17a2,
+ 0x179c, 0x1795, 0x178f, 0x1789, 0x1783, 0x177d, 0x1777, 0x1770,
+ 0x176a, 0x1764, 0x175e, 0x1758, 0x1752, 0x174b, 0x1745, 0x173f,
+ 0x1739, 0x1733, 0x172c, 0x1726, 0x1720, 0x171a, 0x1714, 0x170e,
+ 0x1707, 0x1701, 0x16fb, 0x16f5, 0x16ef, 0x16e8, 0x16e2, 0x16dc,
+ 0x16d6, 0x16d0, 0x16ca, 0x16c3, 0x16bd, 0x16b7, 0x16b1, 0x16ab,
+ 0x16a4, 0x169e, 0x1698, 0x1692, 0x168c, 0x1686, 0x167f, 0x1679,
+ 0x1673, 0x166d, 0x1667, 0x1660, 0x165a, 0x1654, 0x164e, 0x1648,
+ 0x1642, 0x163b, 0x1635, 0x162f, 0x1629, 0x1623, 0x161c, 0x1616,
+ 0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,
+ 0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,
+ 0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,
+ 0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,
+ 0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,
+ 0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,
+ 0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,
+ 0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,
+ 0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,
+ 0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,
+ 0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,
+ 0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,
+ 0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,
+ 0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,
+ 0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,
+ 0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,
+ 0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,
+ 0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,
+ 0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,
+ 0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,
+ 0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,
+ 0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,
+ 0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,
+ 0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,
+ 0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,
+ 0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,
+ 0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,
+ 0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,
+ 0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,
+ 0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,
+ 0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,
+ 0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,
+ 0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,
+ 0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,
+ 0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,
+ 0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,
+ 0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,
+ 0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,
+ 0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,
+ 0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,
+ 0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,
+ 0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,
+ 0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,
+ 0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,
+ 0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,
+ 0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,
+ 0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,
+ 0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,
+ 0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,
+ 0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,
+ 0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,
+ 0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,
+ 0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,
+ 0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,
+ 0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,
+ 0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,
+ 0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,
+ 0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,
+ 0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,
+ 0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,
+ 0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,
+ 0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,
+ 0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,
+ 0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,
+ 0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,
+ 0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,
+ 0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,
+ 0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,
+ 0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,
+ 0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,
+ 0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,
+ 0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,
+ 0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,
+ 0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,
+ 0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,
+ 0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,
+ 0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,
+ 0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,
+ 0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,
+ 0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,
+ 0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,
+ 0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,
+ 0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,
+ 0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,
+ 0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,
+ 0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,
+ 0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,
+ 0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,
+ 0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,
+ 0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,
+ 0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,
+ 0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,
+ 0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,
+ 0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,
+ 0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,
+ 0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,
+ 0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,
+ 0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,
+ 0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,
+ 0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,
+ 0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,
+ 0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,
+ 0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,
+ 0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,
+ 0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,
+ 0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,
+ 0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,
+ 0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,
+ 0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,
+ 0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,
+ 0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,
+ 0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,
+ 0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,
+};
+
+/**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ15Table.gif
+ */
+
+arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+ (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ q15_t *pCosFactor[4] =
+ { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+ (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT */
+ arm_rfft_init_q15(S->pRfft, S->N, 0u, 1u);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,8364 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_q31.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 Q31
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : weights[n] = e^(-j*n*pi/(2*N))
+* \par
+* C command to generate the table
+*
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* }
+* \par
+* where N is the Number of weights to be calculated and c is pi/(2*N)
+* \par
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is 2*N.
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+ 0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+ 0xfb49e6a3,
+ 0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+ 0x7f872bf3, 0xf50497fb,
+ 0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+ 0x7ed5e5c6, 0xeec60f31,
+ 0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+ 0x7dd6668f, 0xe8922622,
+ 0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+ 0x7c894bde, 0xe26cb01b,
+ 0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+ 0x7aef6323, 0xdc597781,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+ 0x7909a92d, 0xd65c3b7b,
+ 0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+ 0x76d94989, 0xd078ad9e,
+ 0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+ 0x745f9dd1, 0xcab26fa9,
+ 0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+ 0x719e2cd2, 0xc50d1149,
+ 0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+ 0x6e96a99d, 0xbf8c0de3,
+ 0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+ 0x6b4af279, 0xba32ca71,
+ 0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+ 0x67bd0fbd, 0xb5049368,
+ 0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+ 0x63ef3290, 0xb0049ab3,
+ 0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+ 0x5fe3b38d, 0xab35f5b5,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+ 0x5b9d1154, 0xa69b9b68,
+ 0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+ 0x571deefa, 0xa2386284,
+ 0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+ 0x5269126e, 0x9e0effc1,
+ 0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+ 0x4d8162c4, 0x9a22042d,
+ 0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+ 0x4869e665, 0x9673db94,
+ 0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+ 0x4325c135, 0x9306cb04,
+ 0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+ 0x3db832a6, 0x8fdcef66,
+ 0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+ 0x382493b0, 0x8cf83c30,
+ 0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+ 0x326e54c7, 0x8a5a7a31,
+ 0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+ 0x2c98fbba, 0x88054677,
+ 0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+ 0x26a82186, 0x85fa1153,
+ 0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+ 0x209f701c, 0x843a1d70,
+ 0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+ 0x1a82a026, 0x82c67f14,
+ 0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+ 0x145576b1, 0x81a01b6d,
+ 0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+ 0xe1bc2e4, 0x80c7a80a,
+ 0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+ 0x7d95b9e, 0x803daa6a,
+ 0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+ 0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+ 0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+ 0xfed2694f,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+ 0x7ff871a2, 0xfd40565c,
+ 0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+ 0x7fed5791, 0xfbae5e89,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+ 0x7fdd4eec, 0xfa1c9157,
+ 0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+ 0x7fc85854, 0xf88afe42,
+ 0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+ 0x7fae7495, 0xf6f9b4c6,
+ 0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+ 0x7f8fa4b0, 0xf568c45b,
+ 0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+ 0x7f6be9d4, 0xf3d83c77,
+ 0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+ 0x7f434563, 0xf2482c8a,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+ 0x7f15b8ee, 0xf0b8a401,
+ 0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+ 0x7ee34636, 0xef29b243,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+ 0x7eabef2c, 0xed9b66b2,
+ 0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+ 0x7e6fb5f4, 0xec0dd0a8,
+ 0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+ 0x7e2e9cdf, 0xea80ff7a,
+ 0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+ 0x7de8a670, 0xe8f50273,
+ 0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+ 0x7d9dd55a, 0xe769e8d8,
+ 0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+ 0x7d4e2c7f, 0xe5dfc1e5,
+ 0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+ 0x7cf9aef0, 0xe4569ccb,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+ 0x7ca05ff1, 0xe2ce88b3,
+ 0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+ 0x7c4242f2, 0xe14794ba,
+ 0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+ 0x7bdf5b94, 0xdfc1cff3,
+ 0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+ 0x7b77ada8, 0xde3d4964,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+ 0x7b0b3d2c, 0xdcba1008,
+ 0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+ 0x7a9a0e50, 0xdb3832cd,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+ 0x7a24256f, 0xd9b7c094,
+ 0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+ 0x79a98715, 0xd838c82d,
+ 0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+ 0x792a37fe, 0xd6bb585e,
+ 0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+ 0x78a63d11, 0xd53f7fda,
+ 0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+ 0x781d9b65, 0xd3c54d47,
+ 0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+ 0x7790583e, 0xd24ccf39,
+ 0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+ 0x76fe790e, 0xd0d61434,
+ 0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+ 0x76680376, 0xcf612aaa,
+ 0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+ 0x75ccfd42, 0xcdee20fc,
+ 0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+ 0x752d6c6c, 0xcc7d0578,
+ 0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+ 0x7489571c, 0xcb0de658,
+ 0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+ 0x73e0c3a3, 0xc9a0d1c5,
+ 0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+ 0x7333b883, 0xc835d5d0,
+ 0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+ 0x72823c67, 0xc6cd0079,
+ 0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+ 0x71cc5626, 0xc5665fa9,
+ 0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+ 0x71120cc5, 0xc4020133,
+ 0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+ 0x70536771, 0xc29ff2d4,
+ 0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+ 0x6f906d84, 0xc1404233,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+ 0x6ec92683, 0xbfe2fcdf,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+ 0x6dfd9a1c, 0xbe88304f,
+ 0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+ 0x6d2dd027, 0xbd2fe9e2,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+ 0x6c59d0a9, 0xbbda36dd,
+ 0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+ 0x6b81a3cd, 0xba87246d,
+ 0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+ 0x6aa551e9, 0xb936bfa4,
+ 0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+ 0x69c4e37a, 0xb7e9157a,
+ 0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+ 0x68e06129, 0xb69e32cd,
+ 0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+ 0x67f7d3c5, 0xb556245e,
+ 0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+ 0x670b4444, 0xb410f6d3,
+ 0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+ 0x661abbc5, 0xb2ceb6b5,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+ 0x6526438f, 0xb18f7071,
+ 0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+ 0x642de50d, 0xb0533055,
+ 0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+ 0x6331a9d4, 0xaf1a0293,
+ 0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+ 0x62319b9d, 0xade3f33e,
+ 0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+ 0x612dc447, 0xacb10e4b,
+ 0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+ 0x60262dd6, 0xab815f8d,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+ 0x5f1ae274, 0xaa54f2ba,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+ 0x5e0bec6e, 0xa92bd367,
+ 0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+ 0x5cf95638, 0xa8060d08,
+ 0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+ 0x5be32a67, 0xa6e3aaf2,
+ 0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+ 0x5ac973b5, 0xa5c4b855,
+ 0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+ 0x59ac3cfd, 0xa4a94043,
+ 0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+ 0x588b9140, 0xa3914da8,
+ 0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+ 0x57677b9d, 0xa27ceb4f,
+ 0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+ 0x56400758, 0xa16c23e1,
+ 0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+ 0x55153fd4, 0xa05f01e1,
+ 0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+ 0x53e73097, 0x9f558fb0,
+ 0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+ 0x52b5e546, 0x9e4fd78a,
+ 0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+ 0x518169a5, 0x9d4de385,
+ 0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+ 0x5049c999, 0x9c4fbd93,
+ 0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+ 0x4f0f1126, 0x9b556f81,
+ 0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+ 0x4dd14c6e, 0x9a5f02f5,
+ 0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+ 0x4c9087b1, 0x996c816f,
+ 0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+ 0x4b4ccf4d, 0x987df449,
+ 0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+ 0x4a062fbd, 0x979364b5,
+ 0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+ 0x48bcb599, 0x96acdbbe,
+ 0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+ 0x47706d93, 0x95ca6247,
+ 0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+ 0x4621647d, 0x94ec010b,
+ 0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+ 0x44cfa740, 0x9411c09e,
+ 0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+ 0x437b42e1, 0x933ba968,
+ 0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+ 0x42244481, 0x9269c3ac,
+ 0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+ 0x40cab958, 0x919c1781,
+ 0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+ 0x3f6eaeb8, 0x90d2acd4,
+ 0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+ 0x3e10320d, 0x900d8b69,
+ 0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+ 0x3caf50da, 0x8f4cbadb,
+ 0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+ 0x3b4c18ba, 0x8e904298,
+ 0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+ 0x39e6975e, 0x8dd829e4,
+ 0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+ 0x387eda8e, 0x8d2477d8,
+ 0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+ 0x3714f02a, 0x8c753362,
+ 0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+ 0x35a8e625, 0x8bca6343,
+ 0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+ 0x343aca87, 0x8b240e11,
+ 0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+ 0x32caab6f, 0x8a823a36,
+ 0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+ 0x3158970e, 0x89e4edef,
+ 0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+ 0x2fe49ba7, 0x894c2f4c,
+ 0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+ 0x2e6ec792, 0x88b80432,
+ 0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+ 0x2cf72939, 0x88287256,
+ 0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+ 0x2b7dcf17, 0x879d7f41,
+ 0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+ 0x2a02c7b8, 0x8717304e,
+ 0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+ 0x288621b9, 0x86958aac,
+ 0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+ 0x2707ebc7, 0x86189359,
+ 0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+ 0x2588349d, 0x85a04f28,
+ 0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+ 0x24070b08, 0x852cc2bb,
+ 0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+ 0x22847de0, 0x84bdf286,
+ 0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+ 0x21009c0c, 0x8453e2cf,
+ 0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+ 0x1f7b7481, 0x83ee97ad,
+ 0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+ 0x1df5163f, 0x838e1507,
+ 0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+ 0x1c6d9053, 0x83325e97,
+ 0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+ 0x1ae4f1d6, 0x82db77e5,
+ 0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+ 0x195b49ea, 0x8289644b,
+ 0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+ 0x17d0a7bc, 0x823c26f3,
+ 0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+ 0x16451a83, 0x81f3c2d7,
+ 0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+ 0x14b8b17f, 0x81b03ac2,
+ 0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+ 0x132b7bf9, 0x8171914e,
+ 0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+ 0x119d8941, 0x8137c8e6,
+ 0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+ 0x100ee8ad, 0x8102e3c4,
+ 0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+ 0xe7fa99e, 0x80d2e3f2,
+ 0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+ 0xcefdb76, 0x80a7cb49,
+ 0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+ 0xb5f8d9f, 0x80819b74,
+ 0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+ 0x9cecf89, 0x806055eb,
+ 0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+ 0x83db0a7, 0x8043fbf6,
+ 0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+ 0x6ac406f, 0x802c8ead,
+ 0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+ 0x51a8e5c, 0x801a0ef8,
+ 0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+ 0x388a9ea, 0x800c7d8c,
+ 0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+ 0x1f6a297, 0x8003daf1,
+ 0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+ 0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+ 0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+ 0xffb49a12,
+ 0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+ 0x7fff8719, 0xff501258,
+ 0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+ 0x7ffed572, 0xfeeb8b0a,
+ 0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+ 0x7ffdd4d7, 0xfe870467,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+ 0x7ffc8549, 0xfe227eac,
+ 0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+ 0x7ffae6c7, 0xfdbdfa18,
+ 0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+ 0x7ff8f954, 0xfd5976e9,
+ 0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+ 0x7ff6bcf0, 0xfcf4f55c,
+ 0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+ 0x7ff4319d, 0xfc9075af,
+ 0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+ 0x7ff1575d, 0xfc2bf821,
+ 0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+ 0x7fee2e30, 0xfbc77cf0,
+ 0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+ 0x7feab61a, 0xfb630459,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+ 0x7fe6ef1c, 0xfafe8e9b,
+ 0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+ 0x7fe2d938, 0xfa9a1bf3,
+ 0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+ 0x7fde7471, 0xfa35ac9f,
+ 0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+ 0x7fd9c0ca, 0xf9d140de,
+ 0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+ 0x7fd4be46, 0xf96cd8ed,
+ 0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+ 0x7fcf6ce8, 0xf908750a,
+ 0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+ 0x7fc9ccb2, 0xf8a41574,
+ 0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+ 0x7fc3dda9, 0xf83fba68,
+ 0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+ 0x7fbd9fd0, 0xf7db6423,
+ 0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+ 0x7fb7132b, 0xf77712e5,
+ 0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+ 0x7fb037bf, 0xf712c6ea,
+ 0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+ 0x7fa90d8e, 0xf6ae8071,
+ 0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+ 0x7fa1949e, 0xf64a3fb8,
+ 0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+ 0x7f99ccf4, 0xf5e604fc,
+ 0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+ 0x7f91b694, 0xf581d07b,
+ 0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+ 0x7f895182, 0xf51da273,
+ 0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+ 0x7f809dc5, 0xf4b97b21,
+ 0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+ 0x7f779b62, 0xf4555ac5,
+ 0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+ 0x7f6e4a5e, 0xf3f1419a,
+ 0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+ 0x7f64aabf, 0xf38d2fe0,
+ 0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+ 0x7f5abc8a, 0xf32925d3,
+ 0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+ 0x7f507fc7, 0xf2c523b2,
+ 0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+ 0x7f45f47b, 0xf26129ba,
+ 0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+ 0x7f3b1aad, 0xf1fd3829,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+ 0x7f2ff263, 0xf1994f3d,
+ 0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+ 0x7f247ba5, 0xf1356f32,
+ 0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+ 0x7f18b679, 0xf0d19848,
+ 0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+ 0x7f0ca2e7, 0xf06dcaba,
+ 0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+ 0x7f0040f6, 0xf00a06c8,
+ 0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+ 0x7ef390ae, 0xefa64cae,
+ 0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+ 0x7ee69217, 0xef429caa,
+ 0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+ 0x7ed94538, 0xeedef6f9,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+ 0x7ecbaa1a, 0xee7b5bd9,
+ 0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+ 0x7ebdc0c6, 0xee17cb88,
+ 0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+ 0x7eaf8943, 0xedb44642,
+ 0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+ 0x7ea1039b, 0xed50cc46,
+ 0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+ 0x7e922fd6, 0xeced5dd0,
+ 0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+ 0x7e830dff, 0xec89fb1e,
+ 0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+ 0x7e739e1d, 0xec26a46d,
+ 0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+ 0x7e63e03b, 0xebc359fb,
+ 0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+ 0x7e53d462, 0xeb601c04,
+ 0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+ 0x7e437a9c, 0xeafceac6,
+ 0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+ 0x7e32d2f4, 0xea99c67e,
+ 0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+ 0x7e21dd73, 0xea36af69,
+ 0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+ 0x7e109a24, 0xe9d3a5c5,
+ 0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+ 0x7dff0911, 0xe970a9ce,
+ 0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+ 0x7ded2a47, 0xe90dbbc2,
+ 0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+ 0x7ddafdce, 0xe8aadbde,
+ 0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+ 0x7dc883b4, 0xe8480a5d,
+ 0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+ 0x7db5bc02, 0xe7e5477f,
+ 0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+ 0x7da2a6c6, 0xe782937e,
+ 0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+ 0x7d8f4409, 0xe71fee99,
+ 0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+ 0x7d7b93da, 0xe6bd590d,
+ 0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+ 0x7d679642, 0xe65ad315,
+ 0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+ 0x7d534b50, 0xe5f85cef,
+ 0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+ 0x7d3eb30f, 0xe595f6d7,
+ 0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+ 0x7d29cd8c, 0xe533a10a,
+ 0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+ 0x7d149ad5, 0xe4d15bc6,
+ 0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+ 0x7cff1af5, 0xe46f2745,
+ 0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+ 0x7ce94dfb, 0xe40d03c6,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+ 0x7cd333f3, 0xe3aaf184,
+ 0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+ 0x7cbcccec, 0xe348f0bd,
+ 0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+ 0x7ca618f3, 0xe2e701ac,
+ 0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+ 0x7c8f1817, 0xe285248d,
+ 0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+ 0x7c77ca65, 0xe223599e,
+ 0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+ 0x7c602fec, 0xe1c1a11b,
+ 0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+ 0x7c4848ba, 0xe15ffb3f,
+ 0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+ 0x7c3014de, 0xe0fe6848,
+ 0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+ 0x7c179467, 0xe09ce871,
+ 0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+ 0x7bfec765, 0xe03b7bf6,
+ 0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+ 0x7be5ade6, 0xdfda2314,
+ 0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+ 0x7bcc47fa, 0xdf78de07,
+ 0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+ 0x7bb295b0, 0xdf17ad0a,
+ 0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+ 0x7b989719, 0xdeb69059,
+ 0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+ 0x7b7e4c45, 0xde558831,
+ 0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+ 0x7b63b543, 0xddf494ce,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+ 0x7b48d225, 0xdd93b66a,
+ 0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+ 0x7b2da2fa, 0xdd32ed43,
+ 0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+ 0x7b1227d3, 0xdcd23993,
+ 0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+ 0x7af660c2, 0xdc719b96,
+ 0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+ 0x7ada4dd8, 0xdc111388,
+ 0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+ 0x7abdef25, 0xdbb0a1a4,
+ 0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+ 0x7aa144bc, 0xdb504626,
+ 0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+ 0x7a844eae, 0xdaf00149,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+ 0x7a670d0d, 0xda8fd349,
+ 0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+ 0x7a497feb, 0xda2fbc61,
+ 0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+ 0x7a2ba75a, 0xd9cfbccd,
+ 0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+ 0x7a0d836d, 0xd96fd4c7,
+ 0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+ 0x79ef1436, 0xd910048a,
+ 0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+ 0x79d059c8, 0xd8b04c52,
+ 0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+ 0x79b15435, 0xd850ac5a,
+ 0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+ 0x79920392, 0xd7f124dd,
+ 0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+ 0x797267f2, 0xd791b616,
+ 0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+ 0x79528167, 0xd732603f,
+ 0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+ 0x79325006, 0xd6d32393,
+ 0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+ 0x7911d3e2, 0xd674004e,
+ 0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+ 0x78f10d0f, 0xd614f6a9,
+ 0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+ 0x78cffba3, 0xd5b606e0,
+ 0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+ 0x78ae9fb0, 0xd557312d,
+ 0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+ 0x788cf94c, 0xd4f875ca,
+ 0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+ 0x786b088c, 0xd499d4f2,
+ 0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+ 0x7848cd83, 0xd43b4ee0,
+ 0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+ 0x78264849, 0xd3dce3cd,
+ 0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+ 0x780378f1, 0xd37e93f4,
+ 0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+ 0x77e05f91, 0xd3205f8f,
+ 0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+ 0x77bcfc3f, 0xd2c246d8,
+ 0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+ 0x77994f11, 0xd2644a0a,
+ 0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+ 0x7775581d, 0xd206695d,
+ 0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+ 0x77511778, 0xd1a8a50d,
+ 0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+ 0x772c8d3a, 0xd14afd52,
+ 0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+ 0x7707b979, 0xd0ed7267,
+ 0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+ 0x76e29c4b, 0xd0900486,
+ 0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+ 0x76bd35c7, 0xd032b3e7,
+ 0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+ 0x76978605, 0xcfd580c6,
+ 0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+ 0x76718d1c, 0xcf786b5a,
+ 0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+ 0x764b4b23, 0xcf1b73de,
+ 0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+ 0x7624c031, 0xcebe9a8a,
+ 0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+ 0x75fdec60, 0xce61df99,
+ 0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+ 0x75d6cfc5, 0xce054343,
+ 0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+ 0x75af6a7b, 0xcda8c5c1,
+ 0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+ 0x7587bc98, 0xcd4c674d,
+ 0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+ 0x755fc635, 0xccf0281f,
+ 0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+ 0x7537876c, 0xcc940871,
+ 0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+ 0x750f0054, 0xcc38087b,
+ 0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+ 0x74e63108, 0xcbdc2876,
+ 0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+ 0x74bd199f, 0xcb80689a,
+ 0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+ 0x7493ba34, 0xcb24c921,
+ 0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+ 0x746a12df, 0xcac94a42,
+ 0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+ 0x744023bc, 0xca6dec37,
+ 0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+ 0x7415ece2, 0xca12af37,
+ 0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+ 0x73eb6e6e, 0xc9b7937a,
+ 0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+ 0x73c0a878, 0xc95c993a,
+ 0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+ 0x73959b1b, 0xc901c0ae,
+ 0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+ 0x736a4671, 0xc8a70a0e,
+ 0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+ 0x733eaa96, 0xc84c7593,
+ 0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+ 0x7312c7a5, 0xc7f20373,
+ 0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+ 0x72e69db7, 0xc797b3e7,
+ 0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+ 0x72ba2cea, 0xc73d8727,
+ 0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+ 0x728d7557, 0xc6e37d69,
+ 0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+ 0x7260771b, 0xc68996e7,
+ 0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+ 0x72333251, 0xc62fd3d6,
+ 0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+ 0x7205a716, 0xc5d6346f,
+ 0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+ 0x71d7d585, 0xc57cb8e9,
+ 0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+ 0x71a9bdba, 0xc523617a,
+ 0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+ 0x717b5fd3, 0xc4ca2e5b,
+ 0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+ 0x714cbbeb, 0xc4711fc2,
+ 0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+ 0x711dd220, 0xc41835e6,
+ 0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+ 0x70eea28e, 0xc3bf70fd,
+ 0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+ 0x70bf2d53, 0xc366d140,
+ 0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+ 0x708f728b, 0xc30e56e4,
+ 0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+ 0x705f7255, 0xc2b6021f,
+ 0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+ 0x702f2ccd, 0xc25dd329,
+ 0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+ 0x6ffea212, 0xc205ca38,
+ 0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+ 0x6fcdd241, 0xc1ade781,
+ 0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+ 0x6f9cbd79, 0xc1562b3d,
+ 0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+ 0x6f6b63d8, 0xc0fe959f,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+ 0x6f39c57d, 0xc0a726df,
+ 0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+ 0x6f07e285, 0xc04fdf32,
+ 0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+ 0x6ed5bb10, 0xbff8bece,
+ 0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+ 0x6ea34f3d, 0xbfa1c5ea,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+ 0x6e709f2a, 0xbf4af4ba,
+ 0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+ 0x6e3daaf8, 0xbef44b74,
+ 0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+ 0x6e0a72c5, 0xbe9dca4e,
+ 0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+ 0x6dd6f6b1, 0xbe47717c,
+ 0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+ 0x6da336dc, 0xbdf14135,
+ 0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+ 0x6d6f3365, 0xbd9b39ad,
+ 0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+ 0x6d3aec6e, 0xbd455b1a,
+ 0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+ 0x6d066215, 0xbcefa5b0,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+ 0x6cd1947c, 0xbc9a19a5,
+ 0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+ 0x6c9c83c3, 0xbc44b72c,
+ 0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+ 0x6c67300b, 0xbbef7e7c,
+ 0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+ 0x6c319975, 0xbb9a6fc7,
+ 0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+ 0x6bfbc021, 0xbb458b43,
+ 0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+ 0x6bc5a431, 0xbaf0d125,
+ 0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+ 0x6b8f45c7, 0xba9c41a0,
+ 0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+ 0x6b58a503, 0xba47dce8,
+ 0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+ 0x6b21c208, 0xb9f3a332,
+ 0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+ 0x6aea9cf8, 0xb99f94b2,
+ 0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+ 0x6ab335f4, 0xb94bb19b,
+ 0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+ 0x6a7b8d1e, 0xb8f7fa21,
+ 0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+ 0x6a43a29a, 0xb8a46e78,
+ 0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+ 0x6a0b7689, 0xb8510ed4,
+ 0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+ 0x69d3090e, 0xb7fddb67,
+ 0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+ 0x699a5a4c, 0xb7aad465,
+ 0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+ 0x69616a65, 0xb757fa01,
+ 0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+ 0x6928397e, 0xb7054c6f,
+ 0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+ 0x68eec7b9, 0xb6b2cbe2,
+ 0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+ 0x68b5153a, 0xb660788c,
+ 0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+ 0x687b2224, 0xb60e529f,
+ 0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+ 0x6840ee9b, 0xb5bc5a50,
+ 0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+ 0x68067ac3, 0xb56a8fd0,
+ 0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+ 0x67cbc6c0, 0xb518f351,
+ 0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+ 0x6790d2b6, 0xb4c78507,
+ 0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+ 0x67559eca, 0xb4764523,
+ 0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+ 0x671a2b20, 0xb42533d8,
+ 0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+ 0x66de77dc, 0xb3d45157,
+ 0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+ 0x66a28524, 0xb3839dd3,
+ 0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+ 0x6666531d, 0xb333197c,
+ 0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+ 0x6629e1ec, 0xb2e2c486,
+ 0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+ 0x65ed31b5, 0xb2929f21,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+ 0x65b0429f, 0xb242a97e,
+ 0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+ 0x657314cf, 0xb1f2e3d0,
+ 0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+ 0x6535a86b, 0xb1a34e47,
+ 0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+ 0x64f7fd98, 0xb153e915,
+ 0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+ 0x64ba147d, 0xb104b46a,
+ 0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+ 0x647bed3f, 0xb0b5b077,
+ 0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+ 0x643d8806, 0xb066dd6d,
+ 0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+ 0x63fee4f8, 0xb0183b7d,
+ 0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+ 0x63c0043b, 0xafc9cad7,
+ 0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+ 0x6380e5f6, 0xaf7b8bac,
+ 0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+ 0x63418a50, 0xaf2d7e2b,
+ 0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+ 0x6301f171, 0xaedfa285,
+ 0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+ 0x62c21b7e, 0xae91f8eb,
+ 0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+ 0x628208a1, 0xae44818b,
+ 0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+ 0x6241b8ff, 0xadf73c96,
+ 0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+ 0x62012cc2, 0xadaa2a3b,
+ 0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+ 0x61c06410, 0xad5d4aaa,
+ 0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+ 0x617f5f12, 0xad109e12,
+ 0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+ 0x613e1df0, 0xacc424a3,
+ 0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+ 0x60fca0d2, 0xac77de8b,
+ 0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+ 0x60bae7e1, 0xac2bcbfa,
+ 0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+ 0x6078f344, 0xabdfed1f,
+ 0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+ 0x6036c325, 0xab944229,
+ 0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+ 0x5ff457ad, 0xab48cb46,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+ 0x5fb1b104, 0xaafd88a4,
+ 0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+ 0x5f6ecf53, 0xaab27a73,
+ 0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+ 0x5f2bb2c5, 0xaa67a0e0,
+ 0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+ 0x5ee85b82, 0xaa1cfc1a,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+ 0x5ea4c9b3, 0xa9d28c4e,
+ 0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+ 0x5e60fd84, 0xa98851ac,
+ 0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+ 0x5e1cf71c, 0xa93e4c5f,
+ 0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+ 0x5dd8b6a7, 0xa8f47c97,
+ 0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+ 0x5d943c4e, 0xa8aae280,
+ 0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+ 0x5d4f883b, 0xa8617e48,
+ 0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+ 0x5d0a9a9a, 0xa818501c,
+ 0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+ 0x5cc57394, 0xa7cf582a,
+ 0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+ 0x5c801354, 0xa786969e,
+ 0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+ 0x5c3a7a05, 0xa73e0ba5,
+ 0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+ 0x5bf4a7d2, 0xa6f5b76d,
+ 0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+ 0x5bae9ce7, 0xa6ad9a21,
+ 0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+ 0x5b68596d, 0xa665b3ee,
+ 0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+ 0x5b21dd90, 0xa61e0501,
+ 0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+ 0x5adb297d, 0xa5d68d85,
+ 0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+ 0x5a943d5e, 0xa58f4da8,
+ 0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+ 0x5a4d1960, 0xa5484594,
+ 0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+ 0x5a05bdae, 0xa5017575,
+ 0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+ 0x59be2a74, 0xa4badd78,
+ 0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+ 0x59765fde, 0xa4747dc7,
+ 0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+ 0x592e5e19, 0xa42e568f,
+ 0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+ 0x58e62552, 0xa3e867fa,
+ 0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+ 0x589db5b3, 0xa3a2b234,
+ 0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+ 0x58550f6c, 0xa35d3567,
+ 0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+ 0x580c32a7, 0xa317f1bf,
+ 0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+ 0x57c31f92, 0xa2d2e766,
+ 0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+ 0x5779d65b, 0xa28e1687,
+ 0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+ 0x5730572e, 0xa2497f4c,
+ 0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+ 0x56e6a239, 0xa20521e0,
+ 0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+ 0x569cb7a8, 0xa1c0fe6c,
+ 0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+ 0x565297ab, 0xa17d151b,
+ 0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+ 0x5608426e, 0xa1396617,
+ 0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+ 0x55bdb81f, 0xa0f5f189,
+ 0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+ 0x5572f8ed, 0xa0b2b79b,
+ 0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+ 0x55280505, 0xa06fb876,
+ 0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+ 0x54dcdc96, 0xa02cf444,
+ 0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+ 0x54917fce, 0x9fea6b2f,
+ 0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+ 0x5445eedb, 0x9fa81d5e,
+ 0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+ 0x53fa29ed, 0x9f660afb,
+ 0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+ 0x53ae3131, 0x9f24342f,
+ 0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+ 0x536204d7, 0x9ee29922,
+ 0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+ 0x5315a50e, 0x9ea139fd,
+ 0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+ 0x52c91204, 0x9e6016e8,
+ 0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+ 0x527c4bea, 0x9e1f300b,
+ 0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+ 0x522f52ee, 0x9dde858e,
+ 0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+ 0x51e22740, 0x9d9e179a,
+ 0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+ 0x5194c910, 0x9d5de656,
+ 0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+ 0x5147388c, 0x9d1df1e9,
+ 0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+ 0x50f975e6, 0x9cde3a7b,
+ 0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+ 0x50ab814d, 0x9c9ec033,
+ 0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+ 0x505d5af1, 0x9c5f8339,
+ 0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+ 0x500f0302, 0x9c2083b3,
+ 0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+ 0x4fc079b1, 0x9be1c1c8,
+ 0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+ 0x4f71bf2e, 0x9ba33da0,
+ 0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+ 0x4f22d3aa, 0x9b64f760,
+ 0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+ 0x4ed3b755, 0x9b26ef2f,
+ 0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+ 0x4e846a60, 0x9ae92533,
+ 0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+ 0x4e34ecfc, 0x9aab9993,
+ 0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+ 0x4de53f5a, 0x9a6e4c74,
+ 0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+ 0x4d9561ac, 0x9a313dfc,
+ 0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+ 0x4d455422, 0x99f46e51,
+ 0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+ 0x4cf516ee, 0x99b7dd99,
+ 0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+ 0x4ca4aa41, 0x997b8bf8,
+ 0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+ 0x4c540e4e, 0x993f7993,
+ 0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+ 0x4c034345, 0x9903a691,
+ 0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+ 0x4bb24958, 0x98c81316,
+ 0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+ 0x4b6120bb, 0x988cbf46,
+ 0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+ 0x4b0fc99d, 0x9851ab46,
+ 0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+ 0x4abe4433, 0x9816d73b,
+ 0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+ 0x4a6c90ad, 0x97dc4349,
+ 0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+ 0x4a1aaf3f, 0x97a1ef94,
+ 0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+ 0x49c8a01b, 0x9767dc41,
+ 0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+ 0x49766373, 0x972e0971,
+ 0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+ 0x4923f97b, 0x96f4774b,
+ 0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+ 0x48d16265, 0x96bb25f0,
+ 0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+ 0x487e9e64, 0x96821585,
+ 0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+ 0x482badab, 0x9649462d,
+ 0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+ 0x47d8906d, 0x9610b80a,
+ 0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+ 0x478546de, 0x95d86b3f,
+ 0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+ 0x4731d131, 0x95a05ff0,
+ 0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+ 0x46de2f99, 0x9568963f,
+ 0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+ 0x468a624a, 0x95310e4e,
+ 0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+ 0x46366978, 0x94f9c83f,
+ 0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+ 0x45e24556, 0x94c2c435,
+ 0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+ 0x458df619, 0x948c0252,
+ 0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+ 0x45397bf4, 0x945582b7,
+ 0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+ 0x44e4d71c, 0x941f4585,
+ 0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+ 0x449007c4, 0x93e94adf,
+ 0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+ 0x443b0e21, 0x93b392e6,
+ 0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+ 0x43e5ea68, 0x937e1dbb,
+ 0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+ 0x43909ccd, 0x9348eb7e,
+ 0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+ 0x433b2585, 0x9313fc51,
+ 0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+ 0x42e584c3, 0x92df5054,
+ 0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+ 0x428fbabe, 0x92aae7a8,
+ 0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+ 0x4239c7aa, 0x9276c26d,
+ 0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+ 0x41e3abbc, 0x9242e0c4,
+ 0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+ 0x418d6729, 0x920f42cb,
+ 0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+ 0x4136fa27, 0x91dbe8a4,
+ 0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+ 0x40e064ea, 0x91a8d26d,
+ 0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+ 0x4089a7a8, 0x91760047,
+ 0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+ 0x4032c297, 0x91437250,
+ 0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+ 0x3fdbb5ec, 0x911128a8,
+ 0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+ 0x3f8481dd, 0x90df236e,
+ 0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+ 0x3f2d26a0, 0x90ad62c0,
+ 0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+ 0x3ed5a46b, 0x907be6be,
+ 0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+ 0x3e7dfb73, 0x904aaf86,
+ 0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+ 0x3e262bee, 0x9019bd36,
+ 0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+ 0x3dce3614, 0x8fe90fec,
+ 0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+ 0x3d761a19, 0x8fb8a7c7,
+ 0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+ 0x3d1dd835, 0x8f8884e4,
+ 0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+ 0x3cc5709e, 0x8f58a761,
+ 0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+ 0x3c6ce38a, 0x8f290f5c,
+ 0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+ 0x3c143130, 0x8ef9bcf2,
+ 0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+ 0x3bbb59c7, 0x8ecab040,
+ 0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+ 0x3b625d86, 0x8e9be963,
+ 0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+ 0x3b093ca3, 0x8e6d6877,
+ 0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+ 0x3aaff755, 0x8e3f2d9b,
+ 0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+ 0x3a568dd4, 0x8e1138ea,
+ 0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+ 0x39fd0056, 0x8de38a80,
+ 0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+ 0x39a34f13, 0x8db6227a,
+ 0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+ 0x39497a43, 0x8d8900f3,
+ 0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+ 0x38ef821c, 0x8d5c2609,
+ 0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+ 0x389566d6, 0x8d2f91d5,
+ 0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+ 0x383b28a9, 0x8d034474,
+ 0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+ 0x37e0c7cc, 0x8cd73e01,
+ 0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+ 0x37864477, 0x8cab7e98,
+ 0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+ 0x372b9ee3, 0x8c800652,
+ 0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+ 0x36d0d746, 0x8c54d54c,
+ 0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+ 0x3675edd9, 0x8c29eb9f,
+ 0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+ 0x361ae2d3, 0x8bff4966,
+ 0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+ 0x35bfb66e, 0x8bd4eebc,
+ 0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+ 0x356468e2, 0x8baadbba,
+ 0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+ 0x3508fa66, 0x8b81107b,
+ 0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+ 0x34ad6b32, 0x8b578d18,
+ 0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+ 0x3451bb81, 0x8b2e51ab,
+ 0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+ 0x33f5eb89, 0x8b055e4d,
+ 0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+ 0x3399fb85, 0x8adcb318,
+ 0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+ 0x333debab, 0x8ab45024,
+ 0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+ 0x32e1bc36, 0x8a8c358b,
+ 0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+ 0x32856d5e, 0x8a646365,
+ 0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+ 0x3228ff5c, 0x8a3cd9cc,
+ 0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+ 0x31cc7269, 0x8a1598d6,
+ 0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+ 0x316fc6be, 0x89eea09d,
+ 0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+ 0x3112fc95, 0x89c7f138,
+ 0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+ 0x30b61426, 0x89a18ac0,
+ 0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+ 0x30590dab, 0x897b6d4c,
+ 0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+ 0x2ffbe95d, 0x895598f3,
+ 0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+ 0x2f9ea775, 0x89300dce,
+ 0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+ 0x2f41482e, 0x890acbf2,
+ 0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+ 0x2ee3cbc1, 0x88e5d378,
+ 0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+ 0x2e863267, 0x88c12475,
+ 0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+ 0x2e287c5a, 0x889cbf01,
+ 0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+ 0x2dcaa9d5, 0x8878a332,
+ 0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+ 0x2d6cbb10, 0x8854d11e,
+ 0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+ 0x2d0eb046, 0x883148db,
+ 0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+ 0x2cb089b1, 0x880e0a7f,
+ 0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+ 0x2c52478a, 0x87eb1621,
+ 0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+ 0x2bf3ea0d, 0x87c86bd5,
+ 0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+ 0x2b957173, 0x87a60bb1,
+ 0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+ 0x2b36ddf7, 0x8783f5ca,
+ 0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+ 0x2ad82fd2, 0x87622a35,
+ 0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+ 0x2a796740, 0x8740a907,
+ 0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+ 0x2a1a847b, 0x871f7255,
+ 0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+ 0x29bb87bc, 0x86fe8633,
+ 0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+ 0x295c7140, 0x86dde4b5,
+ 0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+ 0x28fd4140, 0x86bd8df0,
+ 0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+ 0x289df7f8, 0x869d81f8,
+ 0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+ 0x283e95a1, 0x867dc0e0,
+ 0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+ 0x27df1a77, 0x865e4abb,
+ 0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+ 0x277f86b5, 0x863f1f9e,
+ 0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+ 0x271fda96, 0x86203f9c,
+ 0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+ 0x26c01655, 0x8601aac7,
+ 0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+ 0x26603a2c, 0x85e36132,
+ 0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+ 0x26004657, 0x85c562f1,
+ 0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+ 0x25a03b11, 0x85a7b015,
+ 0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+ 0x25401896, 0x858a48b1,
+ 0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+ 0x24dfdf20, 0x856d2cd7,
+ 0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+ 0x247f8eec, 0x85505c99,
+ 0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+ 0x241f2833, 0x8533d809,
+ 0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+ 0x23beab33, 0x85179f39,
+ 0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+ 0x235e1826, 0x84fbb239,
+ 0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+ 0x22fd6f48, 0x84e0111b,
+ 0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+ 0x229cb0d5, 0x84c4bbf0,
+ 0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+ 0x223bdd08, 0x84a9b2ca,
+ 0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+ 0x21daf41d, 0x848ef5b7,
+ 0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+ 0x2179f64f, 0x847484ca,
+ 0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+ 0x2118e3dc, 0x845a6012,
+ 0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+ 0x20b7bcfe, 0x844087a0,
+ 0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+ 0x205681f1, 0x8426fb84,
+ 0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+ 0x1ff532f2, 0x840dbbcc,
+ 0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+ 0x1f93d03c, 0x83f4c889,
+ 0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+ 0x1f325a0b, 0x83dc21cb,
+ 0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+ 0x1ed0d09d, 0x83c3c7a0,
+ 0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+ 0x1e6f342c, 0x83abba17,
+ 0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+ 0x1e0d84f5, 0x8393f940,
+ 0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+ 0x1dabc334, 0x837c8528,
+ 0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+ 0x1d49ef26, 0x83655ddf,
+ 0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+ 0x1ce80906, 0x834e8373,
+ 0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+ 0x1c861113, 0x8337f5f1,
+ 0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+ 0x1c240786, 0x8321b568,
+ 0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+ 0x1bc1ec9e, 0x830bc1e6,
+ 0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+ 0x1b5fc097, 0x82f61b77,
+ 0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+ 0x1afd83ad, 0x82e0c22a,
+ 0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+ 0x1a9b361d, 0x82cbb60b,
+ 0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+ 0x1a38d823, 0x82b6f727,
+ 0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+ 0x19d669fc, 0x82a2858c,
+ 0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+ 0x1973ebe6, 0x828e6146,
+ 0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+ 0x19115e1c, 0x827a8a61,
+ 0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+ 0x18aec0db, 0x826700e9,
+ 0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+ 0x184c1461, 0x8253c4eb,
+ 0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+ 0x17e958ea, 0x8240d673,
+ 0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+ 0x17868eb3, 0x822e358b,
+ 0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+ 0x1723b5f9, 0x821be240,
+ 0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+ 0x16c0cef9, 0x8209dc9e,
+ 0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+ 0x165dd9f0, 0x81f824ae,
+ 0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+ 0x15fad71b, 0x81e6ba7c,
+ 0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+ 0x1597c6b7, 0x81d59e13,
+ 0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+ 0x1534a901, 0x81c4cf7d,
+ 0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+ 0x14d17e36, 0x81b44ec4,
+ 0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+ 0x146e4694, 0x81a41bf4,
+ 0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+ 0x140b0258, 0x81943715,
+ 0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+ 0x13a7b1bf, 0x8184a032,
+ 0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+ 0x13445505, 0x81755754,
+ 0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+ 0x12e0ec6a, 0x81665c84,
+ 0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+ 0x127d7829, 0x8157afcd,
+ 0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+ 0x1219f880, 0x81495136,
+ 0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+ 0x11b66dad, 0x813b40ca,
+ 0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+ 0x1152d7ed, 0x812d7e8f,
+ 0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+ 0x10ef377d, 0x81200a90,
+ 0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+ 0x108b8c9b, 0x8112e4d4,
+ 0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+ 0x1027d784, 0x81060d63,
+ 0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+ 0xfc41876, 0x80f98446,
+ 0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+ 0xf604faf, 0x80ed4984,
+ 0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+ 0xefc7d6b, 0x80e15d24,
+ 0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+ 0xe98a1e9, 0x80d5bf2e,
+ 0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+ 0xe34bd66, 0x80ca6fa9,
+ 0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+ 0xdd0d01f, 0x80bf6e9c,
+ 0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+ 0xd6cda53, 0x80b4bc0e,
+ 0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+ 0xd08dc3f, 0x80aa5806,
+ 0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+ 0xca4d620, 0x80a04289,
+ 0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+ 0xc40c835, 0x80967b9f,
+ 0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+ 0xbdcb2bb, 0x808d034c,
+ 0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+ 0xb7895f0, 0x8083d998,
+ 0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+ 0xb147211, 0x807afe87,
+ 0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+ 0xab0475c, 0x8072721f,
+ 0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+ 0xa4c1610, 0x806a3466,
+ 0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+ 0x9e7de6a, 0x80624560,
+ 0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+ 0x983a0a7, 0x805aa512,
+ 0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+ 0x91f5d06, 0x80535381,
+ 0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+ 0x8bb13c5, 0x804c50b2,
+ 0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+ 0x856c520, 0x80459ca9,
+ 0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+ 0x7f27157, 0x803f376a,
+ 0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+ 0x78e18a7, 0x803920f8,
+ 0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+ 0x729bb4e, 0x80335959,
+ 0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+ 0x6c5598a, 0x802de08e,
+ 0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+ 0x660f398, 0x8028b69c,
+ 0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+ 0x5fc89b8, 0x8023db86,
+ 0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+ 0x5981c26, 0x801f4f4f,
+ 0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+ 0x533ab20, 0x801b11fa,
+ 0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+ 0x4cf36e5, 0x80172388,
+ 0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+ 0x46abfb3, 0x801383fe,
+ 0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+ 0x40645c7, 0x8010335c,
+ 0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+ 0x3a1c960, 0x800d31a5,
+ 0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+ 0x33d4abb, 0x800a7edb,
+ 0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+ 0x2d8ca16, 0x80081b00,
+ 0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+ 0x27447b0, 0x80060614,
+ 0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+ 0x20fc3c6, 0x8004401a,
+ 0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+ 0x1ab3e97, 0x8002c912,
+ 0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+ 0x146b860, 0x8001a0fd,
+ 0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+ 0xe23160, 0x8000c7dc,
+ 0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+ 0x80003daf,
+ 0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+ 0x80000278,
+};
+
+static const q31_t WeightsQ31_8192[16384] = {
+ 0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,
+ 0xffed2684,
+ 0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,
+ 0x7ffff872, 0xffd40489,
+ 0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,
+ 0x7fffed57, 0xffbae290,
+ 0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,
+ 0x7fffdd4d, 0xffa1c09a,
+ 0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,
+ 0x7fffc854, 0xff889ea7,
+ 0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,
+ 0x7fffae6c, 0xff6f7cba,
+ 0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,
+ 0x7fff8f94, 0xff565ad1,
+ 0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,
+ 0x7fff6bcd, 0xff3d38ef,
+ 0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,
+ 0x7fff4317, 0xff241715,
+ 0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,
+ 0x7fff1572, 0xff0af543,
+ 0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,
+ 0x7ffee2dd, 0xfef1d37b,
+ 0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,
+ 0x7ffeab59, 0xfed8b1bd,
+ 0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,
+ 0x7ffe6ee5, 0xfebf900a,
+ 0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,
+ 0x7ffe2d83, 0xfea66e64,
+ 0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,
+ 0x7ffde731, 0xfe8d4ccb,
+ 0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,
+ 0x7ffd9bf0, 0xfe742b41,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,
+ 0x7ffd4bc0, 0xfe5b09c5,
+ 0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,
+ 0x7ffcf6a0, 0xfe41e85a,
+ 0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,
+ 0x7ffc9c92, 0xfe28c700,
+ 0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,
+ 0x7ffc3d94, 0xfe0fa5b8,
+ 0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,
+ 0x7ffbd9a7, 0xfdf68484,
+ 0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,
+ 0x7ffb70cb, 0xfddd6363,
+ 0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,
+ 0x7ffb0300, 0xfdc44258,
+ 0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,
+ 0x7ffa9045, 0xfdab2162,
+ 0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,
+ 0x7ffa189c, 0xfd920084,
+ 0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,
+ 0x7ff99c03, 0xfd78dfbd,
+ 0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,
+ 0x7ff91a7b, 0xfd5fbf10,
+ 0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,
+ 0x7ff89405, 0xfd469e7c,
+ 0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,
+ 0x7ff8089f, 0xfd2d7e04,
+ 0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,
+ 0x7ff7784a, 0xfd145da7,
+ 0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,
+ 0x7ff6e307, 0xfcfb3d67,
+ 0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,
+ 0x7ff648d4, 0xfce21d45,
+ 0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,
+ 0x7ff5a9b2, 0xfcc8fd41,
+ 0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,
+ 0x7ff505a2, 0xfcafdd5e,
+ 0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,
+ 0x7ff45ca3, 0xfc96bd9b,
+ 0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,
+ 0x7ff3aeb4, 0xfc7d9df9,
+ 0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,
+ 0x7ff2fbd7, 0xfc647e7b,
+ 0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,
+ 0x7ff2440b, 0xfc4b5f20,
+ 0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,
+ 0x7ff18751, 0xfc323fe9,
+ 0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,
+ 0x7ff0c5a7, 0xfc1920d8,
+ 0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,
+ 0x7fefff0f, 0xfc0001ee,
+ 0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,
+ 0x7fef3388, 0xfbe6e32b,
+ 0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,
+ 0x7fee6313, 0xfbcdc490,
+ 0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,
+ 0x7fed8daf, 0xfbb4a61f,
+ 0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,
+ 0x7fecb35c, 0xfb9b87d8,
+ 0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,
+ 0x7febd41b, 0xfb8269bd,
+ 0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,
+ 0x7feaefeb, 0xfb694bce,
+ 0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,
+ 0x7fea06cd, 0xfb502e0c,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,
+ 0x7fe918c0, 0xfb371078,
+ 0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,
+ 0x7fe825c5, 0xfb1df314,
+ 0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,
+ 0x7fe72ddb, 0xfb04d5e0,
+ 0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,
+ 0x7fe63103, 0xfaebb8dd,
+ 0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,
+ 0x7fe52f3d, 0xfad29c0c,
+ 0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,
+ 0x7fe42889, 0xfab97f6e,
+ 0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,
+ 0x7fe31ce6, 0xfaa06305,
+ 0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,
+ 0x7fe20c55, 0xfa8746d0,
+ 0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,
+ 0x7fe0f6d6, 0xfa6e2ad1,
+ 0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,
+ 0x7fdfdc69, 0xfa550f0a,
+ 0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,
+ 0x7fdebd0d, 0xfa3bf37a,
+ 0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,
+ 0x7fdd98c4, 0xfa22d823,
+ 0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,
+ 0x7fdc6f8d, 0xfa09bd06,
+ 0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,
+ 0x7fdb4167, 0xf9f0a224,
+ 0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,
+ 0x7fda0e54, 0xf9d7877e,
+ 0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,
+ 0x7fd8d653, 0xf9be6d15,
+ 0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,
+ 0x7fd79965, 0xf9a552e9,
+ 0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,
+ 0x7fd65788, 0xf98c38fc,
+ 0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,
+ 0x7fd510be, 0xf9731f4e,
+ 0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,
+ 0x7fd3c506, 0xf95a05e2,
+ 0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,
+ 0x7fd27460, 0xf940ecb7,
+ 0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,
+ 0x7fd11ecd, 0xf927d3ce,
+ 0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,
+ 0x7fcfc44d, 0xf90ebb29,
+ 0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,
+ 0x7fce64df, 0xf8f5a2c9,
+ 0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,
+ 0x7fcd0083, 0xf8dc8aae,
+ 0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,
+ 0x7fcb973b, 0xf8c372d9,
+ 0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,
+ 0x7fca2905, 0xf8aa5b4c,
+ 0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,
+ 0x7fc8b5e1, 0xf8914407,
+ 0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,
+ 0x7fc73dd1, 0xf8782d0c,
+ 0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,
+ 0x7fc5c0d3, 0xf85f165b,
+ 0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,
+ 0x7fc43ee9, 0xf845fff5,
+ 0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,
+ 0x7fc2b811, 0xf82ce9dc,
+ 0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,
+ 0x7fc12c4d, 0xf813d410,
+ 0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,
+ 0x7fbf9b9b, 0xf7fabe92,
+ 0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,
+ 0x7fbe05fd, 0xf7e1a963,
+ 0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,
+ 0x7fbc6b72, 0xf7c89484,
+ 0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,
+ 0x7fbacbfa, 0xf7af7ff6,
+ 0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,
+ 0x7fb92796, 0xf7966bbb,
+ 0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,
+ 0x7fb77e45, 0xf77d57d2,
+ 0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,
+ 0x7fb5d007, 0xf764443d,
+ 0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,
+ 0x7fb41cdd, 0xf74b30fe,
+ 0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,
+ 0x7fb264c7, 0xf7321e14,
+ 0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,
+ 0x7fb0a7c4, 0xf7190b81,
+ 0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,
+ 0x7faee5d5, 0xf6fff946,
+ 0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,
+ 0x7fad1efa, 0xf6e6e764,
+ 0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,
+ 0x7fab5333, 0xf6cdd5dc,
+ 0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,
+ 0x7fa98280, 0xf6b4c4ae,
+ 0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,
+ 0x7fa7ace1, 0xf69bb3dd,
+ 0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,
+ 0x7fa5d256, 0xf682a367,
+ 0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,
+ 0x7fa3f2df, 0xf6699350,
+ 0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,
+ 0x7fa20e7c, 0xf6508397,
+ 0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,
+ 0x7fa0252e, 0xf637743e,
+ 0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,
+ 0x7f9e36f4, 0xf61e6545,
+ 0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,
+ 0x7f9c43ce, 0xf60556ae,
+ 0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,
+ 0x7f9a4bbd, 0xf5ec4879,
+ 0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,
+ 0x7f984ec1, 0xf5d33aa8,
+ 0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,
+ 0x7f964cd9, 0xf5ba2d3b,
+ 0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,
+ 0x7f944606, 0xf5a12034,
+ 0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,
+ 0x7f923a48, 0xf5881393,
+ 0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,
+ 0x7f90299f, 0xf56f0759,
+ 0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,
+ 0x7f8e140a, 0xf555fb88,
+ 0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,
+ 0x7f8bf98b, 0xf53cf01f,
+ 0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,
+ 0x7f89da21, 0xf523e521,
+ 0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,
+ 0x7f87b5cd, 0xf50ada8f,
+ 0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,
+ 0x7f858c8d, 0xf4f1d068,
+ 0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,
+ 0x7f835e64, 0xf4d8c6ae,
+ 0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,
+ 0x7f812b4f, 0xf4bfbd63,
+ 0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,
+ 0x7f7ef350, 0xf4a6b486,
+ 0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,
+ 0x7f7cb667, 0xf48dac1a,
+ 0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,
+ 0x7f7a7494, 0xf474a41f,
+ 0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,
+ 0x7f782dd6, 0xf45b9c95,
+ 0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,
+ 0x7f75e22e, 0xf442957e,
+ 0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,
+ 0x7f73919d, 0xf4298edc,
+ 0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,
+ 0x7f713c21, 0xf41088ae,
+ 0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,
+ 0x7f6ee1bc, 0xf3f782f6,
+ 0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,
+ 0x7f6c826d, 0xf3de7db4,
+ 0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,
+ 0x7f6a1e34, 0xf3c578eb,
+ 0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,
+ 0x7f67b512, 0xf3ac749a,
+ 0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,
+ 0x7f654706, 0xf39370c2,
+ 0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,
+ 0x7f62d411, 0xf37a6d66,
+ 0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,
+ 0x7f605c33, 0xf3616a85,
+ 0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,
+ 0x7f5ddf6b, 0xf3486820,
+ 0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,
+ 0x7f5b5dbb, 0xf32f6639,
+ 0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,
+ 0x7f58d721, 0xf31664d1,
+ 0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,
+ 0x7f564b9f, 0xf2fd63e8,
+ 0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,
+ 0x7f53bb34, 0xf2e4637f,
+ 0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,
+ 0x7f5125e0, 0xf2cb6398,
+ 0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,
+ 0x7f4e8ba4, 0xf2b26433,
+ 0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,
+ 0x7f4bec7f, 0xf2996551,
+ 0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,
+ 0x7f494872, 0xf28066f4,
+ 0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,
+ 0x7f469f7d, 0xf267691b,
+ 0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,
+ 0x7f43f19f, 0xf24e6bc9,
+ 0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,
+ 0x7f413ed9, 0xf2356efe,
+ 0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,
+ 0x7f3e872c, 0xf21c72bc,
+ 0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,
+ 0x7f3bca96, 0xf2037702,
+ 0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,
+ 0x7f390919, 0xf1ea7bd2,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,
+ 0x7f3642b4, 0xf1d1812e,
+ 0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,
+ 0x7f337768, 0xf1b88715,
+ 0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,
+ 0x7f30a734, 0xf19f8d89,
+ 0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,
+ 0x7f2dd219, 0xf186948c,
+ 0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,
+ 0x7f2af817, 0xf16d9c1d,
+ 0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,
+ 0x7f28192d, 0xf154a43d,
+ 0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,
+ 0x7f25355d, 0xf13bacef,
+ 0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,
+ 0x7f224ca6, 0xf122b632,
+ 0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,
+ 0x7f1f5f08, 0xf109c009,
+ 0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,
+ 0x7f1c6c83, 0xf0f0ca72,
+ 0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,
+ 0x7f197518, 0xf0d7d571,
+ 0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,
+ 0x7f1678c6, 0xf0bee105,
+ 0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,
+ 0x7f13778e, 0xf0a5ed2f,
+ 0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,
+ 0x7f107170, 0xf08cf9f1,
+ 0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,
+ 0x7f0d666c, 0xf074074c,
+ 0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,
+ 0x7f0a5682, 0xf05b1540,
+ 0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,
+ 0x7f0741b2, 0xf04223ce,
+ 0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,
+ 0x7f0427fc, 0xf02932f8,
+ 0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,
+ 0x7f010961, 0xf01042be,
+ 0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,
+ 0x7efde5e0, 0xeff75321,
+ 0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,
+ 0x7efabd7a, 0xefde6423,
+ 0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,
+ 0x7ef7902f, 0xefc575c3,
+ 0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,
+ 0x7ef45dfe, 0xefac8804,
+ 0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,
+ 0x7ef126e9, 0xef939ae6,
+ 0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,
+ 0x7eedeaee, 0xef7aae6b,
+ 0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,
+ 0x7eeaaa0f, 0xef61c292,
+ 0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,
+ 0x7ee7644c, 0xef48d75d,
+ 0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,
+ 0x7ee419a3, 0xef2feccd,
+ 0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,
+ 0x7ee0ca17, 0xef1702e4,
+ 0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,
+ 0x7edd75a6, 0xeefe19a1,
+ 0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,
+ 0x7eda1c51, 0xeee53105,
+ 0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,
+ 0x7ed6be18, 0xeecc4913,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,
+ 0x7ed35afb, 0xeeb361cb,
+ 0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,
+ 0x7ecff2fb, 0xee9a7b2d,
+ 0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,
+ 0x7ecc8617, 0xee81953b,
+ 0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,
+ 0x7ec9144f, 0xee68aff6,
+ 0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,
+ 0x7ec59da5, 0xee4fcb5e,
+ 0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,
+ 0x7ec22217, 0xee36e775,
+ 0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,
+ 0x7ebea1a6, 0xee1e043b,
+ 0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,
+ 0x7ebb1c52, 0xee0521b2,
+ 0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,
+ 0x7eb7921b, 0xedec3fda,
+ 0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,
+ 0x7eb40301, 0xedd35eb5,
+ 0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,
+ 0x7eb06f05, 0xedba7e43,
+ 0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,
+ 0x7eacd627, 0xeda19e85,
+ 0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,
+ 0x7ea93867, 0xed88bf7d,
+ 0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,
+ 0x7ea595c4, 0xed6fe12b,
+ 0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,
+ 0x7ea1ee3f, 0xed570390,
+ 0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,
+ 0x7e9e41d9, 0xed3e26ad,
+ 0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,
+ 0x7e9a9091, 0xed254a84,
+ 0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,
+ 0x7e96da67, 0xed0c6f14,
+ 0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,
+ 0x7e931f5c, 0xecf39460,
+ 0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,
+ 0x7e8f5f70, 0xecdaba67,
+ 0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,
+ 0x7e8b9aa3, 0xecc1e12c,
+ 0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,
+ 0x7e87d0f5, 0xeca908ae,
+ 0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,
+ 0x7e840265, 0xec9030f0,
+ 0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,
+ 0x7e802ef6, 0xec7759f1,
+ 0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,
+ 0x7e7c56a5, 0xec5e83b3,
+ 0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,
+ 0x7e787975, 0xec45ae36,
+ 0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,
+ 0x7e749764, 0xec2cd97d,
+ 0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,
+ 0x7e70b073, 0xec140587,
+ 0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,
+ 0x7e6cc4a2, 0xebfb3256,
+ 0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,
+ 0x7e68d3f2, 0xebe25fea,
+ 0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,
+ 0x7e64de62, 0xebc98e45,
+ 0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,
+ 0x7e60e3f2, 0xebb0bd67,
+ 0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,
+ 0x7e5ce4a3, 0xeb97ed52,
+ 0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,
+ 0x7e58e075, 0xeb7f1e06,
+ 0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,
+ 0x7e54d768, 0xeb664f84,
+ 0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,
+ 0x7e50c97c, 0xeb4d81ce,
+ 0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,
+ 0x7e4cb6b1, 0xeb34b4e4,
+ 0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,
+ 0x7e489f08, 0xeb1be8c8,
+ 0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,
+ 0x7e448281, 0xeb031d79,
+ 0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,
+ 0x7e40611b, 0xeaea52fa,
+ 0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,
+ 0x7e3c3ad7, 0xead1894b,
+ 0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,
+ 0x7e380fb5, 0xeab8c06c,
+ 0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,
+ 0x7e33dfb6, 0xea9ff860,
+ 0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,
+ 0x7e2faad9, 0xea873127,
+ 0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,
+ 0x7e2b711f, 0xea6e6ac2,
+ 0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,
+ 0x7e273287, 0xea55a531,
+ 0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,
+ 0x7e22ef12, 0xea3ce077,
+ 0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,
+ 0x7e1ea6c1, 0xea241c93,
+ 0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,
+ 0x7e1a5992, 0xea0b5987,
+ 0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,
+ 0x7e160787, 0xe9f29753,
+ 0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,
+ 0x7e11b0a0, 0xe9d9d5fa,
+ 0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,
+ 0x7e0d54dc, 0xe9c1157a,
+ 0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,
+ 0x7e08f43d, 0xe9a855d7,
+ 0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,
+ 0x7e048ec1, 0xe98f9710,
+ 0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,
+ 0x7e00246a, 0xe976d926,
+ 0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,
+ 0x7dfbb537, 0xe95e1c1b,
+ 0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,
+ 0x7df74128, 0xe9455fef,
+ 0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,
+ 0x7df2c83f, 0xe92ca4a4,
+ 0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,
+ 0x7dee4a7a, 0xe913ea39,
+ 0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,
+ 0x7de9c7da, 0xe8fb30b1,
+ 0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,
+ 0x7de54060, 0xe8e2780d,
+ 0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,
+ 0x7de0b40b, 0xe8c9c04c,
+ 0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,
+ 0x7ddc22dc, 0xe8b10971,
+ 0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,
+ 0x7dd78cd3, 0xe898537b,
+ 0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,
+ 0x7dd2f1f0, 0xe87f9e6c,
+ 0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,
+ 0x7dce5232, 0xe866ea46,
+ 0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,
+ 0x7dc9ad9c, 0xe84e3708,
+ 0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,
+ 0x7dc5042b, 0xe83584b4,
+ 0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,
+ 0x7dc055e2, 0xe81cd34b,
+ 0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,
+ 0x7dbba2bf, 0xe80422ce,
+ 0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,
+ 0x7db6eac3, 0xe7eb733e,
+ 0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,
+ 0x7db22def, 0xe7d2c49b,
+ 0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,
+ 0x7dad6c42, 0xe7ba16e7,
+ 0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,
+ 0x7da8a5bc, 0xe7a16a22,
+ 0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,
+ 0x7da3da5f, 0xe788be4e,
+ 0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,
+ 0x7d9f0a29, 0xe770136b,
+ 0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,
+ 0x7d9a351c, 0xe757697b,
+ 0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,
+ 0x7d955b37, 0xe73ec07e,
+ 0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,
+ 0x7d907c7a, 0xe7261875,
+ 0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,
+ 0x7d8b98e6, 0xe70d7162,
+ 0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,
+ 0x7d86b07c, 0xe6f4cb45,
+ 0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,
+ 0x7d81c33a, 0xe6dc261f,
+ 0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,
+ 0x7d7cd121, 0xe6c381f1,
+ 0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,
+ 0x7d77da32, 0xe6aadebc,
+ 0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,
+ 0x7d72de6d, 0xe6923c82,
+ 0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,
+ 0x7d6dddd2, 0xe6799b42,
+ 0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,
+ 0x7d68d860, 0xe660fafe,
+ 0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,
+ 0x7d63ce19, 0xe6485bb7,
+ 0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,
+ 0x7d5ebefc, 0xe62fbd6e,
+ 0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,
+ 0x7d59ab0a, 0xe6172024,
+ 0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,
+ 0x7d549243, 0xe5fe83d9,
+ 0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,
+ 0x7d4f74a7, 0xe5e5e88f,
+ 0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,
+ 0x7d4a5236, 0xe5cd4e47,
+ 0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,
+ 0x7d452af1, 0xe5b4b501,
+ 0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,
+ 0x7d3ffed7, 0xe59c1cbf,
+ 0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,
+ 0x7d3acde9, 0xe5838581,
+ 0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,
+ 0x7d359827, 0xe56aef49,
+ 0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,
+ 0x7d305d91, 0xe5525a17,
+ 0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,
+ 0x7d2b1e28, 0xe539c5ec,
+ 0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,
+ 0x7d25d9eb, 0xe52132c9,
+ 0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,
+ 0x7d2090db, 0xe508a0b0,
+ 0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,
+ 0x7d1b42f9, 0xe4f00fa1,
+ 0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,
+ 0x7d15f043, 0xe4d77f9d,
+ 0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,
+ 0x7d1098bb, 0xe4bef0a5,
+ 0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,
+ 0x7d0b3c60, 0xe4a662ba,
+ 0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,
+ 0x7d05db34, 0xe48dd5dd,
+ 0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,
+ 0x7d007535, 0xe4754a0e,
+ 0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,
+ 0x7cfb0a65, 0xe45cbf50,
+ 0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,
+ 0x7cf59ac4, 0xe44435a2,
+ 0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,
+ 0x7cf02651, 0xe42bad07,
+ 0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,
+ 0x7ceaad0c, 0xe413257d,
+ 0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,
+ 0x7ce52ef7, 0xe3fa9f08,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,
+ 0x7cdfac12, 0xe3e219a7,
+ 0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,
+ 0x7cda245c, 0xe3c9955b,
+ 0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,
+ 0x7cd497d5, 0xe3b11226,
+ 0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,
+ 0x7ccf067f, 0xe3989008,
+ 0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,
+ 0x7cc97059, 0xe3800f03,
+ 0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,
+ 0x7cc3d563, 0xe3678f17,
+ 0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,
+ 0x7cbe359e, 0xe34f1045,
+ 0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,
+ 0x7cb8910a, 0xe336928e,
+ 0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,
+ 0x7cb2e7a6, 0xe31e15f4,
+ 0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,
+ 0x7cad3974, 0xe3059a76,
+ 0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,
+ 0x7ca78674, 0xe2ed2017,
+ 0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,
+ 0x7ca1cea5, 0xe2d4a6d6,
+ 0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,
+ 0x7c9c1208, 0xe2bc2eb5,
+ 0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,
+ 0x7c96509d, 0xe2a3b7b5,
+ 0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,
+ 0x7c908a65, 0xe28b41d7,
+ 0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,
+ 0x7c8abf5f, 0xe272cd1c,
+ 0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,
+ 0x7c84ef8c, 0xe25a5984,
+ 0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,
+ 0x7c7f1aed, 0xe241e711,
+ 0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,
+ 0x7c794180, 0xe22975c4,
+ 0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,
+ 0x7c736347, 0xe211059d,
+ 0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,
+ 0x7c6d8041, 0xe1f8969d,
+ 0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,
+ 0x7c679870, 0xe1e028c6,
+ 0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,
+ 0x7c61abd3, 0xe1c7bc18,
+ 0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,
+ 0x7c5bba6a, 0xe1af5094,
+ 0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,
+ 0x7c55c436, 0xe196e63c,
+ 0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,
+ 0x7c4fc936, 0xe17e7d0f,
+ 0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,
+ 0x7c49c96c, 0xe1661510,
+ 0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,
+ 0x7c43c4d7, 0xe14dae3f,
+ 0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,
+ 0x7c3dbb78, 0xe135489d,
+ 0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,
+ 0x7c37ad4e, 0xe11ce42a,
+ 0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,
+ 0x7c319a5a, 0xe10480e9,
+ 0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,
+ 0x7c2b829d, 0xe0ec1ed9,
+ 0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,
+ 0x7c256616, 0xe0d3bdfc,
+ 0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,
+ 0x7c1f44c6, 0xe0bb5e53,
+ 0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,
+ 0x7c191ead, 0xe0a2ffde,
+ 0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,
+ 0x7c12f3cb, 0xe08aa29f,
+ 0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,
+ 0x7c0cc421, 0xe0724696,
+ 0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,
+ 0x7c068fae, 0xe059ebc5,
+ 0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,
+ 0x7c005673, 0xe041922c,
+ 0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,
+ 0x7bfa1870, 0xe02939cc,
+ 0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,
+ 0x7bf3d5a6, 0xe010e2a7,
+ 0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,
+ 0x7bed8e14, 0xdff88cbc,
+ 0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,
+ 0x7be741bb, 0xdfe0380e,
+ 0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,
+ 0x7be0f09b, 0xdfc7e49d,
+ 0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,
+ 0x7bda9ab5, 0xdfaf926a,
+ 0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,
+ 0x7bd44008, 0xdf974176,
+ 0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,
+ 0x7bcde095, 0xdf7ef1c2,
+ 0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,
+ 0x7bc77c5d, 0xdf66a34e,
+ 0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,
+ 0x7bc1135e, 0xdf4e561c,
+ 0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,
+ 0x7bbaa59a, 0xdf360a2d,
+ 0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,
+ 0x7bb43311, 0xdf1dbf82,
+ 0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,
+ 0x7badbbc3, 0xdf05761b,
+ 0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,
+ 0x7ba73fb1, 0xdeed2dfa,
+ 0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,
+ 0x7ba0beda, 0xded4e71f,
+ 0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,
+ 0x7b9a393f, 0xdebca18b,
+ 0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,
+ 0x7b93aee0, 0xdea45d40,
+ 0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,
+ 0x7b8d1fbd, 0xde8c1a3e,
+ 0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,
+ 0x7b868bd7, 0xde73d886,
+ 0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,
+ 0x7b7ff32e, 0xde5b9819,
+ 0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,
+ 0x7b7955c2, 0xde4358f8,
+ 0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,
+ 0x7b72b393, 0xde2b1b24,
+ 0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,
+ 0x7b6c0ca2, 0xde12de9e,
+ 0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,
+ 0x7b6560ee, 0xddfaa367,
+ 0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,
+ 0x7b5eb079, 0xdde26980,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,
+ 0x7b57fb42, 0xddca30e9,
+ 0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,
+ 0x7b51414a, 0xddb1f9a4,
+ 0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,
+ 0x7b4a8291, 0xdd99c3b2,
+ 0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,
+ 0x7b43bf17, 0xdd818f13,
+ 0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,
+ 0x7b3cf6dc, 0xdd695bc9,
+ 0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,
+ 0x7b3629e1, 0xdd5129d4,
+ 0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,
+ 0x7b2f5826, 0xdd38f935,
+ 0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,
+ 0x7b2881ac, 0xdd20c9ed,
+ 0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,
+ 0x7b21a671, 0xdd089bfe,
+ 0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,
+ 0x7b1ac678, 0xdcf06f68,
+ 0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,
+ 0x7b13e1bf, 0xdcd8442b,
+ 0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,
+ 0x7b0cf848, 0xdcc01a4a,
+ 0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,
+ 0x7b060a12, 0xdca7f1c5,
+ 0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,
+ 0x7aff171e, 0xdc8fca9c,
+ 0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,
+ 0x7af81f6c, 0xdc77a4d2,
+ 0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,
+ 0x7af122fd, 0xdc5f8066,
+ 0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,
+ 0x7aea21d0, 0xdc475d59,
+ 0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,
+ 0x7ae31be6, 0xdc2f3bad,
+ 0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,
+ 0x7adc113f, 0xdc171b63,
+ 0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,
+ 0x7ad501dc, 0xdbfefc7b,
+ 0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,
+ 0x7acdedbc, 0xdbe6def6,
+ 0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,
+ 0x7ac6d4e0, 0xdbcec2d6,
+ 0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,
+ 0x7abfb749, 0xdbb6a81b,
+ 0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,
+ 0x7ab894f6, 0xdb9e8ec6,
+ 0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,
+ 0x7ab16de7, 0xdb8676d8,
+ 0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,
+ 0x7aaa421e, 0xdb6e6052,
+ 0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,
+ 0x7aa3119a, 0xdb564b35,
+ 0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,
+ 0x7a9bdc5c, 0xdb3e3781,
+ 0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,
+ 0x7a94a264, 0xdb262539,
+ 0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,
+ 0x7a8d63b2, 0xdb0e145c,
+ 0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,
+ 0x7a862046, 0xdaf604ec,
+ 0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,
+ 0x7a7ed821, 0xdaddf6ea,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,
+ 0x7a778b43, 0xdac5ea56,
+ 0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,
+ 0x7a7039ad, 0xdaaddf31,
+ 0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,
+ 0x7a68e35e, 0xda95d57d,
+ 0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,
+ 0x7a618857, 0xda7dcd3a,
+ 0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,
+ 0x7a5a2898, 0xda65c669,
+ 0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,
+ 0x7a52c421, 0xda4dc10b,
+ 0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,
+ 0x7a4b5af3, 0xda35bd22,
+ 0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,
+ 0x7a43ed0e, 0xda1dbaad,
+ 0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,
+ 0x7a3c7a73, 0xda05b9ae,
+ 0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,
+ 0x7a350321, 0xd9edba26,
+ 0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,
+ 0x7a2d8719, 0xd9d5bc16,
+ 0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,
+ 0x7a26065b, 0xd9bdbf7e,
+ 0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,
+ 0x7a1e80e7, 0xd9a5c461,
+ 0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,
+ 0x7a16f6be, 0xd98dcabd,
+ 0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,
+ 0x7a0f67e0, 0xd975d295,
+ 0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,
+ 0x7a07d44e, 0xd95ddbea,
+ 0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,
+ 0x7a003c07, 0xd945e6bb,
+ 0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,
+ 0x79f89f0c, 0xd92df30b,
+ 0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,
+ 0x79f0fd5d, 0xd91600da,
+ 0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,
+ 0x79e956fb, 0xd8fe1029,
+ 0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,
+ 0x79e1abe6, 0xd8e620fa,
+ 0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,
+ 0x79d9fc1d, 0xd8ce334c,
+ 0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,
+ 0x79d247a2, 0xd8b64720,
+ 0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,
+ 0x79ca8e75, 0xd89e5c79,
+ 0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,
+ 0x79c2d095, 0xd8867356,
+ 0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,
+ 0x79bb0e04, 0xd86e8bb9,
+ 0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,
+ 0x79b346c2, 0xd856a5a3,
+ 0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,
+ 0x79ab7ace, 0xd83ec114,
+ 0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,
+ 0x79a3aa29, 0xd826de0d,
+ 0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,
+ 0x799bd4d4, 0xd80efc8f,
+ 0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,
+ 0x7993facf, 0xd7f71c9c,
+ 0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,
+ 0x798c1c1a, 0xd7df3e34,
+ 0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,
+ 0x798438b5, 0xd7c76158,
+ 0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,
+ 0x797c50a1, 0xd7af8609,
+ 0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,
+ 0x797463de, 0xd797ac48,
+ 0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,
+ 0x796c726c, 0xd77fd415,
+ 0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,
+ 0x79647c4c, 0xd767fd72,
+ 0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,
+ 0x795c817d, 0xd7502860,
+ 0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,
+ 0x79548201, 0xd73854e0,
+ 0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,
+ 0x794c7dd7, 0xd72082f2,
+ 0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,
+ 0x79447500, 0xd708b297,
+ 0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,
+ 0x793c677d, 0xd6f0e3d1,
+ 0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,
+ 0x7934554d, 0xd6d916a0,
+ 0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,
+ 0x792c3e70, 0xd6c14b05,
+ 0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,
+ 0x792422e8, 0xd6a98101,
+ 0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,
+ 0x791c02b4, 0xd691b895,
+ 0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,
+ 0x7913ddd4, 0xd679f1c2,
+ 0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,
+ 0x790bb44a, 0xd6622c89,
+ 0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,
+ 0x79038615, 0xd64a68eb,
+ 0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,
+ 0x78fb5336, 0xd632a6e8,
+ 0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,
+ 0x78f31bac, 0xd61ae682,
+ 0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,
+ 0x78eadf79, 0xd60327b9,
+ 0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,
+ 0x78e29e9d, 0xd5eb6a8f,
+ 0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,
+ 0x78da5917, 0xd5d3af04,
+ 0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,
+ 0x78d20ee9, 0xd5bbf519,
+ 0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,
+ 0x78c9c012, 0xd5a43cd0,
+ 0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,
+ 0x78c16c93, 0xd58c8628,
+ 0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,
+ 0x78b9146c, 0xd574d124,
+ 0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,
+ 0x78b0b79e, 0xd55d1dc3,
+ 0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,
+ 0x78a85628, 0xd5456c07,
+ 0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,
+ 0x789ff00c, 0xd52dbbf1,
+ 0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,
+ 0x78978549, 0xd5160d82,
+ 0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,
+ 0x788f15e0, 0xd4fe60ba,
+ 0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,
+ 0x7886a1d1, 0xd4e6b59a,
+ 0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,
+ 0x787e291d, 0xd4cf0c24,
+ 0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,
+ 0x7875abc3, 0xd4b76458,
+ 0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,
+ 0x786d29c5, 0xd49fbe37,
+ 0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,
+ 0x7864a322, 0xd48819c3,
+ 0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,
+ 0x785c17db, 0xd47076fb,
+ 0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,
+ 0x785387ef, 0xd458d5e2,
+ 0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,
+ 0x784af361, 0xd4413677,
+ 0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,
+ 0x78425a2f, 0xd42998bc,
+ 0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,
+ 0x7839bc5a, 0xd411fcb2,
+ 0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,
+ 0x783119e2, 0xd3fa6259,
+ 0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,
+ 0x782872c8, 0xd3e2c9b2,
+ 0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,
+ 0x781fc70d, 0xd3cb32c0,
+ 0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,
+ 0x781716b0, 0xd3b39d81,
+ 0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,
+ 0x780e61b1, 0xd39c09f7,
+ 0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,
+ 0x7805a812, 0xd3847824,
+ 0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,
+ 0x77fce9d2, 0xd36ce808,
+ 0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,
+ 0x77f426f2, 0xd35559a4,
+ 0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,
+ 0x77eb5f71, 0xd33dccf8,
+ 0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,
+ 0x77e29352, 0xd3264206,
+ 0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,
+ 0x77d9c293, 0xd30eb8cf,
+ 0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,
+ 0x77d0ed35, 0xd2f73154,
+ 0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,
+ 0x77c81339, 0xd2dfab95,
+ 0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,
+ 0x77bf349f, 0xd2c82793,
+ 0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,
+ 0x77b65166, 0xd2b0a54f,
+ 0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,
+ 0x77ad6990, 0xd29924cb,
+ 0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,
+ 0x77a47d1d, 0xd281a607,
+ 0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,
+ 0x779b8c0e, 0xd26a2904,
+ 0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,
+ 0x77929661, 0xd252adc3,
+ 0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,
+ 0x77899c19, 0xd23b3444,
+ 0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,
+ 0x77809d35, 0xd223bc8a,
+ 0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,
+ 0x777799b5, 0xd20c4694,
+ 0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,
+ 0x776e919a, 0xd1f4d263,
+ 0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,
+ 0x776584e5, 0xd1dd5ff9,
+ 0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,
+ 0x775c7395, 0xd1c5ef56,
+ 0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,
+ 0x77535dab, 0xd1ae807c,
+ 0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,
+ 0x774a4327, 0xd197136b,
+ 0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,
+ 0x7741240a, 0xd17fa823,
+ 0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,
+ 0x77380054, 0xd1683ea7,
+ 0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,
+ 0x772ed805, 0xd150d6f6,
+ 0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,
+ 0x7725ab1f, 0xd1397113,
+ 0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,
+ 0x771c79a0, 0xd1220cfc,
+ 0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,
+ 0x77134389, 0xd10aaab5,
+ 0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,
+ 0x770a08dc, 0xd0f34a3d,
+ 0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,
+ 0x7700c997, 0xd0dbeb95,
+ 0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,
+ 0x76f785bc, 0xd0c48ebf,
+ 0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,
+ 0x76ee3d4b, 0xd0ad33ba,
+ 0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,
+ 0x76e4f044, 0xd095da89,
+ 0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,
+ 0x76db9ea7, 0xd07e832c,
+ 0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,
+ 0x76d24876, 0xd0672da3,
+ 0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,
+ 0x76c8edb0, 0xd04fd9f1,
+ 0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,
+ 0x76bf8e55, 0xd0388815,
+ 0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,
+ 0x76b62a66, 0xd0213810,
+ 0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,
+ 0x76acc1e4, 0xd009e9e4,
+ 0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,
+ 0x76a354cf, 0xcff29d92,
+ 0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,
+ 0x7699e326, 0xcfdb531a,
+ 0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,
+ 0x76906ceb, 0xcfc40a7c,
+ 0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,
+ 0x7686f21e, 0xcfacc3bb,
+ 0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,
+ 0x767d72bf, 0xcf957ed7,
+ 0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,
+ 0x7673eecf, 0xcf7e3bd1,
+ 0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,
+ 0x766a664d, 0xcf66faa9,
+ 0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,
+ 0x7660d93b, 0xcf4fbb61,
+ 0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,
+ 0x76574798, 0xcf387dfa,
+ 0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,
+ 0x764db166, 0xcf214274,
+ 0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,
+ 0x764416a4, 0xcf0a08d0,
+ 0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,
+ 0x763a7752, 0xcef2d110,
+ 0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,
+ 0x7630d372, 0xcedb9b33,
+ 0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,
+ 0x76272b03, 0xcec4673c,
+ 0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,
+ 0x761d7e06, 0xcead352b,
+ 0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,
+ 0x7613cc7c, 0xce960500,
+ 0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,
+ 0x760a1664, 0xce7ed6bd,
+ 0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,
+ 0x76005bbf, 0xce67aa63,
+ 0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,
+ 0x75f69c8d, 0xce507ff2,
+ 0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,
+ 0x75ecd8cf, 0xce39576c,
+ 0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,
+ 0x75e31086, 0xce2230d0,
+ 0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,
+ 0x75d943b0, 0xce0b0c21,
+ 0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,
+ 0x75cf7250, 0xcdf3e95f,
+ 0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,
+ 0x75c59c65, 0xcddcc88b,
+ 0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,
+ 0x75bbc1ef, 0xcdc5a9a6,
+ 0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,
+ 0x75b1e2f0, 0xcdae8cb1,
+ 0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,
+ 0x75a7ff67, 0xcd9771ac,
+ 0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,
+ 0x759e1755, 0xcd805899,
+ 0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,
+ 0x75942ab9, 0xcd694178,
+ 0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,
+ 0x758a3996, 0xcd522c4a,
+ 0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,
+ 0x758043ea, 0xcd3b1911,
+ 0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,
+ 0x757649b7, 0xcd2407cc,
+ 0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,
+ 0x756c4afc, 0xcd0cf87e,
+ 0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,
+ 0x756247bb, 0xccf5eb26,
+ 0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,
+ 0x75583ff3, 0xccdedfc7,
+ 0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,
+ 0x754e33a4, 0xccc7d65f,
+ 0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,
+ 0x754422d0, 0xccb0cef2,
+ 0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,
+ 0x753a0d77, 0xcc99c97e,
+ 0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,
+ 0x752ff399, 0xcc82c607,
+ 0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,
+ 0x7525d536, 0xcc6bc48b,
+ 0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,
+ 0x751bb24f, 0xcc54c50c,
+ 0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,
+ 0x75118ae4, 0xcc3dc78b,
+ 0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,
+ 0x75075ef5, 0xcc26cc09,
+ 0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,
+ 0x74fd2e84, 0xcc0fd287,
+ 0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,
+ 0x74f2f990, 0xcbf8db05,
+ 0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,
+ 0x74e8c01a, 0xcbe1e585,
+ 0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,
+ 0x74de8221, 0xcbcaf208,
+ 0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,
+ 0x74d43fa8, 0xcbb4008d,
+ 0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,
+ 0x74c9f8ad, 0xcb9d1117,
+ 0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,
+ 0x74bfad32, 0xcb8623a5,
+ 0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,
+ 0x74b55d36, 0xcb6f383a,
+ 0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,
+ 0x74ab08bb, 0xcb584ed6,
+ 0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,
+ 0x74a0afc0, 0xcb416779,
+ 0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,
+ 0x74965246, 0xcb2a8224,
+ 0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,
+ 0x748bf04d, 0xcb139ed9,
+ 0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,
+ 0x748189d7, 0xcafcbd99,
+ 0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,
+ 0x74771ee2, 0xcae5de64,
+ 0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,
+ 0x746caf70, 0xcacf013a,
+ 0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,
+ 0x74623b80, 0xcab8261e,
+ 0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,
+ 0x7457c314, 0xcaa14d10,
+ 0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,
+ 0x744d462c, 0xca8a7610,
+ 0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,
+ 0x7442c4c8, 0xca73a120,
+ 0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,
+ 0x74383ee9, 0xca5cce40,
+ 0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,
+ 0x742db48e, 0xca45fd72,
+ 0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,
+ 0x742325b9, 0xca2f2eb6,
+ 0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,
+ 0x74189269, 0xca18620e,
+ 0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,
+ 0x740dfaa0, 0xca019779,
+ 0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,
+ 0x74035e5d, 0xc9eacef9,
+ 0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,
+ 0x73f8bda2, 0xc9d4088f,
+ 0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,
+ 0x73ee186e, 0xc9bd443c,
+ 0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,
+ 0x73e36ec1, 0xc9a68200,
+ 0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,
+ 0x73d8c09d, 0xc98fc1dc,
+ 0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,
+ 0x73ce0e01, 0xc97903d2,
+ 0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,
+ 0x73c356ef, 0xc96247e2,
+ 0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,
+ 0x73b89b66, 0xc94b8e0d,
+ 0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,
+ 0x73addb67, 0xc934d654,
+ 0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,
+ 0x73a316f2, 0xc91e20b8,
+ 0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,
+ 0x73984e07, 0xc9076d39,
+ 0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,
+ 0x738d80a8, 0xc8f0bbd9,
+ 0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,
+ 0x7382aed5, 0xc8da0c99,
+ 0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,
+ 0x7377d88d, 0xc8c35f78,
+ 0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,
+ 0x736cfdd2, 0xc8acb479,
+ 0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,
+ 0x73621ea4, 0xc8960b9c,
+ 0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,
+ 0x73573b03, 0xc87f64e2,
+ 0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,
+ 0x734c52ef, 0xc868c04b,
+ 0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,
+ 0x7341666a, 0xc8521dd9,
+ 0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,
+ 0x73367572, 0xc83b7d8d,
+ 0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,
+ 0x732b800a, 0xc824df67,
+ 0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,
+ 0x73208632, 0xc80e4369,
+ 0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,
+ 0x731587e8, 0xc7f7a992,
+ 0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,
+ 0x730a8530, 0xc7e111e5,
+ 0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,
+ 0x72ff7e07, 0xc7ca7c61,
+ 0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,
+ 0x72f47270, 0xc7b3e909,
+ 0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,
+ 0x72e9626a, 0xc79d57db,
+ 0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,
+ 0x72de4df6, 0xc786c8db,
+ 0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,
+ 0x72d33514, 0xc7703c08,
+ 0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,
+ 0x72c817c6, 0xc759b163,
+ 0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,
+ 0x72bcf60a, 0xc74328ed,
+ 0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,
+ 0x72b1cfe1, 0xc72ca2a7,
+ 0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,
+ 0x72a6a54d, 0xc7161e92,
+ 0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,
+ 0x729b764d, 0xc6ff9cae,
+ 0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,
+ 0x729042e3, 0xc6e91cfd,
+ 0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,
+ 0x72850b0d, 0xc6d29f80,
+ 0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,
+ 0x7279cecd, 0xc6bc2437,
+ 0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,
+ 0x726e8e23, 0xc6a5ab23,
+ 0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,
+ 0x72634910, 0xc68f3446,
+ 0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,
+ 0x7257ff94, 0xc678bf9f,
+ 0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,
+ 0x724cb1b0, 0xc6624d30,
+ 0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,
+ 0x72415f63, 0xc64bdcf9,
+ 0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,
+ 0x723608af, 0xc6356efc,
+ 0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,
+ 0x722aad93, 0xc61f033a,
+ 0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,
+ 0x721f4e11, 0xc60899b2,
+ 0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,
+ 0x7213ea28, 0xc5f23267,
+ 0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,
+ 0x720881d9, 0xc5dbcd59,
+ 0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,
+ 0x71fd1525, 0xc5c56a89,
+ 0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,
+ 0x71f1a40c, 0xc5af09f7,
+ 0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,
+ 0x71e62e8f, 0xc598aba5,
+ 0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,
+ 0x71dab4ad, 0xc5824f93,
+ 0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,
+ 0x71cf3667, 0xc56bf5c2,
+ 0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,
+ 0x71c3b3bf, 0xc5559e34,
+ 0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,
+ 0x71b82cb3, 0xc53f48e9,
+ 0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,
+ 0x71aca145, 0xc528f5e1,
+ 0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,
+ 0x71a11175, 0xc512a51f,
+ 0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,
+ 0x71957d44, 0xc4fc56a2,
+ 0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,
+ 0x7189e4b2, 0xc4e60a6b,
+ 0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,
+ 0x717e47bf, 0xc4cfc07c,
+ 0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,
+ 0x7172a66c, 0xc4b978d4,
+ 0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,
+ 0x716700b9, 0xc4a33376,
+ 0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,
+ 0x715b56a7, 0xc48cf062,
+ 0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,
+ 0x714fa836, 0xc476af98,
+ 0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,
+ 0x7143f567, 0xc460711b,
+ 0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,
+ 0x71383e3a, 0xc44a34e9,
+ 0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,
+ 0x712c82b0, 0xc433fb05,
+ 0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,
+ 0x7120c2c8, 0xc41dc36f,
+ 0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,
+ 0x7114fe84, 0xc4078e28,
+ 0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,
+ 0x710935e4, 0xc3f15b31,
+ 0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,
+ 0x70fd68e9, 0xc3db2a8b,
+ 0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,
+ 0x70f19792, 0xc3c4fc36,
+ 0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,
+ 0x70e5c1e1, 0xc3aed034,
+ 0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,
+ 0x70d9e7d5, 0xc398a685,
+ 0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,
+ 0x70ce096f, 0xc3827f2a,
+ 0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,
+ 0x70c226b0, 0xc36c5a24,
+ 0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,
+ 0x70b63f99, 0xc3563774,
+ 0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,
+ 0x70aa5428, 0xc340171b,
+ 0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,
+ 0x709e6460, 0xc329f919,
+ 0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,
+ 0x70927041, 0xc313dd70,
+ 0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,
+ 0x708677ca, 0xc2fdc420,
+ 0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,
+ 0x707a7afd, 0xc2e7ad2a,
+ 0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,
+ 0x706e79d9, 0xc2d1988f,
+ 0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,
+ 0x70627460, 0xc2bb8650,
+ 0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,
+ 0x70566a92, 0xc2a5766e,
+ 0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,
+ 0x704a5c6f, 0xc28f68e9,
+ 0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,
+ 0x703e49f8, 0xc2795dc3,
+ 0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,
+ 0x7032332d, 0xc26354fc,
+ 0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,
+ 0x7026180e, 0xc24d4e95,
+ 0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,
+ 0x7019f89d, 0xc2374a8f,
+ 0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,
+ 0x700dd4da, 0xc22148ea,
+ 0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,
+ 0x7001acc4, 0xc20b49a9,
+ 0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,
+ 0x6ff5805d, 0xc1f54cca,
+ 0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,
+ 0x6fe94fa5, 0xc1df5251,
+ 0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,
+ 0x6fdd1a9c, 0xc1c95a3c,
+ 0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,
+ 0x6fd0e144, 0xc1b3648d,
+ 0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,
+ 0x6fc4a39c, 0xc19d7145,
+ 0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,
+ 0x6fb861a4, 0xc1878065,
+ 0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,
+ 0x6fac1b5f, 0xc17191ee,
+ 0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,
+ 0x6f9fd0cb, 0xc15ba5df,
+ 0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,
+ 0x6f9381e9, 0xc145bc3c,
+ 0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,
+ 0x6f872eba, 0xc12fd503,
+ 0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,
+ 0x6f7ad73e, 0xc119f036,
+ 0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,
+ 0x6f6e7b76, 0xc1040dd6,
+ 0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,
+ 0x6f621b62, 0xc0ee2de3,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,
+ 0x6f55b703, 0xc0d8505f,
+ 0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,
+ 0x6f494e5a, 0xc0c2754b,
+ 0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,
+ 0x6f3ce165, 0xc0ac9ca6,
+ 0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,
+ 0x6f307027, 0xc096c673,
+ 0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,
+ 0x6f23faa0, 0xc080f2b1,
+ 0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,
+ 0x6f1780cf, 0xc06b2162,
+ 0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,
+ 0x6f0b02b6, 0xc0555287,
+ 0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,
+ 0x6efe8056, 0xc03f8620,
+ 0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,
+ 0x6ef1f9ad, 0xc029bc2e,
+ 0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,
+ 0x6ee56ebe, 0xc013f4b2,
+ 0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,
+ 0x6ed8df88, 0xbffe2fad,
+ 0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,
+ 0x6ecc4c0d, 0xbfe86d20,
+ 0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,
+ 0x6ebfb44b, 0xbfd2ad0b,
+ 0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,
+ 0x6eb31845, 0xbfbcef70,
+ 0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,
+ 0x6ea677fa, 0xbfa7344f,
+ 0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,
+ 0x6e99d36b, 0xbf917ba9,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,
+ 0x6e8d2a99, 0xbf7bc57f,
+ 0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,
+ 0x6e807d83, 0xbf6611d2,
+ 0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,
+ 0x6e73cc2b, 0xbf5060a2,
+ 0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,
+ 0x6e671690, 0xbf3ab1f1,
+ 0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,
+ 0x6e5a5cb4, 0xbf2505bf,
+ 0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,
+ 0x6e4d9e97, 0xbf0f5c0d,
+ 0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,
+ 0x6e40dc39, 0xbef9b4dc,
+ 0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,
+ 0x6e34159b, 0xbee4102d,
+ 0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,
+ 0x6e274abe, 0xbece6e00,
+ 0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,
+ 0x6e1a7ba1, 0xbeb8ce57,
+ 0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,
+ 0x6e0da845, 0xbea33132,
+ 0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,
+ 0x6e00d0ac, 0xbe8d9692,
+ 0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,
+ 0x6df3f4d4, 0xbe77fe78,
+ 0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,
+ 0x6de714c0, 0xbe6268e5,
+ 0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,
+ 0x6dda306f, 0xbe4cd5da,
+ 0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,
+ 0x6dcd47e1, 0xbe374557,
+ 0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,
+ 0x6dc05b18, 0xbe21b75d,
+ 0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,
+ 0x6db36a14, 0xbe0c2bed,
+ 0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,
+ 0x6da674d5, 0xbdf6a309,
+ 0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,
+ 0x6d997b5b, 0xbde11cb0,
+ 0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,
+ 0x6d8c7da8, 0xbdcb98e3,
+ 0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,
+ 0x6d7f7bbc, 0xbdb617a4,
+ 0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,
+ 0x6d727597, 0xbda098f3,
+ 0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,
+ 0x6d656b3a, 0xbd8b1cd2,
+ 0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,
+ 0x6d585ca6, 0xbd75a340,
+ 0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,
+ 0x6d4b49da, 0xbd602c3f,
+ 0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,
+ 0x6d3e32d7, 0xbd4ab7cf,
+ 0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,
+ 0x6d31179e, 0xbd3545f2,
+ 0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,
+ 0x6d23f830, 0xbd1fd6a8,
+ 0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,
+ 0x6d16d48c, 0xbd0a69f2,
+ 0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,
+ 0x6d09acb4, 0xbcf4ffd1,
+ 0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,
+ 0x6cfc80a7, 0xbcdf9846,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,
+ 0x6cef5067, 0xbcca3351,
+ 0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,
+ 0x6ce21bf4, 0xbcb4d0f4,
+ 0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,
+ 0x6cd4e34e, 0xbc9f712e,
+ 0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,
+ 0x6cc7a676, 0xbc8a1402,
+ 0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,
+ 0x6cba656c, 0xbc74b96f,
+ 0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,
+ 0x6cad2031, 0xbc5f6177,
+ 0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,
+ 0x6c9fd6c6, 0xbc4a0c1b,
+ 0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,
+ 0x6c92892a, 0xbc34b95b,
+ 0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,
+ 0x6c85375f, 0xbc1f6938,
+ 0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,
+ 0x6c77e165, 0xbc0a1bb3,
+ 0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,
+ 0x6c6a873d, 0xbbf4d0cc,
+ 0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,
+ 0x6c5d28e6, 0xbbdf8885,
+ 0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,
+ 0x6c4fc662, 0xbbca42df,
+ 0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,
+ 0x6c425fb1, 0xbbb4ffda,
+ 0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,
+ 0x6c34f4d3, 0xbb9fbf77,
+ 0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,
+ 0x6c2785ca, 0xbb8a81b6,
+ 0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,
+ 0x6c1a1295, 0xbb754699,
+ 0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,
+ 0x6c0c9b35, 0xbb600e21,
+ 0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,
+ 0x6bff1faa, 0xbb4ad84e,
+ 0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,
+ 0x6bf19ff6, 0xbb35a521,
+ 0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,
+ 0x6be41c18, 0xbb20749c,
+ 0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,
+ 0x6bd69412, 0xbb0b46bd,
+ 0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,
+ 0x6bc907e3, 0xbaf61b88,
+ 0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,
+ 0x6bbb778d, 0xbae0f2fc,
+ 0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,
+ 0x6bade30f, 0xbacbcd1a,
+ 0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,
+ 0x6ba04a6a, 0xbab6a9e3,
+ 0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,
+ 0x6b92ada0, 0xbaa18958,
+ 0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,
+ 0x6b850caf, 0xba8c6b79,
+ 0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,
+ 0x6b776799, 0xba775048,
+ 0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,
+ 0x6b69be5f, 0xba6237c5,
+ 0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,
+ 0x6b5c1101, 0xba4d21f2,
+ 0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,
+ 0x6b4e5f7f, 0xba380ece,
+ 0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,
+ 0x6b40a9d9, 0xba22fe5b,
+ 0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,
+ 0x6b32f012, 0xba0df099,
+ 0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,
+ 0x6b253228, 0xb9f8e58a,
+ 0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,
+ 0x6b17701d, 0xb9e3dd2e,
+ 0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,
+ 0x6b09a9f1, 0xb9ced786,
+ 0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,
+ 0x6afbdfa4, 0xb9b9d493,
+ 0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,
+ 0x6aee1138, 0xb9a4d455,
+ 0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,
+ 0x6ae03eac, 0xb98fd6cd,
+ 0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,
+ 0x6ad26802, 0xb97adbfd,
+ 0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,
+ 0x6ac48d39, 0xb965e3e5,
+ 0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,
+ 0x6ab6ae52, 0xb950ee86,
+ 0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,
+ 0x6aa8cb4e, 0xb93bfbe0,
+ 0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,
+ 0x6a9ae42e, 0xb9270bf5,
+ 0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,
+ 0x6a8cf8f1, 0xb9121ec5,
+ 0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,
+ 0x6a7f0999, 0xb8fd3451,
+ 0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,
+ 0x6a711625, 0xb8e84c99,
+ 0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,
+ 0x6a631e97, 0xb8d367a0,
+ 0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,
+ 0x6a5522ef, 0xb8be8565,
+ 0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,
+ 0x6a47232e, 0xb8a9a5e9,
+ 0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,
+ 0x6a391f54, 0xb894c92d,
+ 0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,
+ 0x6a2b1761, 0xb87fef33,
+ 0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,
+ 0x6a1d0b57, 0xb86b17f9,
+ 0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,
+ 0x6a0efb35, 0xb8564383,
+ 0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,
+ 0x6a00e6fc, 0xb84171cf,
+ 0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,
+ 0x69f2cead, 0xb82ca2e0,
+ 0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,
+ 0x69e4b249, 0xb817d6b6,
+ 0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,
+ 0x69d691cf, 0xb8030d51,
+ 0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,
+ 0x69c86d41, 0xb7ee46b3,
+ 0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,
+ 0x69ba449f, 0xb7d982dc,
+ 0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,
+ 0x69ac17e9, 0xb7c4c1cd,
+ 0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,
+ 0x699de721, 0xb7b00387,
+ 0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,
+ 0x698fb246, 0xb79b480b,
+ 0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,
+ 0x69817959, 0xb7868f59,
+ 0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,
+ 0x69733c5b, 0xb771d972,
+ 0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,
+ 0x6964fb4c, 0xb75d2658,
+ 0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,
+ 0x6956b62d, 0xb748760b,
+ 0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,
+ 0x69486cfe, 0xb733c88b,
+ 0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,
+ 0x693a1fc0, 0xb71f1dd9,
+ 0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,
+ 0x692bce73, 0xb70a75f7,
+ 0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,
+ 0x691d7919, 0xb6f5d0e5,
+ 0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,
+ 0x690f1fb1, 0xb6e12ea4,
+ 0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,
+ 0x6900c23c, 0xb6cc8f35,
+ 0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,
+ 0x68f260bb, 0xb6b7f298,
+ 0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,
+ 0x68e3fb2e, 0xb6a358ce,
+ 0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,
+ 0x68d59196, 0xb68ec1d9,
+ 0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,
+ 0x68c723f3, 0xb67a2db8,
+ 0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,
+ 0x68b8b247, 0xb6659c6d,
+ 0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,
+ 0x68aa3c90, 0xb6510df8,
+ 0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,
+ 0x689bc2d1, 0xb63c825b,
+ 0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,
+ 0x688d4509, 0xb627f995,
+ 0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,
+ 0x687ec339, 0xb61373a9,
+ 0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,
+ 0x68703d62, 0xb5fef095,
+ 0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,
+ 0x6861b384, 0xb5ea705d,
+ 0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,
+ 0x685325a0, 0xb5d5f2ff,
+ 0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,
+ 0x684493b6, 0xb5c1787e,
+ 0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,
+ 0x6835fdc7, 0xb5ad00d9,
+ 0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,
+ 0x682763d4, 0xb5988c12,
+ 0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,
+ 0x6818c5dd, 0xb5841a29,
+ 0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,
+ 0x680a23e2, 0xb56fab1f,
+ 0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,
+ 0x67fb7de5, 0xb55b3ef5,
+ 0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,
+ 0x67ecd3e5, 0xb546d5ac,
+ 0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,
+ 0x67de25e3, 0xb5326f45,
+ 0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,
+ 0x67cf73e1, 0xb51e0bbf,
+ 0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,
+ 0x67c0bddd, 0xb509ab1d,
+ 0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,
+ 0x67b203da, 0xb4f54d5f,
+ 0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,
+ 0x67a345d8, 0xb4e0f285,
+ 0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,
+ 0x679483d6, 0xb4cc9a90,
+ 0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,
+ 0x6785bdd6, 0xb4b84582,
+ 0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,
+ 0x6776f3d9, 0xb4a3f35b,
+ 0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,
+ 0x676825de, 0xb48fa41c,
+ 0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,
+ 0x675953e7, 0xb47b57c5,
+ 0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,
+ 0x674a7df4, 0xb4670e57,
+ 0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,
+ 0x673ba405, 0xb452c7d4,
+ 0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,
+ 0x672cc61c, 0xb43e843b,
+ 0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,
+ 0x671de438, 0xb42a438e,
+ 0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,
+ 0x670efe5a, 0xb41605ce,
+ 0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,
+ 0x67001483, 0xb401cafb,
+ 0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,
+ 0x66f126b4, 0xb3ed9316,
+ 0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,
+ 0x66e234ed, 0xb3d95e1f,
+ 0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,
+ 0x66d33f2e, 0xb3c52c19,
+ 0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,
+ 0x66c44579, 0xb3b0fd02,
+ 0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,
+ 0x66b547cd, 0xb39cd0dd,
+ 0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,
+ 0x66a6462b, 0xb388a7aa,
+ 0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,
+ 0x66974095, 0xb3748169,
+ 0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,
+ 0x66883709, 0xb3605e1c,
+ 0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,
+ 0x6679298a, 0xb34c3dc3,
+ 0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,
+ 0x666a1818, 0xb338205f,
+ 0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,
+ 0x665b02b3, 0xb32405f1,
+ 0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,
+ 0x664be95b, 0xb30fee79,
+ 0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,
+ 0x663ccc12, 0xb2fbd9f9,
+ 0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,
+ 0x662daad8, 0xb2e7c871,
+ 0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,
+ 0x661e85ad, 0xb2d3b9e2,
+ 0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,
+ 0x660f5c93, 0xb2bfae4c,
+ 0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,
+ 0x66002f89, 0xb2aba5b1,
+ 0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,
+ 0x65f0fe91, 0xb297a011,
+ 0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,
+ 0x65e1c9aa, 0xb2839d6d,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,
+ 0x65d290d6, 0xb26f9dc6,
+ 0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,
+ 0x65c35415, 0xb25ba11d,
+ 0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,
+ 0x65b41367, 0xb247a771,
+ 0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,
+ 0x65a4cece, 0xb233b0c5,
+ 0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,
+ 0x6595864a, 0xb21fbd19,
+ 0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,
+ 0x658639db, 0xb20bcc6d,
+ 0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,
+ 0x6576e982, 0xb1f7dec2,
+ 0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,
+ 0x6567953f, 0xb1e3f41a,
+ 0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,
+ 0x65583d14, 0xb1d00c75,
+ 0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,
+ 0x6548e101, 0xb1bc27d3,
+ 0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,
+ 0x65398105, 0xb1a84636,
+ 0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,
+ 0x652a1d23, 0xb194679e,
+ 0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,
+ 0x651ab55b, 0xb1808c0c,
+ 0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,
+ 0x650b49ac, 0xb16cb380,
+ 0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,
+ 0x64fbda18, 0xb158ddfd,
+ 0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,
+ 0x64ec66a0, 0xb1450b81,
+ 0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,
+ 0x64dcef44, 0xb1313c0e,
+ 0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,
+ 0x64cd7404, 0xb11d6fa6,
+ 0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,
+ 0x64bdf4e1, 0xb109a648,
+ 0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,
+ 0x64ae71dc, 0xb0f5dff5,
+ 0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,
+ 0x649eeaf5, 0xb0e21cae,
+ 0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,
+ 0x648f602d, 0xb0ce5c74,
+ 0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,
+ 0x647fd185, 0xb0ba9f48,
+ 0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,
+ 0x64703efc, 0xb0a6e52a,
+ 0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,
+ 0x6460a895, 0xb0932e1b,
+ 0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,
+ 0x64510e4e, 0xb07f7a1c,
+ 0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,
+ 0x6441702a, 0xb06bc92e,
+ 0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,
+ 0x6431ce28, 0xb0581b51,
+ 0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,
+ 0x6422284a, 0xb0447087,
+ 0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,
+ 0x64127e8f, 0xb030c8cf,
+ 0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,
+ 0x6402d0f8, 0xb01d242b,
+ 0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,
+ 0x63f31f86, 0xb009829c,
+ 0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,
+ 0x63e36a3a, 0xaff5e421,
+ 0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,
+ 0x63d3b114, 0xafe248bd,
+ 0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,
+ 0x63c3f415, 0xafceb06f,
+ 0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,
+ 0x63b4333d, 0xafbb1b39,
+ 0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,
+ 0x63a46e8d, 0xafa7891b,
+ 0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,
+ 0x6394a606, 0xaf93fa16,
+ 0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,
+ 0x6384d9a7, 0xaf806e2b,
+ 0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,
+ 0x63750973, 0xaf6ce55a,
+ 0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,
+ 0x63653569, 0xaf595fa4,
+ 0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,
+ 0x63555d8a, 0xaf45dd0b,
+ 0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,
+ 0x634581d6, 0xaf325d8e,
+ 0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,
+ 0x6335a24f, 0xaf1ee12e,
+ 0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,
+ 0x6325bef5, 0xaf0b67ed,
+ 0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,
+ 0x6315d7c8, 0xaef7f1cb,
+ 0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,
+ 0x6305ecc9, 0xaee47ec9,
+ 0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,
+ 0x62f5fdf9, 0xaed10ee7,
+ 0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,
+ 0x62e60b58, 0xaebda227,
+ 0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,
+ 0x62d614e7, 0xaeaa3888,
+ 0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,
+ 0x62c61aa7, 0xae96d20c,
+ 0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,
+ 0x62b61c98, 0xae836eb4,
+ 0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,
+ 0x62a61aba, 0xae700e80,
+ 0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,
+ 0x6296150f, 0xae5cb171,
+ 0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,
+ 0x62860b97, 0xae495787,
+ 0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,
+ 0x6275fe52, 0xae3600c4,
+ 0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,
+ 0x6265ed42, 0xae22ad29,
+ 0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,
+ 0x6255d866, 0xae0f5cb5,
+ 0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,
+ 0x6245bfc0, 0xadfc0f6a,
+ 0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,
+ 0x6235a351, 0xade8c548,
+ 0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,
+ 0x62258317, 0xadd57e51,
+ 0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,
+ 0x62155f16, 0xadc23a85,
+ 0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,
+ 0x6205374c, 0xadaef9e4,
+ 0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,
+ 0x61f50bba, 0xad9bbc70,
+ 0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,
+ 0x61e4dc62, 0xad888229,
+ 0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,
+ 0x61d4a944, 0xad754b0f,
+ 0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,
+ 0x61c47260, 0xad621725,
+ 0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,
+ 0x61b437b7, 0xad4ee66a,
+ 0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,
+ 0x61a3f94a, 0xad3bb8df,
+ 0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,
+ 0x6193b719, 0xad288e85,
+ 0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,
+ 0x61837126, 0xad15675c,
+ 0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,
+ 0x61732770, 0xad024366,
+ 0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,
+ 0x6162d9f8, 0xacef22a3,
+ 0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,
+ 0x615288be, 0xacdc0514,
+ 0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,
+ 0x614233c5, 0xacc8eab9,
+ 0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,
+ 0x6131db0b, 0xacb5d394,
+ 0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,
+ 0x61217e92, 0xaca2bfa4,
+ 0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,
+ 0x61111e5b, 0xac8faeec,
+ 0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,
+ 0x6100ba65, 0xac7ca16b,
+ 0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,
+ 0x60f052b2, 0xac699722,
+ 0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,
+ 0x60dfe743, 0xac569012,
+ 0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,
+ 0x60cf7817, 0xac438c3c,
+ 0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,
+ 0x60bf0530, 0xac308ba0,
+ 0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,
+ 0x60ae8e8d, 0xac1d8e40,
+ 0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,
+ 0x609e1431, 0xac0a941b,
+ 0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,
+ 0x608d961b, 0xabf79d33,
+ 0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,
+ 0x607d144c, 0xabe4a988,
+ 0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,
+ 0x606c8ec5, 0xabd1b91c,
+ 0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,
+ 0x605c0587, 0xabbecbee,
+ 0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,
+ 0x604b7891, 0xababe200,
+ 0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,
+ 0x603ae7e5, 0xab98fb52,
+ 0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,
+ 0x602a5383, 0xab8617e6,
+ 0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,
+ 0x6019bb6b, 0xab7337bb,
+ 0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,
+ 0x60091fa0, 0xab605ad2,
+ 0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,
+ 0x5ff88021, 0xab4d812d,
+ 0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,
+ 0x5fe7dcee, 0xab3aaacb,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,
+ 0x5fd73609, 0xab27d7ae,
+ 0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,
+ 0x5fc68b72, 0xab1507d7,
+ 0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,
+ 0x5fb5dd29, 0xab023b46,
+ 0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,
+ 0x5fa52b31, 0xaaef71fb,
+ 0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,
+ 0x5f947588, 0xaadcabf8,
+ 0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,
+ 0x5f83bc2f, 0xaac9e93e,
+ 0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,
+ 0x5f72ff28, 0xaab729cc,
+ 0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,
+ 0x5f623e73, 0xaaa46da4,
+ 0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,
+ 0x5f517a11, 0xaa91b4c7,
+ 0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,
+ 0x5f40b202, 0xaa7eff34,
+ 0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,
+ 0x5f2fe647, 0xaa6c4cee,
+ 0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,
+ 0x5f1f16e0, 0xaa599df4,
+ 0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,
+ 0x5f0e43ce, 0xaa46f248,
+ 0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,
+ 0x5efd6d13, 0xaa3449e9,
+ 0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,
+ 0x5eec92ae, 0xaa21a4d9,
+ 0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,
+ 0x5edbb49f, 0xaa0f0319,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,
+ 0x5ecad2e9, 0xa9fc64a9,
+ 0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,
+ 0x5eb9ed8b, 0xa9e9c98a,
+ 0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,
+ 0x5ea90487, 0xa9d731bd,
+ 0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,
+ 0x5e9817dc, 0xa9c49d42,
+ 0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,
+ 0x5e87278b, 0xa9b20c1a,
+ 0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,
+ 0x5e763395, 0xa99f7e46,
+ 0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,
+ 0x5e653bfc, 0xa98cf3c6,
+ 0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,
+ 0x5e5440be, 0xa97a6c9c,
+ 0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,
+ 0x5e4341de, 0xa967e8c7,
+ 0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,
+ 0x5e323f5b, 0xa9556849,
+ 0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,
+ 0x5e213936, 0xa942eb23,
+ 0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,
+ 0x5e102f71, 0xa9307155,
+ 0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,
+ 0x5dff220b, 0xa91dfadf,
+ 0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,
+ 0x5dee1105, 0xa90b87c3,
+ 0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,
+ 0x5ddcfc61, 0xa8f91801,
+ 0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,
+ 0x5dcbe41d, 0xa8e6ab9a,
+ 0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,
+ 0x5dbac83d, 0xa8d4428f,
+ 0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,
+ 0x5da9a8bf, 0xa8c1dce0,
+ 0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,
+ 0x5d9885a5, 0xa8af7a8e,
+ 0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,
+ 0x5d875eef, 0xa89d1b99,
+ 0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,
+ 0x5d76349d, 0xa88ac004,
+ 0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,
+ 0x5d6506b2, 0xa87867cd,
+ 0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,
+ 0x5d53d52d, 0xa86612f6,
+ 0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,
+ 0x5d42a00e, 0xa853c180,
+ 0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,
+ 0x5d316757, 0xa841736c,
+ 0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,
+ 0x5d202b09, 0xa82f28b9,
+ 0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,
+ 0x5d0eeb23, 0xa81ce169,
+ 0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,
+ 0x5cfda7a7, 0xa80a9d7c,
+ 0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,
+ 0x5cec6095, 0xa7f85cf3,
+ 0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,
+ 0x5cdb15ed, 0xa7e61fd0,
+ 0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,
+ 0x5cc9c7b2, 0xa7d3e611,
+ 0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,
+ 0x5cb875e3, 0xa7c1afb9,
+ 0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,
+ 0x5ca72080, 0xa7af7cc8,
+ 0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,
+ 0x5c95c78b, 0xa79d4d3f,
+ 0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,
+ 0x5c846b05, 0xa78b211e,
+ 0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,
+ 0x5c730aed, 0xa778f866,
+ 0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,
+ 0x5c61a745, 0xa766d317,
+ 0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,
+ 0x5c50400d, 0xa754b134,
+ 0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,
+ 0x5c3ed545, 0xa74292bb,
+ 0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,
+ 0x5c2d66f0, 0xa73077ae,
+ 0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,
+ 0x5c1bf50d, 0xa71e600d,
+ 0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,
+ 0x5c0a7f9c, 0xa70c4bda,
+ 0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,
+ 0x5bf906a0, 0xa6fa3b15,
+ 0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,
+ 0x5be78a17, 0xa6e82dbe,
+ 0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,
+ 0x5bd60a03, 0xa6d623d7,
+ 0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,
+ 0x5bc48666, 0xa6c41d60,
+ 0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,
+ 0x5bb2ff3e, 0xa6b21a59,
+ 0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,
+ 0x5ba1748d, 0xa6a01ac4,
+ 0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,
+ 0x5b8fe654, 0xa68e1ea1,
+ 0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,
+ 0x5b7e5493, 0xa67c25f0,
+ 0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,
+ 0x5b6cbf4c, 0xa66a30b3,
+ 0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,
+ 0x5b5b267e, 0xa6583eeb,
+ 0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,
+ 0x5b498a2a, 0xa6465097,
+ 0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,
+ 0x5b37ea51, 0xa63465b9,
+ 0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,
+ 0x5b2646f4, 0xa6227e50,
+ 0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,
+ 0x5b14a014, 0xa6109a5f,
+ 0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,
+ 0x5b02f5b0, 0xa5feb9e6,
+ 0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,
+ 0x5af147ca, 0xa5ecdce5,
+ 0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,
+ 0x5adf9663, 0xa5db035c,
+ 0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,
+ 0x5acde17b, 0xa5c92d4e,
+ 0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,
+ 0x5abc2912, 0xa5b75aba,
+ 0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,
+ 0x5aaa6d2b, 0xa5a58ba1,
+ 0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,
+ 0x5a98adc4, 0xa593c004,
+ 0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,
+ 0x5a86eadf, 0xa581f7e3,
+ 0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,
+ 0x5a75247c, 0xa570333f,
+ 0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,
+ 0x5a635a9d, 0xa55e7219,
+ 0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,
+ 0x5a518d42, 0xa54cb472,
+ 0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,
+ 0x5a3fbc6b, 0xa53afa49,
+ 0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,
+ 0x5a2de81a, 0xa52943a1,
+ 0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,
+ 0x5a1c104f, 0xa5179079,
+ 0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,
+ 0x5a0a350a, 0xa505e0d2,
+ 0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,
+ 0x59f8564c, 0xa4f434ae,
+ 0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,
+ 0x59e67417, 0xa4e28c0c,
+ 0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,
+ 0x59d48e6a, 0xa4d0e6ed,
+ 0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,
+ 0x59c2a547, 0xa4bf4552,
+ 0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,
+ 0x59b0b8ae, 0xa4ada73c,
+ 0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,
+ 0x599ec8a0, 0xa49c0cab,
+ 0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,
+ 0x598cd51d, 0xa48a75a0,
+ 0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,
+ 0x597ade26, 0xa478e21b,
+ 0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,
+ 0x5968e3bc, 0xa467521e,
+ 0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,
+ 0x5956e5e0, 0xa455c5a9,
+ 0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,
+ 0x5944e492, 0xa4443cbd,
+ 0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,
+ 0x5932dfd3, 0xa432b75a,
+ 0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,
+ 0x5920d7a3, 0xa4213581,
+ 0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,
+ 0x590ecc04, 0xa40fb733,
+ 0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,
+ 0x58fcbcf6, 0xa3fe3c71,
+ 0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,
+ 0x58eaaa7a, 0xa3ecc53a,
+ 0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,
+ 0x58d89490, 0xa3db5190,
+ 0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,
+ 0x58c67b39, 0xa3c9e174,
+ 0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,
+ 0x58b45e76, 0xa3b874e5,
+ 0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,
+ 0x58a23e48, 0xa3a70be6,
+ 0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,
+ 0x58901aaf, 0xa395a675,
+ 0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,
+ 0x587df3ab, 0xa3844495,
+ 0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,
+ 0x586bc93f, 0xa372e646,
+ 0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,
+ 0x58599b69, 0xa3618b88,
+ 0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,
+ 0x58476a2c, 0xa350345c,
+ 0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,
+ 0x58353587, 0xa33ee0c3,
+ 0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,
+ 0x5822fd7c, 0xa32d90be,
+ 0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,
+ 0x5810c20b, 0xa31c444c,
+ 0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,
+ 0x57fe8335, 0xa30afb70,
+ 0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,
+ 0x57ec40fa, 0xa2f9b629,
+ 0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,
+ 0x57d9fb5c, 0xa2e87477,
+ 0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,
+ 0x57c7b25a, 0xa2d7365d,
+ 0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,
+ 0x57b565f6, 0xa2c5fbda,
+ 0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,
+ 0x57a31631, 0xa2b4c4f0,
+ 0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,
+ 0x5790c30a, 0xa2a3919e,
+ 0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,
+ 0x577e6c84, 0xa29261e5,
+ 0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,
+ 0x576c129d, 0xa28135c7,
+ 0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,
+ 0x5759b558, 0xa2700d43,
+ 0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,
+ 0x574754b5, 0xa25ee85b,
+ 0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,
+ 0x5734f0b5, 0xa24dc70f,
+ 0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,
+ 0x57228957, 0xa23ca95f,
+ 0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,
+ 0x57101e9e, 0xa22b8f4d,
+ 0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,
+ 0x56fdb08a, 0xa21a78d9,
+ 0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,
+ 0x56eb3f1a, 0xa2096604,
+ 0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,
+ 0x56d8ca51, 0xa1f856ce,
+ 0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,
+ 0x56c6522f, 0xa1e74b38,
+ 0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,
+ 0x56b3d6b5, 0xa1d64343,
+ 0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,
+ 0x56a157e3, 0xa1c53ef0,
+ 0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,
+ 0x568ed5b9, 0xa1b43e3e,
+ 0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,
+ 0x567c503a, 0xa1a3412f,
+ 0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,
+ 0x5669c765, 0xa19247c3,
+ 0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,
+ 0x56573b3b, 0xa18151fb,
+ 0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,
+ 0x5644abbc, 0xa1705fd8,
+ 0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,
+ 0x563218eb, 0xa15f715a,
+ 0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,
+ 0x561f82c7, 0xa14e8682,
+ 0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,
+ 0x560ce950, 0xa13d9f51,
+ 0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,
+ 0x55fa4c89, 0xa12cbbc7,
+ 0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,
+ 0x55e7ac71, 0xa11bdbe4,
+ 0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,
+ 0x55d50909, 0xa10affab,
+ 0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,
+ 0x55c26251, 0xa0fa271a,
+ 0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,
+ 0x55afb84c, 0xa0e95234,
+ 0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,
+ 0x559d0af9, 0xa0d880f7,
+ 0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,
+ 0x558a5a58, 0xa0c7b366,
+ 0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,
+ 0x5577a66c, 0xa0b6e981,
+ 0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,
+ 0x5564ef34, 0xa0a62348,
+ 0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,
+ 0x555234b1, 0xa09560bc,
+ 0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,
+ 0x553f76e4, 0xa084a1de,
+ 0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,
+ 0x552cb5ce, 0xa073e6af,
+ 0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,
+ 0x5519f16f, 0xa0632f2e,
+ 0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,
+ 0x550729c9, 0xa0527b5d,
+ 0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,
+ 0x54f45edb, 0xa041cb3c,
+ 0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,
+ 0x54e190a6, 0xa0311ecd,
+ 0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,
+ 0x54cebf2c, 0xa020760e,
+ 0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,
+ 0x54bbea6d, 0xa00fd102,
+ 0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,
+ 0x54a91269, 0x9fff2fa9,
+ 0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,
+ 0x54963722, 0x9fee9204,
+ 0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,
+ 0x54835898, 0x9fddf812,
+ 0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,
+ 0x547076cc, 0x9fcd61d6,
+ 0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,
+ 0x545d91bf, 0x9fbccf4f,
+ 0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,
+ 0x544aa971, 0x9fac407e,
+ 0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,
+ 0x5437bde3, 0x9f9bb563,
+ 0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,
+ 0x5424cf16, 0x9f8b2e00,
+ 0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,
+ 0x5411dd0a, 0x9f7aaa55,
+ 0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,
+ 0x53fee7c1, 0x9f6a2a63,
+ 0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,
+ 0x53ebef3a, 0x9f59ae29,
+ 0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,
+ 0x53d8f378, 0x9f4935aa,
+ 0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,
+ 0x53c5f479, 0x9f38c0e5,
+ 0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,
+ 0x53b2f240, 0x9f284fdc,
+ 0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,
+ 0x539feccd, 0x9f17e28e,
+ 0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,
+ 0x538ce421, 0x9f0778fd,
+ 0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,
+ 0x5379d83c, 0x9ef71328,
+ 0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,
+ 0x5366c91f, 0x9ee6b112,
+ 0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,
+ 0x5353b6cb, 0x9ed652ba,
+ 0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,
+ 0x5340a140, 0x9ec5f820,
+ 0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,
+ 0x532d8880, 0x9eb5a146,
+ 0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,
+ 0x531a6c8b, 0x9ea54e2d,
+ 0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,
+ 0x53074d62, 0x9e94fed4,
+ 0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,
+ 0x52f42b05, 0x9e84b33d,
+ 0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,
+ 0x52e10576, 0x9e746b68,
+ 0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,
+ 0x52cddcb5, 0x9e642756,
+ 0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,
+ 0x52bab0c2, 0x9e53e707,
+ 0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,
+ 0x52a7819f, 0x9e43aa7c,
+ 0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,
+ 0x52944f4c, 0x9e3371b5,
+ 0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,
+ 0x528119ca, 0x9e233cb4,
+ 0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,
+ 0x526de11a, 0x9e130b79,
+ 0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,
+ 0x525aa53c, 0x9e02de04,
+ 0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,
+ 0x52476631, 0x9df2b456,
+ 0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,
+ 0x523423fb, 0x9de28e70,
+ 0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,
+ 0x5220de99, 0x9dd26c53,
+ 0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,
+ 0x520d960c, 0x9dc24dfe,
+ 0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,
+ 0x51fa4a56, 0x9db23373,
+ 0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,
+ 0x51e6fb76, 0x9da21cb2,
+ 0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,
+ 0x51d3a96f, 0x9d9209bd,
+ 0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,
+ 0x51c0543f, 0x9d81fa92,
+ 0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,
+ 0x51acfbe9, 0x9d71ef34,
+ 0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,
+ 0x5199a06d, 0x9d61e7a2,
+ 0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,
+ 0x518641cb, 0x9d51e3dd,
+ 0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,
+ 0x5172e005, 0x9d41e3e7,
+ 0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,
+ 0x515f7b1a, 0x9d31e7bf,
+ 0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,
+ 0x514c130d, 0x9d21ef66,
+ 0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,
+ 0x5138a7dd, 0x9d11fadd,
+ 0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,
+ 0x5125398c, 0x9d020a25,
+ 0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,
+ 0x5111c81a, 0x9cf21d3d,
+ 0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,
+ 0x50fe5388, 0x9ce23427,
+ 0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,
+ 0x50eadbd6, 0x9cd24ee4,
+ 0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,
+ 0x50d76106, 0x9cc26d73,
+ 0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,
+ 0x50c3e317, 0x9cb28fd5,
+ 0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,
+ 0x50b0620c, 0x9ca2b60c,
+ 0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,
+ 0x509cdde4, 0x9c92e017,
+ 0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,
+ 0x508956a1, 0x9c830df8,
+ 0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,
+ 0x5075cc43, 0x9c733faf,
+ 0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,
+ 0x50623ecb, 0x9c63753c,
+ 0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,
+ 0x504eae39, 0x9c53aea0,
+ 0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,
+ 0x503b1a8f, 0x9c43ebdc,
+ 0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,
+ 0x502783cd, 0x9c342cf0,
+ 0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,
+ 0x5013e9f4, 0x9c2471de,
+ 0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,
+ 0x50004d04, 0x9c14baa4,
+ 0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,
+ 0x4fecacff, 0x9c050745,
+ 0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,
+ 0x4fd909e5, 0x9bf557c1,
+ 0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,
+ 0x4fc563b7, 0x9be5ac18,
+ 0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,
+ 0x4fb1ba76, 0x9bd6044b,
+ 0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,
+ 0x4f9e0e22, 0x9bc6605b,
+ 0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,
+ 0x4f8a5ebd, 0x9bb6c048,
+ 0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,
+ 0x4f76ac46, 0x9ba72413,
+ 0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,
+ 0x4f62f6bf, 0x9b978bbc,
+ 0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,
+ 0x4f4f3e29, 0x9b87f744,
+ 0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,
+ 0x4f3b8284, 0x9b7866ab,
+ 0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,
+ 0x4f27c3d1, 0x9b68d9f3,
+ 0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,
+ 0x4f140210, 0x9b59511c,
+ 0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,
+ 0x4f003d43, 0x9b49cc26,
+ 0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,
+ 0x4eec756b, 0x9b3a4b11,
+ 0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,
+ 0x4ed8aa87, 0x9b2acde0,
+ 0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,
+ 0x4ec4dc99, 0x9b1b5492,
+ 0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,
+ 0x4eb10ba2, 0x9b0bdf27,
+ 0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,
+ 0x4e9d37a3, 0x9afc6da1,
+ 0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,
+ 0x4e89609b, 0x9aed0000,
+ 0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,
+ 0x4e75868c, 0x9add9644,
+ 0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,
+ 0x4e61a977, 0x9ace306f,
+ 0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,
+ 0x4e4dc95c, 0x9abece80,
+ 0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,
+ 0x4e39e63d, 0x9aaf7079,
+ 0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,
+ 0x4e260019, 0x9aa01659,
+ 0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,
+ 0x4e1216f2, 0x9a90c022,
+ 0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,
+ 0x4dfe2ac9, 0x9a816dd5,
+ 0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,
+ 0x4dea3b9d, 0x9a721f71,
+ 0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,
+ 0x4dd64971, 0x9a62d4f7,
+ 0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,
+ 0x4dc25445, 0x9a538e68,
+ 0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,
+ 0x4dae5c19, 0x9a444bc5,
+ 0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,
+ 0x4d9a60ee, 0x9a350d0d,
+ 0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,
+ 0x4d8662c6, 0x9a25d243,
+ 0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,
+ 0x4d7261a0, 0x9a169b65,
+ 0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,
+ 0x4d5e5d7e, 0x9a076875,
+ 0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,
+ 0x4d4a5661, 0x99f83974,
+ 0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,
+ 0x4d364c48, 0x99e90e62,
+ 0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,
+ 0x4d223f36, 0x99d9e73f,
+ 0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,
+ 0x4d0e2f2a, 0x99cac40d,
+ 0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,
+ 0x4cfa1c26, 0x99bba4cb,
+ 0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,
+ 0x4ce6062a, 0x99ac897b,
+ 0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,
+ 0x4cd1ed37, 0x999d721c,
+ 0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,
+ 0x4cbdd14e, 0x998e5eb1,
+ 0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,
+ 0x4ca9b26f, 0x997f4f38,
+ 0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,
+ 0x4c95909c, 0x997043b2,
+ 0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,
+ 0x4c816bd5, 0x99613c22,
+ 0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,
+ 0x4c6d441b, 0x99523885,
+ 0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,
+ 0x4c59196f, 0x994338df,
+ 0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,
+ 0x4c44ebd1, 0x99343d2e,
+ 0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,
+ 0x4c30bb42, 0x99254574,
+ 0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,
+ 0x4c1c87c3, 0x991651b1,
+ 0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,
+ 0x4c085156, 0x990761e5,
+ 0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,
+ 0x4bf417f9, 0x98f87612,
+ 0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,
+ 0x4bdfdbaf, 0x98e98e38,
+ 0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,
+ 0x4bcb9c79, 0x98daaa57,
+ 0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,
+ 0x4bb75a56, 0x98cbca70,
+ 0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,
+ 0x4ba31548, 0x98bcee84,
+ 0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,
+ 0x4b8ecd4f, 0x98ae1693,
+ 0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,
+ 0x4b7a826d, 0x989f429e,
+ 0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,
+ 0x4b6634a2, 0x989072a5,
+ 0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,
+ 0x4b51e3ee, 0x9881a6a9,
+ 0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,
+ 0x4b3d9053, 0x9872deaa,
+ 0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,
+ 0x4b2939d2, 0x98641aa9,
+ 0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,
+ 0x4b14e06b, 0x98555aa7,
+ 0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,
+ 0x4b00841f, 0x98469ea4,
+ 0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,
+ 0x4aec24ee, 0x9837e6a1,
+ 0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,
+ 0x4ad7c2da, 0x9829329e,
+ 0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,
+ 0x4ac35de4, 0x981a829c,
+ 0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,
+ 0x4aaef60b, 0x980bd69b,
+ 0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,
+ 0x4a9a8b52, 0x97fd2e9c,
+ 0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,
+ 0x4a861db8, 0x97ee8aa0,
+ 0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,
+ 0x4a71ad3e, 0x97dfeaa7,
+ 0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,
+ 0x4a5d39e6, 0x97d14eb2,
+ 0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,
+ 0x4a48c3b0, 0x97c2b6c1,
+ 0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,
+ 0x4a344a9d, 0x97b422d4,
+ 0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,
+ 0x4a1fcead, 0x97a592ed,
+ 0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,
+ 0x4a0b4fe2, 0x9797070c,
+ 0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,
+ 0x49f6ce3c, 0x97887f32,
+ 0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,
+ 0x49e249bc, 0x9779fb5e,
+ 0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,
+ 0x49cdc263, 0x976b7b92,
+ 0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,
+ 0x49b93832, 0x975cffcf,
+ 0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,
+ 0x49a4ab28, 0x974e8813,
+ 0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,
+ 0x49901b48, 0x97401462,
+ 0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,
+ 0x497b8892, 0x9731a4ba,
+ 0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,
+ 0x4966f307, 0x9723391c,
+ 0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,
+ 0x49525aa7, 0x9714d18a,
+ 0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,
+ 0x493dbf74, 0x97066e03,
+ 0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,
+ 0x4929216e, 0x96f80e88,
+ 0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,
+ 0x49148095, 0x96e9b319,
+ 0x490f57ee, 0x96e61ce0, 0x490a2f1b, 0x96e286e7, 0x4905061a, 0x96def12f,
+ 0x48ffdcec, 0x96db5bb8,
+ 0x48fab391, 0x96d7c682, 0x48f58a09, 0x96d4318d, 0x48f06054, 0x96d09cd8,
+ 0x48eb3672, 0x96cd0865,
+ 0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,
+ 0x48d68d28, 0x96beb91f,
+ 0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,
+ 0x48c1e10f, 0x96b06de9,
+ 0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,
+ 0x48ad3228, 0x96a226c2,
+ 0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,
+ 0x48988074, 0x9693e3ab,
+ 0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,
+ 0x4883cbf4, 0x9685a4a4,
+ 0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,
+ 0x486f14a8, 0x967769af,
+ 0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,
+ 0x485a5a90, 0x966932cb,
+ 0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,
+ 0x48459daf, 0x965afff9,
+ 0x48406e08, 0x965773e7, 0x483b3e33, 0x9653e817, 0x48360e32, 0x96505c88,
+ 0x4830de05, 0x964cd139,
+ 0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,
+ 0x481c1b92, 0x963ea68d,
+ 0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,
+ 0x48075657, 0x96307ff5,
+ 0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,
+ 0x47f28e56, 0x96225d71,
+ 0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,
+ 0x47ddc38e, 0x96143f02,
+ 0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,
+ 0x47c8f601, 0x960624a9,
+ 0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,
+ 0x47b425af, 0x95f80e65,
+ 0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,
+ 0x479f529a, 0x95e9fc38,
+ 0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,
+ 0x478a7cc2, 0x95dbee21,
+ 0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,
+ 0x4775a428, 0x95cde423,
+ 0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,
+ 0x4760c8cd, 0x95bfde3c,
+ 0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,
+ 0x474beab1, 0x95b1dc6e,
+ 0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,
+ 0x473709d5, 0x95a3deb9,
+ 0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,
+ 0x4722263b, 0x9595e51e,
+ 0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,
+ 0x470d3fe3, 0x9587ef9e,
+ 0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,
+ 0x46f856cd, 0x9579fe38,
+ 0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,
+ 0x46e36afb, 0x956c10ed,
+ 0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,
+ 0x46ce7c6d, 0x955e27bf,
+ 0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,
+ 0x46b98b24, 0x955042ac,
+ 0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,
+ 0x46a49722, 0x954261b7,
+ 0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,
+ 0x468fa066, 0x953484df,
+ 0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,
+ 0x467aa6f2, 0x9526ac25,
+ 0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,
+ 0x4665aac6, 0x9518d78a,
+ 0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,
+ 0x4650abe3, 0x950b070e,
+ 0x464b6bbe, 0x95079394, 0x46462b6d, 0x9504205c, 0x4640eaf2, 0x9500ad66,
+ 0x463baa4a, 0x94fd3ab1,
+ 0x46366978, 0x94f9c83f, 0x4631287a, 0x94f6560f, 0x462be751, 0x94f2e421,
+ 0x4626a5fd, 0x94ef7275,
+ 0x4621647d, 0x94ec010b, 0x461c22d2, 0x94e88fe3, 0x4616e0fc, 0x94e51efd,
+ 0x46119efa, 0x94e1ae59,
+ 0x460c5cce, 0x94de3df8, 0x46071a76, 0x94dacdd8, 0x4601d7f3, 0x94d75dfa,
+ 0x45fc9545, 0x94d3ee5f,
+ 0x45f7526b, 0x94d07f05, 0x45f20f67, 0x94cd0fee, 0x45eccc37, 0x94c9a119,
+ 0x45e788dc, 0x94c63286,
+ 0x45e24556, 0x94c2c435, 0x45dd01a5, 0x94bf5627, 0x45d7bdc9, 0x94bbe85a,
+ 0x45d279c2, 0x94b87ad0,
+ 0x45cd358f, 0x94b50d87, 0x45c7f132, 0x94b1a081, 0x45c2acaa, 0x94ae33be,
+ 0x45bd67f6, 0x94aac73c,
+ 0x45b82318, 0x94a75afd, 0x45b2de0e, 0x94a3eeff, 0x45ad98da, 0x94a08344,
+ 0x45a8537a, 0x949d17cc,
+ 0x45a30df0, 0x9499ac95, 0x459dc83b, 0x949641a1, 0x4598825a, 0x9492d6ef,
+ 0x45933c4f, 0x948f6c7f,
+ 0x458df619, 0x948c0252, 0x4588afb8, 0x94889867, 0x4583692c, 0x94852ebe,
+ 0x457e2275, 0x9481c557,
+ 0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,
+ 0x456905ed, 0x94742254,
+ 0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,
+ 0x4553e6b8, 0x94668376,
+ 0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,
+ 0x453ec4d7, 0x9458e8bf,
+ 0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,
+ 0x4529a04b, 0x944b522d,
+ 0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,
+ 0x45147913, 0x943dbfc3,
+ 0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,
+ 0x44ff4f32, 0x94303180,
+ 0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,
+ 0x44ea22a9, 0x9422a766,
+ 0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,
+ 0x44d4f376, 0x94152174,
+ 0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,
+ 0x44bfc19d, 0x94079fab,
+ 0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,
+ 0x44aa8d1d, 0x93fa220b,
+ 0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,
+ 0x449555f7, 0x93eca896,
+ 0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,
+ 0x44801c2d, 0x93df334c,
+ 0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,
+ 0x446adfbe, 0x93d1c22c,
+ 0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,
+ 0x4455a0ac, 0x93c45539,
+ 0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,
+ 0x44405ef8, 0x93b6ec71,
+ 0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,
+ 0x442b1aa2, 0x93a987d6,
+ 0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,
+ 0x4415d3ab, 0x939c2769,
+ 0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,
+ 0x44008a14, 0x938ecb29,
+ 0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,
+ 0x43eb3ddf, 0x93817318,
+ 0x43e5ea68, 0x937e1dbb, 0x43e096c8, 0x937ac8a1, 0x43db42fe, 0x937773ca,
+ 0x43d5ef0a, 0x93741f35,
+ 0x43d09aed, 0x9370cae4, 0x43cb46a5, 0x936d76d6, 0x43c5f234, 0x936a230a,
+ 0x43c09d99, 0x9366cf82,
+ 0x43bb48d4, 0x93637c3d, 0x43b5f3e5, 0x9360293a, 0x43b09ecc, 0x935cd67b,
+ 0x43ab498a, 0x935983ff,
+ 0x43a5f41e, 0x935631c5, 0x43a09e89, 0x9352dfcf, 0x439b48c9, 0x934f8e1c,
+ 0x4395f2e0, 0x934c3cab,
+ 0x43909ccd, 0x9348eb7e, 0x438b4691, 0x93459a94, 0x4385f02a, 0x934249ed,
+ 0x4380999b, 0x933ef989,
+ 0x437b42e1, 0x933ba968, 0x4375ebfe, 0x9338598a, 0x437094f1, 0x933509f0,
+ 0x436b3dbb, 0x9331ba98,
+ 0x4365e65b, 0x932e6b84, 0x43608ed2, 0x932b1cb2, 0x435b371f, 0x9327ce24,
+ 0x4355df42, 0x93247fd9,
+ 0x4350873c, 0x932131d1, 0x434b2f0c, 0x931de40c, 0x4345d6b3, 0x931a968b,
+ 0x43407e31, 0x9317494c,
+ 0x433b2585, 0x9313fc51, 0x4335ccaf, 0x9310af99, 0x433073b0, 0x930d6324,
+ 0x432b1a87, 0x930a16f3,
+ 0x4325c135, 0x9306cb04, 0x432067ba, 0x93037f59, 0x431b0e15, 0x930033f1,
+ 0x4315b447, 0x92fce8cc,
+ 0x43105a50, 0x92f99deb, 0x430b002f, 0x92f6534c, 0x4305a5e5, 0x92f308f1,
+ 0x43004b71, 0x92efbeda,
+ 0x42faf0d4, 0x92ec7505, 0x42f5960e, 0x92e92b74, 0x42f03b1e, 0x92e5e226,
+ 0x42eae005, 0x92e2991c,
+ 0x42e584c3, 0x92df5054, 0x42e02958, 0x92dc07d0, 0x42dacdc3, 0x92d8bf90,
+ 0x42d57205, 0x92d57792,
+ 0x42d0161e, 0x92d22fd9, 0x42caba0e, 0x92cee862, 0x42c55dd4, 0x92cba12f,
+ 0x42c00172, 0x92c85a3f,
+ 0x42baa4e6, 0x92c51392, 0x42b54831, 0x92c1cd29, 0x42afeb53, 0x92be8703,
+ 0x42aa8e4b, 0x92bb4121,
+ 0x42a5311b, 0x92b7fb82, 0x429fd3c1, 0x92b4b626, 0x429a763f, 0x92b1710e,
+ 0x42951893, 0x92ae2c3a,
+ 0x428fbabe, 0x92aae7a8, 0x428a5cc0, 0x92a7a35a, 0x4284fe99, 0x92a45f50,
+ 0x427fa049, 0x92a11b89,
+ 0x427a41d0, 0x929dd806, 0x4274e32e, 0x929a94c6, 0x426f8463, 0x929751c9,
+ 0x426a256f, 0x92940f10,
+ 0x4264c653, 0x9290cc9b, 0x425f670d, 0x928d8a69, 0x425a079e, 0x928a487a,
+ 0x4254a806, 0x928706cf,
+ 0x424f4845, 0x9283c568, 0x4249e85c, 0x92808444, 0x42448849, 0x927d4363,
+ 0x423f280e, 0x927a02c7,
+ 0x4239c7aa, 0x9276c26d, 0x4234671d, 0x92738258, 0x422f0667, 0x92704286,
+ 0x4229a588, 0x926d02f7,
+ 0x42244481, 0x9269c3ac, 0x421ee350, 0x926684a5, 0x421981f7, 0x926345e1,
+ 0x42142075, 0x92600761,
+ 0x420ebecb, 0x925cc924, 0x42095cf7, 0x92598b2b, 0x4203fafb, 0x92564d76,
+ 0x41fe98d6, 0x92531005,
+ 0x41f93689, 0x924fd2d7, 0x41f3d413, 0x924c95ec, 0x41ee7174, 0x92495946,
+ 0x41e90eac, 0x92461ce3,
+ 0x41e3abbc, 0x9242e0c4, 0x41de48a3, 0x923fa4e8, 0x41d8e561, 0x923c6950,
+ 0x41d381f7, 0x92392dfc,
+ 0x41ce1e65, 0x9235f2ec, 0x41c8baa9, 0x9232b81f, 0x41c356c5, 0x922f7d96,
+ 0x41bdf2b9, 0x922c4351,
+ 0x41b88e84, 0x9229094f, 0x41b32a26, 0x9225cf91, 0x41adc5a0, 0x92229617,
+ 0x41a860f1, 0x921f5ce1,
+ 0x41a2fc1a, 0x921c23ef, 0x419d971b, 0x9218eb40, 0x419831f3, 0x9215b2d5,
+ 0x4192cca2, 0x92127aae,
+ 0x418d6729, 0x920f42cb, 0x41880188, 0x920c0b2c, 0x41829bbe, 0x9208d3d0,
+ 0x417d35cb, 0x92059cb8,
+ 0x4177cfb1, 0x920265e4, 0x4172696e, 0x91ff2f54, 0x416d0302, 0x91fbf908,
+ 0x41679c6f, 0x91f8c300,
+ 0x416235b2, 0x91f58d3b, 0x415ccece, 0x91f257bb, 0x415767c1, 0x91ef227e,
+ 0x4152008c, 0x91ebed85,
+ 0x414c992f, 0x91e8b8d0, 0x414731a9, 0x91e5845f, 0x4141c9fb, 0x91e25032,
+ 0x413c6225, 0x91df1c49,
+ 0x4136fa27, 0x91dbe8a4, 0x41319200, 0x91d8b542, 0x412c29b1, 0x91d58225,
+ 0x4126c13a, 0x91d24f4c,
+ 0x4121589b, 0x91cf1cb6, 0x411befd3, 0x91cbea65, 0x411686e4, 0x91c8b857,
+ 0x41111dcc, 0x91c5868e,
+ 0x410bb48c, 0x91c25508, 0x41064b24, 0x91bf23c7, 0x4100e194, 0x91bbf2c9,
+ 0x40fb77dc, 0x91b8c210,
+ 0x40f60dfb, 0x91b5919a, 0x40f0a3f3, 0x91b26169, 0x40eb39c3, 0x91af317c,
+ 0x40e5cf6a, 0x91ac01d2,
+ 0x40e064ea, 0x91a8d26d, 0x40dafa41, 0x91a5a34c, 0x40d58f71, 0x91a2746f,
+ 0x40d02478, 0x919f45d6,
+ 0x40cab958, 0x919c1781, 0x40c54e0f, 0x9198e970, 0x40bfe29f, 0x9195bba3,
+ 0x40ba7706, 0x91928e1a,
+ 0x40b50b46, 0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,
+ 0x40a4c716, 0x9185daa1,
+ 0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,
+ 0x408f14a7, 0x91792b6a,
+ 0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,
+ 0x40795fbc, 0x916c8076,
+ 0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,
+ 0x4063a854, 0x915fd9c5,
+ 0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,
+ 0x404dee70, 0x91533758,
+ 0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,
+ 0x40383212, 0x9146992f,
+ 0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,
+ 0x4022733a, 0x9139ff4b,
+ 0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,
+ 0x400cb1e9, 0x912d69ad,
+ 0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,
+ 0x3ff6ee1f, 0x9120d854,
+ 0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,
+ 0x3fe127df, 0x91144b41,
+ 0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,
+ 0x3fcb5f28, 0x9107c276,
+ 0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,
+ 0x3fb593fb, 0x90fb3df1,
+ 0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,
+ 0x3f9fc65a, 0x90eebdb4,
+ 0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,
+ 0x3f89f645, 0x90e241bf,
+ 0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,
+ 0x3f7423bc, 0x90d5ca13,
+ 0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,
+ 0x3f5e4ec2, 0x90c956b1,
+ 0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,
+ 0x3f487755, 0x90bce797,
+ 0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,
+ 0x3f329d79, 0x90b07cc8,
+ 0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,
+ 0x3f1cc12c, 0x90a41644,
+ 0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,
+ 0x3f06e271, 0x9097b40a,
+ 0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,
+ 0x3ef10148, 0x908b561c,
+ 0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,
+ 0x3edb1db1, 0x907efc7a,
+ 0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,
+ 0x3ec537ae, 0x9072a725,
+ 0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,
+ 0x3eaf4f40, 0x9066561d,
+ 0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,
+ 0x3e996467, 0x905a0962,
+ 0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,
+ 0x3e837724, 0x904dc0f5,
+ 0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,
+ 0x3e6d8778, 0x90417cd6,
+ 0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,
+ 0x3e579564, 0x90353d06,
+ 0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,
+ 0x3e41a0e8, 0x90290186,
+ 0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,
+ 0x3e2baa07, 0x901cca55,
+ 0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,
+ 0x3e15b0bf, 0x90109775,
+ 0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,
+ 0x3dffb513, 0x900468e5,
+ 0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,
+ 0x3de9b703, 0x8ff83ea7,
+ 0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,
+ 0x3dd3b690, 0x8fec18ba,
+ 0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,
+ 0x3dbdb3ba, 0x8fdff720,
+ 0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,
+ 0x3da7ae84, 0x8fd3d9d8,
+ 0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,
+ 0x3d91a6ed, 0x8fc7c0e3,
+ 0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,
+ 0x3d7b9cf6, 0x8fbbac42,
+ 0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,
+ 0x3d6590a0, 0x8faf9bf5,
+ 0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,
+ 0x3d4f81ec, 0x8fa38ffc,
+ 0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,
+ 0x3d3970dc, 0x8f978859,
+ 0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,
+ 0x3d235d6f, 0x8f8b850a,
+ 0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,
+ 0x3d0d47a6, 0x8f7f8612,
+ 0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,
+ 0x3cf72f83, 0x8f738b70,
+ 0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,
+ 0x3ce11507, 0x8f679525,
+ 0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,
+ 0x3ccaf831, 0x8f5ba331,
+ 0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,
+ 0x3cb4d904, 0x8f4fb595,
+ 0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,
+ 0x3c9eb77f, 0x8f43cc50,
+ 0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,
+ 0x3c8893a4, 0x8f37e765,
+ 0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,
+ 0x3c726d73, 0x8f2c06d3,
+ 0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,
+ 0x3c5c44ee, 0x8f202a9a,
+ 0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,
+ 0x3c461a16, 0x8f1452bb,
+ 0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,
+ 0x3c2fecea, 0x8f087f37,
+ 0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,
+ 0x3c19bd6c, 0x8efcb00e,
+ 0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,
+ 0x3c038b9e, 0x8ef0e540,
+ 0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,
+ 0x3bed577e, 0x8ee51ece,
+ 0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,
+ 0x3bd72110, 0x8ed95cb8,
+ 0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,
+ 0x3bc0e853, 0x8ecd9eff,
+ 0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,
+ 0x3baaad48, 0x8ec1e5a4,
+ 0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,
+ 0x3b946ff0, 0x8eb630a6,
+ 0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,
+ 0x3b7e304c, 0x8eaa8006,
+ 0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,
+ 0x3b67ee5d, 0x8e9ed3c4,
+ 0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,
+ 0x3b51aa24, 0x8e932be2,
+ 0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,
+ 0x3b3b63a1, 0x8e87885f,
+ 0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,
+ 0x3b251ad6, 0x8e7be93c,
+ 0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,
+ 0x3b0ecfc3, 0x8e704e79,
+ 0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,
+ 0x3af88269, 0x8e64b817,
+ 0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,
+ 0x3ae232c9, 0x8e592617,
+ 0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,
+ 0x3acbe0e3, 0x8e4d9878,
+ 0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,
+ 0x3ab58cba, 0x8e420f3b,
+ 0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,
+ 0x3a9f364d, 0x8e368a61,
+ 0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,
+ 0x3a88dd9d, 0x8e2b09e9,
+ 0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,
+ 0x3a7282ac, 0x8e1f8dd6,
+ 0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,
+ 0x3a5c257a, 0x8e141626,
+ 0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,
+ 0x3a45c608, 0x8e08a2db,
+ 0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,
+ 0x3a2f6457, 0x8dfd33f4,
+ 0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,
+ 0x3a190068, 0x8df1c973,
+ 0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,
+ 0x3a029a3b, 0x8de66357,
+ 0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,
+ 0x39ec31d1, 0x8ddb01a1,
+ 0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,
+ 0x39d5c72c, 0x8dcfa452,
+ 0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,
+ 0x39bf5a4d, 0x8dc44b6a,
+ 0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,
+ 0x39a8eb33, 0x8db8f6ea,
+ 0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,
+ 0x399279e0, 0x8dada6d1,
+ 0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,
+ 0x397c0655, 0x8da25b21,
+ 0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,
+ 0x39659092, 0x8d9713d9,
+ 0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,
+ 0x394f1899, 0x8d8bd0fb,
+ 0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,
+ 0x39389e6b, 0x8d809286,
+ 0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,
+ 0x39222208, 0x8d75587b,
+ 0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,
+ 0x390ba371, 0x8d6a22db,
+ 0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,
+ 0x38f522a6, 0x8d5ef1a5,
+ 0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,
+ 0x38de9faa, 0x8d53c4db,
+ 0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,
+ 0x38c81a7c, 0x8d489c7d,
+ 0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,
+ 0x38b1931e, 0x8d3d788b,
+ 0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,
+ 0x389b0991, 0x8d325905,
+ 0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,
+ 0x38847dd5, 0x8d273ded,
+ 0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,
+ 0x386defeb, 0x8d1c2742,
+ 0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,
+ 0x38575fd4, 0x8d111505,
+ 0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,
+ 0x3840cd90, 0x8d060737,
+ 0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,
+ 0x382a3922, 0x8cfafdd7,
+ 0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,
+ 0x3813a28a, 0x8ceff8e6,
+ 0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,
+ 0x37fd09c8, 0x8ce4f865,
+ 0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,
+ 0x37e66edd, 0x8cd9fc54,
+ 0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,
+ 0x37cfd1cb, 0x8ccf04b3,
+ 0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,
+ 0x37b93292, 0x8cc41184,
+ 0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,
+ 0x37a29132, 0x8cb922c6,
+ 0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,
+ 0x378bedae, 0x8cae3879,
+ 0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,
+ 0x37754806, 0x8ca3529f,
+ 0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,
+ 0x375ea03a, 0x8c987137,
+ 0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,
+ 0x3747f64c, 0x8c8d9442,
+ 0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,
+ 0x37314a3c, 0x8c82bbc0,
+ 0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,
+ 0x371a9c0b, 0x8c77e7b3,
+ 0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,
+ 0x3703ebbb, 0x8c6d181a,
+ 0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,
+ 0x36ed394b, 0x8c624cf5,
+ 0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,
+ 0x36d684be, 0x8c578645,
+ 0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,
+ 0x36bfce13, 0x8c4cc40b,
+ 0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,
+ 0x36a9154c, 0x8c420647,
+ 0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,
+ 0x36925a69, 0x8c374cf9,
+ 0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,
+ 0x367b9d6c, 0x8c2c9822,
+ 0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,
+ 0x3664de55, 0x8c21e7c2,
+ 0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,
+ 0x364e1d25, 0x8c173bda,
+ 0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,
+ 0x363759de, 0x8c0c9469,
+ 0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,
+ 0x3620947f, 0x8c01f171,
+ 0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,
+ 0x3609cd0a, 0x8bf752f2,
+ 0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,
+ 0x35f3037f, 0x8becb8ec,
+ 0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 0x8be4c857,
+ 0x35dc37e0, 0x8be22360,
+ 0x35d684a6, 0x8bdf7eb0, 0x35d0d14a, 0x8bdcda47, 0x35cb1dcc, 0x8bda3626,
+ 0x35c56a2e, 0x8bd7924d,
+ 0x35bfb66e, 0x8bd4eebc, 0x35ba028e, 0x8bd24b72, 0x35b44e8c, 0x8bcfa870,
+ 0x35ae9a69, 0x8bcd05b5,
+ 0x35a8e625, 0x8bca6343, 0x35a331c0, 0x8bc7c117, 0x359d7d39, 0x8bc51f34,
+ 0x3597c892, 0x8bc27d98,
+ 0x359213c9, 0x8bbfdc44, 0x358c5ee0, 0x8bbd3b38, 0x3586a9d5, 0x8bba9a73,
+ 0x3580f4aa, 0x8bb7f9f6,
+ 0x357b3f5d, 0x8bb559c1, 0x357589f0, 0x8bb2b9d4, 0x356fd461, 0x8bb01a2e,
+ 0x356a1eb2, 0x8bad7ad0,
+ 0x356468e2, 0x8baadbba, 0x355eb2f0, 0x8ba83cec, 0x3558fcde, 0x8ba59e65,
+ 0x355346ab, 0x8ba30026,
+ 0x354d9057, 0x8ba0622f, 0x3547d9e2, 0x8b9dc480, 0x3542234c, 0x8b9b2718,
+ 0x353c6c95, 0x8b9889f8,
+ 0x3536b5be, 0x8b95ed21, 0x3530fec6, 0x8b935090, 0x352b47ad, 0x8b90b448,
+ 0x35259073, 0x8b8e1848,
+ 0x351fd918, 0x8b8b7c8f, 0x351a219c, 0x8b88e11e, 0x35146a00, 0x8b8645f5,
+ 0x350eb243, 0x8b83ab14,
+ 0x3508fa66, 0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,
+ 0x34f7d208, 0x8b79425e,
+ 0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,
+ 0x34e0efc2, 0x8b6ede26,
+ 0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,
+ 0x34ca0b73, 0x8b647e6d,
+ 0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,
+ 0x34b3251a, 0x8b5a2333,
+ 0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,
+ 0x349c3cb9, 0x8b4fcc77,
+ 0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,
+ 0x34855251, 0x8b457a3c,
+ 0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,
+ 0x346e65e3, 0x8b3b2c80,
+ 0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,
+ 0x3457776f, 0x8b30e345,
+ 0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,
+ 0x344086f6, 0x8b269e8b,
+ 0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,
+ 0x3429947a, 0x8b1c5e52,
+ 0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,
+ 0x34129ffb, 0x8b12229b,
+ 0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,
+ 0x33fba97a, 0x8b07eb66,
+ 0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,
+ 0x33e4b0f8, 0x8afdb8b3,
+ 0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,
+ 0x33cdb676, 0x8af38a83,
+ 0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,
+ 0x33b6b9f4, 0x8ae960d6,
+ 0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,
+ 0x339fbb74, 0x8adf3bad,
+ 0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,
+ 0x3388baf7, 0x8ad51b08,
+ 0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,
+ 0x3371b87d, 0x8acafee8,
+ 0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,
+ 0x335ab407, 0x8ac0e74c,
+ 0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,
+ 0x3343ad97, 0x8ab6d435,
+ 0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,
+ 0x332ca52c, 0x8aacc5a4,
+ 0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,
+ 0x33159ac8, 0x8aa2bb99,
+ 0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,
+ 0x32fe8e6d, 0x8a98b614,
+ 0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,
+ 0x32e7801a, 0x8a8eb516,
+ 0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,
+ 0x32d06fd0, 0x8a84b89e,
+ 0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,
+ 0x32b95d91, 0x8a7ac0af,
+ 0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,
+ 0x32a2495d, 0x8a70cd47,
+ 0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,
+ 0x328b3336, 0x8a66de68,
+ 0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,
+ 0x32741b1c, 0x8a5cf411,
+ 0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,
+ 0x325d0110, 0x8a530e43,
+ 0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,
+ 0x3245e512, 0x8a492cff,
+ 0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,
+ 0x322ec725, 0x8a3f5045,
+ 0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,
+ 0x3217a748, 0x8a357814,
+ 0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,
+ 0x3200857d, 0x8a2ba46e,
+ 0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,
+ 0x31e961c5, 0x8a21d554,
+ 0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,
+ 0x31d23c1f, 0x8a180ac4,
+ 0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,
+ 0x31bb148f, 0x8a0e44c0,
+ 0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,
+ 0x31a3eb13, 0x8a048348,
+ 0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,
+ 0x318cbfad, 0x89fac65d,
+ 0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,
+ 0x3175925e, 0x89f10dff,
+ 0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,
+ 0x315e6328, 0x89e75a2d,
+ 0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,
+ 0x31473209, 0x89ddaae9,
+ 0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,
+ 0x312fff05, 0x89d40033,
+ 0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,
+ 0x3118ca1b, 0x89ca5a0c,
+ 0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,
+ 0x3101934d, 0x89c0b873,
+ 0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,
+ 0x30ea5a9a, 0x89b71b69,
+ 0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,
+ 0x30d32006, 0x89ad82ef,
+ 0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,
+ 0x30bbe38f, 0x89a3ef04,
+ 0x30b61426, 0x89a18ac0, 0x30b0449f, 0x899f26c5, 0x30aa74fa, 0x899cc313,
+ 0x30a4a537, 0x899a5faa,
+ 0x309ed556, 0x8997fc8a, 0x30990557, 0x899599b3, 0x3093353a, 0x89933725,
+ 0x308d64ff, 0x8990d4e0,
+ 0x308794a6, 0x898e72e4, 0x3081c42f, 0x898c1131, 0x307bf39b, 0x8989afc8,
+ 0x307622e8, 0x89874ea7,
+ 0x30705217, 0x8984edcf, 0x306a8129, 0x89828d41, 0x3064b01d, 0x89802cfc,
+ 0x305edef3, 0x897dccff,
+ 0x30590dab, 0x897b6d4c, 0x30533c45, 0x89790de2, 0x304d6ac1, 0x8976aec1,
+ 0x30479920, 0x89744fe9,
+ 0x3041c761, 0x8971f15a, 0x303bf584, 0x896f9315, 0x30362389, 0x896d3518,
+ 0x30305171, 0x896ad765,
+ 0x302a7f3a, 0x896879fb, 0x3024ace6, 0x89661cda, 0x301eda75, 0x8963c002,
+ 0x301907e6, 0x89616373,
+ 0x30133539, 0x895f072e, 0x300d626e, 0x895cab31, 0x30078f86, 0x895a4f7e,
+ 0x3001bc80, 0x8957f414,
+ 0x2ffbe95d, 0x895598f3, 0x2ff6161c, 0x89533e1c, 0x2ff042bd, 0x8950e38e,
+ 0x2fea6f41, 0x894e8948,
+ 0x2fe49ba7, 0x894c2f4c, 0x2fdec7f0, 0x8949d59a, 0x2fd8f41b, 0x89477c30,
+ 0x2fd32028, 0x89452310,
+ 0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,
+ 0x2fbbcf38, 0x893bc16b,
+ 0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,
+ 0x2fa47c71, 0x8932645b,
+ 0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,
+ 0x2f8d27d3, 0x89290bdf,
+ 0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,
+ 0x2f75d160, 0x891fb7f8,
+ 0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,
+ 0x2f5e7919, 0x891668a6,
+ 0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,
+ 0x2f471efe, 0x890d1dea,
+ 0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,
+ 0x2f2fc310, 0x8903d7c4,
+ 0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,
+ 0x2f186551, 0x88fa9634,
+ 0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,
+ 0x2f0105c1, 0x88f1593b,
+ 0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,
+ 0x2ee9a461, 0x88e820d9,
+ 0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,
+ 0x2ed24132, 0x88deed0e,
+ 0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,
+ 0x2ebadc35, 0x88d5bddb,
+ 0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,
+ 0x2ea3756b, 0x88cc9340,
+ 0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,
+ 0x2e8c0cd4, 0x88c36d3e,
+ 0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,
+ 0x2e74a272, 0x88ba4bd4,
+ 0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,
+ 0x2e5d3646, 0x88b12f04,
+ 0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,
+ 0x2e45c850, 0x88a816cd,
+ 0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,
+ 0x2e2e5891, 0x889f0330,
+ 0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,
+ 0x2e16e70b, 0x8895f42d,
+ 0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,
+ 0x2dff73bd, 0x888ce9c5,
+ 0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,
+ 0x2de7feaa, 0x8883e3f8,
+ 0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,
+ 0x2dd087d1, 0x887ae2c6,
+ 0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,
+ 0x2db90f35, 0x8871e630,
+ 0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,
+ 0x2da194d5, 0x8868ee35,
+ 0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,
+ 0x2d8a18b3, 0x885ffad7,
+ 0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,
+ 0x2d729acf, 0x88570c16,
+ 0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,
+ 0x2d5b1b2b, 0x884e21f1,
+ 0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,
+ 0x2d4399c7, 0x88453c6a,
+ 0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,
+ 0x2d2c16a4, 0x883c5b81,
+ 0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,
+ 0x2d1491c4, 0x88337f35,
+ 0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,
+ 0x2cfd0b26, 0x882aa788,
+ 0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,
+ 0x2ce582cd, 0x8821d47a,
+ 0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,
+ 0x2ccdf8b8, 0x8819060a,
+ 0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,
+ 0x2cb66ce9, 0x88103c3b,
+ 0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,
+ 0x2c9edf61, 0x8807770a,
+ 0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,
+ 0x2c875021, 0x87feb67a,
+ 0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,
+ 0x2c6fbf29, 0x87f5fa8b,
+ 0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,
+ 0x2c582c7b, 0x87ed433c,
+ 0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,
+ 0x2c409816, 0x87e4908e,
+ 0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,
+ 0x2c2901fd, 0x87dbe281,
+ 0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,
+ 0x2c116a31, 0x87d33916,
+ 0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,
+ 0x2bf9d0b1, 0x87ca944e,
+ 0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,
+ 0x2be2357f, 0x87c1f427,
+ 0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,
+ 0x2bca989d, 0x87b958a4,
+ 0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,
+ 0x2bb2fa0a, 0x87b0c1c4,
+ 0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,
+ 0x2b9b59c7, 0x87a82f87,
+ 0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,
+ 0x2b83b7d7, 0x879fa1ed,
+ 0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,
+ 0x2b6c1438, 0x879718f8,
+ 0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,
+ 0x2b546eee, 0x878e94a7,
+ 0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,
+ 0x2b3cc7f7, 0x878614fb,
+ 0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,
+ 0x2b251f56, 0x877d99f4,
+ 0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,
+ 0x2b0d750b, 0x87752392,
+ 0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,
+ 0x2af5c917, 0x876cb1d6,
+ 0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,
+ 0x2ade1b7c, 0x876444c1,
+ 0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,
+ 0x2ac66c39, 0x875bdc51,
+ 0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,
+ 0x2aaebb50, 0x87537888,
+ 0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,
+ 0x2a9708c1, 0x874b1966,
+ 0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,
+ 0x2a7f548e, 0x8742beec,
+ 0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,
+ 0x2a679eb8, 0x873a6919,
+ 0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,
+ 0x2a4fe740, 0x873217ee,
+ 0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,
+ 0x2a382e25, 0x8729cb6b,
+ 0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,
+ 0x2a20736a, 0x87218391,
+ 0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,
+ 0x2a08b710, 0x87194060,
+ 0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,
+ 0x29f0f916, 0x871101d8,
+ 0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,
+ 0x29d9397f, 0x8708c7fa,
+ 0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,
+ 0x29c1784a, 0x870092c5,
+ 0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,
+ 0x29a9b579, 0x86f8623b,
+ 0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,
+ 0x2991f10e, 0x86f0365c,
+ 0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,
+ 0x297a2b07, 0x86e80f27,
+ 0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,
+ 0x29626368, 0x86dfec9d,
+ 0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,
+ 0x294a9a30, 0x86d7cebf,
+ 0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,
+ 0x2932cf60, 0x86cfb58c,
+ 0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,
+ 0x291b02fa, 0x86c7a106,
+ 0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,
+ 0x290334ff, 0x86bf912c,
+ 0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,
+ 0x28eb656e, 0x86b785ff,
+ 0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,
+ 0x28d3944a, 0x86af7f7e,
+ 0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,
+ 0x28bbc192, 0x86a77dab,
+ 0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,
+ 0x28a3ed49, 0x869f8086,
+ 0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,
+ 0x288c176e, 0x8697880f,
+ 0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,
+ 0x28744004, 0x868f9445,
+ 0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,
+ 0x285c670a, 0x8687a52b,
+ 0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,
+ 0x28448c81, 0x867fbabf,
+ 0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,
+ 0x282cb06c, 0x8677d503,
+ 0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,
+ 0x2814d2c9, 0x866ff3f6,
+ 0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,
+ 0x27fcf39c, 0x86681798,
+ 0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,
+ 0x27e512e3, 0x86603feb,
+ 0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,
+ 0x27cd30a1, 0x86586cee,
+ 0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,
+ 0x27b54cd6, 0x86509ea2,
+ 0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,
+ 0x279d6783, 0x8648d507,
+ 0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,
+ 0x278580a9, 0x8641101d,
+ 0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,
+ 0x276d9849, 0x86394fe5,
+ 0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,
+ 0x2755ae64, 0x8631945e,
+ 0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,
+ 0x273dc2fa, 0x8629dd8a,
+ 0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,
+ 0x2725d60e, 0x86222b68,
+ 0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,
+ 0x270de79f, 0x861a7df9,
+ 0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,
+ 0x26f5f7ae, 0x8612d53d,
+ 0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,
+ 0x26de063d, 0x860b3135,
+ 0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,
+ 0x26c6134d, 0x860391e0,
+ 0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,
+ 0x26ae1edd, 0x85fbf73f,
+ 0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,
+ 0x269628f0, 0x85f46152,
+ 0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,
+ 0x267e3186, 0x85ecd01a,
+ 0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,
+ 0x266638a1, 0x85e54397,
+ 0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,
+ 0x264e3e40, 0x85ddbbc9,
+ 0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,
+ 0x26364265, 0x85d638b0,
+ 0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,
+ 0x261e4511, 0x85ceba4d,
+ 0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,
+ 0x26064645, 0x85c740a0,
+ 0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,
+ 0x25ee4601, 0x85bfcba9,
+ 0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,
+ 0x25d64447, 0x85b85b68,
+ 0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,
+ 0x25be4118, 0x85b0efdf,
+ 0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,
+ 0x25a63c74, 0x85a9890d,
+ 0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,
+ 0x258e365d, 0x85a226f2,
+ 0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,
+ 0x25762ed3, 0x859ac98f,
+ 0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,
+ 0x255e25d7, 0x859370e4,
+ 0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,
+ 0x25461b6b, 0x858c1cf1,
+ 0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,
+ 0x252e0f8e, 0x8584cdb7,
+ 0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,
+ 0x25160243, 0x857d8335,
+ 0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,
+ 0x24fdf389, 0x85763d6d,
+ 0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,
+ 0x24e5e363, 0x856efc5e,
+ 0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,
+ 0x24cdd1d0, 0x8567c009,
+ 0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,
+ 0x24b5bed2, 0x8560886d,
+ 0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,
+ 0x249daa6a, 0x8559558c,
+ 0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,
+ 0x24859498, 0x85522766,
+ 0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,
+ 0x246d7d5e, 0x854afdfa,
+ 0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,
+ 0x245564bd, 0x8543d949,
+ 0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,
+ 0x243d4ab4, 0x853cb954,
+ 0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,
+ 0x24252f47, 0x85359e1a,
+ 0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,
+ 0x240d1274, 0x852e879d,
+ 0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,
+ 0x23f4f43e, 0x852775db,
+ 0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,
+ 0x23dcd4a4, 0x852068d6,
+ 0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,
+ 0x23c4b3a9, 0x8519608d,
+ 0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,
+ 0x23ac914d, 0x85125d02,
+ 0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,
+ 0x23946d90, 0x850b5e34,
+ 0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,
+ 0x237c4875, 0x85046423,
+ 0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,
+ 0x236421fb, 0x84fd6ed0,
+ 0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,
+ 0x234bfa24, 0x84f67e3b,
+ 0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,
+ 0x2333d0f1, 0x84ef9265,
+ 0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,
+ 0x231ba662, 0x84e8ab4d,
+ 0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,
+ 0x23037a78, 0x84e1c8f3,
+ 0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,
+ 0x22eb4d36, 0x84daeb5a,
+ 0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,
+ 0x22d31e9a, 0x84d4127f,
+ 0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,
+ 0x22baeea7, 0x84cd3e64,
+ 0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,
+ 0x22a2bd5d, 0x84c66f09,
+ 0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,
+ 0x228a8abd, 0x84bfa46e,
+ 0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,
+ 0x227256c8, 0x84b8de94,
+ 0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,
+ 0x225a217f, 0x84b21d7a,
+ 0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,
+ 0x2241eae3, 0x84ab6122,
+ 0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,
+ 0x2229b2f6, 0x84a4a98a,
+ 0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,
+ 0x221179b7, 0x849df6b4,
+ 0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,
+ 0x21f93f27, 0x849748a0,
+ 0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,
+ 0x21e10349, 0x84909f4e,
+ 0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,
+ 0x21c8c61c, 0x8489fabe,
+ 0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,
+ 0x21b087a1, 0x84835af0,
+ 0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,
+ 0x219847da, 0x847cbfe5,
+ 0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,
+ 0x218006c8, 0x8476299e,
+ 0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,
+ 0x2167c46b, 0x846f9819,
+ 0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,
+ 0x214f80c4, 0x84690b58,
+ 0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,
+ 0x21373bd4, 0x8462835b,
+ 0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,
+ 0x211ef59d, 0x845c0022,
+ 0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,
+ 0x2106ae1e, 0x845581ad,
+ 0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,
+ 0x20ee655a, 0x844f07fd,
+ 0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,
+ 0x20d61b51, 0x84489311,
+ 0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,
+ 0x20bdd003, 0x844222eb,
+ 0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,
+ 0x20a58373, 0x843bb78a,
+ 0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,
+ 0x208d35a0, 0x843550ee,
+ 0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,
+ 0x2074e68c, 0x842eef18,
+ 0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,
+ 0x205c9638, 0x84289209,
+ 0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,
+ 0x204444a4, 0x842239bf,
+ 0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,
+ 0x202bf1d2, 0x841be63c,
+ 0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,
+ 0x20139dc2, 0x84159780,
+ 0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,
+ 0x1ffb4876, 0x840f4d8a,
+ 0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,
+ 0x1fe2f1ee, 0x8409085c,
+ 0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,
+ 0x1fca9a2b, 0x8402c7f6,
+ 0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,
+ 0x1fb2412f, 0x83fc8c57,
+ 0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,
+ 0x1f99e6fa, 0x83f65580,
+ 0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,
+ 0x1f818b8d, 0x83f02371,
+ 0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,
+ 0x1f692ee9, 0x83e9f62b,
+ 0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,
+ 0x1f50d10e, 0x83e3cdad,
+ 0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,
+ 0x1f3871ff, 0x83dda9f9,
+ 0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,
+ 0x1f2011bc, 0x83d78b0d,
+ 0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,
+ 0x1f07b045, 0x83d170eb,
+ 0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,
+ 0x1eef4d9d, 0x83cb5b93,
+ 0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,
+ 0x1ed6e9c3, 0x83c54b04,
+ 0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,
+ 0x1ebe84b8, 0x83bf3f3f,
+ 0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,
+ 0x1ea61e7e, 0x83b93845,
+ 0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,
+ 0x1e8db716, 0x83b33616,
+ 0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,
+ 0x1e754e80, 0x83ad38b1,
+ 0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,
+ 0x1e5ce4be, 0x83a74017,
+ 0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,
+ 0x1e4479cf, 0x83a14c48,
+ 0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,
+ 0x1e2c0db6, 0x839b5d45,
+ 0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,
+ 0x1e13a074, 0x8395730e,
+ 0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,
+ 0x1dfb3208, 0x838f8da2,
+ 0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,
+ 0x1de2c275, 0x8389ad03,
+ 0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,
+ 0x1dca51ba, 0x8383d130,
+ 0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,
+ 0x1db1dfda, 0x837dfa2a,
+ 0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,
+ 0x1d996cd4, 0x837827f0,
+ 0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,
+ 0x1d80f8ab, 0x83725a84,
+ 0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,
+ 0x1d68835e, 0x836c91e5,
+ 0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,
+ 0x1d500cef, 0x8366ce14,
+ 0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,
+ 0x1d37955e, 0x83610f10,
+ 0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,
+ 0x1d1f1cae, 0x835b54da,
+ 0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,
+ 0x1d06a2dd, 0x83559f72,
+ 0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,
+ 0x1cee27ef, 0x834feed9,
+ 0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,
+ 0x1cd5abe3, 0x834a430e,
+ 0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,
+ 0x1cbd2eba, 0x83449c12,
+ 0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,
+ 0x1ca4b075, 0x833ef9e6,
+ 0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,
+ 0x1c8c3116, 0x83395c88,
+ 0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,
+ 0x1c73b09d, 0x8333c3fa,
+ 0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,
+ 0x1c5b2f0c, 0x832e303c,
+ 0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,
+ 0x1c42ac62, 0x8328a14d,
+ 0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,
+ 0x1c2a28a2, 0x8323172f,
+ 0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,
+ 0x1c11a3cb, 0x831d91e1,
+ 0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,
+ 0x1bf91de0, 0x83181164,
+ 0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,
+ 0x1be096e0, 0x831295b7,
+ 0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,
+ 0x1bc80ece, 0x830d1edc,
+ 0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,
+ 0x1baf85a9, 0x8307acd1,
+ 0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,
+ 0x1b96fb73, 0x83023f98,
+ 0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,
+ 0x1b7e702c, 0x82fcd731,
+ 0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,
+ 0x1b65e3d7, 0x82f7739c,
+ 0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,
+ 0x1b4d5672, 0x82f214d8,
+ 0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,
+ 0x1b34c801, 0x82ecbae7,
+ 0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,
+ 0x1b1c3883, 0x82e765c8,
+ 0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,
+ 0x1b03a7f9, 0x82e2157c,
+ 0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,
+ 0x1aeb1665, 0x82dcca02,
+ 0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,
+ 0x1ad283c7, 0x82d7835c,
+ 0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,
+ 0x1ab9f020, 0x82d24189,
+ 0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,
+ 0x1aa15b71, 0x82cd048a,
+ 0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,
+ 0x1a88c5bc, 0x82c7cc5e,
+ 0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,
+ 0x1a702f01, 0x82c29906,
+ 0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,
+ 0x1a579741, 0x82bd6a82,
+ 0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,
+ 0x1a3efe7c, 0x82b840d2,
+ 0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,
+ 0x1a2664b5, 0x82b31bf7,
+ 0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,
+ 0x1a0dc9ec, 0x82adfbf0,
+ 0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,
+ 0x19f52e22, 0x82a8e0bf,
+ 0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,
+ 0x19dc9157, 0x82a3ca62,
+ 0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,
+ 0x19c3f38d, 0x829eb8db,
+ 0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,
+ 0x19ab54c5, 0x8299ac29,
+ 0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,
+ 0x1992b4ff, 0x8294a44c,
+ 0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,
+ 0x197a143e, 0x828fa146,
+ 0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,
+ 0x19617280, 0x828aa316,
+ 0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,
+ 0x1948cfc8, 0x8285a9bb,
+ 0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,
+ 0x19302c17, 0x8280b538,
+ 0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,
+ 0x1917876d, 0x827bc58a,
+ 0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,
+ 0x18fee1cb, 0x8276dab4,
+ 0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,
+ 0x18e63b33, 0x8271f4b5,
+ 0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,
+ 0x18cd93a5, 0x826d138d,
+ 0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,
+ 0x18b4eb22, 0x8268373c,
+ 0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,
+ 0x189c41ab, 0x82635fc2,
+ 0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,
+ 0x18839742, 0x825e8d21,
+ 0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,
+ 0x186aebe6, 0x8259bf57,
+ 0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,
+ 0x18523f9a, 0x8254f666,
+ 0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,
+ 0x1839925d, 0x8250324d,
+ 0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,
+ 0x1820e431, 0x824b730c,
+ 0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,
+ 0x18083518, 0x8246b8a4,
+ 0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,
+ 0x17ef8511, 0x82420315,
+ 0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,
+ 0x17d6d41d, 0x823d525e,
+ 0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,
+ 0x17be223f, 0x8238a681,
+ 0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,
+ 0x17a56f76, 0x8233ff7e,
+ 0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,
+ 0x178cbbc4, 0x822f5d54,
+ 0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,
+ 0x17740729, 0x822ac004,
+ 0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,
+ 0x175b51a7, 0x8226278d,
+ 0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,
+ 0x17429b3e, 0x822193f1,
+ 0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,
+ 0x1729e3f0, 0x821d052f,
+ 0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,
+ 0x17112bbd, 0x82187b47,
+ 0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,
+ 0x16f872a7, 0x8213f63a,
+ 0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,
+ 0x16dfb8ae, 0x820f7608,
+ 0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,
+ 0x16c6fdd3, 0x820afab1,
+ 0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,
+ 0x16ae4217, 0x82068435,
+ 0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,
+ 0x1695857b, 0x82021294,
+ 0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,
+ 0x167cc801, 0x81fda5cf,
+ 0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,
+ 0x166409a8, 0x81f93de6,
+ 0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,
+ 0x164b4a73, 0x81f4dad8,
+ 0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,
+ 0x16328a61, 0x81f07ca6,
+ 0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,
+ 0x1619c975, 0x81ec2351,
+ 0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,
+ 0x160107ae, 0x81e7ced8,
+ 0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,
+ 0x15e8450e, 0x81e37f3b,
+ 0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,
+ 0x15cf8196, 0x81df347b,
+ 0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,
+ 0x15b6bd47, 0x81daee98,
+ 0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,
+ 0x159df821, 0x81d6ad92,
+ 0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,
+ 0x15853226, 0x81d27169,
+ 0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,
+ 0x156c6b57, 0x81ce3a1d,
+ 0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,
+ 0x1553a3b4, 0x81ca07af,
+ 0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,
+ 0x153adb3f, 0x81c5da1e,
+ 0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,
+ 0x152211f8, 0x81c1b16b,
+ 0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,
+ 0x150947e1, 0x81bd8d97,
+ 0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,
+ 0x14f07cf9, 0x81b96ea0,
+ 0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,
+ 0x14d7b144, 0x81b55488,
+ 0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,
+ 0x14bee4c0, 0x81b13f4e,
+ 0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,
+ 0x14a61770, 0x81ad2ef2,
+ 0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,
+ 0x148d4954, 0x81a92376,
+ 0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,
+ 0x14747a6d, 0x81a51cd8,
+ 0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,
+ 0x145baabd, 0x81a11b1a,
+ 0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,
+ 0x1442da43, 0x819d1e3a,
+ 0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,
+ 0x142a0902, 0x8199263a,
+ 0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,
+ 0x141136f9, 0x8195331a,
+ 0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,
+ 0x13f8642a, 0x819144d9,
+ 0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,
+ 0x13df9097, 0x818d5b78,
+ 0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,
+ 0x13c6bc3f, 0x818976f8,
+ 0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,
+ 0x13ade724, 0x81859757,
+ 0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,
+ 0x13951146, 0x8181bc96,
+ 0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,
+ 0x137c3aa8, 0x817de6b6,
+ 0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,
+ 0x13636349, 0x817a15b7,
+ 0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,
+ 0x134a8b2b, 0x81764998,
+ 0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,
+ 0x1331b24e, 0x8172825a,
+ 0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,
+ 0x1318d8b4, 0x816ebffe,
+ 0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,
+ 0x12fffe5d, 0x816b0282,
+ 0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,
+ 0x12e7234b, 0x816749e8,
+ 0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,
+ 0x12ce477f, 0x8163962f,
+ 0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,
+ 0x12b56af9, 0x815fe758,
+ 0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,
+ 0x129c8dba, 0x815c3d62,
+ 0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,
+ 0x1283afc3, 0x8158984e,
+ 0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,
+ 0x126ad116, 0x8154f81d,
+ 0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,
+ 0x1251f1b3, 0x81515ccd,
+ 0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,
+ 0x1239119b, 0x814dc660,
+ 0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,
+ 0x122030cf, 0x814a34d6,
+ 0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,
+ 0x12074f50, 0x8146a82e,
+ 0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,
+ 0x11ee6d20, 0x81432068,
+ 0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,
+ 0x11d58a3e, 0x813f9d86,
+ 0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,
+ 0x11bca6ad, 0x813c1f86,
+ 0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,
+ 0x11a3c26c, 0x8138a66a,
+ 0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,
+ 0x118add7d, 0x81353230,
+ 0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,
+ 0x1171f7e2, 0x8131c2db,
+ 0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,
+ 0x1159119a, 0x812e5868,
+ 0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,
+ 0x11402aa6, 0x812af2da,
+ 0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,
+ 0x11274309, 0x8127922f,
+ 0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,
+ 0x110e5ac2, 0x81243668,
+ 0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,
+ 0x10f571d3, 0x8120df85,
+ 0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,
+ 0x10dc883c, 0x811d8d86,
+ 0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,
+ 0x10c39dff, 0x811a406c,
+ 0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,
+ 0x10aab31d, 0x8116f836,
+ 0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,
+ 0x1091c796, 0x8113b4e5,
+ 0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,
+ 0x1078db6c, 0x81107678,
+ 0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,
+ 0x105fee9f, 0x810d3cf0,
+ 0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,
+ 0x10470130, 0x810a084d,
+ 0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,
+ 0x102e1321, 0x8106d88f,
+ 0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,
+ 0x10152472, 0x8103adb6,
+ 0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,
+ 0xffc3524, 0x810087c3,
+ 0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,
+ 0xfe34539, 0x80fd66b5,
+ 0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,
+ 0xfca54b1, 0x80fa4a8c,
+ 0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,
+ 0xfb1638d, 0x80f73349,
+ 0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,
+ 0xf9871ce, 0x80f420ec,
+ 0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,
+ 0xf7f7f75, 0x80f11375,
+ 0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,
+ 0xf668c83, 0x80ee0ae4,
+ 0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,
+ 0xf4d98f9, 0x80eb0739,
+ 0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,
+ 0xf34a4d8, 0x80e80874,
+ 0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,
+ 0xf1bb021, 0x80e50e96,
+ 0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,
+ 0xf02bad5, 0x80e2199e,
+ 0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,
+ 0xee9c4f5, 0x80df298c,
+ 0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,
+ 0xed0ce82, 0x80dc3e62,
+ 0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,
+ 0xeb7d77c, 0x80d9581e,
+ 0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,
+ 0xe9edfe5, 0x80d676c1,
+ 0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,
+ 0xe85e7be, 0x80d39a4b,
+ 0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,
+ 0xe6cef07, 0x80d0c2bc,
+ 0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,
+ 0xe53f5c2, 0x80cdf015,
+ 0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,
+ 0xe3afbf0, 0x80cb2255,
+ 0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,
+ 0xe220191, 0x80c8597c,
+ 0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,
+ 0xe0906a7, 0x80c5958b,
+ 0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,
+ 0xdf00b32, 0x80c2d682,
+ 0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,
+ 0xdd70f34, 0x80c01c60,
+ 0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,
+ 0xdbe12ad, 0x80bd6727,
+ 0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,
+ 0xda5159f, 0x80bab6d5,
+ 0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,
+ 0xd8c1809, 0x80b80b6c,
+ 0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,
+ 0xd7319ee, 0x80b564ea,
+ 0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,
+ 0xd5a1b4f, 0x80b2c351,
+ 0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,
+ 0xd411c2b, 0x80b026a1,
+ 0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,
+ 0xd281c85, 0x80ad8ed9,
+ 0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,
+ 0xd0f1c5d, 0x80aafbf9,
+ 0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,
+ 0xcf61bb4, 0x80a86e03,
+ 0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,
+ 0xcdd1a8b, 0x80a5e4f5,
+ 0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,
+ 0xcc418e3, 0x80a360d0,
+ 0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,
+ 0xcab16bd, 0x80a0e194,
+ 0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,
+ 0xc92141a, 0x809e6741,
+ 0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,
+ 0xc7910fb, 0x809bf1d7,
+ 0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,
+ 0xc600d61, 0x80998157,
+ 0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,
+ 0xc47094d, 0x809715c0,
+ 0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,
+ 0xc2e04c0, 0x8094af13,
+ 0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,
+ 0xc14ffba, 0x80924d4f,
+ 0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,
+ 0xbfbfa3d, 0x808ff074,
+ 0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,
+ 0xbe2f44a, 0x808d9884,
+ 0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,
+ 0xbc9ede2, 0x808b457d,
+ 0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,
+ 0xbb0e705, 0x8088f761,
+ 0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,
+ 0xb97dfb5, 0x8086ae2e,
+ 0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,
+ 0xb7ed7f2, 0x808469e5,
+ 0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,
+ 0xb65cfbe, 0x80822a87,
+ 0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,
+ 0xb4cc719, 0x807ff013,
+ 0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,
+ 0xb33be05, 0x807dba89,
+ 0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,
+ 0xb1ab483, 0x807b89ea,
+ 0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,
+ 0xb01aa92, 0x80795e36,
+ 0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,
+ 0xae8a036, 0x8077376c,
+ 0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,
+ 0xacf956d, 0x8075158c,
+ 0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,
+ 0xab68a3a, 0x8072f898,
+ 0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,
+ 0xa9d7e9d, 0x8070e08e,
+ 0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,
+ 0xa847297, 0x806ecd6f,
+ 0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,
+ 0xa6b662a, 0x806cbf3c,
+ 0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,
+ 0xa525955, 0x806ab5f3,
+ 0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,
+ 0xa394c1b, 0x8068b196,
+ 0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,
+ 0xa203e7c, 0x8066b224,
+ 0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,
+ 0xa073079, 0x8064b79d,
+ 0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,
+ 0x9ee2213, 0x8062c202,
+ 0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,
+ 0x9d5134b, 0x8060d152,
+ 0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,
+ 0x9bc0421, 0x805ee58e,
+ 0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,
+ 0x9a2f498, 0x805cfeb5,
+ 0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,
+ 0x989e4b0, 0x805b1cc8,
+ 0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,
+ 0x970d46a, 0x80593fc7,
+ 0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,
+ 0x957c3c6, 0x805767b2,
+ 0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,
+ 0x93eb2c6, 0x80559489,
+ 0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,
+ 0x925a16b, 0x8053c64c,
+ 0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,
+ 0x90c8fb6, 0x8051fcfb,
+ 0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,
+ 0x8f37da7, 0x80503896,
+ 0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,
+ 0x8da6b40, 0x804e791d,
+ 0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,
+ 0x8c15882, 0x804cbe90,
+ 0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,
+ 0x8a8456d, 0x804b08f0,
+ 0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,
+ 0x88f3203, 0x8049583d,
+ 0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,
+ 0x8761e44, 0x8047ac75,
+ 0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,
+ 0x85d0a32, 0x8046059b,
+ 0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,
+ 0x843f5cd, 0x804463ad,
+ 0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,
+ 0x82ae117, 0x8042c6ab,
+ 0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,
+ 0x811cc10, 0x80412e96,
+ 0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,
+ 0x7f8b6b9, 0x803f9b6f,
+ 0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,
+ 0x7dfa114, 0x803e0d34,
+ 0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,
+ 0x7c68b21, 0x803c83e5,
+ 0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,
+ 0x7ad74e1, 0x803aff84,
+ 0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,
+ 0x7945e56, 0x80398010,
+ 0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,
+ 0x77b4780, 0x80380589,
+ 0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,
+ 0x762305f, 0x80368fef,
+ 0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,
+ 0x74918f6, 0x80351f43,
+ 0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,
+ 0x7300145, 0x8033b383,
+ 0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,
+ 0x716e94e, 0x80324cb1,
+ 0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,
+ 0x6fdd110, 0x8030eacd,
+ 0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,
+ 0x6e4b88d, 0x802f8dd5,
+ 0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,
+ 0x6cb9fc6, 0x802e35cb,
+ 0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,
+ 0x6b286bc, 0x802ce2af,
+ 0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,
+ 0x6996d70, 0x802b9480,
+ 0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,
+ 0x68053e3, 0x802a4b3f,
+ 0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,
+ 0x6673a16, 0x802906ec,
+ 0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,
+ 0x64e2009, 0x8027c786,
+ 0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,
+ 0x63505be, 0x80268d0e,
+ 0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,
+ 0x61beb36, 0x80255784,
+ 0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,
+ 0x602d072, 0x802426e8,
+ 0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,
+ 0x5e9b572, 0x8022fb3a,
+ 0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,
+ 0x5d09a38, 0x8021d47a,
+ 0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,
+ 0x5b77ec5, 0x8020b2a7,
+ 0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,
+ 0x59e6319, 0x801f95c3,
+ 0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,
+ 0x5854736, 0x801e7dcd,
+ 0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,
+ 0x56c2b1c, 0x801d6ac5,
+ 0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,
+ 0x5530ecd, 0x801c5cab,
+ 0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,
+ 0x539f249, 0x801b537f,
+ 0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,
+ 0x520d592, 0x801a4f42,
+ 0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,
+ 0x507b8a8, 0x80194ff3,
+ 0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,
+ 0x4ee9b8c, 0x80185592,
+ 0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,
+ 0x4d57e40, 0x80176020,
+ 0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,
+ 0x4bc60c4, 0x80166f9c,
+ 0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,
+ 0x4a34319, 0x80158406,
+ 0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,
+ 0x48a2540, 0x80149d5f,
+ 0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,
+ 0x471073b, 0x8013bba7,
+ 0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,
+ 0x457e90a, 0x8012dedd,
+ 0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,
+ 0x43ecaae, 0x80120701,
+ 0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,
+ 0x425ac28, 0x80113414,
+ 0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,
+ 0x40c8d79, 0x80106616,
+ 0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,
+ 0x3f36ea2, 0x800f9d07,
+ 0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,
+ 0x3da4fa4, 0x800ed8e6,
+ 0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,
+ 0x3c13080, 0x800e19b4,
+ 0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,
+ 0x3a81137, 0x800d5f71,
+ 0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,
+ 0x38ef1ca, 0x800caa1c,
+ 0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,
+ 0x375d23a, 0x800bf9b7,
+ 0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,
+ 0x35cb288, 0x800b4e40,
+ 0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,
+ 0x34392b4, 0x800aa7b8,
+ 0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,
+ 0x32a72c1, 0x800a061f,
+ 0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,
+ 0x31152ae, 0x80096975,
+ 0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,
+ 0x2f8327d, 0x8008d1ba,
+ 0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,
+ 0x2df122e, 0x80083eed,
+ 0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,
+ 0x2c5f1c3, 0x8007b110,
+ 0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,
+ 0x2acd13d, 0x80072822,
+ 0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,
+ 0x293b09c, 0x8006a423,
+ 0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,
+ 0x27a8fe2, 0x80062513,
+ 0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,
+ 0x2616f10, 0x8005aaf2,
+ 0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,
+ 0x2484e26, 0x800535c0,
+ 0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,
+ 0x22f2d25, 0x8004c57d,
+ 0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,
+ 0x2160c0f, 0x80045a29,
+ 0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,
+ 0x1fceae4, 0x8003f3c5,
+ 0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,
+ 0x1e3c9a6, 0x8003924f,
+ 0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,
+ 0x1caa855, 0x800335c9,
+ 0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,
+ 0x1b186f3, 0x8002de32,
+ 0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,
+ 0x198657f, 0x80028b8a,
+ 0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,
+ 0x17f43fc, 0x80023dd2,
+ 0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,
+ 0x166226a, 0x8001f508,
+ 0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,
+ 0x14d00ca, 0x8001b12e,
+ 0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,
+ 0x133df1e, 0x80017243,
+ 0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,
+ 0x11abd66, 0x80013847,
+ 0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,
+ 0x1019ba2, 0x8001033b,
+ 0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,
+ 0x8000d31e,
+ 0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,
+ 0x8000a7f0,
+ 0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,
+ 0x800081b1,
+ 0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,
+ 0x80006062,
+ 0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,
+ 0x80004402,
+ 0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,
+ 0x80002c91,
+ 0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,
+ 0x80001a10,
+ 0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,
+ 0x80000c7e,
+ 0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,
+ 0x800003db,
+ 0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,
+ 0x80000027,
+
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+* \par
+* C command to generate the table
+*
+* for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* }
+* \par
+* where N is the number of factors to generate and c is pi/(2*N)
+* \par
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+ 0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+ 0x7f97cebd, 0x7f754e80,
+ 0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+ 0x7dfa98a8, 0x7db0fdf8,
+ 0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+ 0x7b26cb4f, 0x7ab6cba4,
+ 0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+ 0x77235f2d, 0x768e0ea6,
+ 0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+ 0x71fa3949, 0x71410805,
+ 0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+ 0x6bb812d1, 0x6adcc964,
+ 0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+ 0x646c59bf, 0x637114cc,
+ 0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+ 0x5c290acc, 0x5b1035cf,
+ 0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+ 0x53028518, 0x51ced46e,
+ 0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+ 0x490f57ee, 0x47c3c22f,
+ 0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+ 0x3e680b2c, 0x3d07c1d6,
+ 0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+ 0x3326e2c3, 0x31b54a5e,
+ 0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+ 0x27679df4, 0x25e845b6,
+ 0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+ 0x1b4732ef, 0x19bdcbf3,
+ 0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+ 0xee38766, 0xd53db92,
+ 0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+ 0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+ 0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+ 0x7ff97c18, 0x7ff75370,
+ 0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+ 0x7fdf9508, 0x7fdaf519,
+ 0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+ 0x7fb1f5fc, 0x7faadf7c,
+ 0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+ 0x7f70a5fe, 0x7f671a05,
+ 0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+ 0x7f1baf1e, 0x7f0faf25,
+ 0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+ 0x7eb31e78, 0x7ea4ac58,
+ 0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+ 0x7e37042a, 0x7e26221f,
+ 0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+ 0x7da77359, 0x7d9423fc,
+ 0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+ 0x7d048228, 0x7ceec873,
+ 0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+ 0x7c4e49b7, 0x7c362904,
+ 0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+ 0x7b84e61f, 0x7b6a6227,
+ 0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+ 0x7aa8766f, 0x7a8b9348,
+ 0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+ 0x79b91ca4, 0x7999dec4,
+ 0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+ 0x78b6fda8, 0x789569df,
+ 0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+ 0x77a24148, 0x777e5cc3,
+ 0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+ 0x767b1231, 0x7654e279,
+ 0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+ 0x75419de7, 0x751928e0,
+ 0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+ 0x73f614c0, 0x73cb60a8,
+ 0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+ 0x7298a9dd, 0x726bbd48,
+ 0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+ 0x7129931f, 0x70fa74fc,
+ 0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+ 0x6fa90921, 0x6f77c0b3,
+ 0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+ 0x6e174730, 0x6de3dc11,
+ 0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+ 0x6c748b3f, 0x6c3f055d,
+ 0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+ 0x6ac115e2, 0x6a897d7d,
+ 0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+ 0x68fd2a3d, 0x68c387e9,
+ 0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+ 0x67290e02, 0x66ed6aa1,
+ 0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+ 0x6545095f, 0x65076e25,
+ 0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+ 0x635166f9, 0x6311dd64,
+ 0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+ 0x614e73da, 0x610d05b7,
+ 0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+ 0x5f3c7f6b, 0x5ef936d1,
+ 0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+ 0x5d1bdb65, 0x5cd6c2b5,
+ 0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+ 0x5aecdbc5, 0x5aa5fda5,
+ 0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+ 0x58afd6bd, 0x58673e1b,
+ 0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+ 0x566524aa, 0x561adcb9,
+ 0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+ 0x540d2005, 0x53c13439,
+ 0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+ 0x51a82555, 0x515aa162,
+ 0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+ 0x4f369320, 0x4ee782fb,
+ 0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+ 0x4cb8c9dd, 0x4c6839b7,
+ 0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+ 0x4a2f2be6, 0x49dd282a,
+ 0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+ 0x479a1d67, 0x4746b2bc,
+ 0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+ 0x44fa0450, 0x44a53f93,
+ 0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+ 0x424f4845, 0x41f93689,
+ 0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+ 0x3f9a5290, 0x3f430119,
+ 0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+ 0x3cdb8e09, 0x3c830a50,
+ 0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+ 0x3a136712, 0x39b9bebc,
+ 0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+ 0x37424b7b, 0x36e78c5b,
+ 0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+ 0x3468aa76, 0x340ce28b,
+ 0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+ 0x3186f487, 0x312a31f8,
+ 0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+ 0x2e9d9b70, 0x2e3fec8b,
+ 0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+ 0x2bad1221, 0x2b4e8558,
+ 0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+ 0x28b5cca5, 0x2856708d,
+ 0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+ 0x25b84012, 0x2558235f,
+ 0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+ 0x22b4e274, 0x225413f8,
+ 0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+ 0x1fac2abf, 0x1f4ab968,
+ 0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+ 0x1c9e90b8, 0x1c3c8b8c,
+ 0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+ 0x198c8ce7, 0x192a0304,
+ 0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+ 0x1676987f, 0x16139918,
+ 0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+ 0x135d2d53, 0x12f9c7aa,
+ 0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+ 0x1040c5bb, 0xfdd0926,
+ 0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+ 0xcbdd865,
+ 0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+ 0x99cb0a7,
+ 0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+ 0x67a0d76,
+ 0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+ 0x3566a96,
+ 0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+ 0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+ 0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+ 0x7fff97c1, 0x7fff7536,
+ 0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+ 0x7ffdf93c, 0x7ffdaf37,
+ 0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+ 0x7ffb1ee9, 0x7ffaad6a,
+ 0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+ 0x7ff708ce, 0x7ff66fd7,
+ 0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+ 0x7ff1b6f6, 0x7ff0f688,
+ 0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+ 0x7feb296d, 0x7fea418b,
+ 0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+ 0x7fe36045, 0x7fe250ef,
+ 0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+ 0x7fda5b8f, 0x7fd924ca,
+ 0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+ 0x7fd01b63, 0x7fcebd31,
+ 0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+ 0x7fc49fda, 0x7fc31a3d,
+ 0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+ 0x7fb7e90f, 0x7fb63c0d,
+ 0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+ 0x7fa9f723, 0x7fa822bf,
+ 0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+ 0x7f9aca37, 0x7f98ce76,
+ 0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+ 0x7f8a6272, 0x7f883f58,
+ 0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+ 0x7f78bffb, 0x7f76758e,
+ 0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+ 0x7f65e2ff, 0x7f637144,
+ 0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+ 0x7f51cbab, 0x7f4f32a9,
+ 0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+ 0x7f3c7a31, 0x7f39b9ee,
+ 0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+ 0x7f25eec7, 0x7f230749,
+ 0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+ 0x7f0e29a3, 0x7f0b1af2,
+ 0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+ 0x7ef52b00, 0x7ef1f524,
+ 0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+ 0x7edaf31c, 0x7ed7961c,
+ 0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+ 0x7ebf8237, 0x7ebbfe1c,
+ 0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+ 0x7ea2d896, 0x7e9f2d68,
+ 0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+ 0x7e84f67e, 0x7e812447,
+ 0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+ 0x7e65dc3b, 0x7e61e303,
+ 0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+ 0x7e458a17, 0x7e4169e9,
+ 0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+ 0x7e240064, 0x7e1fb94a,
+ 0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+ 0x7e013f74, 0x7dfcd178,
+ 0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+ 0x7ddd479d, 0x7dd8b2ca,
+ 0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+ 0x7db81936, 0x7db35d98,
+ 0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+ 0x7d91b49e, 0x7d8cd240,
+ 0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+ 0x7d6a1a31, 0x7d65111f,
+ 0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+ 0x7d414a51, 0x7d3c1a98,
+ 0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+ 0x7d174564, 0x7d11ef11,
+ 0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+ 0x7cec0bd1, 0x7ce68ef0,
+ 0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+ 0x7cbf9e03, 0x7cb9faa2,
+ 0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+ 0x7c91fc66, 0x7c8c3294,
+ 0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+ 0x7c63276d, 0x7c5d3737,
+ 0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+ 0x7c331f8a, 0x7c2d08ff,
+ 0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+ 0x7c01e534, 0x7bfba863,
+ 0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+ 0x7bcf78e5, 0x7bc915dd,
+ 0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+ 0x7b9bdb18, 0x7b9551ea,
+ 0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+ 0x7b670c4d, 0x7b605d09,
+ 0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+ 0x7b310d07, 0x7b2a37bc,
+ 0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+ 0x7af9ddcb, 0x7af2e28b,
+ 0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+ 0x7ac17f20, 0x7aba5dfc,
+ 0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+ 0x7a87f192, 0x7a80aa9c,
+ 0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+ 0x7a4d35b0, 0x7a45c8f9,
+ 0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+ 0x7a114c09, 0x7a09b9a4,
+ 0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+ 0x79d43532, 0x79cc7d31,
+ 0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+ 0x7995f1c1, 0x798e1438,
+ 0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+ 0x79568250, 0x794e7f52,
+ 0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+ 0x7915e77c, 0x790dbf1d,
+ 0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+ 0x78d421e4, 0x78cbd437,
+ 0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+ 0x7891322a, 0x7888bf45,
+ 0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+ 0x784d18f4, 0x784480ea,
+ 0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+ 0x7807d6e9, 0x77ff19d1,
+ 0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+ 0x77c16cb4, 0x77b88aa3,
+ 0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+ 0x7779db03, 0x7770d40f,
+ 0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+ 0x77312287, 0x7727f6c6,
+ 0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+ 0x76e743f4, 0x76ddf37c,
+ 0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+ 0x769c3ffe, 0x7692cae8,
+ 0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+ 0x76501760, 0x76467dc2,
+ 0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+ 0x7602cad5, 0x75f90cc7,
+ 0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+ 0x75b45b1d, 0x75aa78b6,
+ 0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+ 0x7564c8f8, 0x755ac251,
+ 0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+ 0x7514152b, 0x7509ea5d,
+ 0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+ 0x74c2407d, 0x74b7f1a1,
+ 0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+ 0x746f4bb8, 0x7464d8e8,
+ 0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+ 0x741b37a9, 0x7410a0fe,
+ 0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+ 0x73c6051f, 0x73bb4ab3,
+ 0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+ 0x736fb4ec, 0x7364d6da,
+ 0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+ 0x731847e5, 0x730d4648,
+ 0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+ 0x72bfbee3, 0x72b499d6,
+ 0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+ 0x72661abf, 0x725ad25d,
+ 0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+ 0x720b5c57, 0x71fff0bc,
+ 0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+ 0x71af848a, 0x71a3f5d2,
+ 0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+ 0x7152943b, 0x7146e284,
+ 0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+ 0x70f48c50, 0x70e8b7b5,
+ 0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+ 0x70956db1, 0x70897650,
+ 0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+ 0x70353947, 0x70291f3e,
+ 0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+ 0x6fd3f001, 0x6fc7b36d,
+ 0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+ 0x6f7192cf, 0x6f6533ce,
+ 0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+ 0x6f0e22a3, 0x6f01a155,
+ 0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+ 0x6ea9a073, 0x6e9cfcf5,
+ 0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+ 0x6e440d37, 0x6e3747a9,
+ 0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+ 0x6ddd69e9, 0x6dd0826a,
+ 0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+ 0x6d75b786, 0x6d68ae37,
+ 0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+ 0x6d0cf70f, 0x6cffcc0f,
+ 0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+ 0x6ca32985, 0x6c95dcf6,
+ 0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+ 0x6c384fef, 0x6c2ae1f0,
+ 0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+ 0x6bcc6b53, 0x6bbedc06,
+ 0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+ 0x6b5f7cbc, 0x6b51cc42,
+ 0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+ 0x6af18536, 0x6ae3b3b2,
+ 0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+ 0x6a8285d1, 0x6a749365,
+ 0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+ 0x6a127f9f, 0x6a046c6c,
+ 0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+ 0x69a173b5, 0x69933fde,
+ 0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+ 0x692f6328, 0x69210ed1,
+ 0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+ 0x68bc4f13, 0x68adda5f,
+ 0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+ 0x68483891, 0x6839a3a4,
+ 0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+ 0x67d320c1, 0x67c46bbe,
+ 0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+ 0x675d08c4, 0x674e33d0,
+ 0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+ 0x66e5f1be, 0x66d6fcfd,
+ 0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+ 0x666ddcd3, 0x665ec86b,
+ 0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+ 0x65f4cb2d, 0x65e59742,
+ 0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+ 0x657abdf6, 0x656b6aae,
+ 0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+ 0x64ffb65b, 0x64f043dc,
+ 0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+ 0x6483b58c, 0x647423fb,
+ 0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+ 0x6406bcba, 0x63f70c3f,
+ 0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+ 0x6388cd1b, 0x6378fddc,
+ 0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+ 0x6309e7e4, 0x62f9fa09,
+ 0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+ 0x628a0e50, 0x627a01fe,
+ 0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+ 0x62094199, 0x61f916f9,
+ 0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+ 0x618782fd, 0x61773a37,
+ 0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+ 0x6104d3bc, 0x60f46cf9,
+ 0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+ 0x60813519, 0x6070b080,
+ 0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+ 0x5ffca859, 0x5fec0613,
+ 0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+ 0x5f772ec2, 0x5f666ef9,
+ 0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+ 0x5ef0c99f, 0x5edfec7b,
+ 0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+ 0x5e697a39, 0x5e587fe5,
+ 0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+ 0x5de141e1, 0x5dd02a85,
+ 0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+ 0x5d5821e4, 0x5d46edac,
+ 0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+ 0x5cce1b97, 0x5cbccaac,
+ 0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+ 0x5c43304d, 0x5c31c2db,
+ 0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+ 0x5bb7615d, 0x5ba5d78e,
+ 0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+ 0x5b2ab020, 0x5b190a20,
+ 0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+ 0x5a9d1df1, 0x5a8b5bec,
+ 0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+ 0x5a0eac2e, 0x59fcce4f,
+ 0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+ 0x597f5c36, 0x596d62a9,
+ 0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+ 0x58ef2f6b, 0x58dd1a5d,
+ 0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+ 0x585e2730, 0x584bf6cd,
+ 0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+ 0x57cc44ec, 0x57b9f960,
+ 0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+ 0x57398a05, 0x5727237f,
+ 0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+ 0x56a5f7e7, 0x56937694,
+ 0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+ 0x56118ffe, 0x55fef40a,
+ 0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+ 0x557c53b6, 0x55699d51,
+ 0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+ 0x54e64482, 0x54d373d9,
+ 0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+ 0x544f63d2, 0x543c7914,
+ 0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+ 0x53b7b31c, 0x53a4ae77,
+ 0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+ 0x531f33d5, 0x530c1579,
+ 0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+ 0x5285e777, 0x5272af92,
+ 0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+ 0x51ebcf7a, 0x51d87e3c,
+ 0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+ 0x5150ed5c, 0x513d82f4,
+ 0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+ 0x50b5429a, 0x50a1bf39,
+ 0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+ 0x5018d0b4, 0x5005348a,
+ 0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+ 0x4f7b992d, 0x4f67e46a,
+ 0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+ 0x4edd9d89, 0x4ec9d05e,
+ 0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+ 0x4e3edf4d, 0x4e2af9ea,
+ 0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+ 0x4d9f6001, 0x4d8b6298,
+ 0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+ 0x4cff212e, 0x4ceb0bf0,
+ 0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+ 0x4c5e2460, 0x4c49f77f,
+ 0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+ 0x4bbc6b25, 0x4ba826d1,
+ 0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+ 0x4b19f70a, 0x4b059b77,
+ 0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+ 0x4a76c9a2, 0x4a625701,
+ 0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+ 0x49d2e47e, 0x49be5b02,
+ 0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+ 0x492e4933, 0x4919a90f,
+ 0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+ 0x4888f957, 0x487442be,
+ 0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+ 0x47e2f682, 0x47ce29a7,
+ 0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+ 0x473c424e, 0x47275f63,
+ 0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+ 0x4694de56, 0x467fe590,
+ 0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+ 0x45eccc37, 0x45d7bdc9,
+ 0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+ 0x45440d90, 0x452ee9ae,
+ 0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+ 0x449aa400, 0x44856adf,
+ 0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+ 0x43f0912b, 0x43db42fe,
+ 0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+ 0x4345d6b3, 0x433073b0,
+ 0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+ 0x429a763f, 0x4284fe99,
+ 0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+ 0x41ee7174, 0x41d8e561,
+ 0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+ 0x4141c9fb, 0x412c29b1,
+ 0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+ 0x4094817f, 0x407ecd32,
+ 0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+ 0x3fe699aa, 0x3fd0d191,
+ 0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+ 0x3f38142a, 0x3f22387a,
+ 0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+ 0x3e88f2ae, 0x3e73039d,
+ 0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+ 0x3dd936e6, 0x3dc334a9,
+ 0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+ 0x3d28e282, 0x3d12cd51,
+ 0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+ 0x3c77f737, 0x3c61cf48,
+ 0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+ 0x3bc676b9, 0x3bb03c42,
+ 0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+ 0x3b1462be, 0x3afe15f6,
+ 0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+ 0x3a61bcfd, 0x3a4b5e1b,
+ 0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+ 0x39ae872f, 0x3998166a,
+ 0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+ 0x38fac30e, 0x38e4409e,
+ 0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+ 0x38467255, 0x382fde72,
+ 0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+ 0x379196c3, 0x377af1a3,
+ 0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+ 0x36dc3214, 0x36c57bf0,
+ 0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+ 0x36264609, 0x360f7f19,
+ 0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+ 0x356fd461, 0x3558fcde,
+ 0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+ 0x34b8dee1, 0x34a1f702,
+ 0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+ 0x3401674a, 0x33ea6f48,
+ 0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+ 0x33496f62, 0x33326776,
+ 0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+ 0x3290f8ef, 0x3279e151,
+ 0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+ 0x31d805b7, 0x31c0dea1,
+ 0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+ 0x311e9783, 0x3107612e,
+ 0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+ 0x3064b01d, 0x304d6ac1,
+ 0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+ 0x2faa514f, 0x2f92fd26,
+ 0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+ 0x2eef7ce5, 0x2ed81a29,
+ 0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+ 0x2e3434ac, 0x2e1cc397,
+ 0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+ 0x2d787a72, 0x2d60fb3e,
+ 0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+ 0x2cbc5006, 0x2ca4c2ed,
+ 0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+ 0x2bffb73a, 0x2be81c74,
+ 0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+ 0x2b42b1dd, 0x2b2b09a6,
+ 0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+ 0x2a8541c3, 0x2a6d8c55,
+ 0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+ 0x29c768be, 0x29afa654,
+ 0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+ 0x290928a3, 0x28f15978,
+ 0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+ 0x284a8349, 0x2832a796,
+ 0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+ 0x278b7a84, 0x27739285,
+ 0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+ 0x26cc102d, 0x26b41c1d,
+ 0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+ 0x260c461b, 0x25f44635,
+ 0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+ 0x254c1e28, 0x253412a8,
+ 0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+ 0x248b9a2f, 0x2473834f,
+ 0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+ 0x23cabc09, 0x23b29a05,
+ 0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+ 0x23098593, 0x22f158a7,
+ 0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+ 0x2247f8aa, 0x222fc111,
+ 0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+ 0x2186172b, 0x216dd521,
+ 0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+ 0x20c3e2f5, 0x20ab96b5,
+ 0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+ 0x20015de7, 0x1fe907ae,
+ 0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+ 0x1f3e89e0, 0x1f2629ea,
+ 0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+ 0x1e7b68c2, 0x1e62ff4a,
+ 0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+ 0x1db7fc6d, 0x1d9f89b1,
+ 0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+ 0x1cf446c5, 0x1cdbcb00,
+ 0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+ 0x1c3049ac, 0x1c17c51b,
+ 0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+ 0x1b6c0705, 0x1b5379e5,
+ 0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+ 0x1aa780b6, 0x1a8eeb42,
+ 0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+ 0x19e2b8a2, 0x19ca1b17,
+ 0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+ 0x191db0af, 0x19050b4b,
+ 0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+ 0x18586ac3, 0x183fbdc3,
+ 0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+ 0x1792e8c6, 0x177a3466,
+ 0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+ 0x16cd2c9f, 0x16b4711b,
+ 0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+ 0x16073834, 0x15ee75cb,
+ 0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+ 0x15410d70, 0x1528445d,
+ 0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+ 0x147aae3a, 0x1461debc,
+ 0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+ 0x13b41c7d, 0x139b46d0,
+ 0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+ 0x12ed5a21, 0x12d47e83,
+ 0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+ 0x12266913, 0x120d87c1,
+ 0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+ 0x115f4b3c, 0x11466473,
+ 0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+ 0x10980287, 0x107f1686,
+ 0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+ 0xfd090e1, 0xfb79fe4,
+ 0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+ 0xef0027b,
+ 0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+ 0xe284036,
+ 0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+ 0xd605b03,
+ 0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+ 0xc9854cf,
+ 0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+ 0xbd02f87,
+ 0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+ 0xb07ed19,
+ 0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+ 0xa3f8f73,
+ 0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+ 0x9771884,
+ 0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+ 0x8ae8a3a,
+ 0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+ 0x7e5e685,
+ 0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+ 0x71d2f52,
+ 0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+ 0x6546692,
+ 0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+ 0x58b8e34,
+ 0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+ 0x4c2a827,
+ 0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+ 0x3f9b65b,
+ 0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+ 0x330bac1,
+ 0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+ 0x267b747,
+ 0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+ 0x19eaddd,
+ 0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+ 0xd5a075,
+ 0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+ 0xc90fe,
+
+};
+
+static const q31_t cos_factorsQ31_8192[8192] = {
+ 0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,
+ 0x7ffff97c, 0x7ffff753,
+ 0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,
+ 0x7fffdf94, 0x7fffdaf3,
+ 0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,
+ 0x7fffb1ee, 0x7fffaad6,
+ 0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,
+ 0x7fff708b, 0x7fff66fc,
+ 0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,
+ 0x7fff1b6b, 0x7fff0f64,
+ 0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,
+ 0x7ffeb28e, 0x7ffea40f,
+ 0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,
+ 0x7ffe35f4, 0x7ffe24fe,
+ 0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,
+ 0x7ffda59d, 0x7ffd922f,
+ 0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,
+ 0x7ffd0189, 0x7ffceba4,
+ 0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,
+ 0x7ffc49b9, 0x7ffc315b,
+ 0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,
+ 0x7ffb7e2b, 0x7ffb6356,
+ 0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,
+ 0x7ffa9ee2, 0x7ffa8195,
+ 0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,
+ 0x7ff9abdb, 0x7ff98c17,
+ 0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,
+ 0x7ff8a519, 0x7ff882dd,
+ 0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,
+ 0x7ff78a9a, 0x7ff765e7,
+ 0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,
+ 0x7ff65c5f, 0x7ff63535,
+ 0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,
+ 0x7ff51a69, 0x7ff4f0c7,
+ 0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,
+ 0x7ff3c4b7, 0x7ff3989e,
+ 0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,
+ 0x7ff25b4a, 0x7ff22cb9,
+ 0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,
+ 0x7ff0de22, 0x7ff0ad19,
+ 0x7ff07bc2, 0x7ff04a1c, 0x7ff01827, 0x7fefe5e4, 0x7fefb351, 0x7fef806f,
+ 0x7fef4d3e, 0x7fef19bf,
+ 0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,
+ 0x7feda8a0, 0x7fed72aa,
+ 0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,
+ 0x7febf048, 0x7febb7da,
+ 0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,
+ 0x7fea2436, 0x7fe9e950,
+ 0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,
+ 0x7fe84469, 0x7fe8070d,
+ 0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,
+ 0x7fe650e3, 0x7fe61110,
+ 0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,
+ 0x7fe449a4, 0x7fe40759,
+ 0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,
+ 0x7fe22eac, 0x7fe1e9ea,
+ 0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,
+ 0x7fdffffb, 0x7fdfb8c2,
+ 0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,
+ 0x7fddbd92, 0x7fdd73e2,
+ 0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,
+ 0x7fdb6771, 0x7fdb1b4a,
+ 0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,
+ 0x7fd8fd98, 0x7fd8aefa,
+ 0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,
+ 0x7fd68009, 0x7fd62ef4,
+ 0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,
+ 0x7fd3eec2, 0x7fd39b36,
+ 0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,
+ 0x7fd149c5, 0x7fd0f3c2,
+ 0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,
+ 0x7fce9112, 0x7fce3898,
+ 0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,
+ 0x7fcbc4a9, 0x7fcb69b9,
+ 0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,
+ 0x7fc8e48b, 0x7fc88724,
+ 0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,
+ 0x7fc5f0b8, 0x7fc590db,
+ 0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,
+ 0x7fc2e931, 0x7fc286de,
+ 0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,
+ 0x7fbfcdf6, 0x7fbf692c,
+ 0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,
+ 0x7fbc9f08, 0x7fbc37c8,
+ 0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,
+ 0x7fb95c67, 0x7fb8f2b0,
+ 0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,
+ 0x7fb60614, 0x7fb599e7,
+ 0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,
+ 0x7fb29c0f, 0x7fb22d6c,
+ 0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,
+ 0x7faf1e58, 0x7faead3f,
+ 0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,
+ 0x7fab8cf1, 0x7fab1962,
+ 0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,
+ 0x7fa7e7d9, 0x7fa771d4,
+ 0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,
+ 0x7fa42f12, 0x7fa3b697,
+ 0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,
+ 0x7fa0629c, 0x7f9fe7ab,
+ 0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,
+ 0x7f9c8278, 0x7f9c0511,
+ 0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,
+ 0x7f988ea5, 0x7f980ec8,
+ 0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,
+ 0x7f948725, 0x7f9404d3,
+ 0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,
+ 0x7f906bf9, 0x7f8fe731,
+ 0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,
+ 0x7f8c3d20, 0x7f8bb5e3,
+ 0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,
+ 0x7f87fa9c, 0x7f8770ea,
+ 0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,
+ 0x7f83a46e, 0x7f831846,
+ 0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,
+ 0x7f7f3a95, 0x7f7eabf8,
+ 0x7f7e1d0c, 0x7f7d8dd2, 0x7f7cfe49, 0x7f7c6e71, 0x7f7bde4b, 0x7f7b4dd6,
+ 0x7f7abd13, 0x7f7a2c01,
+ 0x7f799aa0, 0x7f7908f0, 0x7f7876f2, 0x7f77e4a6, 0x7f77520a, 0x7f76bf21,
+ 0x7f762be8, 0x7f759861,
+ 0x7f75048b, 0x7f747067, 0x7f73dbf4, 0x7f734732, 0x7f72b222, 0x7f721cc3,
+ 0x7f718715, 0x7f70f119,
+ 0x7f705ace, 0x7f6fc435, 0x7f6f2d4d, 0x7f6e9617, 0x7f6dfe91, 0x7f6d66be,
+ 0x7f6cce9b, 0x7f6c362a,
+ 0x7f6b9d6b, 0x7f6b045d, 0x7f6a6b00, 0x7f69d154, 0x7f69375a, 0x7f689d12,
+ 0x7f68027b, 0x7f676795,
+ 0x7f66cc61, 0x7f6630de, 0x7f65950c, 0x7f64f8ec, 0x7f645c7d, 0x7f63bfc0,
+ 0x7f6322b4, 0x7f62855a,
+ 0x7f61e7b1, 0x7f6149b9, 0x7f60ab73, 0x7f600cdf, 0x7f5f6dfb, 0x7f5ecec9,
+ 0x7f5e2f49, 0x7f5d8f7a,
+ 0x7f5cef5c, 0x7f5c4ef0, 0x7f5bae36, 0x7f5b0d2c, 0x7f5a6bd5, 0x7f59ca2e,
+ 0x7f592839, 0x7f5885f6,
+ 0x7f57e364, 0x7f574083, 0x7f569d54, 0x7f55f9d6, 0x7f55560a, 0x7f54b1ef,
+ 0x7f540d86, 0x7f5368ce,
+ 0x7f52c3c8, 0x7f521e73, 0x7f5178cf, 0x7f50d2dd, 0x7f502c9d, 0x7f4f860e,
+ 0x7f4edf30, 0x7f4e3804,
+ 0x7f4d9089, 0x7f4ce8c0, 0x7f4c40a8, 0x7f4b9842, 0x7f4aef8d, 0x7f4a468a,
+ 0x7f499d38, 0x7f48f398,
+ 0x7f4849a9, 0x7f479f6c, 0x7f46f4e0, 0x7f464a06, 0x7f459edd, 0x7f44f365,
+ 0x7f44479f, 0x7f439b8b,
+ 0x7f42ef28, 0x7f424277, 0x7f419577, 0x7f40e828, 0x7f403a8b, 0x7f3f8ca0,
+ 0x7f3ede66, 0x7f3e2fde,
+ 0x7f3d8107, 0x7f3cd1e2, 0x7f3c226e, 0x7f3b72ab, 0x7f3ac29b, 0x7f3a123b,
+ 0x7f39618e, 0x7f38b091,
+ 0x7f37ff47, 0x7f374dad, 0x7f369bc6, 0x7f35e990, 0x7f35370b, 0x7f348438,
+ 0x7f33d116, 0x7f331da6,
+ 0x7f3269e8, 0x7f31b5db, 0x7f31017f, 0x7f304cd6, 0x7f2f97dd, 0x7f2ee296,
+ 0x7f2e2d01, 0x7f2d771e,
+ 0x7f2cc0eb, 0x7f2c0a6b, 0x7f2b539c, 0x7f2a9c7e, 0x7f29e512, 0x7f292d58,
+ 0x7f28754f, 0x7f27bcf8,
+ 0x7f270452, 0x7f264b5e, 0x7f25921c, 0x7f24d88b, 0x7f241eab, 0x7f23647e,
+ 0x7f22aa01, 0x7f21ef37,
+ 0x7f21341e, 0x7f2078b6, 0x7f1fbd00, 0x7f1f00fc, 0x7f1e44a9, 0x7f1d8808,
+ 0x7f1ccb18, 0x7f1c0dda,
+ 0x7f1b504e, 0x7f1a9273, 0x7f19d44a, 0x7f1915d2, 0x7f18570c, 0x7f1797f8,
+ 0x7f16d895, 0x7f1618e4,
+ 0x7f1558e4, 0x7f149896, 0x7f13d7fa, 0x7f13170f, 0x7f1255d6, 0x7f11944f,
+ 0x7f10d279, 0x7f101054,
+ 0x7f0f4de2, 0x7f0e8b21, 0x7f0dc811, 0x7f0d04b3, 0x7f0c4107, 0x7f0b7d0d,
+ 0x7f0ab8c4, 0x7f09f42d,
+ 0x7f092f47, 0x7f086a13, 0x7f07a491, 0x7f06dec0, 0x7f0618a1, 0x7f055233,
+ 0x7f048b78, 0x7f03c46d,
+ 0x7f02fd15, 0x7f02356e, 0x7f016d79, 0x7f00a535, 0x7effdca4, 0x7eff13c3,
+ 0x7efe4a95, 0x7efd8118,
+ 0x7efcb74d, 0x7efbed33, 0x7efb22cb, 0x7efa5815, 0x7ef98d11, 0x7ef8c1be,
+ 0x7ef7f61d, 0x7ef72a2d,
+ 0x7ef65def, 0x7ef59163, 0x7ef4c489, 0x7ef3f760, 0x7ef329e9, 0x7ef25c24,
+ 0x7ef18e10, 0x7ef0bfae,
+ 0x7eeff0fe, 0x7eef21ff, 0x7eee52b2, 0x7eed8317, 0x7eecb32d, 0x7eebe2f6,
+ 0x7eeb1270, 0x7eea419b,
+ 0x7ee97079, 0x7ee89f08, 0x7ee7cd49, 0x7ee6fb3b, 0x7ee628df, 0x7ee55635,
+ 0x7ee4833d, 0x7ee3aff6,
+ 0x7ee2dc61, 0x7ee2087e, 0x7ee1344d, 0x7ee05fcd, 0x7edf8aff, 0x7edeb5e3,
+ 0x7edde079, 0x7edd0ac0,
+ 0x7edc34b9, 0x7edb5e64, 0x7eda87c0, 0x7ed9b0ce, 0x7ed8d98e, 0x7ed80200,
+ 0x7ed72a24, 0x7ed651f9,
+ 0x7ed57980, 0x7ed4a0b9, 0x7ed3c7a3, 0x7ed2ee40, 0x7ed2148e, 0x7ed13a8e,
+ 0x7ed0603f, 0x7ecf85a3,
+ 0x7eceaab8, 0x7ecdcf7f, 0x7eccf3f8, 0x7ecc1822, 0x7ecb3bff, 0x7eca5f8d,
+ 0x7ec982cd, 0x7ec8a5bf,
+ 0x7ec7c862, 0x7ec6eab7, 0x7ec60cbe, 0x7ec52e77, 0x7ec44fe2, 0x7ec370fe,
+ 0x7ec291cd, 0x7ec1b24d,
+ 0x7ec0d27f, 0x7ebff263, 0x7ebf11f8, 0x7ebe313f, 0x7ebd5039, 0x7ebc6ee4,
+ 0x7ebb8d40, 0x7ebaab4f,
+ 0x7eb9c910, 0x7eb8e682, 0x7eb803a6, 0x7eb7207c, 0x7eb63d04, 0x7eb5593d,
+ 0x7eb47529, 0x7eb390c6,
+ 0x7eb2ac15, 0x7eb1c716, 0x7eb0e1c9, 0x7eaffc2e, 0x7eaf1645, 0x7eae300d,
+ 0x7ead4987, 0x7eac62b3,
+ 0x7eab7b91, 0x7eaa9421, 0x7ea9ac63, 0x7ea8c457, 0x7ea7dbfc, 0x7ea6f353,
+ 0x7ea60a5d, 0x7ea52118,
+ 0x7ea43785, 0x7ea34da4, 0x7ea26374, 0x7ea178f7, 0x7ea08e2b, 0x7e9fa312,
+ 0x7e9eb7aa, 0x7e9dcbf4,
+ 0x7e9cdff0, 0x7e9bf39e, 0x7e9b06fe, 0x7e9a1a10, 0x7e992cd4, 0x7e983f49,
+ 0x7e975171, 0x7e96634a,
+ 0x7e9574d6, 0x7e948613, 0x7e939702, 0x7e92a7a3, 0x7e91b7f6, 0x7e90c7fb,
+ 0x7e8fd7b2, 0x7e8ee71b,
+ 0x7e8df636, 0x7e8d0502, 0x7e8c1381, 0x7e8b21b1, 0x7e8a2f94, 0x7e893d28,
+ 0x7e884a6f, 0x7e875767,
+ 0x7e866411, 0x7e85706d, 0x7e847c7c, 0x7e83883c, 0x7e8293ae, 0x7e819ed2,
+ 0x7e80a9a8, 0x7e7fb430,
+ 0x7e7ebe6a, 0x7e7dc856, 0x7e7cd1f4, 0x7e7bdb44, 0x7e7ae446, 0x7e79ecf9,
+ 0x7e78f55f, 0x7e77fd77,
+ 0x7e770541, 0x7e760cbd, 0x7e7513ea, 0x7e741aca, 0x7e73215c, 0x7e7227a0,
+ 0x7e712d96, 0x7e70333d,
+ 0x7e6f3897, 0x7e6e3da3, 0x7e6d4261, 0x7e6c46d1, 0x7e6b4af2, 0x7e6a4ec6,
+ 0x7e69524c, 0x7e685584,
+ 0x7e67586e, 0x7e665b0a, 0x7e655d58, 0x7e645f58, 0x7e63610a, 0x7e62626e,
+ 0x7e616384, 0x7e60644c,
+ 0x7e5f64c7, 0x7e5e64f3, 0x7e5d64d1, 0x7e5c6461, 0x7e5b63a4, 0x7e5a6298,
+ 0x7e59613f, 0x7e585f97,
+ 0x7e575da2, 0x7e565b5f, 0x7e5558ce, 0x7e5455ef, 0x7e5352c1, 0x7e524f46,
+ 0x7e514b7e, 0x7e504767,
+ 0x7e4f4302, 0x7e4e3e4f, 0x7e4d394f, 0x7e4c3400, 0x7e4b2e64, 0x7e4a287a,
+ 0x7e492241, 0x7e481bbb,
+ 0x7e4714e7, 0x7e460dc5, 0x7e450656, 0x7e43fe98, 0x7e42f68c, 0x7e41ee33,
+ 0x7e40e58c, 0x7e3fdc97,
+ 0x7e3ed353, 0x7e3dc9c3, 0x7e3cbfe4, 0x7e3bb5b7, 0x7e3aab3c, 0x7e39a074,
+ 0x7e38955e, 0x7e3789fa,
+ 0x7e367e48, 0x7e357248, 0x7e3465fa, 0x7e33595e, 0x7e324c75, 0x7e313f3e,
+ 0x7e3031b9, 0x7e2f23e6,
+ 0x7e2e15c5, 0x7e2d0756, 0x7e2bf89a, 0x7e2ae990, 0x7e29da38, 0x7e28ca92,
+ 0x7e27ba9e, 0x7e26aa5d,
+ 0x7e2599cd, 0x7e2488f0, 0x7e2377c5, 0x7e22664c, 0x7e215486, 0x7e204271,
+ 0x7e1f300f, 0x7e1e1d5f,
+ 0x7e1d0a61, 0x7e1bf716, 0x7e1ae37c, 0x7e19cf95, 0x7e18bb60, 0x7e17a6dd,
+ 0x7e16920d, 0x7e157cee,
+ 0x7e146782, 0x7e1351c9, 0x7e123bc1, 0x7e11256c, 0x7e100ec8, 0x7e0ef7d7,
+ 0x7e0de099, 0x7e0cc90c,
+ 0x7e0bb132, 0x7e0a990a, 0x7e098095, 0x7e0867d1, 0x7e074ec0, 0x7e063561,
+ 0x7e051bb4, 0x7e0401ba,
+ 0x7e02e772, 0x7e01ccdc, 0x7e00b1f9, 0x7dff96c7, 0x7dfe7b48, 0x7dfd5f7b,
+ 0x7dfc4361, 0x7dfb26f9,
+ 0x7dfa0a43, 0x7df8ed3f, 0x7df7cfee, 0x7df6b24f, 0x7df59462, 0x7df47628,
+ 0x7df357a0, 0x7df238ca,
+ 0x7df119a7, 0x7deffa35, 0x7deeda77, 0x7dedba6a, 0x7dec9a10, 0x7deb7968,
+ 0x7dea5872, 0x7de9372f,
+ 0x7de8159e, 0x7de6f3c0, 0x7de5d193, 0x7de4af1a, 0x7de38c52, 0x7de2693d,
+ 0x7de145da, 0x7de02229,
+ 0x7ddefe2b, 0x7dddd9e0, 0x7ddcb546, 0x7ddb905f, 0x7dda6b2a, 0x7dd945a8,
+ 0x7dd81fd8, 0x7dd6f9ba,
+ 0x7dd5d34f, 0x7dd4ac96, 0x7dd38590, 0x7dd25e3c, 0x7dd1369a, 0x7dd00eab,
+ 0x7dcee66e, 0x7dcdbde3,
+ 0x7dcc950b, 0x7dcb6be6, 0x7dca4272, 0x7dc918b1, 0x7dc7eea3, 0x7dc6c447,
+ 0x7dc5999d, 0x7dc46ea6,
+ 0x7dc34361, 0x7dc217cf, 0x7dc0ebef, 0x7dbfbfc1, 0x7dbe9346, 0x7dbd667d,
+ 0x7dbc3967, 0x7dbb0c03,
+ 0x7db9de52, 0x7db8b053, 0x7db78207, 0x7db6536d, 0x7db52485, 0x7db3f550,
+ 0x7db2c5cd, 0x7db195fd,
+ 0x7db065df, 0x7daf3574, 0x7dae04bb, 0x7dacd3b5, 0x7daba261, 0x7daa70c0,
+ 0x7da93ed1, 0x7da80c95,
+ 0x7da6da0b, 0x7da5a733, 0x7da4740e, 0x7da3409c, 0x7da20cdc, 0x7da0d8cf,
+ 0x7d9fa474, 0x7d9e6fcb,
+ 0x7d9d3ad6, 0x7d9c0592, 0x7d9ad001, 0x7d999a23, 0x7d9863f7, 0x7d972d7e,
+ 0x7d95f6b7, 0x7d94bfa3,
+ 0x7d938841, 0x7d925092, 0x7d911896, 0x7d8fe04c, 0x7d8ea7b4, 0x7d8d6ecf,
+ 0x7d8c359d, 0x7d8afc1d,
+ 0x7d89c250, 0x7d888835, 0x7d874dcd, 0x7d861317, 0x7d84d814, 0x7d839cc4,
+ 0x7d826126, 0x7d81253a,
+ 0x7d7fe902, 0x7d7eac7c, 0x7d7d6fa8, 0x7d7c3287, 0x7d7af519, 0x7d79b75d,
+ 0x7d787954, 0x7d773afd,
+ 0x7d75fc59, 0x7d74bd68, 0x7d737e29, 0x7d723e9d, 0x7d70fec4, 0x7d6fbe9d,
+ 0x7d6e7e29, 0x7d6d3d67,
+ 0x7d6bfc58, 0x7d6abafc, 0x7d697952, 0x7d68375b, 0x7d66f517, 0x7d65b285,
+ 0x7d646fa6, 0x7d632c79,
+ 0x7d61e8ff, 0x7d60a538, 0x7d5f6124, 0x7d5e1cc2, 0x7d5cd813, 0x7d5b9316,
+ 0x7d5a4dcc, 0x7d590835,
+ 0x7d57c251, 0x7d567c1f, 0x7d5535a0, 0x7d53eed3, 0x7d52a7ba, 0x7d516053,
+ 0x7d50189e, 0x7d4ed09d,
+ 0x7d4d884e, 0x7d4c3fb1, 0x7d4af6c8, 0x7d49ad91, 0x7d48640d, 0x7d471a3c,
+ 0x7d45d01d, 0x7d4485b1,
+ 0x7d433af8, 0x7d41eff1, 0x7d40a49e, 0x7d3f58fd, 0x7d3e0d0e, 0x7d3cc0d3,
+ 0x7d3b744a, 0x7d3a2774,
+ 0x7d38da51, 0x7d378ce0, 0x7d363f23, 0x7d34f118, 0x7d33a2bf, 0x7d32541a,
+ 0x7d310527, 0x7d2fb5e7,
+ 0x7d2e665a, 0x7d2d1680, 0x7d2bc659, 0x7d2a75e4, 0x7d292522, 0x7d27d413,
+ 0x7d2682b6, 0x7d25310d,
+ 0x7d23df16, 0x7d228cd2, 0x7d213a41, 0x7d1fe762, 0x7d1e9437, 0x7d1d40be,
+ 0x7d1becf8, 0x7d1a98e5,
+ 0x7d194485, 0x7d17efd8, 0x7d169add, 0x7d154595, 0x7d13f001, 0x7d129a1f,
+ 0x7d1143ef, 0x7d0fed73,
+ 0x7d0e96aa, 0x7d0d3f93, 0x7d0be82f, 0x7d0a907e, 0x7d093880, 0x7d07e035,
+ 0x7d06879d, 0x7d052eb8,
+ 0x7d03d585, 0x7d027c05, 0x7d012239, 0x7cffc81f, 0x7cfe6db8, 0x7cfd1304,
+ 0x7cfbb803, 0x7cfa5cb4,
+ 0x7cf90119, 0x7cf7a531, 0x7cf648fb, 0x7cf4ec79, 0x7cf38fa9, 0x7cf2328c,
+ 0x7cf0d522, 0x7cef776b,
+ 0x7cee1967, 0x7cecbb16, 0x7ceb5c78, 0x7ce9fd8d, 0x7ce89e55, 0x7ce73ed0,
+ 0x7ce5defd, 0x7ce47ede,
+ 0x7ce31e72, 0x7ce1bdb8, 0x7ce05cb2, 0x7cdefb5e, 0x7cdd99be, 0x7cdc37d0,
+ 0x7cdad596, 0x7cd9730e,
+ 0x7cd8103a, 0x7cd6ad18, 0x7cd549aa, 0x7cd3e5ee, 0x7cd281e5, 0x7cd11d90,
+ 0x7ccfb8ed, 0x7cce53fe,
+ 0x7ccceec1, 0x7ccb8937, 0x7cca2361, 0x7cc8bd3d, 0x7cc756cd, 0x7cc5f010,
+ 0x7cc48905, 0x7cc321ae,
+ 0x7cc1ba09, 0x7cc05218, 0x7cbee9da, 0x7cbd814f, 0x7cbc1877, 0x7cbaaf51,
+ 0x7cb945df, 0x7cb7dc20,
+ 0x7cb67215, 0x7cb507bc, 0x7cb39d16, 0x7cb23223, 0x7cb0c6e4, 0x7caf5b57,
+ 0x7cadef7e, 0x7cac8358,
+ 0x7cab16e4, 0x7ca9aa24, 0x7ca83d17, 0x7ca6cfbd, 0x7ca56216, 0x7ca3f423,
+ 0x7ca285e2, 0x7ca11755,
+ 0x7c9fa87a, 0x7c9e3953, 0x7c9cc9df, 0x7c9b5a1e, 0x7c99ea10, 0x7c9879b6,
+ 0x7c97090e, 0x7c95981a,
+ 0x7c9426d8, 0x7c92b54a, 0x7c91436f, 0x7c8fd148, 0x7c8e5ed3, 0x7c8cec12,
+ 0x7c8b7903, 0x7c8a05a8,
+ 0x7c889200, 0x7c871e0c, 0x7c85a9ca, 0x7c84353c, 0x7c82c060, 0x7c814b39,
+ 0x7c7fd5c4, 0x7c7e6002,
+ 0x7c7ce9f4, 0x7c7b7399, 0x7c79fcf1, 0x7c7885fc, 0x7c770eba, 0x7c75972c,
+ 0x7c741f51, 0x7c72a729,
+ 0x7c712eb5, 0x7c6fb5f3, 0x7c6e3ce5, 0x7c6cc38a, 0x7c6b49e3, 0x7c69cfee,
+ 0x7c6855ad, 0x7c66db1f,
+ 0x7c656045, 0x7c63e51e, 0x7c6269aa, 0x7c60ede9, 0x7c5f71db, 0x7c5df581,
+ 0x7c5c78da, 0x7c5afbe6,
+ 0x7c597ea6, 0x7c580119, 0x7c56833f, 0x7c550519, 0x7c5386a6, 0x7c5207e6,
+ 0x7c5088d9, 0x7c4f0980,
+ 0x7c4d89da, 0x7c4c09e8, 0x7c4a89a8, 0x7c49091c, 0x7c478844, 0x7c46071f,
+ 0x7c4485ad, 0x7c4303ee,
+ 0x7c4181e3, 0x7c3fff8b, 0x7c3e7ce7, 0x7c3cf9f5, 0x7c3b76b8, 0x7c39f32d,
+ 0x7c386f56, 0x7c36eb33,
+ 0x7c3566c2, 0x7c33e205, 0x7c325cfc, 0x7c30d7a6, 0x7c2f5203, 0x7c2dcc14,
+ 0x7c2c45d8, 0x7c2abf4f,
+ 0x7c29387a, 0x7c27b158, 0x7c2629ea, 0x7c24a22f, 0x7c231a28, 0x7c2191d4,
+ 0x7c200933, 0x7c1e8046,
+ 0x7c1cf70c, 0x7c1b6d86, 0x7c19e3b3, 0x7c185994, 0x7c16cf28, 0x7c15446f,
+ 0x7c13b96a, 0x7c122e19,
+ 0x7c10a27b, 0x7c0f1690, 0x7c0d8a59, 0x7c0bfdd5, 0x7c0a7105, 0x7c08e3e8,
+ 0x7c07567f, 0x7c05c8c9,
+ 0x7c043ac7, 0x7c02ac78, 0x7c011ddd, 0x7bff8ef5, 0x7bfdffc1, 0x7bfc7041,
+ 0x7bfae073, 0x7bf9505a,
+ 0x7bf7bff4, 0x7bf62f41, 0x7bf49e42, 0x7bf30cf6, 0x7bf17b5e, 0x7befe97a,
+ 0x7bee5749, 0x7becc4cc,
+ 0x7beb3202, 0x7be99eec, 0x7be80b89, 0x7be677da, 0x7be4e3df, 0x7be34f97,
+ 0x7be1bb02, 0x7be02621,
+ 0x7bde90f4, 0x7bdcfb7b, 0x7bdb65b5, 0x7bd9cfa2, 0x7bd83944, 0x7bd6a298,
+ 0x7bd50ba1, 0x7bd3745d,
+ 0x7bd1dccc, 0x7bd044f0, 0x7bceacc7, 0x7bcd1451, 0x7bcb7b8f, 0x7bc9e281,
+ 0x7bc84927, 0x7bc6af80,
+ 0x7bc5158c, 0x7bc37b4d, 0x7bc1e0c1, 0x7bc045e9, 0x7bbeaac4, 0x7bbd0f53,
+ 0x7bbb7396, 0x7bb9d78c,
+ 0x7bb83b36, 0x7bb69e94, 0x7bb501a5, 0x7bb3646a, 0x7bb1c6e3, 0x7bb02910,
+ 0x7bae8af0, 0x7bacec84,
+ 0x7bab4dcc, 0x7ba9aec7, 0x7ba80f76, 0x7ba66fd9, 0x7ba4cfef, 0x7ba32fba,
+ 0x7ba18f38, 0x7b9fee69,
+ 0x7b9e4d4f, 0x7b9cabe8, 0x7b9b0a35, 0x7b996836, 0x7b97c5ea, 0x7b962352,
+ 0x7b94806e, 0x7b92dd3e,
+ 0x7b9139c2, 0x7b8f95f9, 0x7b8df1e4, 0x7b8c4d83, 0x7b8aa8d6, 0x7b8903dc,
+ 0x7b875e96, 0x7b85b904,
+ 0x7b841326, 0x7b826cfc, 0x7b80c686, 0x7b7f1fc3, 0x7b7d78b4, 0x7b7bd159,
+ 0x7b7a29b2, 0x7b7881be,
+ 0x7b76d97f, 0x7b7530f3, 0x7b73881b, 0x7b71def7, 0x7b703587, 0x7b6e8bcb,
+ 0x7b6ce1c2, 0x7b6b376e,
+ 0x7b698ccd, 0x7b67e1e0, 0x7b6636a7, 0x7b648b22, 0x7b62df51, 0x7b613334,
+ 0x7b5f86ca, 0x7b5dda15,
+ 0x7b5c2d13, 0x7b5a7fc6, 0x7b58d22c, 0x7b572446, 0x7b557614, 0x7b53c796,
+ 0x7b5218cc, 0x7b5069b6,
+ 0x7b4eba53, 0x7b4d0aa5, 0x7b4b5aab, 0x7b49aa64, 0x7b47f9d2, 0x7b4648f3,
+ 0x7b4497c9, 0x7b42e652,
+ 0x7b413490, 0x7b3f8281, 0x7b3dd026, 0x7b3c1d80, 0x7b3a6a8d, 0x7b38b74e,
+ 0x7b3703c3, 0x7b354fed,
+ 0x7b339bca, 0x7b31e75b, 0x7b3032a0, 0x7b2e7d9a, 0x7b2cc847, 0x7b2b12a8,
+ 0x7b295cbe, 0x7b27a687,
+ 0x7b25f004, 0x7b243936, 0x7b22821b, 0x7b20cab5, 0x7b1f1302, 0x7b1d5b04,
+ 0x7b1ba2b9, 0x7b19ea23,
+ 0x7b183141, 0x7b167813, 0x7b14be99, 0x7b1304d3, 0x7b114ac1, 0x7b0f9063,
+ 0x7b0dd5b9, 0x7b0c1ac4,
+ 0x7b0a5f82, 0x7b08a3f5, 0x7b06e81b, 0x7b052bf6, 0x7b036f85, 0x7b01b2c8,
+ 0x7afff5bf, 0x7afe386a,
+ 0x7afc7aca, 0x7afabcdd, 0x7af8fea5, 0x7af74021, 0x7af58151, 0x7af3c235,
+ 0x7af202cd, 0x7af0431a,
+ 0x7aee831a, 0x7aecc2cf, 0x7aeb0238, 0x7ae94155, 0x7ae78026, 0x7ae5beac,
+ 0x7ae3fce6, 0x7ae23ad4,
+ 0x7ae07876, 0x7adeb5cc, 0x7adcf2d6, 0x7adb2f95, 0x7ad96c08, 0x7ad7a82f,
+ 0x7ad5e40a, 0x7ad41f9a,
+ 0x7ad25ade, 0x7ad095d6, 0x7aced082, 0x7acd0ae3, 0x7acb44f8, 0x7ac97ec1,
+ 0x7ac7b83e, 0x7ac5f170,
+ 0x7ac42a55, 0x7ac262ef, 0x7ac09b3e, 0x7abed341, 0x7abd0af7, 0x7abb4263,
+ 0x7ab97982, 0x7ab7b056,
+ 0x7ab5e6de, 0x7ab41d1b, 0x7ab2530b, 0x7ab088b0, 0x7aaebe0a, 0x7aacf318,
+ 0x7aab27da, 0x7aa95c50,
+ 0x7aa7907b, 0x7aa5c45a, 0x7aa3f7ed, 0x7aa22b35, 0x7aa05e31, 0x7a9e90e1,
+ 0x7a9cc346, 0x7a9af55f,
+ 0x7a99272d, 0x7a9758af, 0x7a9589e5, 0x7a93bad0, 0x7a91eb6f, 0x7a901bc2,
+ 0x7a8e4bca, 0x7a8c7b87,
+ 0x7a8aaaf7, 0x7a88da1c, 0x7a8708f6, 0x7a853784, 0x7a8365c6, 0x7a8193bd,
+ 0x7a7fc168, 0x7a7deec8,
+ 0x7a7c1bdc, 0x7a7a48a4, 0x7a787521, 0x7a76a153, 0x7a74cd38, 0x7a72f8d3,
+ 0x7a712422, 0x7a6f4f25,
+ 0x7a6d79dd, 0x7a6ba449, 0x7a69ce6a, 0x7a67f83f, 0x7a6621c9, 0x7a644b07,
+ 0x7a6273fa, 0x7a609ca1,
+ 0x7a5ec4fc, 0x7a5ced0d, 0x7a5b14d1, 0x7a593c4b, 0x7a576379, 0x7a558a5b,
+ 0x7a53b0f2, 0x7a51d73d,
+ 0x7a4ffd3d, 0x7a4e22f2, 0x7a4c485b, 0x7a4a6d78, 0x7a48924b, 0x7a46b6d1,
+ 0x7a44db0d, 0x7a42fefd,
+ 0x7a4122a1, 0x7a3f45fa, 0x7a3d6908, 0x7a3b8bca, 0x7a39ae41, 0x7a37d06d,
+ 0x7a35f24d, 0x7a3413e2,
+ 0x7a32352b, 0x7a305629, 0x7a2e76dc, 0x7a2c9743, 0x7a2ab75f, 0x7a28d72f,
+ 0x7a26f6b4, 0x7a2515ee,
+ 0x7a2334dd, 0x7a215380, 0x7a1f71d7, 0x7a1d8fe4, 0x7a1bada5, 0x7a19cb1b,
+ 0x7a17e845, 0x7a160524,
+ 0x7a1421b8, 0x7a123e01, 0x7a1059fe, 0x7a0e75b0, 0x7a0c9117, 0x7a0aac32,
+ 0x7a08c702, 0x7a06e187,
+ 0x7a04fbc1, 0x7a0315af, 0x7a012f52, 0x79ff48aa, 0x79fd61b6, 0x79fb7a77,
+ 0x79f992ed, 0x79f7ab18,
+ 0x79f5c2f8, 0x79f3da8c, 0x79f1f1d5, 0x79f008d3, 0x79ee1f86, 0x79ec35ed,
+ 0x79ea4c09, 0x79e861da,
+ 0x79e67760, 0x79e48c9b, 0x79e2a18a, 0x79e0b62e, 0x79deca87, 0x79dcde95,
+ 0x79daf258, 0x79d905d0,
+ 0x79d718fc, 0x79d52bdd, 0x79d33e73, 0x79d150be, 0x79cf62be, 0x79cd7473,
+ 0x79cb85dc, 0x79c996fb,
+ 0x79c7a7ce, 0x79c5b856, 0x79c3c893, 0x79c1d885, 0x79bfe82c, 0x79bdf788,
+ 0x79bc0698, 0x79ba155e,
+ 0x79b823d8, 0x79b63207, 0x79b43fec, 0x79b24d85, 0x79b05ad3, 0x79ae67d6,
+ 0x79ac748e, 0x79aa80fb,
+ 0x79a88d1d, 0x79a698f4, 0x79a4a480, 0x79a2afc1, 0x79a0bab6, 0x799ec561,
+ 0x799ccfc1, 0x799ad9d5,
+ 0x7998e39f, 0x7996ed1e, 0x7994f651, 0x7992ff3a, 0x799107d8, 0x798f102a,
+ 0x798d1832, 0x798b1fef,
+ 0x79892761, 0x79872e87, 0x79853563, 0x79833bf4, 0x7981423a, 0x797f4835,
+ 0x797d4de5, 0x797b534a,
+ 0x79795864, 0x79775d33, 0x797561b8, 0x797365f1, 0x797169df, 0x796f6d83,
+ 0x796d70dc, 0x796b73e9,
+ 0x796976ac, 0x79677924, 0x79657b51, 0x79637d33, 0x79617eca, 0x795f8017,
+ 0x795d8118, 0x795b81cf,
+ 0x7959823b, 0x7957825c, 0x79558232, 0x795381bd, 0x795180fe, 0x794f7ff3,
+ 0x794d7e9e, 0x794b7cfe,
+ 0x79497b13, 0x794778dd, 0x7945765d, 0x79437391, 0x7941707b, 0x793f6d1a,
+ 0x793d696f, 0x793b6578,
+ 0x79396137, 0x79375cab, 0x793557d4, 0x793352b2, 0x79314d46, 0x792f478f,
+ 0x792d418d, 0x792b3b40,
+ 0x792934a9, 0x79272dc7, 0x7925269a, 0x79231f22, 0x79211760, 0x791f0f53,
+ 0x791d06fb, 0x791afe59,
+ 0x7918f56c, 0x7916ec34, 0x7914e2b2, 0x7912d8e4, 0x7910cecc, 0x790ec46a,
+ 0x790cb9bd, 0x790aaec5,
+ 0x7908a382, 0x790697f5, 0x79048c1d, 0x79027ffa, 0x7900738d, 0x78fe66d5,
+ 0x78fc59d3, 0x78fa4c86,
+ 0x78f83eee, 0x78f6310c, 0x78f422df, 0x78f21467, 0x78f005a5, 0x78edf698,
+ 0x78ebe741, 0x78e9d79f,
+ 0x78e7c7b2, 0x78e5b77b, 0x78e3a6f9, 0x78e1962d, 0x78df8516, 0x78dd73b5,
+ 0x78db6209, 0x78d95012,
+ 0x78d73dd1, 0x78d52b46, 0x78d31870, 0x78d1054f, 0x78cef1e4, 0x78ccde2e,
+ 0x78caca2e, 0x78c8b5e3,
+ 0x78c6a14e, 0x78c48c6e, 0x78c27744, 0x78c061cf, 0x78be4c10, 0x78bc3606,
+ 0x78ba1fb2, 0x78b80913,
+ 0x78b5f22a, 0x78b3daf7, 0x78b1c379, 0x78afabb0, 0x78ad939d, 0x78ab7b40,
+ 0x78a96298, 0x78a749a6,
+ 0x78a53069, 0x78a316e2, 0x78a0fd11, 0x789ee2f5, 0x789cc88f, 0x789aadde,
+ 0x789892e3, 0x7896779d,
+ 0x78945c0d, 0x78924033, 0x7890240e, 0x788e07a0, 0x788beae6, 0x7889cde2,
+ 0x7887b094, 0x788592fc,
+ 0x78837519, 0x788156ec, 0x787f3875, 0x787d19b3, 0x787afaa7, 0x7878db50,
+ 0x7876bbb0, 0x78749bc5,
+ 0x78727b8f, 0x78705b10, 0x786e3a46, 0x786c1932, 0x7869f7d3, 0x7867d62a,
+ 0x7865b437, 0x786391fa,
+ 0x78616f72, 0x785f4ca1, 0x785d2984, 0x785b061e, 0x7858e26e, 0x7856be73,
+ 0x78549a2e, 0x7852759e,
+ 0x785050c5, 0x784e2ba1, 0x784c0633, 0x7849e07b, 0x7847ba79, 0x7845942c,
+ 0x78436d96, 0x784146b5,
+ 0x783f1f8a, 0x783cf815, 0x783ad055, 0x7838a84c, 0x78367ff8, 0x7834575a,
+ 0x78322e72, 0x78300540,
+ 0x782ddbc4, 0x782bb1fd, 0x782987ed, 0x78275d92, 0x782532ed, 0x782307fe,
+ 0x7820dcc5, 0x781eb142,
+ 0x781c8575, 0x781a595d, 0x78182cfc, 0x78160051, 0x7813d35b, 0x7811a61b,
+ 0x780f7892, 0x780d4abe,
+ 0x780b1ca0, 0x7808ee38, 0x7806bf86, 0x7804908a, 0x78026145, 0x780031b5,
+ 0x77fe01db, 0x77fbd1b6,
+ 0x77f9a148, 0x77f77090, 0x77f53f8e, 0x77f30e42, 0x77f0dcac, 0x77eeaacc,
+ 0x77ec78a2, 0x77ea462e,
+ 0x77e81370, 0x77e5e068, 0x77e3ad17, 0x77e1797b, 0x77df4595, 0x77dd1165,
+ 0x77dadcec, 0x77d8a828,
+ 0x77d6731a, 0x77d43dc3, 0x77d20822, 0x77cfd236, 0x77cd9c01, 0x77cb6582,
+ 0x77c92eb9, 0x77c6f7a6,
+ 0x77c4c04a, 0x77c288a3, 0x77c050b2, 0x77be1878, 0x77bbdff4, 0x77b9a726,
+ 0x77b76e0e, 0x77b534ac,
+ 0x77b2fb00, 0x77b0c10b, 0x77ae86cc, 0x77ac4c43, 0x77aa1170, 0x77a7d653,
+ 0x77a59aec, 0x77a35f3c,
+ 0x77a12342, 0x779ee6fe, 0x779caa70, 0x779a6d99, 0x77983077, 0x7795f30c,
+ 0x7793b557, 0x77917759,
+ 0x778f3910, 0x778cfa7e, 0x778abba2, 0x77887c7d, 0x77863d0d, 0x7783fd54,
+ 0x7781bd52, 0x777f7d05,
+ 0x777d3c6f, 0x777afb8f, 0x7778ba65, 0x777678f2, 0x77743735, 0x7771f52e,
+ 0x776fb2de, 0x776d7044,
+ 0x776b2d60, 0x7768ea33, 0x7766a6bc, 0x776462fb, 0x77621ef1, 0x775fda9d,
+ 0x775d95ff, 0x775b5118,
+ 0x77590be7, 0x7756c66c, 0x775480a8, 0x77523a9b, 0x774ff443, 0x774dada2,
+ 0x774b66b8, 0x77491f84,
+ 0x7746d806, 0x7744903f, 0x7742482e, 0x773fffd4, 0x773db730, 0x773b6e42,
+ 0x7739250b, 0x7736db8b,
+ 0x773491c0, 0x773247ad, 0x772ffd50, 0x772db2a9, 0x772b67b9, 0x77291c7f,
+ 0x7726d0fc, 0x7724852f,
+ 0x77223919, 0x771fecb9, 0x771da010, 0x771b531d, 0x771905e1, 0x7716b85b,
+ 0x77146a8c, 0x77121c74,
+ 0x770fce12, 0x770d7f66, 0x770b3072, 0x7708e133, 0x770691ab, 0x770441da,
+ 0x7701f1c0, 0x76ffa15c,
+ 0x76fd50ae, 0x76faffb8, 0x76f8ae78, 0x76f65cee, 0x76f40b1b, 0x76f1b8ff,
+ 0x76ef6699, 0x76ed13ea,
+ 0x76eac0f2, 0x76e86db0, 0x76e61a25, 0x76e3c650, 0x76e17233, 0x76df1dcb,
+ 0x76dcc91b, 0x76da7421,
+ 0x76d81ede, 0x76d5c952, 0x76d3737c, 0x76d11d5d, 0x76cec6f5, 0x76cc7043,
+ 0x76ca1948, 0x76c7c204,
+ 0x76c56a77, 0x76c312a0, 0x76c0ba80, 0x76be6217, 0x76bc0965, 0x76b9b069,
+ 0x76b75724, 0x76b4fd96,
+ 0x76b2a3bf, 0x76b0499e, 0x76adef34, 0x76ab9481, 0x76a93985, 0x76a6de40,
+ 0x76a482b1, 0x76a226da,
+ 0x769fcab9, 0x769d6e4f, 0x769b119b, 0x7698b49f, 0x76965759, 0x7693f9ca,
+ 0x76919bf3, 0x768f3dd2,
+ 0x768cdf67, 0x768a80b4, 0x768821b8, 0x7685c272, 0x768362e4, 0x7681030c,
+ 0x767ea2eb, 0x767c4281,
+ 0x7679e1ce, 0x767780d2, 0x76751f8d, 0x7672bdfe, 0x76705c27, 0x766dfa07,
+ 0x766b979d, 0x766934eb,
+ 0x7666d1ef, 0x76646eab, 0x76620b1d, 0x765fa747, 0x765d4327, 0x765adebe,
+ 0x76587a0d, 0x76561512,
+ 0x7653afce, 0x76514a42, 0x764ee46c, 0x764c7e4d, 0x764a17e6, 0x7647b135,
+ 0x76454a3c, 0x7642e2f9,
+ 0x76407b6e, 0x763e139a, 0x763bab7c, 0x76394316, 0x7636da67, 0x7634716f,
+ 0x7632082e, 0x762f9ea4,
+ 0x762d34d1, 0x762acab6, 0x76286051, 0x7625f5a3, 0x76238aad, 0x76211f6e,
+ 0x761eb3e6, 0x761c4815,
+ 0x7619dbfb, 0x76176f98, 0x761502ed, 0x761295f9, 0x761028bb, 0x760dbb35,
+ 0x760b4d67, 0x7608df4f,
+ 0x760670ee, 0x76040245, 0x76019353, 0x75ff2418, 0x75fcb495, 0x75fa44c8,
+ 0x75f7d4b3, 0x75f56455,
+ 0x75f2f3ae, 0x75f082bf, 0x75ee1187, 0x75eba006, 0x75e92e3c, 0x75e6bc2a,
+ 0x75e449ce, 0x75e1d72b,
+ 0x75df643e, 0x75dcf109, 0x75da7d8b, 0x75d809c4, 0x75d595b4, 0x75d3215c,
+ 0x75d0acbc, 0x75ce37d2,
+ 0x75cbc2a0, 0x75c94d25, 0x75c6d762, 0x75c46156, 0x75c1eb01, 0x75bf7464,
+ 0x75bcfd7e, 0x75ba864f,
+ 0x75b80ed8, 0x75b59718, 0x75b31f0f, 0x75b0a6be, 0x75ae2e25, 0x75abb542,
+ 0x75a93c18, 0x75a6c2a4,
+ 0x75a448e8, 0x75a1cee4, 0x759f5496, 0x759cda01, 0x759a5f22, 0x7597e3fc,
+ 0x7595688c, 0x7592ecd4,
+ 0x759070d4, 0x758df48b, 0x758b77fa, 0x7588fb20, 0x75867dfd, 0x75840093,
+ 0x758182df, 0x757f04e3,
+ 0x757c869f, 0x757a0812, 0x7577893d, 0x75750a1f, 0x75728ab9, 0x75700b0a,
+ 0x756d8b13, 0x756b0ad3,
+ 0x75688a4b, 0x7566097b, 0x75638862, 0x75610701, 0x755e8557, 0x755c0365,
+ 0x7559812b, 0x7556fea8,
+ 0x75547bdd, 0x7551f8c9, 0x754f756e, 0x754cf1c9, 0x754a6ddd, 0x7547e9a8,
+ 0x7545652a, 0x7542e065,
+ 0x75405b57, 0x753dd600, 0x753b5061, 0x7538ca7b, 0x7536444b, 0x7533bdd4,
+ 0x75313714, 0x752eb00c,
+ 0x752c28bb, 0x7529a122, 0x75271941, 0x75249118, 0x752208a7, 0x751f7fed,
+ 0x751cf6eb, 0x751a6da0,
+ 0x7517e40e, 0x75155a33, 0x7512d010, 0x751045a5, 0x750dbaf2, 0x750b2ff6,
+ 0x7508a4b2, 0x75061926,
+ 0x75038d52, 0x75010136, 0x74fe74d1, 0x74fbe825, 0x74f95b30, 0x74f6cdf3,
+ 0x74f4406d, 0x74f1b2a0,
+ 0x74ef248b, 0x74ec962d, 0x74ea0787, 0x74e7789a, 0x74e4e964, 0x74e259e6,
+ 0x74dfca20, 0x74dd3a11,
+ 0x74daa9bb, 0x74d8191d, 0x74d58836, 0x74d2f708, 0x74d06591, 0x74cdd3d2,
+ 0x74cb41cc, 0x74c8af7d,
+ 0x74c61ce6, 0x74c38a07, 0x74c0f6e0, 0x74be6372, 0x74bbcfbb, 0x74b93bbc,
+ 0x74b6a775, 0x74b412e6,
+ 0x74b17e0f, 0x74aee8f0, 0x74ac5389, 0x74a9bddb, 0x74a727e4, 0x74a491a5,
+ 0x74a1fb1e, 0x749f6450,
+ 0x749ccd39, 0x749a35db, 0x74979e34, 0x74950646, 0x74926e10, 0x748fd592,
+ 0x748d3ccb, 0x748aa3be,
+ 0x74880a68, 0x748570ca, 0x7482d6e4, 0x74803cb7, 0x747da242, 0x747b0784,
+ 0x74786c7f, 0x7475d132,
+ 0x7473359e, 0x747099c1, 0x746dfd9d, 0x746b6131, 0x7468c47c, 0x74662781,
+ 0x74638a3d, 0x7460ecb2,
+ 0x745e4ede, 0x745bb0c3, 0x74591261, 0x745673b6, 0x7453d4c4, 0x7451358a,
+ 0x744e9608, 0x744bf63e,
+ 0x7449562d, 0x7446b5d4, 0x74441533, 0x7441744b, 0x743ed31b, 0x743c31a3,
+ 0x74398fe3, 0x7436eddc,
+ 0x74344b8d, 0x7431a8f6, 0x742f0618, 0x742c62f2, 0x7429bf84, 0x74271bcf,
+ 0x742477d2, 0x7421d38e,
+ 0x741f2f01, 0x741c8a2d, 0x7419e512, 0x74173faf, 0x74149a04, 0x7411f412,
+ 0x740f4dd8, 0x740ca756,
+ 0x740a008d, 0x7407597d, 0x7404b224, 0x74020a85, 0x73ff629d, 0x73fcba6e,
+ 0x73fa11f8, 0x73f7693a,
+ 0x73f4c034, 0x73f216e7, 0x73ef6d53, 0x73ecc377, 0x73ea1953, 0x73e76ee8,
+ 0x73e4c435, 0x73e2193b,
+ 0x73df6df9, 0x73dcc270, 0x73da16a0, 0x73d76a88, 0x73d4be28, 0x73d21182,
+ 0x73cf6493, 0x73ccb75d,
+ 0x73ca09e0, 0x73c75c1c, 0x73c4ae10, 0x73c1ffbc, 0x73bf5121, 0x73bca23f,
+ 0x73b9f315, 0x73b743a4,
+ 0x73b493ec, 0x73b1e3ec, 0x73af33a5, 0x73ac8316, 0x73a9d240, 0x73a72123,
+ 0x73a46fbf, 0x73a1be13,
+ 0x739f0c20, 0x739c59e5, 0x7399a763, 0x7396f49a, 0x73944189, 0x73918e32,
+ 0x738eda93, 0x738c26ac,
+ 0x7389727f, 0x7386be0a, 0x7384094e, 0x7381544a, 0x737e9f00, 0x737be96e,
+ 0x73793395, 0x73767d74,
+ 0x7373c70d, 0x7371105e, 0x736e5968, 0x736ba22b, 0x7368eaa6, 0x736632db,
+ 0x73637ac8, 0x7360c26e,
+ 0x735e09cd, 0x735b50e4, 0x735897b5, 0x7355de3e, 0x73532481, 0x73506a7c,
+ 0x734db030, 0x734af59d,
+ 0x73483ac2, 0x73457fa1, 0x7342c438, 0x73400889, 0x733d4c92, 0x733a9054,
+ 0x7337d3d0, 0x73351704,
+ 0x733259f1, 0x732f9c97, 0x732cdef6, 0x732a210d, 0x732762de, 0x7324a468,
+ 0x7321e5ab, 0x731f26a7,
+ 0x731c675b, 0x7319a7c9, 0x7316e7f0, 0x731427cf, 0x73116768, 0x730ea6ba,
+ 0x730be5c5, 0x73092489,
+ 0x73066306, 0x7303a13b, 0x7300df2a, 0x72fe1cd2, 0x72fb5a34, 0x72f8974e,
+ 0x72f5d421, 0x72f310ad,
+ 0x72f04cf3, 0x72ed88f1, 0x72eac4a9, 0x72e8001a, 0x72e53b44, 0x72e27627,
+ 0x72dfb0c3, 0x72dceb18,
+ 0x72da2526, 0x72d75eee, 0x72d4986f, 0x72d1d1a9, 0x72cf0a9c, 0x72cc4348,
+ 0x72c97bad, 0x72c6b3cc,
+ 0x72c3eba4, 0x72c12335, 0x72be5a7f, 0x72bb9183, 0x72b8c83f, 0x72b5feb5,
+ 0x72b334e4, 0x72b06acd,
+ 0x72ada06f, 0x72aad5c9, 0x72a80ade, 0x72a53fab, 0x72a27432, 0x729fa872,
+ 0x729cdc6b, 0x729a101e,
+ 0x7297438a, 0x729476af, 0x7291a98e, 0x728edc26, 0x728c0e77, 0x72894082,
+ 0x72867245, 0x7283a3c3,
+ 0x7280d4f9, 0x727e05e9, 0x727b3693, 0x727866f6, 0x72759712, 0x7272c6e7,
+ 0x726ff676, 0x726d25bf,
+ 0x726a54c1, 0x7267837c, 0x7264b1f0, 0x7261e01e, 0x725f0e06, 0x725c3ba7,
+ 0x72596901, 0x72569615,
+ 0x7253c2e3, 0x7250ef6a, 0x724e1baa, 0x724b47a4, 0x72487357, 0x72459ec4,
+ 0x7242c9ea, 0x723ff4ca,
+ 0x723d1f63, 0x723a49b6, 0x723773c3, 0x72349d89, 0x7231c708, 0x722ef041,
+ 0x722c1934, 0x722941e0,
+ 0x72266a46, 0x72239266, 0x7220ba3f, 0x721de1d1, 0x721b091d, 0x72183023,
+ 0x721556e3, 0x72127d5c,
+ 0x720fa38e, 0x720cc97b, 0x7209ef21, 0x72071480, 0x7204399a, 0x72015e6d,
+ 0x71fe82f9, 0x71fba740,
+ 0x71f8cb40, 0x71f5eefa, 0x71f3126d, 0x71f0359a, 0x71ed5881, 0x71ea7b22,
+ 0x71e79d7c, 0x71e4bf90,
+ 0x71e1e15e, 0x71df02e5, 0x71dc2427, 0x71d94522, 0x71d665d6, 0x71d38645,
+ 0x71d0a66d, 0x71cdc650,
+ 0x71cae5ec, 0x71c80542, 0x71c52451, 0x71c2431b, 0x71bf619e, 0x71bc7fdb,
+ 0x71b99dd2, 0x71b6bb83,
+ 0x71b3d8ed, 0x71b0f612, 0x71ae12f0, 0x71ab2f89, 0x71a84bdb, 0x71a567e7,
+ 0x71a283ad, 0x719f9f2c,
+ 0x719cba66, 0x7199d55a, 0x7196f008, 0x71940a6f, 0x71912490, 0x718e3e6c,
+ 0x718b5801, 0x71887151,
+ 0x71858a5a, 0x7182a31d, 0x717fbb9a, 0x717cd3d2, 0x7179ebc3, 0x7177036e,
+ 0x71741ad3, 0x717131f3,
+ 0x716e48cc, 0x716b5f5f, 0x716875ad, 0x71658bb4, 0x7162a175, 0x715fb6f1,
+ 0x715ccc26, 0x7159e116,
+ 0x7156f5c0, 0x71540a24, 0x71511e42, 0x714e321a, 0x714b45ac, 0x714858f8,
+ 0x71456bfe, 0x71427ebf,
+ 0x713f9139, 0x713ca36e, 0x7139b55d, 0x7136c706, 0x7133d869, 0x7130e987,
+ 0x712dfa5e, 0x712b0af0,
+ 0x71281b3c, 0x71252b42, 0x71223b02, 0x711f4a7d, 0x711c59b2, 0x711968a1,
+ 0x7116774a, 0x711385ad,
+ 0x711093cb, 0x710da1a3, 0x710aaf35, 0x7107bc82, 0x7104c989, 0x7101d64a,
+ 0x70fee2c5, 0x70fbeefb,
+ 0x70f8faeb, 0x70f60695, 0x70f311fa, 0x70f01d19, 0x70ed27f2, 0x70ea3286,
+ 0x70e73cd4, 0x70e446dc,
+ 0x70e1509f, 0x70de5a1c, 0x70db6353, 0x70d86c45, 0x70d574f1, 0x70d27d58,
+ 0x70cf8579, 0x70cc8d54,
+ 0x70c994ea, 0x70c69c3a, 0x70c3a345, 0x70c0aa0a, 0x70bdb08a, 0x70bab6c4,
+ 0x70b7bcb8, 0x70b4c267,
+ 0x70b1c7d1, 0x70aeccf5, 0x70abd1d3, 0x70a8d66c, 0x70a5dac0, 0x70a2dece,
+ 0x709fe296, 0x709ce619,
+ 0x7099e957, 0x7096ec4f, 0x7093ef01, 0x7090f16e, 0x708df396, 0x708af579,
+ 0x7087f715, 0x7084f86d,
+ 0x7081f97f, 0x707efa4c, 0x707bfad3, 0x7078fb15, 0x7075fb11, 0x7072fac9,
+ 0x706ffa3a, 0x706cf967,
+ 0x7069f84e, 0x7066f6f0, 0x7063f54c, 0x7060f363, 0x705df135, 0x705aeec1,
+ 0x7057ec08, 0x7054e90a,
+ 0x7051e5c7, 0x704ee23e, 0x704bde70, 0x7048da5d, 0x7045d604, 0x7042d166,
+ 0x703fcc83, 0x703cc75b,
+ 0x7039c1ed, 0x7036bc3b, 0x7033b643, 0x7030b005, 0x702da983, 0x702aa2bb,
+ 0x70279baf, 0x7024945d,
+ 0x70218cc6, 0x701e84e9, 0x701b7cc8, 0x70187461, 0x70156bb5, 0x701262c4,
+ 0x700f598e, 0x700c5013,
+ 0x70094653, 0x70063c4e, 0x70033203, 0x70002774, 0x6ffd1c9f, 0x6ffa1185,
+ 0x6ff70626, 0x6ff3fa82,
+ 0x6ff0ee99, 0x6fede26b, 0x6fead5f8, 0x6fe7c940, 0x6fe4bc43, 0x6fe1af01,
+ 0x6fdea17a, 0x6fdb93ae,
+ 0x6fd8859d, 0x6fd57746, 0x6fd268ab, 0x6fcf59cb, 0x6fcc4aa6, 0x6fc93b3c,
+ 0x6fc62b8d, 0x6fc31b99,
+ 0x6fc00b60, 0x6fbcfae2, 0x6fb9ea20, 0x6fb6d918, 0x6fb3c7cb, 0x6fb0b63a,
+ 0x6fada464, 0x6faa9248,
+ 0x6fa77fe8, 0x6fa46d43, 0x6fa15a59, 0x6f9e472b, 0x6f9b33b7, 0x6f981fff,
+ 0x6f950c01, 0x6f91f7bf,
+ 0x6f8ee338, 0x6f8bce6c, 0x6f88b95c, 0x6f85a407, 0x6f828e6c, 0x6f7f788d,
+ 0x6f7c626a, 0x6f794c01,
+ 0x6f763554, 0x6f731e62, 0x6f70072b, 0x6f6cefb0, 0x6f69d7f0, 0x6f66bfeb,
+ 0x6f63a7a1, 0x6f608f13,
+ 0x6f5d7640, 0x6f5a5d28, 0x6f5743cb, 0x6f542a2a, 0x6f511044, 0x6f4df61a,
+ 0x6f4adbab, 0x6f47c0f7,
+ 0x6f44a5ff, 0x6f418ac2, 0x6f3e6f40, 0x6f3b537a, 0x6f38376f, 0x6f351b1f,
+ 0x6f31fe8b, 0x6f2ee1b2,
+ 0x6f2bc495, 0x6f28a733, 0x6f25898d, 0x6f226ba2, 0x6f1f4d72, 0x6f1c2efe,
+ 0x6f191045, 0x6f15f148,
+ 0x6f12d206, 0x6f0fb280, 0x6f0c92b6, 0x6f0972a6, 0x6f065253, 0x6f0331ba,
+ 0x6f0010de, 0x6efcefbd,
+ 0x6ef9ce57, 0x6ef6acad, 0x6ef38abe, 0x6ef0688b, 0x6eed4614, 0x6eea2358,
+ 0x6ee70058, 0x6ee3dd13,
+ 0x6ee0b98a, 0x6edd95bd, 0x6eda71ab, 0x6ed74d55, 0x6ed428ba, 0x6ed103db,
+ 0x6ecddeb8, 0x6ecab950,
+ 0x6ec793a4, 0x6ec46db4, 0x6ec1477f, 0x6ebe2106, 0x6ebafa49, 0x6eb7d347,
+ 0x6eb4ac02, 0x6eb18477,
+ 0x6eae5ca9, 0x6eab3496, 0x6ea80c3f, 0x6ea4e3a4, 0x6ea1bac4, 0x6e9e91a1,
+ 0x6e9b6839, 0x6e983e8d,
+ 0x6e95149c, 0x6e91ea67, 0x6e8ebfef, 0x6e8b9532, 0x6e886a30, 0x6e853eeb,
+ 0x6e821361, 0x6e7ee794,
+ 0x6e7bbb82, 0x6e788f2c, 0x6e756291, 0x6e7235b3, 0x6e6f0890, 0x6e6bdb2a,
+ 0x6e68ad7f, 0x6e657f90,
+ 0x6e62515d, 0x6e5f22e6, 0x6e5bf42b, 0x6e58c52c, 0x6e5595e9, 0x6e526662,
+ 0x6e4f3696, 0x6e4c0687,
+ 0x6e48d633, 0x6e45a59c, 0x6e4274c1, 0x6e3f43a1, 0x6e3c123e, 0x6e38e096,
+ 0x6e35aeab, 0x6e327c7b,
+ 0x6e2f4a08, 0x6e2c1750, 0x6e28e455, 0x6e25b115, 0x6e227d92, 0x6e1f49cb,
+ 0x6e1c15c0, 0x6e18e171,
+ 0x6e15acde, 0x6e127807, 0x6e0f42ec, 0x6e0c0d8e, 0x6e08d7eb, 0x6e05a205,
+ 0x6e026bda, 0x6dff356c,
+ 0x6dfbfeba, 0x6df8c7c4, 0x6df5908b, 0x6df2590d, 0x6def214c, 0x6debe947,
+ 0x6de8b0fe, 0x6de57871,
+ 0x6de23fa0, 0x6ddf068c, 0x6ddbcd34, 0x6dd89398, 0x6dd559b9, 0x6dd21f95,
+ 0x6dcee52e, 0x6dcbaa83,
+ 0x6dc86f95, 0x6dc53462, 0x6dc1f8ec, 0x6dbebd33, 0x6dbb8135, 0x6db844f4,
+ 0x6db5086f, 0x6db1cba7,
+ 0x6dae8e9b, 0x6dab514b, 0x6da813b8, 0x6da4d5e1, 0x6da197c6, 0x6d9e5968,
+ 0x6d9b1ac6, 0x6d97dbe0,
+ 0x6d949cb7, 0x6d915d4a, 0x6d8e1d9a, 0x6d8adda6, 0x6d879d6e, 0x6d845cf3,
+ 0x6d811c35, 0x6d7ddb33,
+ 0x6d7a99ed, 0x6d775864, 0x6d741697, 0x6d70d487, 0x6d6d9233, 0x6d6a4f9c,
+ 0x6d670cc1, 0x6d63c9a3,
+ 0x6d608641, 0x6d5d429c, 0x6d59feb3, 0x6d56ba87, 0x6d537617, 0x6d503164,
+ 0x6d4cec6e, 0x6d49a734,
+ 0x6d4661b7, 0x6d431bf6, 0x6d3fd5f2, 0x6d3c8fab, 0x6d394920, 0x6d360252,
+ 0x6d32bb40, 0x6d2f73eb,
+ 0x6d2c2c53, 0x6d28e477, 0x6d259c58, 0x6d2253f6, 0x6d1f0b50, 0x6d1bc267,
+ 0x6d18793b, 0x6d152fcc,
+ 0x6d11e619, 0x6d0e9c23, 0x6d0b51e9, 0x6d08076d, 0x6d04bcad, 0x6d0171aa,
+ 0x6cfe2663, 0x6cfadada,
+ 0x6cf78f0d, 0x6cf442fd, 0x6cf0f6aa, 0x6cedaa13, 0x6cea5d3a, 0x6ce7101d,
+ 0x6ce3c2bd, 0x6ce0751a,
+ 0x6cdd2733, 0x6cd9d90a, 0x6cd68a9d, 0x6cd33bed, 0x6ccfecfa, 0x6ccc9dc4,
+ 0x6cc94e4b, 0x6cc5fe8f,
+ 0x6cc2ae90, 0x6cbf5e4d, 0x6cbc0dc8, 0x6cb8bcff, 0x6cb56bf4, 0x6cb21aa5,
+ 0x6caec913, 0x6cab773e,
+ 0x6ca82527, 0x6ca4d2cc, 0x6ca1802e, 0x6c9e2d4d, 0x6c9ada29, 0x6c9786c2,
+ 0x6c943318, 0x6c90df2c,
+ 0x6c8d8afc, 0x6c8a3689, 0x6c86e1d3, 0x6c838cdb, 0x6c80379f, 0x6c7ce220,
+ 0x6c798c5f, 0x6c76365b,
+ 0x6c72e013, 0x6c6f8989, 0x6c6c32bc, 0x6c68dbac, 0x6c658459, 0x6c622cc4,
+ 0x6c5ed4eb, 0x6c5b7cd0,
+ 0x6c582472, 0x6c54cbd1, 0x6c5172ed, 0x6c4e19c6, 0x6c4ac05d, 0x6c4766b0,
+ 0x6c440cc1, 0x6c40b28f,
+ 0x6c3d581b, 0x6c39fd63, 0x6c36a269, 0x6c33472c, 0x6c2febad, 0x6c2c8fea,
+ 0x6c2933e5, 0x6c25d79d,
+ 0x6c227b13, 0x6c1f1e45, 0x6c1bc136, 0x6c1863e3, 0x6c15064e, 0x6c11a876,
+ 0x6c0e4a5b, 0x6c0aebfe,
+ 0x6c078d5e, 0x6c042e7b, 0x6c00cf56, 0x6bfd6fee, 0x6bfa1044, 0x6bf6b056,
+ 0x6bf35027, 0x6befefb5,
+ 0x6bec8f00, 0x6be92e08, 0x6be5ccce, 0x6be26b52, 0x6bdf0993, 0x6bdba791,
+ 0x6bd8454d, 0x6bd4e2c6,
+ 0x6bd17ffd, 0x6bce1cf1, 0x6bcab9a3, 0x6bc75613, 0x6bc3f23f, 0x6bc08e2a,
+ 0x6bbd29d2, 0x6bb9c537,
+ 0x6bb6605a, 0x6bb2fb3b, 0x6baf95d9, 0x6bac3034, 0x6ba8ca4e, 0x6ba56425,
+ 0x6ba1fdb9, 0x6b9e970b,
+ 0x6b9b301b, 0x6b97c8e8, 0x6b946173, 0x6b90f9bc, 0x6b8d91c2, 0x6b8a2986,
+ 0x6b86c107, 0x6b835846,
+ 0x6b7fef43, 0x6b7c85fe, 0x6b791c76, 0x6b75b2ac, 0x6b7248a0, 0x6b6ede51,
+ 0x6b6b73c0, 0x6b6808ed,
+ 0x6b649dd8, 0x6b613280, 0x6b5dc6e6, 0x6b5a5b0a, 0x6b56eeec, 0x6b53828b,
+ 0x6b5015e9, 0x6b4ca904,
+ 0x6b493bdd, 0x6b45ce73, 0x6b4260c8, 0x6b3ef2da, 0x6b3b84ab, 0x6b381639,
+ 0x6b34a785, 0x6b31388e,
+ 0x6b2dc956, 0x6b2a59dc, 0x6b26ea1f, 0x6b237a21, 0x6b2009e0, 0x6b1c995d,
+ 0x6b192898, 0x6b15b791,
+ 0x6b124648, 0x6b0ed4bd, 0x6b0b62f0, 0x6b07f0e1, 0x6b047e90, 0x6b010bfd,
+ 0x6afd9928, 0x6afa2610,
+ 0x6af6b2b7, 0x6af33f1c, 0x6aefcb3f, 0x6aec5720, 0x6ae8e2bf, 0x6ae56e1c,
+ 0x6ae1f937, 0x6ade8410,
+ 0x6adb0ea8, 0x6ad798fd, 0x6ad42311, 0x6ad0ace2, 0x6acd3672, 0x6ac9bfc0,
+ 0x6ac648cb, 0x6ac2d195,
+ 0x6abf5a1e, 0x6abbe264, 0x6ab86a68, 0x6ab4f22b, 0x6ab179ac, 0x6aae00eb,
+ 0x6aaa87e8, 0x6aa70ea4,
+ 0x6aa3951d, 0x6aa01b55, 0x6a9ca14b, 0x6a992700, 0x6a95ac72, 0x6a9231a3,
+ 0x6a8eb692, 0x6a8b3b3f,
+ 0x6a87bfab, 0x6a8443d5, 0x6a80c7bd, 0x6a7d4b64, 0x6a79cec8, 0x6a7651ec,
+ 0x6a72d4cd, 0x6a6f576d,
+ 0x6a6bd9cb, 0x6a685be8, 0x6a64ddc2, 0x6a615f5c, 0x6a5de0b3, 0x6a5a61c9,
+ 0x6a56e29e, 0x6a536331,
+ 0x6a4fe382, 0x6a4c6391, 0x6a48e360, 0x6a4562ec, 0x6a41e237, 0x6a3e6140,
+ 0x6a3ae008, 0x6a375e8f,
+ 0x6a33dcd4, 0x6a305ad7, 0x6a2cd899, 0x6a295619, 0x6a25d358, 0x6a225055,
+ 0x6a1ecd11, 0x6a1b498c,
+ 0x6a17c5c5, 0x6a1441bc, 0x6a10bd72, 0x6a0d38e7, 0x6a09b41a, 0x6a062f0c,
+ 0x6a02a9bc, 0x69ff242b,
+ 0x69fb9e59, 0x69f81845, 0x69f491f0, 0x69f10b5a, 0x69ed8482, 0x69e9fd69,
+ 0x69e6760f, 0x69e2ee73,
+ 0x69df6696, 0x69dbde77, 0x69d85618, 0x69d4cd77, 0x69d14494, 0x69cdbb71,
+ 0x69ca320c, 0x69c6a866,
+ 0x69c31e7f, 0x69bf9456, 0x69bc09ec, 0x69b87f41, 0x69b4f455, 0x69b16928,
+ 0x69adddb9, 0x69aa5209,
+ 0x69a6c618, 0x69a339e6, 0x699fad73, 0x699c20be, 0x699893c9, 0x69950692,
+ 0x6991791a, 0x698deb61,
+ 0x698a5d67, 0x6986cf2c, 0x698340af, 0x697fb1f2, 0x697c22f3, 0x697893b4,
+ 0x69750433, 0x69717472,
+ 0x696de46f, 0x696a542b, 0x6966c3a6, 0x696332e1, 0x695fa1da, 0x695c1092,
+ 0x69587f09, 0x6954ed40,
+ 0x69515b35, 0x694dc8e9, 0x694a365c, 0x6946a38f, 0x69431080, 0x693f7d31,
+ 0x693be9a0, 0x693855cf,
+ 0x6934c1bd, 0x69312d6a, 0x692d98d6, 0x692a0401, 0x69266eeb, 0x6922d995,
+ 0x691f43fd, 0x691bae25,
+ 0x6918180c, 0x691481b2, 0x6910eb17, 0x690d543b, 0x6909bd1f, 0x690625c2,
+ 0x69028e24, 0x68fef645,
+ 0x68fb5e25, 0x68f7c5c5, 0x68f42d24, 0x68f09442, 0x68ecfb20, 0x68e961bd,
+ 0x68e5c819, 0x68e22e34,
+ 0x68de940f, 0x68daf9a9, 0x68d75f02, 0x68d3c41b, 0x68d028f2, 0x68cc8d8a,
+ 0x68c8f1e0, 0x68c555f6,
+ 0x68c1b9cc, 0x68be1d61, 0x68ba80b5, 0x68b6e3c8, 0x68b3469b, 0x68afa92e,
+ 0x68ac0b7f, 0x68a86d91,
+ 0x68a4cf61, 0x68a130f1, 0x689d9241, 0x6899f350, 0x6896541f, 0x6892b4ad,
+ 0x688f14fa, 0x688b7507,
+ 0x6887d4d4, 0x68843460, 0x688093ab, 0x687cf2b6, 0x68795181, 0x6875b00b,
+ 0x68720e55, 0x686e6c5e,
+ 0x686aca27, 0x686727b0, 0x686384f8, 0x685fe200, 0x685c3ec7, 0x68589b4e,
+ 0x6854f795, 0x6851539b,
+ 0x684daf61, 0x684a0ae6, 0x6846662c, 0x6842c131, 0x683f1bf5, 0x683b7679,
+ 0x6837d0bd, 0x68342ac1,
+ 0x68308485, 0x682cde08, 0x6829374b, 0x6825904d, 0x6821e910, 0x681e4192,
+ 0x681a99d4, 0x6816f1d6,
+ 0x68134997, 0x680fa118, 0x680bf85a, 0x68084f5a, 0x6804a61b, 0x6800fc9c,
+ 0x67fd52dc, 0x67f9a8dd,
+ 0x67f5fe9d, 0x67f2541d, 0x67eea95d, 0x67eafe5d, 0x67e7531c, 0x67e3a79c,
+ 0x67dffbdc, 0x67dc4fdb,
+ 0x67d8a39a, 0x67d4f71a, 0x67d14a59, 0x67cd9d58, 0x67c9f017, 0x67c64297,
+ 0x67c294d6, 0x67bee6d5,
+ 0x67bb3894, 0x67b78a13, 0x67b3db53, 0x67b02c52, 0x67ac7d11, 0x67a8cd91,
+ 0x67a51dd0, 0x67a16dcf,
+ 0x679dbd8f, 0x679a0d0f, 0x67965c4e, 0x6792ab4e, 0x678efa0e, 0x678b488e,
+ 0x678796ce, 0x6783e4cf,
+ 0x6780328f, 0x677c8010, 0x6778cd50, 0x67751a51, 0x67716713, 0x676db394,
+ 0x6769ffd5, 0x67664bd7,
+ 0x67629799, 0x675ee31b, 0x675b2e5e, 0x67577960, 0x6753c423, 0x67500ea7,
+ 0x674c58ea, 0x6748a2ee,
+ 0x6744ecb2, 0x67413636, 0x673d7f7b, 0x6739c880, 0x67361145, 0x673259ca,
+ 0x672ea210, 0x672aea17,
+ 0x672731dd, 0x67237964, 0x671fc0ac, 0x671c07b4, 0x67184e7c, 0x67149504,
+ 0x6710db4d, 0x670d2157,
+ 0x67096721, 0x6705acab, 0x6701f1f6, 0x66fe3701, 0x66fa7bcd, 0x66f6c059,
+ 0x66f304a6, 0x66ef48b3,
+ 0x66eb8c80, 0x66e7d00f, 0x66e4135d, 0x66e0566c, 0x66dc993c, 0x66d8dbcd,
+ 0x66d51e1d, 0x66d1602f,
+ 0x66cda201, 0x66c9e393, 0x66c624e7, 0x66c265fa, 0x66bea6cf, 0x66bae764,
+ 0x66b727ba, 0x66b367d0,
+ 0x66afa7a7, 0x66abe73f, 0x66a82697, 0x66a465b0, 0x66a0a489, 0x669ce324,
+ 0x6699217f, 0x66955f9b,
+ 0x66919d77, 0x668ddb14, 0x668a1872, 0x66865591, 0x66829270, 0x667ecf11,
+ 0x667b0b72, 0x66774793,
+ 0x66738376, 0x666fbf19, 0x666bfa7d, 0x666835a2, 0x66647088, 0x6660ab2f,
+ 0x665ce596, 0x66591fbf,
+ 0x665559a8, 0x66519352, 0x664dccbd, 0x664a05e9, 0x66463ed6, 0x66427784,
+ 0x663eaff2, 0x663ae822,
+ 0x66372012, 0x663357c4, 0x662f8f36, 0x662bc66a, 0x6627fd5e, 0x66243413,
+ 0x66206a8a, 0x661ca0c1,
+ 0x6618d6b9, 0x66150c73, 0x661141ed, 0x660d7729, 0x6609ac25, 0x6605e0e3,
+ 0x66021561, 0x65fe49a1,
+ 0x65fa7da2, 0x65f6b164, 0x65f2e4e7, 0x65ef182b, 0x65eb4b30, 0x65e77df6,
+ 0x65e3b07e, 0x65dfe2c6,
+ 0x65dc14d0, 0x65d8469b, 0x65d47827, 0x65d0a975, 0x65ccda83, 0x65c90b53,
+ 0x65c53be4, 0x65c16c36,
+ 0x65bd9c49, 0x65b9cc1e, 0x65b5fbb4, 0x65b22b0b, 0x65ae5a23, 0x65aa88fd,
+ 0x65a6b798, 0x65a2e5f4,
+ 0x659f1412, 0x659b41f1, 0x65976f91, 0x65939cf3, 0x658fca15, 0x658bf6fa,
+ 0x6588239f, 0x65845006,
+ 0x65807c2f, 0x657ca818, 0x6578d3c4, 0x6574ff30, 0x65712a5e, 0x656d554d,
+ 0x65697ffe, 0x6565aa71,
+ 0x6561d4a4, 0x655dfe99, 0x655a2850, 0x655651c8, 0x65527b02, 0x654ea3fd,
+ 0x654accba, 0x6546f538,
+ 0x65431d77, 0x653f4579, 0x653b6d3b, 0x653794c0, 0x6533bc06, 0x652fe30d,
+ 0x652c09d6, 0x65283061,
+ 0x652456ad, 0x65207cbb, 0x651ca28a, 0x6518c81b, 0x6514ed6e, 0x65111283,
+ 0x650d3759, 0x65095bf0,
+ 0x6505804a, 0x6501a465, 0x64fdc841, 0x64f9ebe0, 0x64f60f40, 0x64f23262,
+ 0x64ee5546, 0x64ea77eb,
+ 0x64e69a52, 0x64e2bc7b, 0x64dede66, 0x64db0012, 0x64d72180, 0x64d342b0,
+ 0x64cf63a2, 0x64cb8456,
+ 0x64c7a4cb, 0x64c3c502, 0x64bfe4fc, 0x64bc04b6, 0x64b82433, 0x64b44372,
+ 0x64b06273, 0x64ac8135,
+ 0x64a89fba, 0x64a4be00, 0x64a0dc08, 0x649cf9d2, 0x6499175e, 0x649534ac,
+ 0x649151bc, 0x648d6e8e,
+ 0x64898b22, 0x6485a778, 0x6481c390, 0x647ddf6a, 0x6479fb06, 0x64761664,
+ 0x64723184, 0x646e4c66,
+ 0x646a670a, 0x64668170, 0x64629b98, 0x645eb582, 0x645acf2e, 0x6456e89d,
+ 0x645301cd, 0x644f1ac0,
+ 0x644b3375, 0x64474bec, 0x64436425, 0x643f7c20, 0x643b93dd, 0x6437ab5d,
+ 0x6433c29f, 0x642fd9a3,
+ 0x642bf069, 0x642806f1, 0x64241d3c, 0x64203348, 0x641c4917, 0x64185ea9,
+ 0x641473fc, 0x64108912,
+ 0x640c9dea, 0x6408b284, 0x6404c6e1, 0x6400db00, 0x63fceee1, 0x63f90285,
+ 0x63f515eb, 0x63f12913,
+ 0x63ed3bfd, 0x63e94eaa, 0x63e5611a, 0x63e1734b, 0x63dd853f, 0x63d996f6,
+ 0x63d5a86f, 0x63d1b9aa,
+ 0x63cdcaa8, 0x63c9db68, 0x63c5ebeb, 0x63c1fc30, 0x63be0c37, 0x63ba1c01,
+ 0x63b62b8e, 0x63b23add,
+ 0x63ae49ee, 0x63aa58c2, 0x63a66759, 0x63a275b2, 0x639e83cd, 0x639a91ac,
+ 0x63969f4c, 0x6392acaf,
+ 0x638eb9d5, 0x638ac6be, 0x6386d369, 0x6382dfd6, 0x637eec07, 0x637af7fa,
+ 0x637703af, 0x63730f27,
+ 0x636f1a62, 0x636b2560, 0x63673020, 0x63633aa3, 0x635f44e8, 0x635b4ef0,
+ 0x635758bb, 0x63536249,
+ 0x634f6b99, 0x634b74ad, 0x63477d82, 0x6343861b, 0x633f8e76, 0x633b9695,
+ 0x63379e76, 0x6333a619,
+ 0x632fad80, 0x632bb4a9, 0x6327bb96, 0x6323c245, 0x631fc8b7, 0x631bceeb,
+ 0x6317d4e3, 0x6313da9e,
+ 0x630fe01b, 0x630be55b, 0x6307ea5e, 0x6303ef25, 0x62fff3ae, 0x62fbf7fa,
+ 0x62f7fc08, 0x62f3ffda,
+ 0x62f0036f, 0x62ec06c7, 0x62e809e2, 0x62e40cbf, 0x62e00f60, 0x62dc11c4,
+ 0x62d813eb, 0x62d415d4,
+ 0x62d01781, 0x62cc18f1, 0x62c81a24, 0x62c41b1a, 0x62c01bd3, 0x62bc1c4f,
+ 0x62b81c8f, 0x62b41c91,
+ 0x62b01c57, 0x62ac1bdf, 0x62a81b2b, 0x62a41a3a, 0x62a0190c, 0x629c17a1,
+ 0x629815fa, 0x62941415,
+ 0x629011f4, 0x628c0f96, 0x62880cfb, 0x62840a23, 0x6280070f, 0x627c03be,
+ 0x62780030, 0x6273fc65,
+ 0x626ff85e, 0x626bf41a, 0x6267ef99, 0x6263eadc, 0x625fe5e1, 0x625be0ab,
+ 0x6257db37, 0x6253d587,
+ 0x624fcf9a, 0x624bc970, 0x6247c30a, 0x6243bc68, 0x623fb588, 0x623bae6c,
+ 0x6237a714, 0x62339f7e,
+ 0x622f97ad, 0x622b8f9e, 0x62278754, 0x62237ecc, 0x621f7608, 0x621b6d08,
+ 0x621763cb, 0x62135a51,
+ 0x620f509b, 0x620b46a9, 0x62073c7a, 0x6203320e, 0x61ff2766, 0x61fb1c82,
+ 0x61f71161, 0x61f30604,
+ 0x61eefa6b, 0x61eaee95, 0x61e6e282, 0x61e2d633, 0x61dec9a8, 0x61dabce0,
+ 0x61d6afdd, 0x61d2a29c,
+ 0x61ce9520, 0x61ca8767, 0x61c67971, 0x61c26b40, 0x61be5cd2, 0x61ba4e28,
+ 0x61b63f41, 0x61b2301e,
+ 0x61ae20bf, 0x61aa1124, 0x61a6014d, 0x61a1f139, 0x619de0e9, 0x6199d05d,
+ 0x6195bf94, 0x6191ae90,
+ 0x618d9d4f, 0x61898bd2, 0x61857a19, 0x61816824, 0x617d55f2, 0x61794385,
+ 0x617530db, 0x61711df5,
+ 0x616d0ad3, 0x6168f775, 0x6164e3db, 0x6160d005, 0x615cbbf3, 0x6158a7a4,
+ 0x6154931a, 0x61507e54,
+ 0x614c6951, 0x61485413, 0x61443e98, 0x614028e2, 0x613c12f0, 0x6137fcc1,
+ 0x6133e657, 0x612fcfb0,
+ 0x612bb8ce, 0x6127a1b0, 0x61238a56, 0x611f72c0, 0x611b5aee, 0x611742e0,
+ 0x61132a96, 0x610f1210,
+ 0x610af94f, 0x6106e051, 0x6102c718, 0x60feada3, 0x60fa93f2, 0x60f67a05,
+ 0x60f25fdd, 0x60ee4579,
+ 0x60ea2ad8, 0x60e60ffd, 0x60e1f4e5, 0x60ddd991, 0x60d9be02, 0x60d5a237,
+ 0x60d18631, 0x60cd69ee,
+ 0x60c94d70, 0x60c530b6, 0x60c113c1, 0x60bcf690, 0x60b8d923, 0x60b4bb7a,
+ 0x60b09d96, 0x60ac7f76,
+ 0x60a8611b, 0x60a44284, 0x60a023b1, 0x609c04a3, 0x6097e559, 0x6093c5d3,
+ 0x608fa612, 0x608b8616,
+ 0x608765dd, 0x6083456a, 0x607f24ba, 0x607b03d0, 0x6076e2a9, 0x6072c148,
+ 0x606e9faa, 0x606a7dd2,
+ 0x60665bbd, 0x6062396e, 0x605e16e2, 0x6059f41c, 0x6055d11a, 0x6051addc,
+ 0x604d8a63, 0x604966af,
+ 0x604542bf, 0x60411e94, 0x603cfa2e, 0x6038d58c, 0x6034b0af, 0x60308b97,
+ 0x602c6643, 0x602840b4,
+ 0x60241ae9, 0x601ff4e3, 0x601bcea2, 0x6017a826, 0x6013816e, 0x600f5a7b,
+ 0x600b334d, 0x60070be4,
+ 0x6002e43f, 0x5ffebc5f, 0x5ffa9444, 0x5ff66bee, 0x5ff2435d, 0x5fee1a90,
+ 0x5fe9f188, 0x5fe5c845,
+ 0x5fe19ec7, 0x5fdd750e, 0x5fd94b19, 0x5fd520ea, 0x5fd0f67f, 0x5fcccbd9,
+ 0x5fc8a0f8, 0x5fc475dc,
+ 0x5fc04a85, 0x5fbc1ef3, 0x5fb7f326, 0x5fb3c71e, 0x5faf9adb, 0x5fab6e5d,
+ 0x5fa741a3, 0x5fa314af,
+ 0x5f9ee780, 0x5f9aba16, 0x5f968c70, 0x5f925e90, 0x5f8e3075, 0x5f8a021f,
+ 0x5f85d38e, 0x5f81a4c2,
+ 0x5f7d75bb, 0x5f794679, 0x5f7516fd, 0x5f70e745, 0x5f6cb753, 0x5f688726,
+ 0x5f6456be, 0x5f60261b,
+ 0x5f5bf53d, 0x5f57c424, 0x5f5392d1, 0x5f4f6143, 0x5f4b2f7a, 0x5f46fd76,
+ 0x5f42cb37, 0x5f3e98be,
+ 0x5f3a660a, 0x5f36331b, 0x5f31fff1, 0x5f2dcc8d, 0x5f2998ee, 0x5f256515,
+ 0x5f213100, 0x5f1cfcb1,
+ 0x5f18c827, 0x5f149363, 0x5f105e64, 0x5f0c292a, 0x5f07f3b6, 0x5f03be07,
+ 0x5eff881d, 0x5efb51f9,
+ 0x5ef71b9b, 0x5ef2e501, 0x5eeeae2d, 0x5eea771f, 0x5ee63fd6, 0x5ee20853,
+ 0x5eddd094, 0x5ed9989c,
+ 0x5ed56069, 0x5ed127fb, 0x5eccef53, 0x5ec8b671, 0x5ec47d54, 0x5ec043fc,
+ 0x5ebc0a6a, 0x5eb7d09e,
+ 0x5eb39697, 0x5eaf5c56, 0x5eab21da, 0x5ea6e724, 0x5ea2ac34, 0x5e9e7109,
+ 0x5e9a35a4, 0x5e95fa05,
+ 0x5e91be2b, 0x5e8d8217, 0x5e8945c8, 0x5e85093f, 0x5e80cc7c, 0x5e7c8f7f,
+ 0x5e785247, 0x5e7414d5,
+ 0x5e6fd729, 0x5e6b9943, 0x5e675b22, 0x5e631cc7, 0x5e5ede32, 0x5e5a9f62,
+ 0x5e566059, 0x5e522115,
+ 0x5e4de197, 0x5e49a1df, 0x5e4561ed, 0x5e4121c0, 0x5e3ce15a, 0x5e38a0b9,
+ 0x5e345fde, 0x5e301ec9,
+ 0x5e2bdd7a, 0x5e279bf1, 0x5e235a2e, 0x5e1f1830, 0x5e1ad5f9, 0x5e169388,
+ 0x5e1250dc, 0x5e0e0df7,
+ 0x5e09cad7, 0x5e05877e, 0x5e0143ea, 0x5dfd001d, 0x5df8bc15, 0x5df477d4,
+ 0x5df03359, 0x5debeea3,
+ 0x5de7a9b4, 0x5de3648b, 0x5ddf1f28, 0x5ddad98b, 0x5dd693b4, 0x5dd24da3,
+ 0x5dce0759, 0x5dc9c0d4,
+ 0x5dc57a16, 0x5dc1331d, 0x5dbcebeb, 0x5db8a480, 0x5db45cda, 0x5db014fa,
+ 0x5dabcce1, 0x5da7848e,
+ 0x5da33c01, 0x5d9ef33b, 0x5d9aaa3a, 0x5d966100, 0x5d92178d, 0x5d8dcddf,
+ 0x5d8983f8, 0x5d8539d7,
+ 0x5d80ef7c, 0x5d7ca4e8, 0x5d785a1a, 0x5d740f12, 0x5d6fc3d1, 0x5d6b7856,
+ 0x5d672ca2, 0x5d62e0b4,
+ 0x5d5e948c, 0x5d5a482a, 0x5d55fb90, 0x5d51aebb, 0x5d4d61ad, 0x5d491465,
+ 0x5d44c6e4, 0x5d40792a,
+ 0x5d3c2b35, 0x5d37dd08, 0x5d338ea0, 0x5d2f4000, 0x5d2af125, 0x5d26a212,
+ 0x5d2252c5, 0x5d1e033e,
+ 0x5d19b37e, 0x5d156385, 0x5d111352, 0x5d0cc2e5, 0x5d087240, 0x5d042161,
+ 0x5cffd048, 0x5cfb7ef7,
+ 0x5cf72d6b, 0x5cf2dba7, 0x5cee89a9, 0x5cea3772, 0x5ce5e501, 0x5ce19258,
+ 0x5cdd3f75, 0x5cd8ec58,
+ 0x5cd49903, 0x5cd04574, 0x5ccbf1ab, 0x5cc79daa, 0x5cc3496f, 0x5cbef4fc,
+ 0x5cbaa04f, 0x5cb64b68,
+ 0x5cb1f649, 0x5cada0f0, 0x5ca94b5e, 0x5ca4f594, 0x5ca09f8f, 0x5c9c4952,
+ 0x5c97f2dc, 0x5c939c2c,
+ 0x5c8f4544, 0x5c8aee22, 0x5c8696c7, 0x5c823f34, 0x5c7de767, 0x5c798f61,
+ 0x5c753722, 0x5c70deaa,
+ 0x5c6c85f9, 0x5c682d0f, 0x5c63d3eb, 0x5c5f7a8f, 0x5c5b20fa, 0x5c56c72c,
+ 0x5c526d25, 0x5c4e12e5,
+ 0x5c49b86d, 0x5c455dbb, 0x5c4102d0, 0x5c3ca7ad, 0x5c384c50, 0x5c33f0bb,
+ 0x5c2f94ec, 0x5c2b38e5,
+ 0x5c26dca5, 0x5c22802c, 0x5c1e237b, 0x5c19c690, 0x5c15696d, 0x5c110c11,
+ 0x5c0cae7c, 0x5c0850ae,
+ 0x5c03f2a8, 0x5bff9469, 0x5bfb35f1, 0x5bf6d740, 0x5bf27857, 0x5bee1935,
+ 0x5be9b9da, 0x5be55a46,
+ 0x5be0fa7a, 0x5bdc9a75, 0x5bd83a37, 0x5bd3d9c1, 0x5bcf7912, 0x5bcb182b,
+ 0x5bc6b70b, 0x5bc255b2,
+ 0x5bbdf421, 0x5bb99257, 0x5bb53054, 0x5bb0ce19, 0x5bac6ba6, 0x5ba808f9,
+ 0x5ba3a615, 0x5b9f42f7,
+ 0x5b9adfa2, 0x5b967c13, 0x5b92184d, 0x5b8db44d, 0x5b895016, 0x5b84eba6,
+ 0x5b8086fd, 0x5b7c221c,
+ 0x5b77bd02, 0x5b7357b0, 0x5b6ef226, 0x5b6a8c63, 0x5b662668, 0x5b61c035,
+ 0x5b5d59c9, 0x5b58f324,
+ 0x5b548c48, 0x5b502533, 0x5b4bbde6, 0x5b475660, 0x5b42eea2, 0x5b3e86ac,
+ 0x5b3a1e7e, 0x5b35b617,
+ 0x5b314d78, 0x5b2ce4a1, 0x5b287b91, 0x5b241249, 0x5b1fa8c9, 0x5b1b3f11,
+ 0x5b16d521, 0x5b126af8,
+ 0x5b0e0098, 0x5b0995ff, 0x5b052b2e, 0x5b00c025, 0x5afc54e3, 0x5af7e96a,
+ 0x5af37db8, 0x5aef11cf,
+ 0x5aeaa5ad, 0x5ae63953, 0x5ae1ccc1, 0x5add5ff7, 0x5ad8f2f5, 0x5ad485bb,
+ 0x5ad01849, 0x5acbaa9f,
+ 0x5ac73cbd, 0x5ac2cea3, 0x5abe6050, 0x5ab9f1c6, 0x5ab58304, 0x5ab1140a,
+ 0x5aaca4d8, 0x5aa8356f,
+ 0x5aa3c5cd, 0x5a9f55f3, 0x5a9ae5e2, 0x5a967598, 0x5a920517, 0x5a8d945d,
+ 0x5a89236c, 0x5a84b243,
+ 0x5a8040e3, 0x5a7bcf4a, 0x5a775d7a, 0x5a72eb71, 0x5a6e7931, 0x5a6a06ba,
+ 0x5a65940a, 0x5a612123,
+ 0x5a5cae04, 0x5a583aad, 0x5a53c71e, 0x5a4f5358, 0x5a4adf5a, 0x5a466b24,
+ 0x5a41f6b7, 0x5a3d8212,
+ 0x5a390d35, 0x5a349821, 0x5a3022d5, 0x5a2bad51, 0x5a273796, 0x5a22c1a3,
+ 0x5a1e4b79, 0x5a19d517,
+ 0x5a155e7d, 0x5a10e7ac, 0x5a0c70a3, 0x5a07f963, 0x5a0381eb, 0x59ff0a3c,
+ 0x59fa9255, 0x59f61a36,
+ 0x59f1a1e0, 0x59ed2953, 0x59e8b08e, 0x59e43792, 0x59dfbe5e, 0x59db44f3,
+ 0x59d6cb50, 0x59d25176,
+ 0x59cdd765, 0x59c95d1c, 0x59c4e29c, 0x59c067e4, 0x59bbecf5, 0x59b771cf,
+ 0x59b2f671, 0x59ae7add,
+ 0x59a9ff10, 0x59a5830d, 0x59a106d2, 0x599c8a60, 0x59980db6, 0x599390d5,
+ 0x598f13bd, 0x598a966e,
+ 0x598618e8, 0x59819b2a, 0x597d1d35, 0x59789f09, 0x597420a6, 0x596fa20b,
+ 0x596b233a, 0x5966a431,
+ 0x596224f1, 0x595da57a, 0x595925cc, 0x5954a5e6, 0x595025ca, 0x594ba576,
+ 0x594724ec, 0x5942a42a,
+ 0x593e2331, 0x5939a202, 0x5935209b, 0x59309efd, 0x592c1d28, 0x59279b1c,
+ 0x592318d9, 0x591e9660,
+ 0x591a13af, 0x591590c7, 0x59110da8, 0x590c8a53, 0x590806c6, 0x59038302,
+ 0x58feff08, 0x58fa7ad7,
+ 0x58f5f66e, 0x58f171cf, 0x58ececf9, 0x58e867ed, 0x58e3e2a9, 0x58df5d2e,
+ 0x58dad77d, 0x58d65195,
+ 0x58d1cb76, 0x58cd4520, 0x58c8be94, 0x58c437d1, 0x58bfb0d7, 0x58bb29a6,
+ 0x58b6a23e, 0x58b21aa0,
+ 0x58ad92cb, 0x58a90ac0, 0x58a4827d, 0x589ffa04, 0x589b7155, 0x5896e86f,
+ 0x58925f52, 0x588dd5fe,
+ 0x58894c74, 0x5884c2b3, 0x588038bb, 0x587bae8d, 0x58772429, 0x5872998e,
+ 0x586e0ebc, 0x586983b4,
+ 0x5864f875, 0x58606d00, 0x585be154, 0x58575571, 0x5852c958, 0x584e3d09,
+ 0x5849b083, 0x584523c7,
+ 0x584096d4, 0x583c09ab, 0x58377c4c, 0x5832eeb6, 0x582e60e9, 0x5829d2e6,
+ 0x582544ad, 0x5820b63e,
+ 0x581c2798, 0x581798bb, 0x581309a9, 0x580e7a60, 0x5809eae1, 0x58055b2b,
+ 0x5800cb3f, 0x57fc3b1d,
+ 0x57f7aac5, 0x57f31a36, 0x57ee8971, 0x57e9f876, 0x57e56744, 0x57e0d5dd,
+ 0x57dc443f, 0x57d7b26b,
+ 0x57d32061, 0x57ce8e20, 0x57c9fbaa, 0x57c568fd, 0x57c0d61a, 0x57bc4301,
+ 0x57b7afb2, 0x57b31c2d,
+ 0x57ae8872, 0x57a9f480, 0x57a56059, 0x57a0cbfb, 0x579c3768, 0x5797a29e,
+ 0x57930d9e, 0x578e7869,
+ 0x5789e2fd, 0x57854d5b, 0x5780b784, 0x577c2176, 0x57778b32, 0x5772f4b9,
+ 0x576e5e09, 0x5769c724,
+ 0x57653009, 0x576098b7, 0x575c0130, 0x57576973, 0x5752d180, 0x574e3957,
+ 0x5749a0f9, 0x57450864,
+ 0x57406f9a, 0x573bd69a, 0x57373d64, 0x5732a3f8, 0x572e0a56, 0x5729707f,
+ 0x5724d672, 0x57203c2f,
+ 0x571ba1b7, 0x57170708, 0x57126c24, 0x570dd10a, 0x570935bb, 0x57049a36,
+ 0x56fffe7b, 0x56fb628b,
+ 0x56f6c664, 0x56f22a09, 0x56ed8d77, 0x56e8f0b0, 0x56e453b4, 0x56dfb681,
+ 0x56db1919, 0x56d67b7c,
+ 0x56d1dda9, 0x56cd3fa1, 0x56c8a162, 0x56c402ef, 0x56bf6446, 0x56bac567,
+ 0x56b62653, 0x56b18709,
+ 0x56ace78a, 0x56a847d6, 0x56a3a7ec, 0x569f07cc, 0x569a6777, 0x5695c6ed,
+ 0x5691262d, 0x568c8538,
+ 0x5687e40e, 0x568342ae, 0x567ea118, 0x5679ff4e, 0x56755d4e, 0x5670bb19,
+ 0x566c18ae, 0x5667760e,
+ 0x5662d339, 0x565e302e, 0x56598cee, 0x5654e979, 0x565045cf, 0x564ba1f0,
+ 0x5646fddb, 0x56425991,
+ 0x563db512, 0x5639105d, 0x56346b74, 0x562fc655, 0x562b2101, 0x56267b78,
+ 0x5621d5ba, 0x561d2fc6,
+ 0x5618899e, 0x5613e340, 0x560f3cae, 0x560a95e6, 0x5605eee9, 0x560147b7,
+ 0x55fca050, 0x55f7f8b4,
+ 0x55f350e3, 0x55eea8dd, 0x55ea00a2, 0x55e55832, 0x55e0af8d, 0x55dc06b3,
+ 0x55d75da4, 0x55d2b460,
+ 0x55ce0ae7, 0x55c96139, 0x55c4b757, 0x55c00d3f, 0x55bb62f3, 0x55b6b871,
+ 0x55b20dbb, 0x55ad62d0,
+ 0x55a8b7b0, 0x55a40c5b, 0x559f60d1, 0x559ab513, 0x55960920, 0x55915cf8,
+ 0x558cb09b, 0x55880409,
+ 0x55835743, 0x557eaa48, 0x5579fd18, 0x55754fb3, 0x5570a21a, 0x556bf44c,
+ 0x55674649, 0x55629812,
+ 0x555de9a6, 0x55593b05, 0x55548c30, 0x554fdd26, 0x554b2de7, 0x55467e74,
+ 0x5541cecc, 0x553d1ef0,
+ 0x55386edf, 0x5533be99, 0x552f0e1f, 0x552a5d70, 0x5525ac8d, 0x5520fb75,
+ 0x551c4a29, 0x551798a8,
+ 0x5512e6f3, 0x550e3509, 0x550982eb, 0x5504d099, 0x55001e12, 0x54fb6b56,
+ 0x54f6b866, 0x54f20542,
+ 0x54ed51e9, 0x54e89e5c, 0x54e3ea9a, 0x54df36a5, 0x54da827a, 0x54d5ce1c,
+ 0x54d11989, 0x54cc64c2,
+ 0x54c7afc6, 0x54c2fa96, 0x54be4532, 0x54b98f9a, 0x54b4d9cd, 0x54b023cc,
+ 0x54ab6d97, 0x54a6b72e,
+ 0x54a20090, 0x549d49bf, 0x549892b9, 0x5493db7f, 0x548f2410, 0x548a6c6e,
+ 0x5485b497, 0x5480fc8c,
+ 0x547c444d, 0x54778bda, 0x5472d333, 0x546e1a58, 0x54696149, 0x5464a805,
+ 0x545fee8e, 0x545b34e3,
+ 0x54567b03, 0x5451c0f0, 0x544d06a8, 0x54484c2d, 0x5443917d, 0x543ed699,
+ 0x543a1b82, 0x54356037,
+ 0x5430a4b7, 0x542be904, 0x54272d1d, 0x54227102, 0x541db4b3, 0x5418f830,
+ 0x54143b79, 0x540f7e8e,
+ 0x540ac170, 0x5406041d, 0x54014697, 0x53fc88dd, 0x53f7caef, 0x53f30cce,
+ 0x53ee4e78, 0x53e98fef,
+ 0x53e4d132, 0x53e01242, 0x53db531d, 0x53d693c5, 0x53d1d439, 0x53cd147a,
+ 0x53c85486, 0x53c3945f,
+ 0x53bed405, 0x53ba1377, 0x53b552b5, 0x53b091bf, 0x53abd096, 0x53a70f39,
+ 0x53a24da9, 0x539d8be5,
+ 0x5398c9ed, 0x539407c2, 0x538f4564, 0x538a82d1, 0x5385c00c, 0x5380fd12,
+ 0x537c39e6, 0x53777685,
+ 0x5372b2f2, 0x536def2a, 0x53692b30, 0x53646701, 0x535fa2a0, 0x535ade0b,
+ 0x53561942, 0x53515447,
+ 0x534c8f17, 0x5347c9b5, 0x5343041f, 0x533e3e55, 0x53397859, 0x5334b229,
+ 0x532febc5, 0x532b252f,
+ 0x53265e65, 0x53219767, 0x531cd037, 0x531808d3, 0x5313413c, 0x530e7972,
+ 0x5309b174, 0x5304e943,
+ 0x530020df, 0x52fb5848, 0x52f68f7e, 0x52f1c680, 0x52ecfd4f, 0x52e833ec,
+ 0x52e36a55, 0x52dea08a,
+ 0x52d9d68d, 0x52d50c5d, 0x52d041f9, 0x52cb7763, 0x52c6ac99, 0x52c1e19d,
+ 0x52bd166d, 0x52b84b0a,
+ 0x52b37f74, 0x52aeb3ac, 0x52a9e7b0, 0x52a51b81, 0x52a04f1f, 0x529b828a,
+ 0x5296b5c3, 0x5291e8c8,
+ 0x528d1b9b, 0x52884e3a, 0x528380a7, 0x527eb2e0, 0x5279e4e7, 0x527516bb,
+ 0x5270485c, 0x526b79ca,
+ 0x5266ab06, 0x5261dc0e, 0x525d0ce4, 0x52583d87, 0x52536df7, 0x524e9e34,
+ 0x5249ce3f, 0x5244fe17,
+ 0x52402dbc, 0x523b5d2e, 0x52368c6e, 0x5231bb7b, 0x522cea55, 0x522818fc,
+ 0x52234771, 0x521e75b3,
+ 0x5219a3c3, 0x5214d1a0, 0x520fff4a, 0x520b2cc2, 0x52065a07, 0x52018719,
+ 0x51fcb3f9, 0x51f7e0a6,
+ 0x51f30d21, 0x51ee3969, 0x51e9657e, 0x51e49162, 0x51dfbd12, 0x51dae890,
+ 0x51d613dc, 0x51d13ef5,
+ 0x51cc69db, 0x51c79490, 0x51c2bf11, 0x51bde960, 0x51b9137d, 0x51b43d68,
+ 0x51af6720, 0x51aa90a5,
+ 0x51a5b9f9, 0x51a0e31a, 0x519c0c08, 0x519734c4, 0x51925d4e, 0x518d85a6,
+ 0x5188adcb, 0x5183d5be,
+ 0x517efd7f, 0x517a250d, 0x51754c69, 0x51707393, 0x516b9a8b, 0x5166c150,
+ 0x5161e7e4, 0x515d0e45,
+ 0x51583473, 0x51535a70, 0x514e803b, 0x5149a5d3, 0x5144cb39, 0x513ff06d,
+ 0x513b156f, 0x51363a3f,
+ 0x51315edd, 0x512c8348, 0x5127a782, 0x5122cb8a, 0x511def5f, 0x51191302,
+ 0x51143674, 0x510f59b3,
+ 0x510a7cc1, 0x51059f9c, 0x5100c246, 0x50fbe4bd, 0x50f70703, 0x50f22916,
+ 0x50ed4af8, 0x50e86ca8,
+ 0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,
+ 0x50c65301, 0x50c17322,
+ 0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,
+ 0x509f4e95, 0x509a6d28,
+ 0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,
+ 0x50783dba, 0x50735abf,
+ 0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,
+ 0x50512077, 0x504c3bef,
+ 0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,
+ 0x5029f6d1, 0x502510bd,
+ 0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,
+ 0x5002c0cd, 0x4ffdd92f,
+ 0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,
+ 0x4fdb7e74, 0x4fd6954b,
+ 0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,
+ 0x4fb42fc9, 0x4faf4517,
+ 0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,
+ 0x4f8cd4d4, 0x4f87e899,
+ 0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 0x4f7435c0, 0x4f6f488f, 0x4f6a5b2e,
+ 0x4f656d9b, 0x4f607fd7,
+ 0x4f5b91e3, 0x4f56a3bd, 0x4f51b566, 0x4f4cc6df, 0x4f47d827, 0x4f42e93d,
+ 0x4f3dfa23, 0x4f390ad8,
+ 0x4f341b5c, 0x4f2f2baf, 0x4f2a3bd2, 0x4f254bc3, 0x4f205b84, 0x4f1b6b14,
+ 0x4f167a73, 0x4f1189a1,
+ 0x4f0c989f, 0x4f07a76b, 0x4f02b608, 0x4efdc473, 0x4ef8d2ad, 0x4ef3e0b7,
+ 0x4eeeee90, 0x4ee9fc39,
+ 0x4ee509b1, 0x4ee016f8, 0x4edb240e, 0x4ed630f4, 0x4ed13da9, 0x4ecc4a2e,
+ 0x4ec75682, 0x4ec262a5,
+ 0x4ebd6e98, 0x4eb87a5a, 0x4eb385ec, 0x4eae914d, 0x4ea99c7d, 0x4ea4a77d,
+ 0x4e9fb24d, 0x4e9abcec,
+ 0x4e95c75b, 0x4e90d199, 0x4e8bdba6, 0x4e86e583, 0x4e81ef30, 0x4e7cf8ac,
+ 0x4e7801f8, 0x4e730b14,
+ 0x4e6e13ff, 0x4e691cba, 0x4e642544, 0x4e5f2d9e, 0x4e5a35c7, 0x4e553dc1,
+ 0x4e50458a, 0x4e4b4d22,
+ 0x4e46548b, 0x4e415bc3, 0x4e3c62cb, 0x4e3769a2, 0x4e32704a, 0x4e2d76c1,
+ 0x4e287d08, 0x4e23831e,
+ 0x4e1e8905, 0x4e198ebb, 0x4e149441, 0x4e0f9997, 0x4e0a9ebd, 0x4e05a3b2,
+ 0x4e00a878, 0x4dfbad0d,
+ 0x4df6b173, 0x4df1b5a8, 0x4decb9ad, 0x4de7bd82, 0x4de2c127, 0x4dddc49c,
+ 0x4dd8c7e1, 0x4dd3caf6,
+ 0x4dcecdda, 0x4dc9d08f, 0x4dc4d314, 0x4dbfd569, 0x4dbad78e, 0x4db5d983,
+ 0x4db0db48, 0x4dabdcdd,
+ 0x4da6de43, 0x4da1df78, 0x4d9ce07d, 0x4d97e153, 0x4d92e1f9, 0x4d8de26f,
+ 0x4d88e2b5, 0x4d83e2cb,
+ 0x4d7ee2b1, 0x4d79e268, 0x4d74e1ef, 0x4d6fe146, 0x4d6ae06d, 0x4d65df64,
+ 0x4d60de2c, 0x4d5bdcc4,
+ 0x4d56db2d, 0x4d51d965, 0x4d4cd76e, 0x4d47d547, 0x4d42d2f1, 0x4d3dd06b,
+ 0x4d38cdb5, 0x4d33cad0,
+ 0x4d2ec7bb, 0x4d29c476, 0x4d24c102, 0x4d1fbd5e, 0x4d1ab98b, 0x4d15b588,
+ 0x4d10b155, 0x4d0bacf3,
+ 0x4d06a862, 0x4d01a3a0, 0x4cfc9eb0, 0x4cf79990, 0x4cf29440, 0x4ced8ec1,
+ 0x4ce88913, 0x4ce38335,
+ 0x4cde7d28, 0x4cd976eb, 0x4cd4707f, 0x4ccf69e3, 0x4cca6318, 0x4cc55c1e,
+ 0x4cc054f4, 0x4cbb4d9b,
+ 0x4cb64613, 0x4cb13e5b, 0x4cac3674, 0x4ca72e5e, 0x4ca22619, 0x4c9d1da4,
+ 0x4c981500, 0x4c930c2d,
+ 0x4c8e032a, 0x4c88f9f8, 0x4c83f097, 0x4c7ee707, 0x4c79dd48, 0x4c74d359,
+ 0x4c6fc93b, 0x4c6abeef,
+ 0x4c65b473, 0x4c60a9c8, 0x4c5b9eed, 0x4c5693e4, 0x4c5188ac, 0x4c4c7d44,
+ 0x4c4771ae, 0x4c4265e8,
+ 0x4c3d59f3, 0x4c384dd0, 0x4c33417d, 0x4c2e34fb, 0x4c29284b, 0x4c241b6b,
+ 0x4c1f0e5c, 0x4c1a011f,
+ 0x4c14f3b2, 0x4c0fe617, 0x4c0ad84c, 0x4c05ca53, 0x4c00bc2b, 0x4bfbadd4,
+ 0x4bf69f4e, 0x4bf19099,
+ 0x4bec81b5, 0x4be772a3, 0x4be26362, 0x4bdd53f2, 0x4bd84453, 0x4bd33485,
+ 0x4bce2488, 0x4bc9145d,
+ 0x4bc40403, 0x4bbef37b, 0x4bb9e2c3, 0x4bb4d1dd, 0x4bafc0c8, 0x4baaaf85,
+ 0x4ba59e12, 0x4ba08c72,
+ 0x4b9b7aa2, 0x4b9668a4, 0x4b915677, 0x4b8c441c, 0x4b873192, 0x4b821ed9,
+ 0x4b7d0bf2, 0x4b77f8dc,
+ 0x4b72e598, 0x4b6dd225, 0x4b68be84, 0x4b63aab4, 0x4b5e96b6, 0x4b598289,
+ 0x4b546e2d, 0x4b4f59a4,
+ 0x4b4a44eb, 0x4b453005, 0x4b401aef, 0x4b3b05ac, 0x4b35f03a, 0x4b30da9a,
+ 0x4b2bc4cb, 0x4b26aece,
+ 0x4b2198a2, 0x4b1c8248, 0x4b176bc0, 0x4b12550a, 0x4b0d3e25, 0x4b082712,
+ 0x4b030fd1, 0x4afdf861,
+ 0x4af8e0c3, 0x4af3c8f7, 0x4aeeb0fd, 0x4ae998d4, 0x4ae4807d, 0x4adf67f8,
+ 0x4ada4f45, 0x4ad53664,
+ 0x4ad01d54, 0x4acb0417, 0x4ac5eaab, 0x4ac0d111, 0x4abbb749, 0x4ab69d53,
+ 0x4ab1832f, 0x4aac68dc,
+ 0x4aa74e5c, 0x4aa233ae, 0x4a9d18d1, 0x4a97fdc7, 0x4a92e28e, 0x4a8dc728,
+ 0x4a88ab93, 0x4a838fd1,
+ 0x4a7e73e0, 0x4a7957c2, 0x4a743b76, 0x4a6f1efc, 0x4a6a0253, 0x4a64e57d,
+ 0x4a5fc879, 0x4a5aab48,
+ 0x4a558de8, 0x4a50705a, 0x4a4b529f, 0x4a4634b6, 0x4a41169f, 0x4a3bf85a,
+ 0x4a36d9e7, 0x4a31bb47,
+ 0x4a2c9c79, 0x4a277d7d, 0x4a225e53, 0x4a1d3efc, 0x4a181f77, 0x4a12ffc4,
+ 0x4a0ddfe4, 0x4a08bfd5,
+ 0x4a039f9a, 0x49fe7f30, 0x49f95e99, 0x49f43dd4, 0x49ef1ce2, 0x49e9fbc2,
+ 0x49e4da74, 0x49dfb8f9,
+ 0x49da9750, 0x49d5757a, 0x49d05376, 0x49cb3145, 0x49c60ee6, 0x49c0ec59,
+ 0x49bbc9a0, 0x49b6a6b8,
+ 0x49b183a3, 0x49ac6061, 0x49a73cf1, 0x49a21954, 0x499cf589, 0x4997d191,
+ 0x4992ad6c, 0x498d8919,
+ 0x49886499, 0x49833fec, 0x497e1b11, 0x4978f609, 0x4973d0d3, 0x496eab70,
+ 0x496985e0, 0x49646023,
+ 0x495f3a38, 0x495a1420, 0x4954eddb, 0x494fc768, 0x494aa0c9, 0x494579fc,
+ 0x49405302, 0x493b2bdb,
+ 0x49360486, 0x4930dd05, 0x492bb556, 0x49268d7a, 0x49216571, 0x491c3d3b,
+ 0x491714d8, 0x4911ec47,
+ 0x490cc38a, 0x49079aa0, 0x49027188, 0x48fd4844, 0x48f81ed2, 0x48f2f534,
+ 0x48edcb68, 0x48e8a170,
+ 0x48e3774a, 0x48de4cf8, 0x48d92278, 0x48d3f7cc, 0x48ceccf3, 0x48c9a1ed,
+ 0x48c476b9, 0x48bf4b59,
+ 0x48ba1fcd, 0x48b4f413, 0x48afc82c, 0x48aa9c19, 0x48a56fd9, 0x48a0436c,
+ 0x489b16d2, 0x4895ea0b,
+ 0x4890bd18, 0x488b8ff8, 0x488662ab, 0x48813531, 0x487c078b, 0x4876d9b8,
+ 0x4871abb8, 0x486c7d8c,
+ 0x48674f33, 0x486220ad, 0x485cf1fa, 0x4857c31b, 0x48529410, 0x484d64d7,
+ 0x48483572, 0x484305e1,
+ 0x483dd623, 0x4838a638, 0x48337621, 0x482e45dd, 0x4829156d, 0x4823e4d0,
+ 0x481eb407, 0x48198311,
+ 0x481451ef, 0x480f20a0, 0x4809ef25, 0x4804bd7e, 0x47ff8baa, 0x47fa59a9,
+ 0x47f5277d, 0x47eff523,
+ 0x47eac29e, 0x47e58fec, 0x47e05d0e, 0x47db2a03, 0x47d5f6cc, 0x47d0c369,
+ 0x47cb8fd9, 0x47c65c1d,
+ 0x47c12835, 0x47bbf421, 0x47b6bfe0, 0x47b18b74, 0x47ac56da, 0x47a72215,
+ 0x47a1ed24, 0x479cb806,
+ 0x479782bc, 0x47924d46, 0x478d17a4, 0x4787e1d6, 0x4782abdb, 0x477d75b5,
+ 0x47783f62, 0x477308e3,
+ 0x476dd239, 0x47689b62, 0x4763645f, 0x475e2d30, 0x4758f5d5, 0x4753be4e,
+ 0x474e869b, 0x47494ebc,
+ 0x474416b1, 0x473ede7a, 0x4739a617, 0x47346d89, 0x472f34ce, 0x4729fbe7,
+ 0x4724c2d5, 0x471f8996,
+ 0x471a502c, 0x47151696, 0x470fdcd4, 0x470aa2e6, 0x470568cd, 0x47002e87,
+ 0x46faf416, 0x46f5b979,
+ 0x46f07eb0, 0x46eb43bc, 0x46e6089b, 0x46e0cd4f, 0x46db91d8, 0x46d65634,
+ 0x46d11a65, 0x46cbde6a,
+ 0x46c6a244, 0x46c165f1, 0x46bc2974, 0x46b6ecca, 0x46b1aff5, 0x46ac72f4,
+ 0x46a735c8, 0x46a1f870,
+ 0x469cbaed, 0x46977d3e, 0x46923f63, 0x468d015d, 0x4687c32c, 0x468284cf,
+ 0x467d4646, 0x46780792,
+ 0x4672c8b3, 0x466d89a8, 0x46684a71, 0x46630b0f, 0x465dcb82, 0x46588bc9,
+ 0x46534be5, 0x464e0bd6,
+ 0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,
+ 0x462946ac, 0x46240542,
+ 0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,
+ 0x45ff36a1, 0x45f9f3dd,
+ 0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,
+ 0x45d51bcb, 0x45cfd7ae,
+ 0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,
+ 0x45aaf630, 0x45a5b0bb,
+ 0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,
+ 0x4580c5d6, 0x457b7f0a,
+ 0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,
+ 0x45568ac4, 0x455142a2,
+ 0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,
+ 0x452c4502, 0x4526fb89,
+ 0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,
+ 0x4501f494, 0x44fca9c6,
+ 0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,
+ 0x44d79982, 0x44d24d60,
+ 0x44cd0114, 0x44c7b49e, 0x44c267fd, 0x44bd1b32, 0x44b7ce3c, 0x44b2811c,
+ 0x44ad33d2, 0x44a7e65d,
+ 0x44a298be, 0x449d4af5, 0x4497fd01, 0x4492aee3, 0x448d609b, 0x44881228,
+ 0x4482c38b, 0x447d74c4,
+ 0x447825d2, 0x4472d6b7, 0x446d8771, 0x44683801, 0x4462e866, 0x445d98a2,
+ 0x445848b3, 0x4452f89b,
+ 0x444da858, 0x444857ea, 0x44430753, 0x443db692, 0x443865a7, 0x44331491,
+ 0x442dc351, 0x442871e8,
+ 0x44232054, 0x441dce96, 0x44187caf, 0x44132a9d, 0x440dd861, 0x440885fc,
+ 0x4403336c, 0x43fde0b2,
+ 0x43f88dcf, 0x43f33ac1, 0x43ede78a, 0x43e89429, 0x43e3409d, 0x43ddece8,
+ 0x43d8990a, 0x43d34501,
+ 0x43cdf0ce, 0x43c89c72, 0x43c347eb, 0x43bdf33b, 0x43b89e62, 0x43b3495e,
+ 0x43adf431, 0x43a89ed9,
+ 0x43a34959, 0x439df3ae, 0x43989dda, 0x439347dc, 0x438df1b4, 0x43889b63,
+ 0x438344e8, 0x437dee43,
+ 0x43789775, 0x4373407d, 0x436de95b, 0x43689210, 0x43633a9c, 0x435de2fd,
+ 0x43588b36, 0x43533344,
+ 0x434ddb29, 0x434882e5, 0x43432a77, 0x433dd1e0, 0x4338791f, 0x43332035,
+ 0x432dc721, 0x43286de4,
+ 0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,
+ 0x4302f8b0, 0x42fd9e28,
+ 0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,
+ 0x42d81fe9, 0x42d2c417,
+ 0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,
+ 0x42ad3cd4, 0x42a7dfb8,
+ 0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,
+ 0x42824f76, 0x427cf112,
+ 0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,
+ 0x425757d7, 0x4251f82b,
+ 0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,
+ 0x422c55fd, 0x4226f50a,
+ 0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,
+ 0x420149ee, 0x41fbe7b5,
+ 0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,
+ 0x41d633b1, 0x41d0d033,
+ 0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,
+ 0x41ab134e, 0x41a5ae8b,
+ 0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,
+ 0x417fe8ca, 0x417a82c3,
+ 0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,
+ 0x4154b42c, 0x414f4ce2,
+ 0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,
+ 0x4129757b, 0x41240cef,
+ 0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,
+ 0x40fe2cbd, 0x40f8c2f1,
+ 0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,
+ 0x40d2d9f9, 0x40cd6eed,
+ 0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,
+ 0x40a77d37, 0x40a210eb,
+ 0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,
+ 0x407c167c, 0x4076a8f1,
+ 0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,
+ 0x4050a5cf, 0x404b3707,
+ 0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,
+ 0x40252b37, 0x401fbb32,
+ 0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,
+ 0x3ff9a6bb, 0x3ff4357a,
+ 0x3feec411, 0x3fe95281, 0x3fe3e0c9, 0x3fde6eeb, 0x3fd8fce4, 0x3fd38ab6,
+ 0x3fce1861, 0x3fc8a5e5,
+ 0x3fc33341, 0x3fbdc076, 0x3fb84d83, 0x3fb2da6a, 0x3fad6729, 0x3fa7f3c0,
+ 0x3fa28031, 0x3f9d0c7a,
+ 0x3f97989c, 0x3f922496, 0x3f8cb06a, 0x3f873c16, 0x3f81c79b, 0x3f7c52f9,
+ 0x3f76de30, 0x3f71693f,
+ 0x3f6bf428, 0x3f667ee9, 0x3f610983, 0x3f5b93f6, 0x3f561e42, 0x3f50a867,
+ 0x3f4b3265, 0x3f45bc3c,
+ 0x3f4045ec, 0x3f3acf75, 0x3f3558d7, 0x3f2fe211, 0x3f2a6b25, 0x3f24f412,
+ 0x3f1f7cd8, 0x3f1a0577,
+ 0x3f148def, 0x3f0f1640, 0x3f099e6b, 0x3f04266e, 0x3efeae4a, 0x3ef93600,
+ 0x3ef3bd8f, 0x3eee44f7,
+ 0x3ee8cc38, 0x3ee35352, 0x3eddda46, 0x3ed86113, 0x3ed2e7b9, 0x3ecd6e38,
+ 0x3ec7f491, 0x3ec27ac2,
+ 0x3ebd00cd, 0x3eb786b2, 0x3eb20c6f, 0x3eac9206, 0x3ea71777, 0x3ea19cc1,
+ 0x3e9c21e4, 0x3e96a6e0,
+ 0x3e912bb6, 0x3e8bb065, 0x3e8634ee, 0x3e80b950, 0x3e7b3d8c, 0x3e75c1a1,
+ 0x3e70458f, 0x3e6ac957,
+ 0x3e654cf8, 0x3e5fd073, 0x3e5a53c8, 0x3e54d6f6, 0x3e4f59fe, 0x3e49dcdf,
+ 0x3e445f99, 0x3e3ee22e,
+ 0x3e39649c, 0x3e33e6e3, 0x3e2e6904, 0x3e28eaff, 0x3e236cd4, 0x3e1dee82,
+ 0x3e18700a, 0x3e12f16b,
+ 0x3e0d72a6, 0x3e07f3bb, 0x3e0274aa, 0x3dfcf572, 0x3df77615, 0x3df1f691,
+ 0x3dec76e6, 0x3de6f716,
+ 0x3de1771f, 0x3ddbf703, 0x3dd676c0, 0x3dd0f656, 0x3dcb75c7, 0x3dc5f512,
+ 0x3dc07436, 0x3dbaf335,
+ 0x3db5720d, 0x3daff0c0, 0x3daa6f4c, 0x3da4edb2, 0x3d9f6bf2, 0x3d99ea0d,
+ 0x3d946801, 0x3d8ee5cf,
+ 0x3d896377, 0x3d83e0f9, 0x3d7e5e56, 0x3d78db8c, 0x3d73589d, 0x3d6dd587,
+ 0x3d68524c, 0x3d62ceeb,
+ 0x3d5d4b64, 0x3d57c7b7, 0x3d5243e4, 0x3d4cbfeb, 0x3d473bcd, 0x3d41b789,
+ 0x3d3c331f, 0x3d36ae8f,
+ 0x3d3129da, 0x3d2ba4fe, 0x3d261ffd, 0x3d209ad7, 0x3d1b158a, 0x3d159018,
+ 0x3d100a80, 0x3d0a84c3,
+ 0x3d04fee0, 0x3cff78d7, 0x3cf9f2a9, 0x3cf46c55, 0x3ceee5db, 0x3ce95f3c,
+ 0x3ce3d877, 0x3cde518d,
+ 0x3cd8ca7d, 0x3cd34347, 0x3ccdbbed, 0x3cc8346c, 0x3cc2acc6, 0x3cbd24fb,
+ 0x3cb79d0a, 0x3cb214f4,
+ 0x3cac8cb8, 0x3ca70457, 0x3ca17bd0, 0x3c9bf324, 0x3c966a53, 0x3c90e15c,
+ 0x3c8b5840, 0x3c85cefe,
+ 0x3c804598, 0x3c7abc0c, 0x3c75325a, 0x3c6fa883, 0x3c6a1e87, 0x3c649466,
+ 0x3c5f0a20, 0x3c597fb4,
+ 0x3c53f523, 0x3c4e6a6d, 0x3c48df91, 0x3c435491, 0x3c3dc96b, 0x3c383e20,
+ 0x3c32b2b0, 0x3c2d271b,
+ 0x3c279b61, 0x3c220f81, 0x3c1c837d, 0x3c16f753, 0x3c116b04, 0x3c0bde91,
+ 0x3c0651f8, 0x3c00c53a,
+ 0x3bfb3857, 0x3bf5ab50, 0x3bf01e23, 0x3bea90d1, 0x3be5035a, 0x3bdf75bf,
+ 0x3bd9e7fe, 0x3bd45a19,
+ 0x3bcecc0e, 0x3bc93ddf, 0x3bc3af8b, 0x3bbe2112, 0x3bb89274, 0x3bb303b1,
+ 0x3bad74c9, 0x3ba7e5bd,
+ 0x3ba2568c, 0x3b9cc736, 0x3b9737bb, 0x3b91a81c, 0x3b8c1857, 0x3b86886e,
+ 0x3b80f861, 0x3b7b682e,
+ 0x3b75d7d7, 0x3b70475c, 0x3b6ab6bb, 0x3b6525f6, 0x3b5f950c, 0x3b5a03fe,
+ 0x3b5472cb, 0x3b4ee173,
+ 0x3b494ff7, 0x3b43be57, 0x3b3e2c91, 0x3b389aa8, 0x3b330899, 0x3b2d7666,
+ 0x3b27e40f, 0x3b225193,
+ 0x3b1cbef3, 0x3b172c2e, 0x3b119945, 0x3b0c0637, 0x3b067305, 0x3b00dfaf,
+ 0x3afb4c34, 0x3af5b894,
+ 0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,
+ 0x3aceab40, 0x3ac9167e,
+ 0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,
+ 0x3aa2013a, 0x3a9c6b57,
+ 0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,
+ 0x3a754e2a, 0x3a6fb726,
+ 0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,
+ 0x3a489216, 0x3a42f9f2,
+ 0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,
+ 0x3a1bcd05, 0x3a1633c1,
+ 0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,
+ 0x39eefefe, 0x39e9649c,
+ 0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,
+ 0x39c22808, 0x39bc8c89,
+ 0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,
+ 0x39954829, 0x398fab8e,
+ 0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,
+ 0x39685f6a, 0x3962c1b2,
+ 0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,
+ 0x393b6dd0, 0x3935cefd,
+ 0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,
+ 0x390e7362, 0x3908d376,
+ 0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,
+ 0x38e17028, 0x38dbcf23,
+ 0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,
+ 0x38b46429, 0x38aec20b,
+ 0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,
+ 0x38874f6b, 0x3881ac36,
+ 0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,
+ 0x385a31f5, 0x38548daa,
+ 0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,
+ 0x382d0bce, 0x3827666d,
+ 0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,
+ 0x37ffdcfe, 0x37fa3688,
+ 0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,
+ 0x37d2a58b, 0x37ccfe02,
+ 0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,
+ 0x37a5657c, 0x379fbce0,
+ 0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,
+ 0x37781cd9, 0x3772732a,
+ 0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,
+ 0x374acba7, 0x374520e7,
+ 0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,
+ 0x371d71ef, 0x3717c61f,
+ 0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,
+ 0x36f00fb7, 0x36ea62d7,
+ 0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,
+ 0x36c2a506, 0x36bcf718,
+ 0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,
+ 0x369531e3, 0x368f82e7,
+ 0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,
+ 0x3667b655, 0x3662064c,
+ 0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,
+ 0x363a3264, 0x3634814f,
+ 0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,
+ 0x360ca615, 0x3606f3f5,
+ 0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,
+ 0x35df1171, 0x35d95e47,
+ 0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,
+ 0x35b1747e, 0x35abc04b,
+ 0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,
+ 0x3583cf44, 0x357e1a08,
+ 0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,
+ 0x355621c9, 0x35506b85,
+ 0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,
+ 0x35286c14, 0x3522b4c9,
+ 0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,
+ 0x34faae2c, 0x34f4f5dc,
+ 0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,
+ 0x34cce819, 0x34c72ec4,
+ 0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,
+ 0x349f19e2, 0x34995f88,
+ 0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,
+ 0x3471438d, 0x346b8830,
+ 0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,
+ 0x34436521, 0x343da8c3,
+ 0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,
+ 0x34157ea7, 0x340fc147,
+ 0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,
+ 0x33e79024, 0x33e1d1c4,
+ 0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,
+ 0x33b999a0, 0x33b3da40,
+ 0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,
+ 0x338b9b22, 0x3385dac4,
+ 0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,
+ 0x335d94b2, 0x3357d355,
+ 0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,
+ 0x332f8655, 0x3329c3fb,
+ 0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,
+ 0x33017014, 0x32fbacbe,
+ 0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,
+ 0x32d351f5, 0x32cd8da4,
+ 0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,
+ 0x32a52bff, 0x329f66b4,
+ 0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,
+ 0x3276fe3a, 0x327137f6,
+ 0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,
+ 0x3248c8ad, 0x32430170,
+ 0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,
+ 0x321a8b5f, 0x3214c32a,
+ 0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,
+ 0x31ec4657, 0x31e67d2b,
+ 0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,
+ 0x31bdf99b, 0x31b82f7a,
+ 0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,
+ 0x318fa535, 0x3189da1e,
+ 0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,
+ 0x31614929, 0x315b7d1e,
+ 0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,
+ 0x3132e580, 0x312d1882,
+ 0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,
+ 0x31047a41, 0x30feac51,
+ 0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,
+ 0x30d60772, 0x30d03891,
+ 0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,
+ 0x30a78d1c, 0x30a1bd4a,
+ 0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,
+ 0x30790b45, 0x30733a83,
+ 0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,
+ 0x304a81f4, 0x3044b044,
+ 0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,
+ 0x301bf131, 0x30161e93,
+ 0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,
+ 0x2fed5902, 0x2fe78577,
+ 0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,
+ 0x2fbeb970, 0x2fb8e4f9,
+ 0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,
+ 0x2f901280, 0x2f8a3d1e,
+ 0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,
+ 0x2f61643b, 0x2f5b8def,
+ 0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,
+ 0x2f32aea8, 0x2f2cd772,
+ 0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,
+ 0x2f03f1cd, 0x2efe19ae,
+ 0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,
+ 0x2ed52db1, 0x2ecf54ac,
+ 0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,
+ 0x2ea6625d, 0x2ea08871,
+ 0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,
+ 0x2e778fd8, 0x2e71b506,
+ 0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,
+ 0x2e48b628, 0x2e42da71,
+ 0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,
+ 0x2e19d554, 0x2e13f8ba,
+ 0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,
+ 0x2deaed65, 0x2de50fe8,
+ 0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,
+ 0x2dbbfe61, 0x2db62001,
+ 0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,
+ 0x2d8d084f, 0x2d87290f,
+ 0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,
+ 0x2d5e0b38, 0x2d582b17,
+ 0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,
+ 0x2d2f0721, 0x2d292620,
+ 0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,
+ 0x2cfffc12, 0x2cfa1a33,
+ 0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,
+ 0x2cd0ea13, 0x2ccb0756,
+ 0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,
+ 0x2ca1d12a, 0x2c9bed91,
+ 0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,
+ 0x2c72b160, 0x2c6ccceb,
+ 0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,
+ 0x2c438abb, 0x2c3da56b,
+ 0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,
+ 0x2c145d42, 0x2c0e7719,
+ 0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,
+ 0x2be528fd, 0x2bdf41fb,
+ 0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,
+ 0x2bb5edf4, 0x2bb00619,
+ 0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,
+ 0x2b86ac2c, 0x2b80c37a,
+ 0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,
+ 0x2b5763ae, 0x2b517a26,
+ 0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,
+ 0x2b281482, 0x2b222a24,
+ 0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,
+ 0x2af8bead, 0x2af2d37b,
+ 0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,
+ 0x2ac96238, 0x2ac37633,
+ 0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,
+ 0x2a99ff2a, 0x2a941252,
+ 0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,
+ 0x2a6a958a, 0x2a64a7e0,
+ 0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,
+ 0x2a3b2560, 0x2a3536e5,
+ 0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,
+ 0x2a0baeb2, 0x2a05bf67,
+ 0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,
+ 0x29dc3188, 0x29d6416f,
+ 0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,
+ 0x29acadea, 0x29a6bd02,
+ 0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,
+ 0x297d23df, 0x2977322a,
+ 0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,
+ 0x294d936d, 0x2947a0ec,
+ 0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,
+ 0x291dfc9d, 0x29180951,
+ 0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,
+ 0x28ee5f76, 0x28e86b5f,
+ 0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,
+ 0x28bebbff, 0x28b8c71f,
+ 0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,
+ 0x288f123f, 0x28891c97,
+ 0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,
+ 0x285f623f, 0x28596bce,
+ 0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,
+ 0x282fac04, 0x2829b4cd,
+ 0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,
+ 0x27ffef97, 0x27f9f79a,
+ 0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,
+ 0x27d02cff, 0x27ca343d,
+ 0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,
+ 0x27a06443, 0x279a6abd,
+ 0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,
+ 0x2770956a, 0x276a9b21,
+ 0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,
+ 0x2740c07d, 0x273ac572,
+ 0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,
+ 0x2710e582, 0x270ae9b6,
+ 0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,
+ 0x26e10480, 0x26db07f4,
+ 0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,
+ 0x26b11d80, 0x26ab2034,
+ 0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,
+ 0x26813088, 0x267b327e,
+ 0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,
+ 0x26513da1, 0x264b3ed9,
+ 0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,
+ 0x262144d0, 0x261b454c,
+ 0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,
+ 0x25f1461e, 0x25eb45de,
+ 0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,
+ 0x25c14192, 0x25bb4098,
+ 0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,
+ 0x25913734, 0x258b3580,
+ 0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,
+ 0x2561270b, 0x255b249e,
+ 0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,
+ 0x2531111e, 0x252b0df9,
+ 0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,
+ 0x2500f574, 0x24faf198,
+ 0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,
+ 0x24d0d416, 0x24cacf84,
+ 0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,
+ 0x24a0ad0b, 0x249aa7c4,
+ 0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,
+ 0x24708059, 0x246a7a5e,
+ 0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,
+ 0x24404e09, 0x243a475a,
+ 0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,
+ 0x24101622, 0x240a0ec1,
+ 0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,
+ 0x23dfd8ab, 0x23d9d098,
+ 0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,
+ 0x23af95ac, 0x23a98ce8,
+ 0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,
+ 0x237f4d2b, 0x237943b9,
+ 0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,
+ 0x234eff32, 0x2348f511,
+ 0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,
+ 0x231eabc7, 0x2318a0f8,
+ 0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,
+ 0x22ee52f1, 0x22e84775,
+ 0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,
+ 0x22bdf4b8, 0x22b7e890,
+ 0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,
+ 0x228d9123, 0x22878451,
+ 0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,
+ 0x225d283b, 0x22571abe,
+ 0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,
+ 0x222cba06, 0x2226abe0,
+ 0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,
+ 0x21fc468b, 0x21f637be,
+ 0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,
+ 0x21cbcdd3, 0x21c5be5e,
+ 0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,
+ 0x219b4fe5, 0x21953fca,
+ 0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,
+ 0x216accc8, 0x2164bc08,
+ 0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,
+ 0x213a4484, 0x2134331f,
+ 0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,
+ 0x2109b720, 0x2103a518,
+ 0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,
+ 0x20d924a4, 0x20d311f9,
+ 0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,
+ 0x20a88d17, 0x20a279ca,
+ 0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,
+ 0x2077f080, 0x2071dc93,
+ 0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,
+ 0x20474ee8, 0x20413a5b,
+ 0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,
+ 0x2016a856, 0x2010932a,
+ 0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,
+ 0x1fe5fcd0, 0x1fdfe707,
+ 0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,
+ 0x1fb54c60, 0x1faf35f9,
+ 0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,
+ 0x1f84970b, 0x1f7e8009,
+ 0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,
+ 0x1f53dcdb, 0x1f4dc53d,
+ 0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,
+ 0x1f231dd5, 0x1f1d059e,
+ 0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,
+ 0x1ef25a03, 0x1eec4132,
+ 0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,
+ 0x1ec1916a, 0x1ebb7802,
+ 0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,
+ 0x1e90c414, 0x1e8aaa14,
+ 0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,
+ 0x1e5ff206, 0x1e59d770,
+ 0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,
+ 0x1e2f1b4a, 0x1e29001e,
+ 0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,
+ 0x1dfe3fe6, 0x1df82426,
+ 0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,
+ 0x1dcd5fe2, 0x1dc7438e,
+ 0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,
+ 0x1d9c7b45, 0x1d965e5f,
+ 0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,
+ 0x1d6b9217, 0x1d6574a0,
+ 0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,
+ 0x1d3aa460, 0x1d348658,
+ 0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,
+ 0x1d09b227, 0x1d03938f,
+ 0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,
+ 0x1cd8bb74, 0x1cd29c4d,
+ 0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,
+ 0x1ca7c04d, 0x1ca1a099,
+ 0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,
+ 0x1c76c0bc, 0x1c70a07b,
+ 0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,
+ 0x1c45bcc7, 0x1c3f9bf9,
+ 0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,
+ 0x1c14b475, 0x1c0e931d,
+ 0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,
+ 0x1be3a7cf, 0x1bdd85ed,
+ 0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,
+ 0x1bb296dc, 0x1bac7471,
+ 0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,
+ 0x1b8181a4, 0x1b7b5eb0,
+ 0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,
+ 0x1b50682e, 0x1b4a44b3,
+ 0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,
+ 0x1b1f4a81, 0x1b192680,
+ 0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,
+ 0x1aee28a6, 0x1ae8041f,
+ 0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,
+ 0x1abd02a3, 0x1ab6dd98,
+ 0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,
+ 0x1a8bd881, 0x1a85b2f3,
+ 0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,
+ 0x1a5aaa47, 0x1a548436,
+ 0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,
+ 0x1a2977fc, 0x1a23516a,
+ 0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,
+ 0x19f841a9, 0x19f21a96,
+ 0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,
+ 0x19c70754, 0x19c0dfc2,
+ 0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,
+ 0x1995c906, 0x198fa0f5,
+ 0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,
+ 0x196486c6, 0x195e5e37,
+ 0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,
+ 0x1933409b, 0x192d178f,
+ 0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,
+ 0x1901f68d, 0x18fbcd06,
+ 0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,
+ 0x18d0a8a4, 0x18ca7ea2,
+ 0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,
+ 0x189f56e8, 0x18992c6b,
+ 0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,
+ 0x186e015f, 0x1867d66a,
+ 0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,
+ 0x183ca812, 0x18367ca5,
+ 0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,
+ 0x180b4b08, 0x18051f24,
+ 0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,
+ 0x17d9ea49, 0x17d3bdee,
+ 0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,
+ 0x17a885dc, 0x17a2590d,
+ 0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,
+ 0x17771dc9, 0x1770f086,
+ 0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,
+ 0x1745b218, 0x173f8461,
+ 0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,
+ 0x171442d0, 0x170e14a7,
+ 0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,
+ 0x16e2cff9, 0x16dca15f,
+ 0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,
+ 0x16b1599b, 0x16ab2a90,
+ 0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,
+ 0x167fdfbc, 0x1679b042,
+ 0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,
+ 0x164e6266, 0x1648327d,
+ 0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,
+ 0x161ce19e, 0x1616b148,
+ 0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,
+ 0x15eb5d6e, 0x15e52cab,
+ 0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,
+ 0x15b9d5dd, 0x15b3a4ae,
+ 0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,
+ 0x15884af1, 0x15821958,
+ 0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,
+ 0x1556bcb4, 0x15508ab1,
+ 0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,
+ 0x15252b2c, 0x151ef8c0,
+ 0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,
+ 0x14f39662, 0x14ed638e,
+ 0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,
+ 0x14c1fe5c, 0x14bbcb22,
+ 0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,
+ 0x14906323, 0x148a2f82,
+ 0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,
+ 0x145ec4be, 0x145890b9,
+ 0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,
+ 0x142d2335, 0x1426eecb,
+ 0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,
+ 0x13fb7e8f, 0x13f549c3,
+ 0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,
+ 0x13c9d6d4, 0x13c3a1a6,
+ 0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,
+ 0x13982c0d, 0x1391f67d,
+ 0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,
+ 0x13667e3f, 0x13604850,
+ 0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,
+ 0x1334cd74, 0x132e9725,
+ 0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,
+ 0x130319b3, 0x12fce305,
+ 0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,
+ 0x12d16303, 0x12cb2bf8,
+ 0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,
+ 0x129fa96c, 0x12997205,
+ 0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,
+ 0x126decf5, 0x1267b533,
+ 0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,
+ 0x123c2da8, 0x1235f58b,
+ 0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,
+ 0x120a6b8a, 0x12043314,
+ 0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,
+ 0x11d8a6a4, 0x11d26dd6,
+ 0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,
+ 0x11a6defe, 0x11a0a5d8,
+ 0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,
+ 0x1175149e, 0x116edb22,
+ 0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,
+ 0x1143478e, 0x113d0dbc,
+ 0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,
+ 0x111177d4, 0x110b3dad,
+ 0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,
+ 0x10dfa578, 0x10d96afe,
+ 0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,
+ 0x10add082, 0x10a795b5,
+ 0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,
+ 0x107bf8fa, 0x1075bddb,
+ 0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,
+ 0x104a1ee7, 0x1043e377,
+ 0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,
+ 0x10184251, 0x10120691,
+ 0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,
+ 0xfe6633f, 0xfe02730,
+ 0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,
+ 0xfae455d,
+ 0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,
+ 0xf7c611f,
+ 0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,
+ 0xf4a7a7d,
+ 0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,
+ 0xf189180,
+ 0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,
+ 0xee6a62f,
+ 0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,
+ 0xeb4b891,
+ 0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,
+ 0xe82c8af,
+ 0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,
+ 0xe50d690,
+ 0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,
+ 0xe1ee23c,
+ 0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,
+ 0xdecebba,
+ 0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,
+ 0xdbaf313,
+ 0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,
+ 0xd88f84d,
+ 0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,
+ 0xd56fb71,
+ 0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,
+ 0xd24fc87,
+ 0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,
+ 0xcf2fb96,
+ 0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,
+ 0xcc0f8a5,
+ 0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,
+ 0xc8ef3bd,
+ 0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,
+ 0xc5cece5,
+ 0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,
+ 0xc2ae425,
+ 0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,
+ 0xbf8d985,
+ 0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,
+ 0xbc6cd0c,
+ 0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,
+ 0xb94bec2,
+ 0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,
+ 0xb62aeaf,
+ 0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,
+ 0xb309cdb,
+ 0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,
+ 0xafe894d,
+ 0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,
+ 0xacc740c,
+ 0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,
+ 0xa9a5d22,
+ 0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,
+ 0xa684495,
+ 0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,
+ 0xa362a6d,
+ 0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,
+ 0xa040eb1,
+ 0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,
+ 0x9d1f16b,
+ 0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,
+ 0x99fd2a0,
+ 0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,
+ 0x96db25a,
+ 0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,
+ 0x93b90a0,
+ 0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,
+ 0x9096d79,
+ 0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,
+ 0x8d748ed,
+ 0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,
+ 0x8a52304,
+ 0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,
+ 0x872fbc6,
+ 0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,
+ 0x840d33b,
+ 0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,
+ 0x80ea969,
+ 0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,
+ 0x7dc7e5a,
+ 0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,
+ 0x7aa5214,
+ 0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,
+ 0x77824a0,
+ 0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,
+ 0x745f604,
+ 0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,
+ 0x713c64a,
+ 0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,
+ 0x6e19578,
+ 0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,
+ 0x6af6396,
+ 0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,
+ 0x67d30ad,
+ 0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,
+ 0x64afcc3,
+ 0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,
+ 0x618c7e1,
+ 0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,
+ 0x5e6920e,
+ 0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,
+ 0x5b45b53,
+ 0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,
+ 0x58223b6,
+ 0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,
+ 0x54feb3f,
+ 0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,
+ 0x51db1f7,
+ 0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,
+ 0x4eb77e5,
+ 0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,
+ 0x4b93d11,
+ 0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,
+ 0x4870182,
+ 0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,
+ 0x454c541,
+ 0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,
+ 0x4228854,
+ 0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,
+ 0x3f04ac4,
+ 0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,
+ 0x3be0c99,
+ 0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,
+ 0x38bcdda,
+ 0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,
+ 0x3598e8f,
+ 0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,
+ 0x3274ec0,
+ 0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,
+ 0x2f50e74,
+ 0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,
+ 0x2c2cdb4,
+ 0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,
+ 0x2908c87,
+ 0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,
+ 0x25e4af4,
+ 0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,
+ 0x22c0904,
+ 0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,
+ 0x1f9c6be,
+ 0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,
+ 0x1c7842a,
+ 0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,
+ 0x1954150,
+ 0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,
+ 0x162fe37,
+ 0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,
+ 0x130bae7,
+ 0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,
+ 0xfe7769,
+ 0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,
+ 0xcc33c3,
+ 0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,
+ 0x99effe,
+ 0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,
+ 0x67ac21,
+ 0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,
+ 0x356835,
+ 0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,
+
+};
+
+/**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ31Table.gif
+ */
+
+arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+ (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ q31_t *pCosFactor[4] =
+ { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+ (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT Function */
+ arm_rfft_init_q31(S->pRfft, S->N, 0, 1);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,394 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_q15.c
+*
+* Description: Processing function of DCT4 & IDCT4 Q15.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ15Table.gif
+ */
+
+void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer)
+{
+ uint32_t i; /* Loop counter */
+ q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ q15_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+ arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = (uint32_t) S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.13 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+ arm_shift_q15(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = ((uint32_t) S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = ((uint32_t) S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = (uint32_t) S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.13 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+ arm_shift_q15(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter */
+ i = ((uint32_t) S->N - 1u);
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_q31.c
+*
+* Description: Processing function of DCT4 & IDCT4 Q31.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ * \par Input an output formats:
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,
+ * as the conversion from DCT2 to DCT4 involves one subtraction.
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ31Table.gif
+ */
+
+void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer)
+{
+ uint16_t i; /* Loop counter */
+ q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ q31_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+ arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.29 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+ arm_shift_q31(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = (S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = (S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.29 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+ arm_shift_q31(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* Initializing the loop counter */
+ i = (S->N - 1u);
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,329 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_f32.c
+*
+* Description: RFFT & RIFFT Floating point process function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/*--------------------------------------------------------------------
+ * Internal functions prototypes
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed
+ * in the future.
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst)
+{
+ const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+ /* Calculation of Real IFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+ /* Complex radix-4 IFFT process */
+ arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+ S_CFFT->pTwiddle,
+ S_CFFT->twidCoefModifier,
+ S_CFFT->onebyfftLen);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+
+ /* Calculation of RFFT of input */
+
+ /* Complex radix-4 FFT process */
+ arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+ S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+
+ /* Real FFT core process */
+ arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+/**
+ * @} end of RealFFT group
+ */
+
+/**
+ * @brief Core Real FFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ float32_t outR, outI; /* Temporary variables for output */
+ float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u]; /* temp pointers for output buffer */
+ float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u]; /* temp pointers for input buffer */
+
+ /* Init coefficient pointers */
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ i = fftLen - 1u;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+ /* read pATable[2 * i] */
+ CoefA1 = *pCoefA++;
+ /* pATable[2 * i + 1] */
+ CoefA2 = *pCoefA;
+
+ /* pSrc[2 * i] * pATable[2 * i] */
+ outR = *pSrc1 * CoefA1;
+ /* pSrc[2 * i] * CoefA2 */
+ outI = *pSrc1++ * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR -= (*pSrc1 + *pSrc2) * CoefA2;
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += *pSrc1++ * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI -= *pSrc2 * CoefA2;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2-- * CoefB1;
+
+ /* write output */
+ *pDst1++ = outR;
+ *pDst1++ = outI;
+
+ /* write complex conjugate output */
+ *pDst2-- = -outI;
+ *pDst2-- = outR;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ i--;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0.0f;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0.0f;
+
+}
+
+
+/**
+ * @brief Core Real IFFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ float32_t outR, outI; /* Temporary variables for output */
+ float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ while(fftLen > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+ */
+
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pSrc[2 * i] * CoefA1 */
+ outR = *pSrc1 * CoefA1;
+
+ /* - pSrc[2 * i] * CoefA2 */
+ outI = -(*pSrc1++) * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += (*pSrc1++) * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2 * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI += *pSrc2-- * CoefA2;
+
+ /* write output */
+ *pDst++ = outR;
+ *pDst++ = outI;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ /* Decrement loop count */
+ fftLen--;
+ }
+
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_f32.c
+*
+* Description: RFFT & RIFFT Floating point process function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void stage_rfft_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b; /* temporary variables */
+ float32_t p0, p1, p2, p3; /* temporary variables */
+
+
+ k = (S->Sint).fftLen - 1;
+
+ /* Pack first and last sample of the frequency domain together */
+
+ xBR = pB[0];
+ xBI = pB[1];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++ ;
+ twI = *pCoeff++ ;
+
+ // U1 = XA(1) + XB(1); % It is real
+ t1a = xBR + xAR ;
+
+ // U2 = XB(1) - XA(1); % It is imaginary
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ *pOut++ = 0.5f * ( t1a + t1b );
+ *pOut++ = 0.5f * ( t1a - t1b );
+
+ // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) ));
+ pB = p + 2*k;
+ pA += 2;
+
+ do
+ {
+ /*
+ function X = my_split_rfft(X, ifftFlag)
+ % X is a series of real numbers
+ L = length(X);
+ XC = X(1:2:end) +i*X(2:2:end);
+ XA = fft(XC);
+ XB = conj(XA([1 end:-1:2]));
+ TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
+ for l = 2:L/2
+ XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
+ end
+ XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
+ X = XA;
+ */
+
+ xBI = pB[1];
+ xBR = pB[0];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xBR - xAR ;
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ p0 = twR * t1a;
+ p1 = twI * t1a;
+ p2 = twR * t1b;
+ p3 = twI * t1b;
+
+ *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ } while(k > 0u);
+}
+
+/* Prepares data for inverse cfft */
+void merge_rfft_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b, r, s, t, u; /* temporary variables */
+
+ k = (S->Sint).fftLen - 1;
+
+ xAR = pA[0];
+ xAI = pA[1];
+
+ pCoeff += 2 ;
+
+ *pOut++ = 0.5f * ( xAR + xAI );
+ *pOut++ = 0.5f * ( xAR - xAI );
+
+ pB = p + 2*k ;
+ pA += 2 ;
+
+ while(k > 0u)
+ {
+ /* G is half of the frequency complex spectrum */
+ //for k = 2:N
+ // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
+ xBI = pB[1] ;
+ xBR = pB[0] ;
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xAR - xBR ;
+ t1b = xAI + xBI ;
+
+ r = twR * t1a;
+ s = twI * t1b;
+ t = twI * t1a;
+ u = twR * t1b;
+
+ // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
+ // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
+ *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ }
+
+}
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+ * @defgroup Fast Real FFT Functions
+ *
+ * \par
+ * The CMSIS DSP library includes specialized algorithms for computing the
+ * FFT of real data sequences. The FFT is defined over complex data but
+ * in many applications the input is real. Real FFT algorithms take advantage
+ * of the symmetry properties of the FFT and have a speed advantage over complex
+ * algorithms of the same length.
+ * \par
+ * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
+ * \par
+ * The real length N forward FFT of a sequence is computed using the steps shown below.
+ * \par
+ * \image html RFFT.gif "Real Fast Fourier Transform"
+ * \par
+ * The real sequence is initially treated as if it were complex to perform a CFFT.
+ * Later, a processing stage reshapes the data to obtain half of the frequency spectrum
+ * in complex format. Except the first complex number that contains the two real numbers
+ * X[0] and X[N/2] all the data is complex. In other words, the first complex sample
+ * contains two real values packed.
+ * \par
+ * The input for the inverse RFFT should keep the same format as the output of the
+ * forward RFFT. A first processing stage pre-process the data to later perform an
+ * inverse CFFT.
+ * \par
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"
+ * \par
+ * The algorithms for floating-point, Q15, and Q31 data are slightly different
+ * and we describe each algorithm in turn.
+ * \par Floating-point
+ * The main functions are arm_rfft_fast_f32()
+ * and arm_rfft_fast_init_f32(). The older functions
+ * arm_rfft_f32() and arm_rfft_init_f32() have been
+ * deprecated but are still documented.
+ * \par
+ * The FFT of a real N-point sequence has even symmetry in the frequency
+ * domain. The second half of the data equals the conjugate of the first half
+ * flipped in frequency:
+ *
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ *X[fftLen/2+1] - conjugate of X[fftLen/2-1]
+ *X[fftLen/2+2] - conjugate of X[fftLen/2-2]
+ *...
+ *X[fftLen-1] - conjugate of X[1]
+ *
+ * Looking at the data, we see that we can uniquely represent the FFT using only
+ *
+ *N/2+1 samples:
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ *
+ * Looking more closely we see that the first and last samples are real valued.
+ * They can be packed together and we can thus represent the FFT of an N-point
+ * real sequence by N/2 complex values:
+ *
+ *X[0],X[N/2] - packed real data: X[0] + jX[N/2]
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ *
+ * The real FFT functions pack the frequency domain data in this fashion. The
+ * forward transform outputs the data in this form and the inverse transform
+ * expects input data in this form. The function always performs the needed
+ * bitreversal so that the input and output data is always in normal order. The
+ * functions support lengths of [32, 64, 128, ..., 4096] samples.
+ * \par
+ * The forward and inverse real FFT functions apply the standard FFT scaling; no
+ * scaling on the forward transform and 1/fftLen scaling on the inverse
+ * transform.
+ * \par Q15 and Q31
+ * The real algorithms are defined in a similar manner and utilize N/2 complex
+ * transforms behind the scenes.
+ * \par
+ * The complex transforms used internally include scaling to prevent fixed-point
+ * overflows. The overall scaling equals 1/(fftLen/2).
+ * \par
+ * A separate instance structure must be defined for each transform used but
+ * twiddle factor and bit reversal tables can be reused.
+ * \par
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes twiddle factor table and bit reversal table pointers.
+ * - Initializes the internal complex FFT data structure.
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure
+ * cannot be placed into a const data section. To place an instance structure
+ * into a const data section, the instance structure should be manually
+ * initialized as follows:
+ *
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ *
+ * where fftLenReal is the length of the real transform;
+ * fftLenBy2 length of the internal complex transform.
+ * ifftFlagR Selects forward (=0) or inverse (=1) transform.
+ * bitReverseFlagR Selects bit reversed output (=0) or normal order
+ * output (=1).
+ * twidCoefRModifier stride modifier for the twiddle factor table.
+ * The value is based on the FFT length;
+ * pTwiddleARealpoints to the A array of twiddle coefficients;
+ * pTwiddleBRealpoints to the B array of twiddle coefficients;
+ * pCfft points to the CFFT Instance structure. The CFFT structure
+ * must also be initialized. Refer to arm_cfft_radix4_f32() for details regarding
+ * static initialization of the complex FFT instance structure.
+ */
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point real FFT.
+* @param[in] *S points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] *p points to the input buffer.
+* @param[in] *pOut points to the output buffer.
+* @param[in] ifftFlag RFFT if flag is 0, RIFFT if flag is 1
+* @return none.
+*/
+
+void arm_rfft_fast_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut,
+uint8_t ifftFlag)
+{
+ arm_cfft_instance_f32 * Sint = &(S->Sint);
+ Sint->fftLen = S->fftLenRFFT / 2;
+
+ /* Calculation of Real FFT */
+ if(ifftFlag)
+ {
+ /* Real FFT compression */
+ merge_rfft_f32(S, p, pOut);
+
+ /* Complex radix-4 IFFT process */
+ arm_cfft_f32( Sint, pOut, ifftFlag, 1);
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+ arm_cfft_f32( Sint, p, ifftFlag, 1);
+
+ /* Real FFT extraction */
+ stage_rfft_f32(S, p, pOut);
+ }
+}
+
+/**
+* @} end of RealFFT group
+*/
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_init_f32.c
+*
+* Description: Split Radix Decimation in Frequency CFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point real FFT.
+* @param[in,out] *S points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] fftLen length of the Real Sequence.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLen Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_rfft_fast_init_f32(
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen)
+{
+ arm_cfft_instance_f32 * Sint;
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ Sint = &(S->Sint);
+ Sint->fftLen = fftLen/2;
+ S->fftLenRFFT = fftLen;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (Sint->fftLen)
+ {
+ case 2048u:
+ /* Initializations of structure parameters for 2048 point FFT */
+ /* Initialise the bit reversal table length */
+ Sint->bitRevLength = ARMBITREVINDEXTABLE2048_TABLE_LENGTH;
+ /* Initialise the bit reversal table pointer */
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
+ /* Initialise the Twiddle coefficient pointers */
+ Sint->pTwiddle = (float32_t *) twiddleCoef_2048;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096;
+ break;
+ case 1024u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE1024_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_1024;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048;
+ break;
+ case 512u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_512;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024;
+ break;
+ case 256u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_256;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512;
+ break;
+ case 128u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_128;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256;
+ break;
+ case 64u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__64_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_64;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128;
+ break;
+ case 32u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__32_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_32;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64;
+ break;
+ case 16u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__16_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_16;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32;
+ break;
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of RealFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,8376 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_f32.c
+*
+* Description: RFFT & RIFFT Floating point initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* \par
+* Generation of realCoefA array:
+* \par
+* n = 4096
+* for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }
+*/
+
+
+
+static const float32_t realCoefA[8192] = {
+ 0.500000000000000f, -0.500000000000000f, 0.499616503715515f,
+ -0.499999850988388f,
+ 0.499233007431030f, -0.499999403953552f, 0.498849511146545f,
+ -0.499998688697815f,
+ 0.498466014862061f, -0.499997645616531f, 0.498082518577576f,
+ -0.499996334314346f,
+ 0.497699022293091f, -0.499994695186615f, 0.497315555810928f,
+ -0.499992787837982f,
+ 0.496932059526443f, -0.499990582466125f, 0.496548563241959f,
+ -0.499988079071045f,
+ 0.496165096759796f, -0.499985307455063f, 0.495781600475311f,
+ -0.499982208013535f,
+ 0.495398133993149f, -0.499978810548782f, 0.495014637708664f,
+ -0.499975144863129f,
+ 0.494631171226501f, -0.499971181154251f, 0.494247704744339f,
+ -0.499966919422150f,
+ 0.493864238262177f, -0.499962359666824f, 0.493480771780014f,
+ -0.499957501888275f,
+ 0.493097305297852f, -0.499952346086502f, 0.492713838815689f,
+ -0.499946922063828f,
+ 0.492330402135849f, -0.499941170215607f, 0.491946935653687f,
+ -0.499935150146484f,
+ 0.491563498973846f, -0.499928832054138f, 0.491180062294006f,
+ -0.499922215938568f,
+ 0.490796625614166f, -0.499915301799774f, 0.490413218736649f,
+ -0.499908089637756f,
+ 0.490029782056808f, -0.499900579452515f, 0.489646375179291f,
+ -0.499892801046371f,
+ 0.489262968301773f, -0.499884694814682f, 0.488879561424255f,
+ -0.499876320362091f,
+ 0.488496154546738f, -0.499867647886276f, 0.488112777471542f,
+ -0.499858677387238f,
+ 0.487729400396347f, -0.499849408864975f, 0.487346023321152f,
+ -0.499839842319489f,
+ 0.486962646245956f, -0.499830007553101f, 0.486579269170761f,
+ -0.499819844961166f,
+ 0.486195921897888f, -0.499809414148331f, 0.485812574625015f,
+ -0.499798685312271f,
+ 0.485429257154465f, -0.499787658452988f, 0.485045909881592f,
+ -0.499776333570480f,
+ 0.484662592411041f, -0.499764710664749f, 0.484279274940491f,
+ -0.499752789735794f,
+ 0.483895987272263f, -0.499740600585938f, 0.483512699604034f,
+ -0.499728083610535f,
+ 0.483129411935806f, -0.499715298414230f, 0.482746154069901f,
+ -0.499702215194702f,
+ 0.482362866401672f, -0.499688833951950f, 0.481979638338089f,
+ -0.499675154685974f,
+ 0.481596380472183f, -0.499661177396774f, 0.481213152408600f,
+ -0.499646931886673f,
+ 0.480829954147339f, -0.499632388353348f, 0.480446726083755f,
+ -0.499617516994476f,
+ 0.480063527822495f, -0.499602377414703f, 0.479680359363556f,
+ -0.499586939811707f,
+ 0.479297190904617f, -0.499571204185486f, 0.478914022445679f,
+ -0.499555170536041f,
+ 0.478530883789063f, -0.499538868665695f, 0.478147745132446f,
+ -0.499522238969803f,
+ 0.477764606475830f, -0.499505341053009f, 0.477381497621536f,
+ -0.499488145112991f,
+ 0.476998418569565f, -0.499470651149750f, 0.476615339517593f,
+ -0.499452859163284f,
+ 0.476232260465622f, -0.499434769153595f, 0.475849211215973f,
+ -0.499416410923004f,
+ 0.475466161966324f, -0.499397724866867f, 0.475083142518997f,
+ -0.499378770589828f,
+ 0.474700123071671f, -0.499359518289566f, 0.474317133426666f,
+ -0.499339967966080f,
+ 0.473934143781662f, -0.499320119619370f, 0.473551183938980f,
+ -0.499299973249435f,
+ 0.473168224096298f, -0.499279528856277f, 0.472785294055939f,
+ -0.499258816242218f,
+ 0.472402364015579f, -0.499237775802612f, 0.472019463777542f,
+ -0.499216467142105f,
+ 0.471636593341827f, -0.499194860458374f, 0.471253722906113f,
+ -0.499172955751419f,
+ 0.470870882272720f, -0.499150782823563f, 0.470488041639328f,
+ -0.499128282070160f,
+ 0.470105201005936f, -0.499105513095856f, 0.469722419977188f,
+ -0.499082416296005f,
+ 0.469339638948441f, -0.499059051275253f, 0.468956857919693f,
+ -0.499035388231277f,
+ 0.468574106693268f, -0.499011427164078f, 0.468191385269165f,
+ -0.498987197875977f,
+ 0.467808693647385f, -0.498962640762329f, 0.467426002025604f,
+ -0.498937815427780f,
+ 0.467043310403824f, -0.498912662267685f, 0.466660678386688f,
+ -0.498887240886688f,
+ 0.466278046369553f, -0.498861521482468f, 0.465895414352417f,
+ -0.498835533857346f,
+ 0.465512841939926f, -0.498809218406677f, 0.465130269527435f,
+ -0.498782604932785f,
+ 0.464747726917267f, -0.498755723237991f, 0.464365184307098f,
+ -0.498728543519974f,
+ 0.463982671499252f, -0.498701065778732f, 0.463600188493729f,
+ -0.498673290014267f,
+ 0.463217705488205f, -0.498645216226578f, 0.462835282087326f,
+ -0.498616874217987f,
+ 0.462452858686447f, -0.498588204383850f, 0.462070435285568f,
+ -0.498559266328812f,
+ 0.461688071489334f, -0.498530030250549f, 0.461305707693100f,
+ -0.498500496149063f,
+ 0.460923373699188f, -0.498470664024353f, 0.460541069507599f,
+ -0.498440563678741f,
+ 0.460158795118332f, -0.498410135507584f, 0.459776520729065f,
+ -0.498379439115524f,
+ 0.459394276142120f, -0.498348444700241f, 0.459012061357498f,
+ -0.498317152261734f,
+ 0.458629876375198f, -0.498285561800003f, 0.458247691392899f,
+ -0.498253703117371f,
+ 0.457865566015244f, -0.498221516609192f, 0.457483440637589f,
+ -0.498189061880112f,
+ 0.457101345062256f, -0.498156309127808f, 0.456719279289246f,
+ -0.498123258352280f,
+ 0.456337243318558f, -0.498089909553528f, 0.455955207347870f,
+ -0.498056292533875f,
+ 0.455573230981827f, -0.498022347688675f, 0.455191254615784f,
+ -0.497988134622574f,
+ 0.454809308052063f, -0.497953623533249f, 0.454427421092987f,
+ -0.497918814420700f,
+ 0.454045534133911f, -0.497883707284927f, 0.453663676977158f,
+ -0.497848302125931f,
+ 0.453281819820404f, -0.497812628746033f, 0.452900022268295f,
+ -0.497776657342911f,
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+ 0.492963016033173f,
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+ 0.493342459201813f,
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+ 0.493466645479202f,
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+ 0.493589639663696f,
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+ 0.493711471557617f,
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+ 0.493832170963287f,
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+ 0.493951678276062f,
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+ 0.494531840085983f,
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+ 0.494755744934082f,
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+ 0.494865983724594f,
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+ 0.494975030422211f,
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+ 0.495082914829254f,
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+ 0.495189607143402f,
+ 0.431189924478531f, 0.495242536067963f, 0.431569814682007f,
+ 0.495295166969299f,
+ 0.431949704885483f, 0.495347499847412f, 0.432329654693604f,
+ 0.495399564504623f,
+ 0.432709634304047f, 0.495451331138611f, 0.433089673519135f,
+ 0.495502769947052f,
+ 0.433469742536545f, 0.495553970336914f, 0.433849841356277f,
+ 0.495604842901230f,
+ 0.434229999780655f, 0.495655417442322f, 0.434610158205032f,
+ 0.495705723762512f,
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+ 0.495805442333221f,
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+ 0.496001392602921f,
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+ 0.496097624301910f,
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+ 0.496192663908005f,
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+ 0.496286571025848f,
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+ 0.496379286050797f,
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+ 0.496470838785172f,
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+ 0.496561229228973f,
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+ 0.496738493442535f,
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+ 0.496825367212296f,
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+ 0.496911078691483f,
+ 0.444888889789581f, 0.496953487396240f, 0.445270061492920f,
+ 0.496995598077774f,
+ 0.445651292800903f, 0.497037440538406f, 0.446032524108887f,
+ 0.497078984975815f,
+ 0.446413785219193f, 0.497120231389999f, 0.446795076131821f,
+ 0.497161179780960f,
+ 0.447176426649094f, 0.497201830148697f, 0.447557777166367f,
+ 0.497242212295532f,
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+ 0.497322082519531f,
+ 0.448702067136765f, 0.497361570596695f, 0.449083566665649f,
+ 0.497400760650635f,
+ 0.449465066194534f, 0.497439652681351f, 0.449846625328064f,
+ 0.497478276491165f,
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+ 0.497554630041122f,
+ 0.450991421937943f, 0.497592359781265f, 0.451373100280762f,
+ 0.497629791498184f,
+ 0.451754778623581f, 0.497666954994202f, 0.452136516571045f,
+ 0.497703820466995f,
+ 0.452518254518509f, 0.497740387916565f, 0.452900022268295f,
+ 0.497776657342911f,
+ 0.453281819820404f, 0.497812628746033f, 0.453663676977158f,
+ 0.497848302125931f,
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+ 0.497918814420700f,
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+ 0.497988134622574f,
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+ 0.498056292533875f,
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+ 0.498123258352280f,
+ 0.457101345062256f, 0.498156309127808f, 0.457483440637589f,
+ 0.498189061880112f,
+ 0.457865566015244f, 0.498221516609192f, 0.458247691392899f,
+ 0.498253703117371f,
+ 0.458629876375198f, 0.498285561800003f, 0.459012061357498f,
+ 0.498317152261734f,
+ 0.459394276142120f, 0.498348444700241f, 0.459776520729065f,
+ 0.498379439115524f,
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+ 0.498440563678741f,
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+ 0.498500496149063f,
+ 0.461688071489334f, 0.498530030250549f, 0.462070435285568f,
+ 0.498559266328812f,
+ 0.462452858686447f, 0.498588204383850f, 0.462835282087326f,
+ 0.498616874217987f,
+ 0.463217705488205f, 0.498645216226578f, 0.463600188493729f,
+ 0.498673290014267f,
+ 0.463982671499252f, 0.498701065778732f, 0.464365184307098f,
+ 0.498728543519974f,
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+ 0.498782604932785f,
+ 0.465512841939926f, 0.498809218406677f, 0.465895414352417f,
+ 0.498835533857346f,
+ 0.466278046369553f, 0.498861521482468f, 0.466660678386688f,
+ 0.498887240886688f,
+ 0.467043310403824f, 0.498912662267685f, 0.467426002025604f,
+ 0.498937815427780f,
+ 0.467808693647385f, 0.498962640762329f, 0.468191385269165f,
+ 0.498987197875977f,
+ 0.468574106693268f, 0.499011427164078f, 0.468956857919693f,
+ 0.499035388231277f,
+ 0.469339638948441f, 0.499059051275253f, 0.469722419977188f,
+ 0.499082416296005f,
+ 0.470105201005936f, 0.499105513095856f, 0.470488041639328f,
+ 0.499128282070160f,
+ 0.470870882272720f, 0.499150782823563f, 0.471253722906113f,
+ 0.499172955751419f,
+ 0.471636593341827f, 0.499194860458374f, 0.472019463777542f,
+ 0.499216467142105f,
+ 0.472402364015579f, 0.499237775802612f, 0.472785294055939f,
+ 0.499258816242218f,
+ 0.473168224096298f, 0.499279528856277f, 0.473551183938980f,
+ 0.499299973249435f,
+ 0.473934143781662f, 0.499320119619370f, 0.474317133426666f,
+ 0.499339967966080f,
+ 0.474700123071671f, 0.499359518289566f, 0.475083142518997f,
+ 0.499378770589828f,
+ 0.475466161966324f, 0.499397724866867f, 0.475849211215973f,
+ 0.499416410923004f,
+ 0.476232260465622f, 0.499434769153595f, 0.476615339517593f,
+ 0.499452859163284f,
+ 0.476998418569565f, 0.499470651149750f, 0.477381497621536f,
+ 0.499488145112991f,
+ 0.477764606475830f, 0.499505341053009f, 0.478147745132446f,
+ 0.499522238969803f,
+ 0.478530883789063f, 0.499538868665695f, 0.478914022445679f,
+ 0.499555170536041f,
+ 0.479297190904617f, 0.499571204185486f, 0.479680359363556f,
+ 0.499586939811707f,
+ 0.480063527822495f, 0.499602377414703f, 0.480446726083755f,
+ 0.499617516994476f,
+ 0.480829954147339f, 0.499632388353348f, 0.481213152408600f,
+ 0.499646931886673f,
+ 0.481596380472183f, 0.499661177396774f, 0.481979638338089f,
+ 0.499675154685974f,
+ 0.482362866401672f, 0.499688833951950f, 0.482746154069901f,
+ 0.499702215194702f,
+ 0.483129411935806f, 0.499715298414230f, 0.483512699604034f,
+ 0.499728083610535f,
+ 0.483895987272263f, 0.499740600585938f, 0.484279274940491f,
+ 0.499752789735794f,
+ 0.484662592411041f, 0.499764710664749f, 0.485045909881592f,
+ 0.499776333570480f,
+ 0.485429257154465f, 0.499787658452988f, 0.485812574625015f,
+ 0.499798685312271f,
+ 0.486195921897888f, 0.499809414148331f, 0.486579269170761f,
+ 0.499819844961166f,
+ 0.486962646245956f, 0.499830007553101f, 0.487346023321152f,
+ 0.499839842319489f,
+ 0.487729400396347f, 0.499849408864975f, 0.488112777471542f,
+ 0.499858677387238f,
+ 0.488496154546738f, 0.499867647886276f, 0.488879561424255f,
+ 0.499876320362091f,
+ 0.489262968301773f, 0.499884694814682f, 0.489646375179291f,
+ 0.499892801046371f,
+ 0.490029782056808f, 0.499900579452515f, 0.490413218736649f,
+ 0.499908089637756f,
+ 0.490796625614166f, 0.499915301799774f, 0.491180062294006f,
+ 0.499922215938568f,
+ 0.491563498973846f, 0.499928832054138f, 0.491946935653687f,
+ 0.499935150146484f,
+ 0.492330402135849f, 0.499941170215607f, 0.492713838815689f,
+ 0.499946922063828f,
+ 0.493097305297852f, 0.499952346086502f, 0.493480771780014f,
+ 0.499957501888275f,
+ 0.493864238262177f, 0.499962359666824f, 0.494247704744339f,
+ 0.499966919422150f,
+ 0.494631171226501f, 0.499971181154251f, 0.495014637708664f,
+ 0.499975144863129f,
+ 0.495398133993149f, 0.499978810548782f, 0.495781600475311f,
+ 0.499982208013535f,
+ 0.496165096759796f, 0.499985307455063f, 0.496548563241959f,
+ 0.499988079071045f,
+ 0.496932059526443f, 0.499990582466125f, 0.497315555810928f,
+ 0.499992787837982f,
+ 0.497699022293091f, 0.499994695186615f, 0.498082518577576f,
+ 0.499996334314346f,
+ 0.498466014862061f, 0.499997645616531f, 0.498849511146545f,
+ 0.499998688697815f,
+ 0.499233007431030f, 0.499999403953552f, 0.499616503715515f,
+ 0.499999850988388f,
+};
+
+
+/**
+* \par
+* Generation of realCoefB array:
+* \par
+* n = 4096
+* for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }
+*
+*/
+static const float32_t realCoefB[8192] = {
+ 0.500000000000000f, 0.500000000000000f, 0.500383496284485f,
+ 0.499999850988388f,
+ 0.500766992568970f, 0.499999403953552f, 0.501150488853455f,
+ 0.499998688697815f,
+ 0.501533985137939f, 0.499997645616531f, 0.501917481422424f,
+ 0.499996334314346f,
+ 0.502300977706909f, 0.499994695186615f, 0.502684473991394f,
+ 0.499992787837982f,
+ 0.503067970275879f, 0.499990582466125f, 0.503451406955719f,
+ 0.499988079071045f,
+ 0.503834903240204f, 0.499985307455063f, 0.504218399524689f,
+ 0.499982208013535f,
+ 0.504601895809174f, 0.499978810548782f, 0.504985332489014f,
+ 0.499975144863129f,
+ 0.505368828773499f, 0.499971181154251f, 0.505752325057983f,
+ 0.499966919422150f,
+ 0.506135761737823f, 0.499962359666824f, 0.506519258022308f,
+ 0.499957501888275f,
+ 0.506902694702148f, 0.499952346086502f, 0.507286131381989f,
+ 0.499946922063828f,
+ 0.507669627666473f, 0.499941170215607f, 0.508053064346313f,
+ 0.499935150146484f,
+ 0.508436501026154f, 0.499928832054138f, 0.508819937705994f,
+ 0.499922215938568f,
+ 0.509203374385834f, 0.499915301799774f, 0.509586811065674f,
+ 0.499908089637756f,
+ 0.509970188140869f, 0.499900579452515f, 0.510353624820709f,
+ 0.499892801046371f,
+ 0.510737061500549f, 0.499884694814682f, 0.511120438575745f,
+ 0.499876320362091f,
+ 0.511503815650940f, 0.499867647886276f, 0.511887252330780f,
+ 0.499858677387238f,
+ 0.512270629405975f, 0.499849408864975f, 0.512654006481171f,
+ 0.499839842319489f,
+ 0.513037383556366f, 0.499830007553101f, 0.513420701026917f,
+ 0.499819844961166f,
+ 0.513804078102112f, 0.499809414148331f, 0.514187395572662f,
+ 0.499798685312271f,
+ 0.514570772647858f, 0.499787658452988f, 0.514954090118408f,
+ 0.499776333570480f,
+ 0.515337407588959f, 0.499764710664749f, 0.515720725059509f,
+ 0.499752789735794f,
+ 0.516103982925415f, 0.499740600585938f, 0.516487300395966f,
+ 0.499728083610535f,
+ 0.516870558261871f, 0.499715298414230f, 0.517253875732422f,
+ 0.499702215194702f,
+ 0.517637133598328f, 0.499688833951950f, 0.518020391464233f,
+ 0.499675154685974f,
+ 0.518403589725494f, 0.499661177396774f, 0.518786847591400f,
+ 0.499646931886673f,
+ 0.519170045852661f, 0.499632388353348f, 0.519553244113922f,
+ 0.499617516994476f,
+ 0.519936442375183f, 0.499602377414703f, 0.520319640636444f,
+ 0.499586939811707f,
+ 0.520702838897705f, 0.499571204185486f, 0.521085977554321f,
+ 0.499555170536041f,
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+ 0.514570772647858f, -0.499787658452988f, 0.514187395572662f,
+ -0.499798685312271f,
+ 0.513804078102112f, -0.499809414148331f, 0.513420701026917f,
+ -0.499819844961166f,
+ 0.513037383556366f, -0.499830007553101f, 0.512654006481171f,
+ -0.499839842319489f,
+ 0.512270629405975f, -0.499849408864975f, 0.511887252330780f,
+ -0.499858677387238f,
+ 0.511503815650940f, -0.499867647886276f, 0.511120438575745f,
+ -0.499876320362091f,
+ 0.510737061500549f, -0.499884694814682f, 0.510353624820709f,
+ -0.499892801046371f,
+ 0.509970188140869f, -0.499900579452515f, 0.509586811065674f,
+ -0.499908089637756f,
+ 0.509203374385834f, -0.499915301799774f, 0.508819937705994f,
+ -0.499922215938568f,
+ 0.508436501026154f, -0.499928832054138f, 0.508053064346313f,
+ -0.499935150146484f,
+ 0.507669627666473f, -0.499941170215607f, 0.507286131381989f,
+ -0.499946922063828f,
+ 0.506902694702148f, -0.499952346086502f, 0.506519258022308f,
+ -0.499957501888275f,
+ 0.506135761737823f, -0.499962359666824f, 0.505752325057983f,
+ -0.499966919422150f,
+ 0.505368828773499f, -0.499971181154251f, 0.504985332489014f,
+ -0.499975144863129f,
+ 0.504601895809174f, -0.499978810548782f, 0.504218399524689f,
+ -0.499982208013535f,
+ 0.503834903240204f, -0.499985307455063f, 0.503451406955719f,
+ -0.499988079071045f,
+ 0.503067970275879f, -0.499990582466125f, 0.502684473991394f,
+ -0.499992787837982f,
+ 0.502300977706909f, -0.499994695186615f, 0.501917481422424f,
+ -0.499996334314346f,
+ 0.501533985137939f, -0.499997645616531f, 0.501150488853455f,
+ -0.499998688697815f,
+ 0.500766992568970f, -0.499999403953552f, 0.500383496284485f,
+ -0.499999850988388f,
+};
+
+
+
+/**
+* @brief Initialization function for the floating-point RFFT/RIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
+* @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (float32_t *) realCoefA;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (float32_t *) realCoefB;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ /* Init table modifier value */
+ case 8192u:
+ S->twidCoefRModifier = 1u;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if(S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,2235 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_q15.c
+*
+* Description: RFFT & RIFFT Q15 initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_const_structs.h"
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+
+
+/**
+* \par
+* Generation fixed-point realCoefAQ15 array in Q15 format:
+* \par
+* n = 4096
+* for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }
+* \par
+* Convert to fixed point Q15 format
+* round(pATable[i] * pow(2, 15))
+*/
+static const q15_t ALIGN4 realCoefAQ15[8192] = {
+ 0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,
+ 0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,
+ 0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,
+ 0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,
+ 0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,
+ 0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,
+ 0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,
+ 0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,
+ 0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,
+ 0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,
+ 0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,
+ 0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,
+ 0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,
+ 0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,
+ 0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,
+ 0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,
+ 0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,
+ 0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,
+ 0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,
+ 0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,
+ 0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,
+ 0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,
+ 0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,
+ 0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,
+ 0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,
+ 0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,
+ 0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,
+ 0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,
+ 0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,
+ 0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,
+ 0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,
+ 0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,
+ 0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,
+ 0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,
+ 0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,
+ 0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,
+ 0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,
+ 0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,
+ 0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,
+ 0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,
+ 0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,
+ 0x37f9, 0xc081, 0x37ec, 0xc083, 0x37e0, 0xc085, 0x37d3, 0xc086,
+ 0x37c7, 0xc088, 0x37ba, 0xc089, 0x37ae, 0xc08b, 0x37a1, 0xc08d,
+ 0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,
+ 0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,
+ 0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,
+ 0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,
+ 0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,
+ 0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,
+ 0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,
+ 0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,
+ 0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,
+ 0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,
+ 0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,
+ 0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,
+ 0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,
+ 0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,
+ 0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,
+ 0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,
+ 0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,
+ 0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,
+ 0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,
+ 0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,
+ 0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,
+ 0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,
+ 0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,
+ 0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,
+ 0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,
+ 0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,
+ 0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,
+ 0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,
+ 0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,
+ 0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,
+ 0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,
+ 0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,
+ 0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,
+ 0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,
+ 0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,
+ 0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,
+ 0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,
+ 0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,
+ 0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,
+ 0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,
+ 0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,
+ 0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,
+ 0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,
+ 0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,
+ 0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,
+ 0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,
+ 0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,
+ 0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,
+ 0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,
+ 0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,
+ 0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,
+ 0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,
+ 0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,
+ 0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,
+ 0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,
+ 0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,
+ 0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,
+ 0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,
+ 0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,
+ 0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,
+ 0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,
+ 0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,
+ 0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,
+ 0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,
+ 0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,
+ 0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,
+ 0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,
+ 0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,
+ 0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,
+ 0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,
+ 0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,
+ 0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,
+ 0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,
+ 0x29b4, 0xc403, 0x29a8, 0xc407, 0x299c, 0xc40b, 0x2990, 0xc410,
+ 0x2984, 0xc414, 0x2979, 0xc419, 0x296d, 0xc41d, 0x2961, 0xc422,
+ 0x2955, 0xc426, 0x294a, 0xc42a, 0x293e, 0xc42f, 0x2932, 0xc433,
+ 0x2926, 0xc438, 0x291b, 0xc43c, 0x290f, 0xc441, 0x2903, 0xc445,
+ 0x28f7, 0xc44a, 0x28ec, 0xc44e, 0x28e0, 0xc453, 0x28d4, 0xc457,
+ 0x28c9, 0xc45c, 0x28bd, 0xc461, 0x28b1, 0xc465, 0x28a5, 0xc46a,
+ 0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,
+ 0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,
+ 0x283c, 0xc493, 0x2831, 0xc498, 0x2825, 0xc49d, 0x2819, 0xc4a1,
+ 0x280e, 0xc4a6, 0x2802, 0xc4ab, 0x27f6, 0xc4b0, 0x27eb, 0xc4b4,
+ 0x27df, 0xc4b9, 0x27d3, 0xc4be, 0x27c8, 0xc4c2, 0x27bc, 0xc4c7,
+ 0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,
+ 0x2782, 0xc4df, 0x2777, 0xc4e4, 0x276b, 0xc4e9, 0x275f, 0xc4ee,
+ 0x2754, 0xc4f2, 0x2748, 0xc4f7, 0x273d, 0xc4fc, 0x2731, 0xc501,
+ 0x2725, 0xc506, 0x271a, 0xc50b, 0x270e, 0xc510, 0x2703, 0xc515,
+ 0x26f7, 0xc51a, 0x26ec, 0xc51e, 0x26e0, 0xc523, 0x26d4, 0xc528,
+ 0x26c9, 0xc52d, 0x26bd, 0xc532, 0x26b2, 0xc537, 0x26a6, 0xc53c,
+ 0x269b, 0xc541, 0x268f, 0xc546, 0x2684, 0xc54b, 0x2678, 0xc550,
+ 0x266d, 0xc555, 0x2661, 0xc55a, 0x2656, 0xc55f, 0x264a, 0xc564,
+ 0x263f, 0xc569, 0x2633, 0xc56e, 0x2628, 0xc573, 0x261c, 0xc578,
+ 0x2611, 0xc57e, 0x2605, 0xc583, 0x25fa, 0xc588, 0x25ee, 0xc58d,
+ 0x25e3, 0xc592, 0x25d7, 0xc597, 0x25cc, 0xc59c, 0x25c0, 0xc5a1,
+ 0x25b5, 0xc5a7, 0x25a9, 0xc5ac, 0x259e, 0xc5b1, 0x2592, 0xc5b6,
+ 0x2587, 0xc5bb, 0x257c, 0xc5c1, 0x2570, 0xc5c6, 0x2565, 0xc5cb,
+ 0x2559, 0xc5d0, 0x254e, 0xc5d5, 0x2542, 0xc5db, 0x2537, 0xc5e0,
+ 0x252c, 0xc5e5, 0x2520, 0xc5ea, 0x2515, 0xc5f0, 0x2509, 0xc5f5,
+ 0x24fe, 0xc5fa, 0x24f3, 0xc600, 0x24e7, 0xc605, 0x24dc, 0xc60a,
+ 0x24d0, 0xc610, 0x24c5, 0xc615, 0x24ba, 0xc61a, 0x24ae, 0xc620,
+ 0x24a3, 0xc625, 0x2498, 0xc62a, 0x248c, 0xc630, 0x2481, 0xc635,
+ 0x2476, 0xc63b, 0x246a, 0xc640, 0x245f, 0xc645, 0x2454, 0xc64b,
+ 0x2448, 0xc650, 0x243d, 0xc656, 0x2432, 0xc65b, 0x2426, 0xc661,
+ 0x241b, 0xc666, 0x2410, 0xc66c, 0x2404, 0xc671, 0x23f9, 0xc677,
+ 0x23ee, 0xc67c, 0x23e2, 0xc682, 0x23d7, 0xc687, 0x23cc, 0xc68d,
+ 0x23c1, 0xc692, 0x23b5, 0xc698, 0x23aa, 0xc69d, 0x239f, 0xc6a3,
+ 0x2394, 0xc6a8, 0x2388, 0xc6ae, 0x237d, 0xc6b4, 0x2372, 0xc6b9,
+ 0x2367, 0xc6bf, 0x235b, 0xc6c5, 0x2350, 0xc6ca, 0x2345, 0xc6d0,
+ 0x233a, 0xc6d5, 0x232e, 0xc6db, 0x2323, 0xc6e1, 0x2318, 0xc6e6,
+ 0x230d, 0xc6ec, 0x2301, 0xc6f2, 0x22f6, 0xc6f7, 0x22eb, 0xc6fd,
+ 0x22e0, 0xc703, 0x22d5, 0xc709, 0x22ca, 0xc70e, 0x22be, 0xc714,
+ 0x22b3, 0xc71a, 0x22a8, 0xc720, 0x229d, 0xc725, 0x2292, 0xc72b,
+ 0x2287, 0xc731, 0x227b, 0xc737, 0x2270, 0xc73d, 0x2265, 0xc742,
+ 0x225a, 0xc748, 0x224f, 0xc74e, 0x2244, 0xc754, 0x2239, 0xc75a,
+ 0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,
+ 0x2201, 0xc777, 0x21f6, 0xc77d, 0x21eb, 0xc783, 0x21e0, 0xc789,
+ 0x21d5, 0xc78f, 0x21ca, 0xc795, 0x21be, 0xc79a, 0x21b3, 0xc7a0,
+ 0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,
+ 0x217c, 0xc7be, 0x2171, 0xc7c4, 0x2166, 0xc7ca, 0x215b, 0xc7d0,
+ 0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,
+ 0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,
+ 0x20f8, 0xc807, 0x20ed, 0xc80d, 0x20e2, 0xc813, 0x20d7, 0xc819,
+ 0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,
+ 0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,
+ 0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,
+ 0x2049, 0xc869, 0x203e, 0xc870, 0x2033, 0xc876, 0x2028, 0xc87c,
+ 0x201d, 0xc882, 0x2012, 0xc889, 0x2007, 0xc88f, 0x1ffc, 0xc895,
+ 0x1ff1, 0xc89b, 0x1fe7, 0xc8a2, 0x1fdc, 0xc8a8, 0x1fd1, 0xc8ae,
+ 0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,
+ 0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,
+ 0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,
+ 0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,
+ 0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,
+ 0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,
+ 0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,
+ 0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,
+ 0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,
+ 0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,
+ 0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,
+ 0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,
+ 0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,
+ 0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,
+ 0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,
+ 0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,
+ 0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,
+ 0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,
+ 0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,
+ 0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,
+ 0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,
+ 0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,
+ 0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,
+ 0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,
+ 0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,
+ 0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,
+ 0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,
+ 0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,
+ 0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,
+ 0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,
+ 0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,
+ 0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,
+ 0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,
+ 0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,
+ 0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,
+ 0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,
+ 0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,
+ 0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,
+ 0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,
+ 0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,
+ 0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,
+ 0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,
+ 0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,
+ 0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,
+ 0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,
+ 0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,
+ 0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,
+ 0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,
+ 0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,
+ 0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,
+ 0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,
+ 0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,
+ 0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,
+ 0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,
+ 0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,
+ 0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,
+ 0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,
+ 0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,
+ 0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,
+ 0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,
+ 0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,
+ 0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,
+ 0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,
+ 0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,
+ 0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,
+ 0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,
+ 0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,
+ 0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,
+ 0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,
+ 0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,
+ 0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,
+ 0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,
+ 0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,
+ 0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,
+ 0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,
+ 0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,
+ 0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,
+ 0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,
+ 0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,
+ 0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,
+ 0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,
+ 0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,
+ 0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,
+ 0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,
+ 0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,
+ 0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,
+ 0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,
+ 0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,
+ 0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,
+ 0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,
+ 0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,
+ 0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,
+ 0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,
+ 0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,
+ 0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,
+ 0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,
+ 0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,
+ 0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,
+ 0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,
+ 0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,
+ 0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,
+ 0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,
+ 0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,
+ 0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,
+ 0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,
+ 0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,
+ 0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,
+ 0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,
+ 0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,
+ 0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,
+ 0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,
+ 0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,
+ 0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,
+ 0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,
+ 0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,
+ 0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,
+ 0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,
+ 0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,
+ 0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,
+ 0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,
+ 0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,
+ 0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,
+ 0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,
+ 0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,
+ 0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,
+ 0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,
+ 0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,
+ 0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,
+ 0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,
+ 0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,
+ 0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,
+ 0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,
+ 0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,
+ 0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,
+ 0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,
+ 0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,
+ 0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,
+ 0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,
+ 0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,
+ 0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,
+ 0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,
+ 0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,
+ 0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,
+ 0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,
+ 0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,
+ 0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,
+ 0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,
+ 0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,
+ 0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,
+ 0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,
+ 0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,
+ 0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,
+ 0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,
+ 0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,
+ 0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,
+ 0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,
+ 0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,
+ 0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,
+ 0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,
+ 0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,
+ 0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,
+ 0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,
+ 0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,
+ 0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,
+ 0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,
+ 0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,
+ 0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,
+ 0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,
+ 0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,
+ 0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,
+ 0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,
+ 0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,
+ 0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,
+ 0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,
+ 0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,
+ 0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,
+ 0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,
+ 0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,
+ 0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,
+ 0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,
+ 0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,
+ 0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,
+ 0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,
+ 0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,
+ 0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,
+ 0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,
+ 0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,
+ 0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 0xe32e,
+ 0x6d5, 0xe33a, 0x6d0, 0xe345, 0x6ca, 0xe350, 0x6c5, 0xe35b,
+ 0x6bf, 0xe367, 0x6b9, 0xe372, 0x6b4, 0xe37d, 0x6ae, 0xe388,
+ 0x6a8, 0xe394, 0x6a3, 0xe39f, 0x69d, 0xe3aa, 0x698, 0xe3b5,
+ 0x692, 0xe3c1, 0x68d, 0xe3cc, 0x687, 0xe3d7, 0x682, 0xe3e2,
+ 0x67c, 0xe3ee, 0x677, 0xe3f9, 0x671, 0xe404, 0x66c, 0xe410,
+ 0x666, 0xe41b, 0x661, 0xe426, 0x65b, 0xe432, 0x656, 0xe43d,
+ 0x650, 0xe448, 0x64b, 0xe454, 0x645, 0xe45f, 0x640, 0xe46a,
+ 0x63b, 0xe476, 0x635, 0xe481, 0x630, 0xe48c, 0x62a, 0xe498,
+ 0x625, 0xe4a3, 0x620, 0xe4ae, 0x61a, 0xe4ba, 0x615, 0xe4c5,
+ 0x610, 0xe4d0, 0x60a, 0xe4dc, 0x605, 0xe4e7, 0x600, 0xe4f3,
+ 0x5fa, 0xe4fe, 0x5f5, 0xe509, 0x5f0, 0xe515, 0x5ea, 0xe520,
+ 0x5e5, 0xe52c, 0x5e0, 0xe537, 0x5db, 0xe542, 0x5d5, 0xe54e,
+ 0x5d0, 0xe559, 0x5cb, 0xe565, 0x5c6, 0xe570, 0x5c1, 0xe57c,
+ 0x5bb, 0xe587, 0x5b6, 0xe592, 0x5b1, 0xe59e, 0x5ac, 0xe5a9,
+ 0x5a7, 0xe5b5, 0x5a1, 0xe5c0, 0x59c, 0xe5cc, 0x597, 0xe5d7,
+ 0x592, 0xe5e3, 0x58d, 0xe5ee, 0x588, 0xe5fa, 0x583, 0xe605,
+ 0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,
+ 0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,
+ 0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,
+ 0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,
+ 0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,
+ 0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,
+ 0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,
+ 0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,
+ 0x4df, 0xe782, 0x4da, 0xe78e, 0x4d6, 0xe799, 0x4d1, 0xe7a5,
+ 0x4cc, 0xe7b1, 0x4c7, 0xe7bc, 0x4c2, 0xe7c8, 0x4be, 0xe7d3,
+ 0x4b9, 0xe7df, 0x4b4, 0xe7eb, 0x4b0, 0xe7f6, 0x4ab, 0xe802,
+ 0x4a6, 0xe80e, 0x4a1, 0xe819, 0x49d, 0xe825, 0x498, 0xe831,
+ 0x493, 0xe83c, 0x48f, 0xe848, 0x48a, 0xe854, 0x485, 0xe85f,
+ 0x481, 0xe86b, 0x47c, 0xe877, 0x478, 0xe882, 0x473, 0xe88e,
+ 0x46e, 0xe89a, 0x46a, 0xe8a5, 0x465, 0xe8b1, 0x461, 0xe8bd,
+ 0x45c, 0xe8c9, 0x457, 0xe8d4, 0x453, 0xe8e0, 0x44e, 0xe8ec,
+ 0x44a, 0xe8f7, 0x445, 0xe903, 0x441, 0xe90f, 0x43c, 0xe91b,
+ 0x438, 0xe926, 0x433, 0xe932, 0x42f, 0xe93e, 0x42a, 0xe94a,
+ 0x426, 0xe955, 0x422, 0xe961, 0x41d, 0xe96d, 0x419, 0xe979,
+ 0x414, 0xe984, 0x410, 0xe990, 0x40b, 0xe99c, 0x407, 0xe9a8,
+ 0x403, 0xe9b4, 0x3fe, 0xe9bf, 0x3fa, 0xe9cb, 0x3f6, 0xe9d7,
+ 0x3f1, 0xe9e3, 0x3ed, 0xe9ee, 0x3e9, 0xe9fa, 0x3e4, 0xea06,
+ 0x3e0, 0xea12, 0x3dc, 0xea1e, 0x3d7, 0xea29, 0x3d3, 0xea35,
+ 0x3cf, 0xea41, 0x3ca, 0xea4d, 0x3c6, 0xea59, 0x3c2, 0xea65,
+ 0x3be, 0xea70, 0x3ba, 0xea7c, 0x3b5, 0xea88, 0x3b1, 0xea94,
+ 0x3ad, 0xeaa0, 0x3a9, 0xeaac, 0x3a5, 0xeab7, 0x3a0, 0xeac3,
+ 0x39c, 0xeacf, 0x398, 0xeadb, 0x394, 0xeae7, 0x390, 0xeaf3,
+ 0x38c, 0xeaff, 0x387, 0xeb0a, 0x383, 0xeb16, 0x37f, 0xeb22,
+ 0x37b, 0xeb2e, 0x377, 0xeb3a, 0x373, 0xeb46, 0x36f, 0xeb52,
+ 0x36b, 0xeb5e, 0x367, 0xeb6a, 0x363, 0xeb75, 0x35f, 0xeb81,
+ 0x35b, 0xeb8d, 0x357, 0xeb99, 0x353, 0xeba5, 0x34f, 0xebb1,
+ 0x34b, 0xebbd, 0x347, 0xebc9, 0x343, 0xebd5, 0x33f, 0xebe1,
+ 0x33b, 0xebed, 0x337, 0xebf9, 0x333, 0xec05, 0x32f, 0xec10,
+ 0x32b, 0xec1c, 0x327, 0xec28, 0x323, 0xec34, 0x320, 0xec40,
+ 0x31c, 0xec4c, 0x318, 0xec58, 0x314, 0xec64, 0x310, 0xec70,
+ 0x30c, 0xec7c, 0x308, 0xec88, 0x305, 0xec94, 0x301, 0xeca0,
+ 0x2fd, 0xecac, 0x2f9, 0xecb8, 0x2f5, 0xecc4, 0x2f2, 0xecd0,
+ 0x2ee, 0xecdc, 0x2ea, 0xece8, 0x2e6, 0xecf4, 0x2e3, 0xed00,
+ 0x2df, 0xed0c, 0x2db, 0xed18, 0x2d8, 0xed24, 0x2d4, 0xed30,
+ 0x2d0, 0xed3c, 0x2cc, 0xed48, 0x2c9, 0xed54, 0x2c5, 0xed60,
+ 0x2c1, 0xed6c, 0x2be, 0xed78, 0x2ba, 0xed84, 0x2b7, 0xed90,
+ 0x2b3, 0xed9c, 0x2af, 0xeda8, 0x2ac, 0xedb4, 0x2a8, 0xedc0,
+ 0x2a5, 0xedcc, 0x2a1, 0xedd8, 0x29d, 0xede4, 0x29a, 0xedf0,
+ 0x296, 0xedfc, 0x293, 0xee09, 0x28f, 0xee15, 0x28c, 0xee21,
+ 0x288, 0xee2d, 0x285, 0xee39, 0x281, 0xee45, 0x27e, 0xee51,
+ 0x27a, 0xee5d, 0x277, 0xee69, 0x273, 0xee75, 0x270, 0xee81,
+ 0x26d, 0xee8d, 0x269, 0xee99, 0x266, 0xeea6, 0x262, 0xeeb2,
+ 0x25f, 0xeebe, 0x25c, 0xeeca, 0x258, 0xeed6, 0x255, 0xeee2,
+ 0x251, 0xeeee, 0x24e, 0xeefa, 0x24b, 0xef06, 0x247, 0xef13,
+ 0x244, 0xef1f, 0x241, 0xef2b, 0x23e, 0xef37, 0x23a, 0xef43,
+ 0x237, 0xef4f, 0x234, 0xef5b, 0x230, 0xef67, 0x22d, 0xef74,
+ 0x22a, 0xef80, 0x227, 0xef8c, 0x223, 0xef98, 0x220, 0xefa4,
+ 0x21d, 0xefb0, 0x21a, 0xefbc, 0x217, 0xefc9, 0x213, 0xefd5,
+ 0x210, 0xefe1, 0x20d, 0xefed, 0x20a, 0xeff9, 0x207, 0xf005,
+ 0x204, 0xf012, 0x201, 0xf01e, 0x1fd, 0xf02a, 0x1fa, 0xf036,
+ 0x1f7, 0xf042, 0x1f4, 0xf04e, 0x1f1, 0xf05b, 0x1ee, 0xf067,
+ 0x1eb, 0xf073, 0x1e8, 0xf07f, 0x1e5, 0xf08b, 0x1e2, 0xf098,
+ 0x1df, 0xf0a4, 0x1dc, 0xf0b0, 0x1d9, 0xf0bc, 0x1d6, 0xf0c8,
+ 0x1d3, 0xf0d5, 0x1d0, 0xf0e1, 0x1cd, 0xf0ed, 0x1ca, 0xf0f9,
+ 0x1c7, 0xf105, 0x1c4, 0xf112, 0x1c1, 0xf11e, 0x1be, 0xf12a,
+ 0x1bb, 0xf136, 0x1b8, 0xf143, 0x1b6, 0xf14f, 0x1b3, 0xf15b,
+ 0x1b0, 0xf167, 0x1ad, 0xf174, 0x1aa, 0xf180, 0x1a7, 0xf18c,
+ 0x1a4, 0xf198, 0x1a2, 0xf1a4, 0x19f, 0xf1b1, 0x19c, 0xf1bd,
+ 0x199, 0xf1c9, 0x196, 0xf1d5, 0x194, 0xf1e2, 0x191, 0xf1ee,
+ 0x18e, 0xf1fa, 0x18b, 0xf207, 0x189, 0xf213, 0x186, 0xf21f,
+ 0x183, 0xf22b, 0x180, 0xf238, 0x17e, 0xf244, 0x17b, 0xf250,
+ 0x178, 0xf25c, 0x176, 0xf269, 0x173, 0xf275, 0x170, 0xf281,
+ 0x16e, 0xf28e, 0x16b, 0xf29a, 0x168, 0xf2a6, 0x166, 0xf2b2,
+ 0x163, 0xf2bf, 0x161, 0xf2cb, 0x15e, 0xf2d7, 0x15b, 0xf2e4,
+ 0x159, 0xf2f0, 0x156, 0xf2fc, 0x154, 0xf308, 0x151, 0xf315,
+ 0x14f, 0xf321, 0x14c, 0xf32d, 0x14a, 0xf33a, 0x147, 0xf346,
+ 0x145, 0xf352, 0x142, 0xf35f, 0x140, 0xf36b, 0x13d, 0xf377,
+ 0x13b, 0xf384, 0x138, 0xf390, 0x136, 0xf39c, 0x134, 0xf3a9,
+ 0x131, 0xf3b5, 0x12f, 0xf3c1, 0x12c, 0xf3ce, 0x12a, 0xf3da,
+ 0x128, 0xf3e6, 0x125, 0xf3f3, 0x123, 0xf3ff, 0x120, 0xf40b,
+ 0x11e, 0xf418, 0x11c, 0xf424, 0x119, 0xf430, 0x117, 0xf43d,
+ 0x115, 0xf449, 0x113, 0xf455, 0x110, 0xf462, 0x10e, 0xf46e,
+ 0x10c, 0xf47b, 0x109, 0xf487, 0x107, 0xf493, 0x105, 0xf4a0,
+ 0x103, 0xf4ac, 0x100, 0xf4b8, 0xfe, 0xf4c5, 0xfc, 0xf4d1,
+ 0xfa, 0xf4dd, 0xf8, 0xf4ea, 0xf6, 0xf4f6, 0xf3, 0xf503,
+ 0xf1, 0xf50f, 0xef, 0xf51b, 0xed, 0xf528, 0xeb, 0xf534,
+ 0xe9, 0xf540, 0xe7, 0xf54d, 0xe4, 0xf559, 0xe2, 0xf566,
+ 0xe0, 0xf572, 0xde, 0xf57e, 0xdc, 0xf58b, 0xda, 0xf597,
+ 0xd8, 0xf5a4, 0xd6, 0xf5b0, 0xd4, 0xf5bc, 0xd2, 0xf5c9,
+ 0xd0, 0xf5d5, 0xce, 0xf5e2, 0xcc, 0xf5ee, 0xca, 0xf5fa,
+ 0xc8, 0xf607, 0xc6, 0xf613, 0xc4, 0xf620, 0xc2, 0xf62c,
+ 0xc0, 0xf639, 0xbe, 0xf645, 0xbd, 0xf651, 0xbb, 0xf65e,
+ 0xb9, 0xf66a, 0xb7, 0xf677, 0xb5, 0xf683, 0xb3, 0xf690,
+ 0xb1, 0xf69c, 0xaf, 0xf6a8, 0xae, 0xf6b5, 0xac, 0xf6c1,
+ 0xaa, 0xf6ce, 0xa8, 0xf6da, 0xa6, 0xf6e7, 0xa5, 0xf6f3,
+ 0xa3, 0xf6ff, 0xa1, 0xf70c, 0x9f, 0xf718, 0x9e, 0xf725,
+ 0x9c, 0xf731, 0x9a, 0xf73e, 0x98, 0xf74a, 0x97, 0xf757,
+ 0x95, 0xf763, 0x93, 0xf76f, 0x92, 0xf77c, 0x90, 0xf788,
+ 0x8e, 0xf795, 0x8d, 0xf7a1, 0x8b, 0xf7ae, 0x89, 0xf7ba,
+ 0x88, 0xf7c7, 0x86, 0xf7d3, 0x85, 0xf7e0, 0x83, 0xf7ec,
+ 0x81, 0xf7f9, 0x80, 0xf805, 0x7e, 0xf811, 0x7d, 0xf81e,
+ 0x7b, 0xf82a, 0x7a, 0xf837, 0x78, 0xf843, 0x77, 0xf850,
+ 0x75, 0xf85c, 0x74, 0xf869, 0x72, 0xf875, 0x71, 0xf882,
+ 0x6f, 0xf88e, 0x6e, 0xf89b, 0x6c, 0xf8a7, 0x6b, 0xf8b4,
+ 0x69, 0xf8c0, 0x68, 0xf8cd, 0x67, 0xf8d9, 0x65, 0xf8e6,
+ 0x64, 0xf8f2, 0x62, 0xf8ff, 0x61, 0xf90b, 0x60, 0xf918,
+ 0x5e, 0xf924, 0x5d, 0xf931, 0x5c, 0xf93d, 0x5a, 0xf94a,
+ 0x59, 0xf956, 0x58, 0xf963, 0x56, 0xf96f, 0x55, 0xf97c,
+ 0x54, 0xf988, 0x53, 0xf995, 0x51, 0xf9a1, 0x50, 0xf9ae,
+ 0x4f, 0xf9ba, 0x4e, 0xf9c7, 0x4c, 0xf9d3, 0x4b, 0xf9e0,
+ 0x4a, 0xf9ec, 0x49, 0xf9f9, 0x48, 0xfa05, 0x47, 0xfa12,
+ 0x45, 0xfa1e, 0x44, 0xfa2b, 0x43, 0xfa37, 0x42, 0xfa44,
+ 0x41, 0xfa50, 0x40, 0xfa5d, 0x3f, 0xfa69, 0x3d, 0xfa76,
+ 0x3c, 0xfa82, 0x3b, 0xfa8f, 0x3a, 0xfa9b, 0x39, 0xfaa8,
+ 0x38, 0xfab4, 0x37, 0xfac1, 0x36, 0xfacd, 0x35, 0xfada,
+ 0x34, 0xfae6, 0x33, 0xfaf3, 0x32, 0xfb00, 0x31, 0xfb0c,
+ 0x30, 0xfb19, 0x2f, 0xfb25, 0x2e, 0xfb32, 0x2d, 0xfb3e,
+ 0x2c, 0xfb4b, 0x2b, 0xfb57, 0x2b, 0xfb64, 0x2a, 0xfb70,
+ 0x29, 0xfb7d, 0x28, 0xfb89, 0x27, 0xfb96, 0x26, 0xfba2,
+ 0x25, 0xfbaf, 0x24, 0xfbbc, 0x24, 0xfbc8, 0x23, 0xfbd5,
+ 0x22, 0xfbe1, 0x21, 0xfbee, 0x20, 0xfbfa, 0x20, 0xfc07,
+ 0x1f, 0xfc13, 0x1e, 0xfc20, 0x1d, 0xfc2c, 0x1d, 0xfc39,
+ 0x1c, 0xfc45, 0x1b, 0xfc52, 0x1a, 0xfc5f, 0x1a, 0xfc6b,
+ 0x19, 0xfc78, 0x18, 0xfc84, 0x18, 0xfc91, 0x17, 0xfc9d,
+ 0x16, 0xfcaa, 0x16, 0xfcb6, 0x15, 0xfcc3, 0x14, 0xfcd0,
+ 0x14, 0xfcdc, 0x13, 0xfce9, 0x13, 0xfcf5, 0x12, 0xfd02,
+ 0x11, 0xfd0e, 0x11, 0xfd1b, 0x10, 0xfd27, 0x10, 0xfd34,
+ 0xf, 0xfd40, 0xf, 0xfd4d, 0xe, 0xfd5a, 0xe, 0xfd66,
+ 0xd, 0xfd73, 0xd, 0xfd7f, 0xc, 0xfd8c, 0xc, 0xfd98,
+ 0xb, 0xfda5, 0xb, 0xfdb2, 0xa, 0xfdbe, 0xa, 0xfdcb,
+ 0x9, 0xfdd7, 0x9, 0xfde4, 0x9, 0xfdf0, 0x8, 0xfdfd,
+ 0x8, 0xfe09, 0x7, 0xfe16, 0x7, 0xfe23, 0x7, 0xfe2f,
+ 0x6, 0xfe3c, 0x6, 0xfe48, 0x6, 0xfe55, 0x5, 0xfe61,
+ 0x5, 0xfe6e, 0x5, 0xfe7a, 0x4, 0xfe87, 0x4, 0xfe94,
+ 0x4, 0xfea0, 0x4, 0xfead, 0x3, 0xfeb9, 0x3, 0xfec6,
+ 0x3, 0xfed2, 0x3, 0xfedf, 0x2, 0xfeec, 0x2, 0xfef8,
+ 0x2, 0xff05, 0x2, 0xff11, 0x2, 0xff1e, 0x1, 0xff2a,
+ 0x1, 0xff37, 0x1, 0xff44, 0x1, 0xff50, 0x1, 0xff5d,
+ 0x1, 0xff69, 0x1, 0xff76, 0x0, 0xff82, 0x0, 0xff8f,
+ 0x0, 0xff9b, 0x0, 0xffa8, 0x0, 0xffb5, 0x0, 0xffc1,
+ 0x0, 0xffce, 0x0, 0xffda, 0x0, 0xffe7, 0x0, 0xfff3,
+ 0x0, 0x0, 0x0, 0xd, 0x0, 0x19, 0x0, 0x26,
+ 0x0, 0x32, 0x0, 0x3f, 0x0, 0x4b, 0x0, 0x58,
+ 0x0, 0x65, 0x0, 0x71, 0x0, 0x7e, 0x1, 0x8a,
+ 0x1, 0x97, 0x1, 0xa3, 0x1, 0xb0, 0x1, 0xbc,
+ 0x1, 0xc9, 0x1, 0xd6, 0x2, 0xe2, 0x2, 0xef,
+ 0x2, 0xfb, 0x2, 0x108, 0x2, 0x114, 0x3, 0x121,
+ 0x3, 0x12e, 0x3, 0x13a, 0x3, 0x147, 0x4, 0x153,
+ 0x4, 0x160, 0x4, 0x16c, 0x4, 0x179, 0x5, 0x186,
+ 0x5, 0x192, 0x5, 0x19f, 0x6, 0x1ab, 0x6, 0x1b8,
+ 0x6, 0x1c4, 0x7, 0x1d1, 0x7, 0x1dd, 0x7, 0x1ea,
+ 0x8, 0x1f7, 0x8, 0x203, 0x9, 0x210, 0x9, 0x21c,
+ 0x9, 0x229, 0xa, 0x235, 0xa, 0x242, 0xb, 0x24e,
+ 0xb, 0x25b, 0xc, 0x268, 0xc, 0x274, 0xd, 0x281,
+ 0xd, 0x28d, 0xe, 0x29a, 0xe, 0x2a6, 0xf, 0x2b3,
+ 0xf, 0x2c0, 0x10, 0x2cc, 0x10, 0x2d9, 0x11, 0x2e5,
+ 0x11, 0x2f2, 0x12, 0x2fe, 0x13, 0x30b, 0x13, 0x317,
+ 0x14, 0x324, 0x14, 0x330, 0x15, 0x33d, 0x16, 0x34a,
+ 0x16, 0x356, 0x17, 0x363, 0x18, 0x36f, 0x18, 0x37c,
+ 0x19, 0x388, 0x1a, 0x395, 0x1a, 0x3a1, 0x1b, 0x3ae,
+ 0x1c, 0x3bb, 0x1d, 0x3c7, 0x1d, 0x3d4, 0x1e, 0x3e0,
+ 0x1f, 0x3ed, 0x20, 0x3f9, 0x20, 0x406, 0x21, 0x412,
+ 0x22, 0x41f, 0x23, 0x42b, 0x24, 0x438, 0x24, 0x444,
+ 0x25, 0x451, 0x26, 0x45e, 0x27, 0x46a, 0x28, 0x477,
+ 0x29, 0x483, 0x2a, 0x490, 0x2b, 0x49c, 0x2b, 0x4a9,
+ 0x2c, 0x4b5, 0x2d, 0x4c2, 0x2e, 0x4ce, 0x2f, 0x4db,
+ 0x30, 0x4e7, 0x31, 0x4f4, 0x32, 0x500, 0x33, 0x50d,
+ 0x34, 0x51a, 0x35, 0x526, 0x36, 0x533, 0x37, 0x53f,
+ 0x38, 0x54c, 0x39, 0x558, 0x3a, 0x565, 0x3b, 0x571,
+ 0x3c, 0x57e, 0x3d, 0x58a, 0x3f, 0x597, 0x40, 0x5a3,
+ 0x41, 0x5b0, 0x42, 0x5bc, 0x43, 0x5c9, 0x44, 0x5d5,
+ 0x45, 0x5e2, 0x47, 0x5ee, 0x48, 0x5fb, 0x49, 0x607,
+ 0x4a, 0x614, 0x4b, 0x620, 0x4c, 0x62d, 0x4e, 0x639,
+ 0x4f, 0x646, 0x50, 0x652, 0x51, 0x65f, 0x53, 0x66b,
+ 0x54, 0x678, 0x55, 0x684, 0x56, 0x691, 0x58, 0x69d,
+ 0x59, 0x6aa, 0x5a, 0x6b6, 0x5c, 0x6c3, 0x5d, 0x6cf,
+ 0x5e, 0x6dc, 0x60, 0x6e8, 0x61, 0x6f5, 0x62, 0x701,
+ 0x64, 0x70e, 0x65, 0x71a, 0x67, 0x727, 0x68, 0x733,
+ 0x69, 0x740, 0x6b, 0x74c, 0x6c, 0x759, 0x6e, 0x765,
+ 0x6f, 0x772, 0x71, 0x77e, 0x72, 0x78b, 0x74, 0x797,
+ 0x75, 0x7a4, 0x77, 0x7b0, 0x78, 0x7bd, 0x7a, 0x7c9,
+ 0x7b, 0x7d6, 0x7d, 0x7e2, 0x7e, 0x7ef, 0x80, 0x7fb,
+ 0x81, 0x807, 0x83, 0x814, 0x85, 0x820, 0x86, 0x82d,
+ 0x88, 0x839, 0x89, 0x846, 0x8b, 0x852, 0x8d, 0x85f,
+ 0x8e, 0x86b, 0x90, 0x878, 0x92, 0x884, 0x93, 0x891,
+ 0x95, 0x89d, 0x97, 0x8a9, 0x98, 0x8b6, 0x9a, 0x8c2,
+ 0x9c, 0x8cf, 0x9e, 0x8db, 0x9f, 0x8e8, 0xa1, 0x8f4,
+ 0xa3, 0x901, 0xa5, 0x90d, 0xa6, 0x919, 0xa8, 0x926,
+ 0xaa, 0x932, 0xac, 0x93f, 0xae, 0x94b, 0xaf, 0x958,
+ 0xb1, 0x964, 0xb3, 0x970, 0xb5, 0x97d, 0xb7, 0x989,
+ 0xb9, 0x996, 0xbb, 0x9a2, 0xbd, 0x9af, 0xbe, 0x9bb,
+ 0xc0, 0x9c7, 0xc2, 0x9d4, 0xc4, 0x9e0, 0xc6, 0x9ed,
+ 0xc8, 0x9f9, 0xca, 0xa06, 0xcc, 0xa12, 0xce, 0xa1e,
+ 0xd0, 0xa2b, 0xd2, 0xa37, 0xd4, 0xa44, 0xd6, 0xa50,
+ 0xd8, 0xa5c, 0xda, 0xa69, 0xdc, 0xa75, 0xde, 0xa82,
+ 0xe0, 0xa8e, 0xe2, 0xa9a, 0xe4, 0xaa7, 0xe7, 0xab3,
+ 0xe9, 0xac0, 0xeb, 0xacc, 0xed, 0xad8, 0xef, 0xae5,
+ 0xf1, 0xaf1, 0xf3, 0xafd, 0xf6, 0xb0a, 0xf8, 0xb16,
+ 0xfa, 0xb23, 0xfc, 0xb2f, 0xfe, 0xb3b, 0x100, 0xb48,
+ 0x103, 0xb54, 0x105, 0xb60, 0x107, 0xb6d, 0x109, 0xb79,
+ 0x10c, 0xb85, 0x10e, 0xb92, 0x110, 0xb9e, 0x113, 0xbab,
+ 0x115, 0xbb7, 0x117, 0xbc3, 0x119, 0xbd0, 0x11c, 0xbdc,
+ 0x11e, 0xbe8, 0x120, 0xbf5, 0x123, 0xc01, 0x125, 0xc0d,
+ 0x128, 0xc1a, 0x12a, 0xc26, 0x12c, 0xc32, 0x12f, 0xc3f,
+ 0x131, 0xc4b, 0x134, 0xc57, 0x136, 0xc64, 0x138, 0xc70,
+ 0x13b, 0xc7c, 0x13d, 0xc89, 0x140, 0xc95, 0x142, 0xca1,
+ 0x145, 0xcae, 0x147, 0xcba, 0x14a, 0xcc6, 0x14c, 0xcd3,
+ 0x14f, 0xcdf, 0x151, 0xceb, 0x154, 0xcf8, 0x156, 0xd04,
+ 0x159, 0xd10, 0x15b, 0xd1c, 0x15e, 0xd29, 0x161, 0xd35,
+ 0x163, 0xd41, 0x166, 0xd4e, 0x168, 0xd5a, 0x16b, 0xd66,
+ 0x16e, 0xd72, 0x170, 0xd7f, 0x173, 0xd8b, 0x176, 0xd97,
+ 0x178, 0xda4, 0x17b, 0xdb0, 0x17e, 0xdbc, 0x180, 0xdc8,
+ 0x183, 0xdd5, 0x186, 0xde1, 0x189, 0xded, 0x18b, 0xdf9,
+ 0x18e, 0xe06, 0x191, 0xe12, 0x194, 0xe1e, 0x196, 0xe2b,
+ 0x199, 0xe37, 0x19c, 0xe43, 0x19f, 0xe4f, 0x1a2, 0xe5c,
+ 0x1a4, 0xe68, 0x1a7, 0xe74, 0x1aa, 0xe80, 0x1ad, 0xe8c,
+ 0x1b0, 0xe99, 0x1b3, 0xea5, 0x1b6, 0xeb1, 0x1b8, 0xebd,
+ 0x1bb, 0xeca, 0x1be, 0xed6, 0x1c1, 0xee2, 0x1c4, 0xeee,
+ 0x1c7, 0xefb, 0x1ca, 0xf07, 0x1cd, 0xf13, 0x1d0, 0xf1f,
+ 0x1d3, 0xf2b, 0x1d6, 0xf38, 0x1d9, 0xf44, 0x1dc, 0xf50,
+ 0x1df, 0xf5c, 0x1e2, 0xf68, 0x1e5, 0xf75, 0x1e8, 0xf81,
+ 0x1eb, 0xf8d, 0x1ee, 0xf99, 0x1f1, 0xfa5, 0x1f4, 0xfb2,
+ 0x1f7, 0xfbe, 0x1fa, 0xfca, 0x1fd, 0xfd6, 0x201, 0xfe2,
+ 0x204, 0xfee, 0x207, 0xffb, 0x20a, 0x1007, 0x20d, 0x1013,
+ 0x210, 0x101f, 0x213, 0x102b, 0x217, 0x1037, 0x21a, 0x1044,
+ 0x21d, 0x1050, 0x220, 0x105c, 0x223, 0x1068, 0x227, 0x1074,
+ 0x22a, 0x1080, 0x22d, 0x108c, 0x230, 0x1099, 0x234, 0x10a5,
+ 0x237, 0x10b1, 0x23a, 0x10bd, 0x23e, 0x10c9, 0x241, 0x10d5,
+ 0x244, 0x10e1, 0x247, 0x10ed, 0x24b, 0x10fa, 0x24e, 0x1106,
+ 0x251, 0x1112, 0x255, 0x111e, 0x258, 0x112a, 0x25c, 0x1136,
+ 0x25f, 0x1142, 0x262, 0x114e, 0x266, 0x115a, 0x269, 0x1167,
+ 0x26d, 0x1173, 0x270, 0x117f, 0x273, 0x118b, 0x277, 0x1197,
+ 0x27a, 0x11a3, 0x27e, 0x11af, 0x281, 0x11bb, 0x285, 0x11c7,
+ 0x288, 0x11d3, 0x28c, 0x11df, 0x28f, 0x11eb, 0x293, 0x11f7,
+ 0x296, 0x1204, 0x29a, 0x1210, 0x29d, 0x121c, 0x2a1, 0x1228,
+ 0x2a5, 0x1234, 0x2a8, 0x1240, 0x2ac, 0x124c, 0x2af, 0x1258,
+ 0x2b3, 0x1264, 0x2b7, 0x1270, 0x2ba, 0x127c, 0x2be, 0x1288,
+ 0x2c1, 0x1294, 0x2c5, 0x12a0, 0x2c9, 0x12ac, 0x2cc, 0x12b8,
+ 0x2d0, 0x12c4, 0x2d4, 0x12d0, 0x2d8, 0x12dc, 0x2db, 0x12e8,
+ 0x2df, 0x12f4, 0x2e3, 0x1300, 0x2e6, 0x130c, 0x2ea, 0x1318,
+ 0x2ee, 0x1324, 0x2f2, 0x1330, 0x2f5, 0x133c, 0x2f9, 0x1348,
+ 0x2fd, 0x1354, 0x301, 0x1360, 0x305, 0x136c, 0x308, 0x1378,
+ 0x30c, 0x1384, 0x310, 0x1390, 0x314, 0x139c, 0x318, 0x13a8,
+ 0x31c, 0x13b4, 0x320, 0x13c0, 0x323, 0x13cc, 0x327, 0x13d8,
+ 0x32b, 0x13e4, 0x32f, 0x13f0, 0x333, 0x13fb, 0x337, 0x1407,
+ 0x33b, 0x1413, 0x33f, 0x141f, 0x343, 0x142b, 0x347, 0x1437,
+ 0x34b, 0x1443, 0x34f, 0x144f, 0x353, 0x145b, 0x357, 0x1467,
+ 0x35b, 0x1473, 0x35f, 0x147f, 0x363, 0x148b, 0x367, 0x1496,
+ 0x36b, 0x14a2, 0x36f, 0x14ae, 0x373, 0x14ba, 0x377, 0x14c6,
+ 0x37b, 0x14d2, 0x37f, 0x14de, 0x383, 0x14ea, 0x387, 0x14f6,
+ 0x38c, 0x1501, 0x390, 0x150d, 0x394, 0x1519, 0x398, 0x1525,
+ 0x39c, 0x1531, 0x3a0, 0x153d, 0x3a5, 0x1549, 0x3a9, 0x1554,
+ 0x3ad, 0x1560, 0x3b1, 0x156c, 0x3b5, 0x1578, 0x3ba, 0x1584,
+ 0x3be, 0x1590, 0x3c2, 0x159b, 0x3c6, 0x15a7, 0x3ca, 0x15b3,
+ 0x3cf, 0x15bf, 0x3d3, 0x15cb, 0x3d7, 0x15d7, 0x3dc, 0x15e2,
+ 0x3e0, 0x15ee, 0x3e4, 0x15fa, 0x3e9, 0x1606, 0x3ed, 0x1612,
+ 0x3f1, 0x161d, 0x3f6, 0x1629, 0x3fa, 0x1635, 0x3fe, 0x1641,
+ 0x403, 0x164c, 0x407, 0x1658, 0x40b, 0x1664, 0x410, 0x1670,
+ 0x414, 0x167c, 0x419, 0x1687, 0x41d, 0x1693, 0x422, 0x169f,
+ 0x426, 0x16ab, 0x42a, 0x16b6, 0x42f, 0x16c2, 0x433, 0x16ce,
+ 0x438, 0x16da, 0x43c, 0x16e5, 0x441, 0x16f1, 0x445, 0x16fd,
+ 0x44a, 0x1709, 0x44e, 0x1714, 0x453, 0x1720, 0x457, 0x172c,
+ 0x45c, 0x1737, 0x461, 0x1743, 0x465, 0x174f, 0x46a, 0x175b,
+ 0x46e, 0x1766, 0x473, 0x1772, 0x478, 0x177e, 0x47c, 0x1789,
+ 0x481, 0x1795, 0x485, 0x17a1, 0x48a, 0x17ac, 0x48f, 0x17b8,
+ 0x493, 0x17c4, 0x498, 0x17cf, 0x49d, 0x17db, 0x4a1, 0x17e7,
+ 0x4a6, 0x17f2, 0x4ab, 0x17fe, 0x4b0, 0x180a, 0x4b4, 0x1815,
+ 0x4b9, 0x1821, 0x4be, 0x182d, 0x4c2, 0x1838, 0x4c7, 0x1844,
+ 0x4cc, 0x184f, 0x4d1, 0x185b, 0x4d6, 0x1867, 0x4da, 0x1872,
+ 0x4df, 0x187e, 0x4e4, 0x1889, 0x4e9, 0x1895, 0x4ee, 0x18a1,
+ 0x4f2, 0x18ac, 0x4f7, 0x18b8, 0x4fc, 0x18c3, 0x501, 0x18cf,
+ 0x506, 0x18db, 0x50b, 0x18e6, 0x510, 0x18f2, 0x515, 0x18fd,
+ 0x51a, 0x1909, 0x51e, 0x1914, 0x523, 0x1920, 0x528, 0x192c,
+ 0x52d, 0x1937, 0x532, 0x1943, 0x537, 0x194e, 0x53c, 0x195a,
+ 0x541, 0x1965, 0x546, 0x1971, 0x54b, 0x197c, 0x550, 0x1988,
+ 0x555, 0x1993, 0x55a, 0x199f, 0x55f, 0x19aa, 0x564, 0x19b6,
+ 0x569, 0x19c1, 0x56e, 0x19cd, 0x573, 0x19d8, 0x578, 0x19e4,
+ 0x57e, 0x19ef, 0x583, 0x19fb, 0x588, 0x1a06, 0x58d, 0x1a12,
+ 0x592, 0x1a1d, 0x597, 0x1a29, 0x59c, 0x1a34, 0x5a1, 0x1a40,
+ 0x5a7, 0x1a4b, 0x5ac, 0x1a57, 0x5b1, 0x1a62, 0x5b6, 0x1a6e,
+ 0x5bb, 0x1a79, 0x5c1, 0x1a84, 0x5c6, 0x1a90, 0x5cb, 0x1a9b,
+ 0x5d0, 0x1aa7, 0x5d5, 0x1ab2, 0x5db, 0x1abe, 0x5e0, 0x1ac9,
+ 0x5e5, 0x1ad4, 0x5ea, 0x1ae0, 0x5f0, 0x1aeb, 0x5f5, 0x1af7,
+ 0x5fa, 0x1b02, 0x600, 0x1b0d, 0x605, 0x1b19, 0x60a, 0x1b24,
+ 0x610, 0x1b30, 0x615, 0x1b3b, 0x61a, 0x1b46, 0x620, 0x1b52,
+ 0x625, 0x1b5d, 0x62a, 0x1b68, 0x630, 0x1b74, 0x635, 0x1b7f,
+ 0x63b, 0x1b8a, 0x640, 0x1b96, 0x645, 0x1ba1, 0x64b, 0x1bac,
+ 0x650, 0x1bb8, 0x656, 0x1bc3, 0x65b, 0x1bce, 0x661, 0x1bda,
+ 0x666, 0x1be5, 0x66c, 0x1bf0, 0x671, 0x1bfc, 0x677, 0x1c07,
+ 0x67c, 0x1c12, 0x682, 0x1c1e, 0x687, 0x1c29, 0x68d, 0x1c34,
+ 0x692, 0x1c3f, 0x698, 0x1c4b, 0x69d, 0x1c56, 0x6a3, 0x1c61,
+ 0x6a8, 0x1c6c, 0x6ae, 0x1c78, 0x6b4, 0x1c83, 0x6b9, 0x1c8e,
+ 0x6bf, 0x1c99, 0x6c5, 0x1ca5, 0x6ca, 0x1cb0, 0x6d0, 0x1cbb,
+ 0x6d5, 0x1cc6, 0x6db, 0x1cd2, 0x6e1, 0x1cdd, 0x6e6, 0x1ce8,
+ 0x6ec, 0x1cf3, 0x6f2, 0x1cff, 0x6f7, 0x1d0a, 0x6fd, 0x1d15,
+ 0x703, 0x1d20, 0x709, 0x1d2b, 0x70e, 0x1d36, 0x714, 0x1d42,
+ 0x71a, 0x1d4d, 0x720, 0x1d58, 0x725, 0x1d63, 0x72b, 0x1d6e,
+ 0x731, 0x1d79, 0x737, 0x1d85, 0x73d, 0x1d90, 0x742, 0x1d9b,
+ 0x748, 0x1da6, 0x74e, 0x1db1, 0x754, 0x1dbc, 0x75a, 0x1dc7,
+ 0x75f, 0x1dd3, 0x765, 0x1dde, 0x76b, 0x1de9, 0x771, 0x1df4,
+ 0x777, 0x1dff, 0x77d, 0x1e0a, 0x783, 0x1e15, 0x789, 0x1e20,
+ 0x78f, 0x1e2b, 0x795, 0x1e36, 0x79a, 0x1e42, 0x7a0, 0x1e4d,
+ 0x7a6, 0x1e58, 0x7ac, 0x1e63, 0x7b2, 0x1e6e, 0x7b8, 0x1e79,
+ 0x7be, 0x1e84, 0x7c4, 0x1e8f, 0x7ca, 0x1e9a, 0x7d0, 0x1ea5,
+ 0x7d6, 0x1eb0, 0x7dc, 0x1ebb, 0x7e2, 0x1ec6, 0x7e8, 0x1ed1,
+ 0x7ee, 0x1edc, 0x7f5, 0x1ee7, 0x7fb, 0x1ef2, 0x801, 0x1efd,
+ 0x807, 0x1f08, 0x80d, 0x1f13, 0x813, 0x1f1e, 0x819, 0x1f29,
+ 0x81f, 0x1f34, 0x825, 0x1f3f, 0x82b, 0x1f4a, 0x832, 0x1f55,
+ 0x838, 0x1f60, 0x83e, 0x1f6b, 0x844, 0x1f76, 0x84a, 0x1f81,
+ 0x850, 0x1f8c, 0x857, 0x1f97, 0x85d, 0x1fa2, 0x863, 0x1fac,
+ 0x869, 0x1fb7, 0x870, 0x1fc2, 0x876, 0x1fcd, 0x87c, 0x1fd8,
+ 0x882, 0x1fe3, 0x889, 0x1fee, 0x88f, 0x1ff9, 0x895, 0x2004,
+ 0x89b, 0x200f, 0x8a2, 0x2019, 0x8a8, 0x2024, 0x8ae, 0x202f,
+ 0x8b5, 0x203a, 0x8bb, 0x2045, 0x8c1, 0x2050, 0x8c8, 0x205b,
+ 0x8ce, 0x2065, 0x8d4, 0x2070, 0x8db, 0x207b, 0x8e1, 0x2086,
+ 0x8e8, 0x2091, 0x8ee, 0x209b, 0x8f4, 0x20a6, 0x8fb, 0x20b1,
+ 0x901, 0x20bc, 0x908, 0x20c7, 0x90e, 0x20d1, 0x915, 0x20dc,
+ 0x91b, 0x20e7, 0x921, 0x20f2, 0x928, 0x20fd, 0x92e, 0x2107,
+ 0x935, 0x2112, 0x93b, 0x211d, 0x942, 0x2128, 0x948, 0x2132,
+ 0x94f, 0x213d, 0x955, 0x2148, 0x95c, 0x2153, 0x963, 0x215d,
+ 0x969, 0x2168, 0x970, 0x2173, 0x976, 0x217d, 0x97d, 0x2188,
+ 0x983, 0x2193, 0x98a, 0x219e, 0x991, 0x21a8, 0x997, 0x21b3,
+ 0x99e, 0x21be, 0x9a4, 0x21c8, 0x9ab, 0x21d3, 0x9b2, 0x21de,
+ 0x9b8, 0x21e8, 0x9bf, 0x21f3, 0x9c6, 0x21fe, 0x9cc, 0x2208,
+ 0x9d3, 0x2213, 0x9da, 0x221e, 0x9e0, 0x2228, 0x9e7, 0x2233,
+ 0x9ee, 0x223d, 0x9f5, 0x2248, 0x9fb, 0x2253, 0xa02, 0x225d,
+ 0xa09, 0x2268, 0xa10, 0x2272, 0xa16, 0x227d, 0xa1d, 0x2288,
+ 0xa24, 0x2292, 0xa2b, 0x229d, 0xa32, 0x22a7, 0xa38, 0x22b2,
+ 0xa3f, 0x22bc, 0xa46, 0x22c7, 0xa4d, 0x22d2, 0xa54, 0x22dc,
+ 0xa5b, 0x22e7, 0xa61, 0x22f1, 0xa68, 0x22fc, 0xa6f, 0x2306,
+ 0xa76, 0x2311, 0xa7d, 0x231b, 0xa84, 0x2326, 0xa8b, 0x2330,
+ 0xa92, 0x233b, 0xa99, 0x2345, 0xa9f, 0x2350, 0xaa6, 0x235a,
+ 0xaad, 0x2365, 0xab4, 0x236f, 0xabb, 0x237a, 0xac2, 0x2384,
+ 0xac9, 0x238e, 0xad0, 0x2399, 0xad7, 0x23a3, 0xade, 0x23ae,
+ 0xae5, 0x23b8, 0xaec, 0x23c3, 0xaf3, 0x23cd, 0xafa, 0x23d7,
+ 0xb01, 0x23e2, 0xb08, 0x23ec, 0xb0f, 0x23f7, 0xb16, 0x2401,
+ 0xb1e, 0x240b, 0xb25, 0x2416, 0xb2c, 0x2420, 0xb33, 0x242b,
+ 0xb3a, 0x2435, 0xb41, 0x243f, 0xb48, 0x244a, 0xb4f, 0x2454,
+ 0xb56, 0x245e, 0xb5e, 0x2469, 0xb65, 0x2473, 0xb6c, 0x247d,
+ 0xb73, 0x2488, 0xb7a, 0x2492, 0xb81, 0x249c, 0xb89, 0x24a7,
+ 0xb90, 0x24b1, 0xb97, 0x24bb, 0xb9e, 0x24c5, 0xba5, 0x24d0,
+ 0xbad, 0x24da, 0xbb4, 0x24e4, 0xbbb, 0x24ef, 0xbc2, 0x24f9,
+ 0xbca, 0x2503, 0xbd1, 0x250d, 0xbd8, 0x2518, 0xbe0, 0x2522,
+ 0xbe7, 0x252c, 0xbee, 0x2536, 0xbf5, 0x2541, 0xbfd, 0x254b,
+ 0xc04, 0x2555, 0xc0b, 0x255f, 0xc13, 0x2569, 0xc1a, 0x2574,
+ 0xc21, 0x257e, 0xc29, 0x2588, 0xc30, 0x2592, 0xc38, 0x259c,
+ 0xc3f, 0x25a6, 0xc46, 0x25b1, 0xc4e, 0x25bb, 0xc55, 0x25c5,
+ 0xc5d, 0x25cf, 0xc64, 0x25d9, 0xc6b, 0x25e3, 0xc73, 0x25ed,
+ 0xc7a, 0x25f8, 0xc82, 0x2602, 0xc89, 0x260c, 0xc91, 0x2616,
+ 0xc98, 0x2620, 0xca0, 0x262a, 0xca7, 0x2634, 0xcaf, 0x263e,
+ 0xcb6, 0x2648, 0xcbe, 0x2652, 0xcc5, 0x265c, 0xccd, 0x2666,
+ 0xcd4, 0x2671, 0xcdc, 0x267b, 0xce3, 0x2685, 0xceb, 0x268f,
+ 0xcf3, 0x2699, 0xcfa, 0x26a3, 0xd02, 0x26ad, 0xd09, 0x26b7,
+ 0xd11, 0x26c1, 0xd19, 0x26cb, 0xd20, 0x26d5, 0xd28, 0x26df,
+ 0xd30, 0x26e9, 0xd37, 0x26f3, 0xd3f, 0x26fd, 0xd46, 0x2707,
+ 0xd4e, 0x2711, 0xd56, 0x271a, 0xd5d, 0x2724, 0xd65, 0x272e,
+ 0xd6d, 0x2738, 0xd75, 0x2742, 0xd7c, 0x274c, 0xd84, 0x2756,
+ 0xd8c, 0x2760, 0xd93, 0x276a, 0xd9b, 0x2774, 0xda3, 0x277e,
+ 0xdab, 0x2788, 0xdb2, 0x2791, 0xdba, 0x279b, 0xdc2, 0x27a5,
+ 0xdca, 0x27af, 0xdd2, 0x27b9, 0xdd9, 0x27c3, 0xde1, 0x27cd,
+ 0xde9, 0x27d6, 0xdf1, 0x27e0, 0xdf9, 0x27ea, 0xe01, 0x27f4,
+ 0xe08, 0x27fe, 0xe10, 0x2808, 0xe18, 0x2811, 0xe20, 0x281b,
+ 0xe28, 0x2825, 0xe30, 0x282f, 0xe38, 0x2838, 0xe40, 0x2842,
+ 0xe47, 0x284c, 0xe4f, 0x2856, 0xe57, 0x2860, 0xe5f, 0x2869,
+ 0xe67, 0x2873, 0xe6f, 0x287d, 0xe77, 0x2886, 0xe7f, 0x2890,
+ 0xe87, 0x289a, 0xe8f, 0x28a4, 0xe97, 0x28ad, 0xe9f, 0x28b7,
+ 0xea7, 0x28c1, 0xeaf, 0x28ca, 0xeb7, 0x28d4, 0xebf, 0x28de,
+ 0xec7, 0x28e7, 0xecf, 0x28f1, 0xed7, 0x28fb, 0xedf, 0x2904,
+ 0xee7, 0x290e, 0xeef, 0x2918, 0xef7, 0x2921, 0xeff, 0x292b,
+ 0xf07, 0x2935, 0xf10, 0x293e, 0xf18, 0x2948, 0xf20, 0x2951,
+ 0xf28, 0x295b, 0xf30, 0x2965, 0xf38, 0x296e, 0xf40, 0x2978,
+ 0xf48, 0x2981, 0xf51, 0x298b, 0xf59, 0x2994, 0xf61, 0x299e,
+ 0xf69, 0x29a7, 0xf71, 0x29b1, 0xf79, 0x29bb, 0xf82, 0x29c4,
+ 0xf8a, 0x29ce, 0xf92, 0x29d7, 0xf9a, 0x29e1, 0xfa3, 0x29ea,
+ 0xfab, 0x29f4, 0xfb3, 0x29fd, 0xfbb, 0x2a07, 0xfc4, 0x2a10,
+ 0xfcc, 0x2a1a, 0xfd4, 0x2a23, 0xfdc, 0x2a2c, 0xfe5, 0x2a36,
+ 0xfed, 0x2a3f, 0xff5, 0x2a49, 0xffe, 0x2a52, 0x1006, 0x2a5c,
+ 0x100e, 0x2a65, 0x1016, 0x2a6e, 0x101f, 0x2a78, 0x1027, 0x2a81,
+ 0x1030, 0x2a8b, 0x1038, 0x2a94, 0x1040, 0x2a9d, 0x1049, 0x2aa7,
+ 0x1051, 0x2ab0, 0x1059, 0x2ab9, 0x1062, 0x2ac3, 0x106a, 0x2acc,
+ 0x1073, 0x2ad6, 0x107b, 0x2adf, 0x1083, 0x2ae8, 0x108c, 0x2af2,
+ 0x1094, 0x2afb, 0x109d, 0x2b04, 0x10a5, 0x2b0d, 0x10ae, 0x2b17,
+ 0x10b6, 0x2b20, 0x10bf, 0x2b29, 0x10c7, 0x2b33, 0x10d0, 0x2b3c,
+ 0x10d8, 0x2b45, 0x10e0, 0x2b4e, 0x10e9, 0x2b58, 0x10f2, 0x2b61,
+ 0x10fa, 0x2b6a, 0x1103, 0x2b73, 0x110b, 0x2b7d, 0x1114, 0x2b86,
+ 0x111c, 0x2b8f, 0x1125, 0x2b98, 0x112d, 0x2ba1, 0x1136, 0x2bab,
+ 0x113e, 0x2bb4, 0x1147, 0x2bbd, 0x1150, 0x2bc6, 0x1158, 0x2bcf,
+ 0x1161, 0x2bd8, 0x1169, 0x2be2, 0x1172, 0x2beb, 0x117b, 0x2bf4,
+ 0x1183, 0x2bfd, 0x118c, 0x2c06, 0x1195, 0x2c0f, 0x119d, 0x2c18,
+ 0x11a6, 0x2c21, 0x11af, 0x2c2b, 0x11b7, 0x2c34, 0x11c0, 0x2c3d,
+ 0x11c9, 0x2c46, 0x11d1, 0x2c4f, 0x11da, 0x2c58, 0x11e3, 0x2c61,
+ 0x11eb, 0x2c6a, 0x11f4, 0x2c73, 0x11fd, 0x2c7c, 0x1206, 0x2c85,
+ 0x120e, 0x2c8e, 0x1217, 0x2c97, 0x1220, 0x2ca0, 0x1229, 0x2ca9,
+ 0x1231, 0x2cb2, 0x123a, 0x2cbb, 0x1243, 0x2cc4, 0x124c, 0x2ccd,
+ 0x1255, 0x2cd6, 0x125d, 0x2cdf, 0x1266, 0x2ce8, 0x126f, 0x2cf1,
+ 0x1278, 0x2cfa, 0x1281, 0x2d03, 0x128a, 0x2d0c, 0x1292, 0x2d15,
+ 0x129b, 0x2d1e, 0x12a4, 0x2d27, 0x12ad, 0x2d2f, 0x12b6, 0x2d38,
+ 0x12bf, 0x2d41, 0x12c8, 0x2d4a, 0x12d1, 0x2d53, 0x12d9, 0x2d5c,
+ 0x12e2, 0x2d65, 0x12eb, 0x2d6e, 0x12f4, 0x2d76, 0x12fd, 0x2d7f,
+ 0x1306, 0x2d88, 0x130f, 0x2d91, 0x1318, 0x2d9a, 0x1321, 0x2da3,
+ 0x132a, 0x2dab, 0x1333, 0x2db4, 0x133c, 0x2dbd, 0x1345, 0x2dc6,
+ 0x134e, 0x2dcf, 0x1357, 0x2dd7, 0x1360, 0x2de0, 0x1369, 0x2de9,
+ 0x1372, 0x2df2, 0x137b, 0x2dfa, 0x1384, 0x2e03, 0x138d, 0x2e0c,
+ 0x1396, 0x2e15, 0x139f, 0x2e1d, 0x13a8, 0x2e26, 0x13b1, 0x2e2f,
+ 0x13ba, 0x2e37, 0x13c3, 0x2e40, 0x13cc, 0x2e49, 0x13d5, 0x2e51,
+ 0x13df, 0x2e5a, 0x13e8, 0x2e63, 0x13f1, 0x2e6b, 0x13fa, 0x2e74,
+ 0x1403, 0x2e7d, 0x140c, 0x2e85, 0x1415, 0x2e8e, 0x141e, 0x2e97,
+ 0x1428, 0x2e9f, 0x1431, 0x2ea8, 0x143a, 0x2eb0, 0x1443, 0x2eb9,
+ 0x144c, 0x2ec2, 0x1455, 0x2eca, 0x145f, 0x2ed3, 0x1468, 0x2edb,
+ 0x1471, 0x2ee4, 0x147a, 0x2eec, 0x1483, 0x2ef5, 0x148d, 0x2efd,
+ 0x1496, 0x2f06, 0x149f, 0x2f0e, 0x14a8, 0x2f17, 0x14b2, 0x2f20,
+ 0x14bb, 0x2f28, 0x14c4, 0x2f30, 0x14cd, 0x2f39, 0x14d7, 0x2f41,
+ 0x14e0, 0x2f4a, 0x14e9, 0x2f52, 0x14f3, 0x2f5b, 0x14fc, 0x2f63,
+ 0x1505, 0x2f6c, 0x150e, 0x2f74, 0x1518, 0x2f7d, 0x1521, 0x2f85,
+ 0x152a, 0x2f8d, 0x1534, 0x2f96, 0x153d, 0x2f9e, 0x1547, 0x2fa7,
+ 0x1550, 0x2faf, 0x1559, 0x2fb7, 0x1563, 0x2fc0, 0x156c, 0x2fc8,
+ 0x1575, 0x2fd0, 0x157f, 0x2fd9, 0x1588, 0x2fe1, 0x1592, 0x2fea,
+ 0x159b, 0x2ff2, 0x15a4, 0x2ffa, 0x15ae, 0x3002, 0x15b7, 0x300b,
+ 0x15c1, 0x3013, 0x15ca, 0x301b, 0x15d4, 0x3024, 0x15dd, 0x302c,
+ 0x15e6, 0x3034, 0x15f0, 0x303c, 0x15f9, 0x3045, 0x1603, 0x304d,
+ 0x160c, 0x3055, 0x1616, 0x305d, 0x161f, 0x3066, 0x1629, 0x306e,
+ 0x1632, 0x3076, 0x163c, 0x307e, 0x1645, 0x3087, 0x164f, 0x308f,
+ 0x1659, 0x3097, 0x1662, 0x309f, 0x166c, 0x30a7, 0x1675, 0x30af,
+ 0x167f, 0x30b8, 0x1688, 0x30c0, 0x1692, 0x30c8, 0x169b, 0x30d0,
+ 0x16a5, 0x30d8, 0x16af, 0x30e0, 0x16b8, 0x30e8, 0x16c2, 0x30f0,
+ 0x16cb, 0x30f9, 0x16d5, 0x3101, 0x16df, 0x3109, 0x16e8, 0x3111,
+ 0x16f2, 0x3119, 0x16fc, 0x3121, 0x1705, 0x3129, 0x170f, 0x3131,
+ 0x1719, 0x3139, 0x1722, 0x3141, 0x172c, 0x3149, 0x1736, 0x3151,
+ 0x173f, 0x3159, 0x1749, 0x3161, 0x1753, 0x3169, 0x175c, 0x3171,
+ 0x1766, 0x3179, 0x1770, 0x3181, 0x177a, 0x3189, 0x1783, 0x3191,
+ 0x178d, 0x3199, 0x1797, 0x31a1, 0x17a0, 0x31a9, 0x17aa, 0x31b1,
+ 0x17b4, 0x31b9, 0x17be, 0x31c0, 0x17c8, 0x31c8, 0x17d1, 0x31d0,
+ 0x17db, 0x31d8, 0x17e5, 0x31e0, 0x17ef, 0x31e8, 0x17f8, 0x31f0,
+ 0x1802, 0x31f8, 0x180c, 0x31ff, 0x1816, 0x3207, 0x1820, 0x320f,
+ 0x182a, 0x3217, 0x1833, 0x321f, 0x183d, 0x3227, 0x1847, 0x322e,
+ 0x1851, 0x3236, 0x185b, 0x323e, 0x1865, 0x3246, 0x186f, 0x324e,
+ 0x1878, 0x3255, 0x1882, 0x325d, 0x188c, 0x3265, 0x1896, 0x326d,
+ 0x18a0, 0x3274, 0x18aa, 0x327c, 0x18b4, 0x3284, 0x18be, 0x328b,
+ 0x18c8, 0x3293, 0x18d2, 0x329b, 0x18dc, 0x32a3, 0x18e6, 0x32aa,
+ 0x18ef, 0x32b2, 0x18f9, 0x32ba, 0x1903, 0x32c1, 0x190d, 0x32c9,
+ 0x1917, 0x32d0, 0x1921, 0x32d8, 0x192b, 0x32e0, 0x1935, 0x32e7,
+ 0x193f, 0x32ef, 0x1949, 0x32f7, 0x1953, 0x32fe, 0x195d, 0x3306,
+ 0x1967, 0x330d, 0x1971, 0x3315, 0x197b, 0x331d, 0x1985, 0x3324,
+ 0x198f, 0x332c, 0x199a, 0x3333, 0x19a4, 0x333b, 0x19ae, 0x3342,
+ 0x19b8, 0x334a, 0x19c2, 0x3351, 0x19cc, 0x3359, 0x19d6, 0x3360,
+ 0x19e0, 0x3368, 0x19ea, 0x336f, 0x19f4, 0x3377, 0x19fe, 0x337e,
+ 0x1a08, 0x3386, 0x1a13, 0x338d, 0x1a1d, 0x3395, 0x1a27, 0x339c,
+ 0x1a31, 0x33a3, 0x1a3b, 0x33ab, 0x1a45, 0x33b2, 0x1a4f, 0x33ba,
+ 0x1a5a, 0x33c1, 0x1a64, 0x33c8, 0x1a6e, 0x33d0, 0x1a78, 0x33d7,
+ 0x1a82, 0x33df, 0x1a8c, 0x33e6, 0x1a97, 0x33ed, 0x1aa1, 0x33f5,
+ 0x1aab, 0x33fc, 0x1ab5, 0x3403, 0x1abf, 0x340b, 0x1aca, 0x3412,
+ 0x1ad4, 0x3419, 0x1ade, 0x3420, 0x1ae8, 0x3428, 0x1af3, 0x342f,
+ 0x1afd, 0x3436, 0x1b07, 0x343e, 0x1b11, 0x3445, 0x1b1c, 0x344c,
+ 0x1b26, 0x3453, 0x1b30, 0x345b, 0x1b3b, 0x3462, 0x1b45, 0x3469,
+ 0x1b4f, 0x3470, 0x1b59, 0x3477, 0x1b64, 0x347f, 0x1b6e, 0x3486,
+ 0x1b78, 0x348d, 0x1b83, 0x3494, 0x1b8d, 0x349b, 0x1b97, 0x34a2,
+ 0x1ba2, 0x34aa, 0x1bac, 0x34b1, 0x1bb6, 0x34b8, 0x1bc1, 0x34bf,
+ 0x1bcb, 0x34c6, 0x1bd5, 0x34cd, 0x1be0, 0x34d4, 0x1bea, 0x34db,
+ 0x1bf5, 0x34e2, 0x1bff, 0x34ea, 0x1c09, 0x34f1, 0x1c14, 0x34f8,
+ 0x1c1e, 0x34ff, 0x1c29, 0x3506, 0x1c33, 0x350d, 0x1c3d, 0x3514,
+ 0x1c48, 0x351b, 0x1c52, 0x3522, 0x1c5d, 0x3529, 0x1c67, 0x3530,
+ 0x1c72, 0x3537, 0x1c7c, 0x353e, 0x1c86, 0x3545, 0x1c91, 0x354c,
+ 0x1c9b, 0x3553, 0x1ca6, 0x355a, 0x1cb0, 0x3561, 0x1cbb, 0x3567,
+ 0x1cc5, 0x356e, 0x1cd0, 0x3575, 0x1cda, 0x357c, 0x1ce5, 0x3583,
+ 0x1cef, 0x358a, 0x1cfa, 0x3591, 0x1d04, 0x3598, 0x1d0f, 0x359f,
+ 0x1d19, 0x35a5, 0x1d24, 0x35ac, 0x1d2e, 0x35b3, 0x1d39, 0x35ba,
+ 0x1d44, 0x35c1, 0x1d4e, 0x35c8, 0x1d59, 0x35ce, 0x1d63, 0x35d5,
+ 0x1d6e, 0x35dc, 0x1d78, 0x35e3, 0x1d83, 0x35ea, 0x1d8e, 0x35f0,
+ 0x1d98, 0x35f7, 0x1da3, 0x35fe, 0x1dad, 0x3605, 0x1db8, 0x360b,
+ 0x1dc3, 0x3612, 0x1dcd, 0x3619, 0x1dd8, 0x3620, 0x1de2, 0x3626,
+ 0x1ded, 0x362d, 0x1df8, 0x3634, 0x1e02, 0x363a, 0x1e0d, 0x3641,
+ 0x1e18, 0x3648, 0x1e22, 0x364e, 0x1e2d, 0x3655, 0x1e38, 0x365c,
+ 0x1e42, 0x3662, 0x1e4d, 0x3669, 0x1e58, 0x366f, 0x1e62, 0x3676,
+ 0x1e6d, 0x367d, 0x1e78, 0x3683, 0x1e83, 0x368a, 0x1e8d, 0x3690,
+ 0x1e98, 0x3697, 0x1ea3, 0x369d, 0x1ead, 0x36a4, 0x1eb8, 0x36ab,
+ 0x1ec3, 0x36b1, 0x1ece, 0x36b8, 0x1ed8, 0x36be, 0x1ee3, 0x36c5,
+ 0x1eee, 0x36cb, 0x1ef9, 0x36d2, 0x1f03, 0x36d8, 0x1f0e, 0x36df,
+ 0x1f19, 0x36e5, 0x1f24, 0x36eb, 0x1f2f, 0x36f2, 0x1f39, 0x36f8,
+ 0x1f44, 0x36ff, 0x1f4f, 0x3705, 0x1f5a, 0x370c, 0x1f65, 0x3712,
+ 0x1f6f, 0x3718, 0x1f7a, 0x371f, 0x1f85, 0x3725, 0x1f90, 0x372c,
+ 0x1f9b, 0x3732, 0x1fa5, 0x3738, 0x1fb0, 0x373f, 0x1fbb, 0x3745,
+ 0x1fc6, 0x374b, 0x1fd1, 0x3752, 0x1fdc, 0x3758, 0x1fe7, 0x375e,
+ 0x1ff1, 0x3765, 0x1ffc, 0x376b, 0x2007, 0x3771, 0x2012, 0x3777,
+ 0x201d, 0x377e, 0x2028, 0x3784, 0x2033, 0x378a, 0x203e, 0x3790,
+ 0x2049, 0x3797, 0x2054, 0x379d, 0x205e, 0x37a3, 0x2069, 0x37a9,
+ 0x2074, 0x37b0, 0x207f, 0x37b6, 0x208a, 0x37bc, 0x2095, 0x37c2,
+ 0x20a0, 0x37c8, 0x20ab, 0x37ce, 0x20b6, 0x37d5, 0x20c1, 0x37db,
+ 0x20cc, 0x37e1, 0x20d7, 0x37e7, 0x20e2, 0x37ed, 0x20ed, 0x37f3,
+ 0x20f8, 0x37f9, 0x2103, 0x37ff, 0x210e, 0x3805, 0x2119, 0x380b,
+ 0x2124, 0x3812, 0x212f, 0x3818, 0x213a, 0x381e, 0x2145, 0x3824,
+ 0x2150, 0x382a, 0x215b, 0x3830, 0x2166, 0x3836, 0x2171, 0x383c,
+ 0x217c, 0x3842, 0x2187, 0x3848, 0x2192, 0x384e, 0x219d, 0x3854,
+ 0x21a8, 0x385a, 0x21b3, 0x3860, 0x21be, 0x3866, 0x21ca, 0x386b,
+ 0x21d5, 0x3871, 0x21e0, 0x3877, 0x21eb, 0x387d, 0x21f6, 0x3883,
+ 0x2201, 0x3889, 0x220c, 0x388f, 0x2217, 0x3895, 0x2222, 0x389b,
+ 0x222d, 0x38a1, 0x2239, 0x38a6, 0x2244, 0x38ac, 0x224f, 0x38b2,
+ 0x225a, 0x38b8, 0x2265, 0x38be, 0x2270, 0x38c3, 0x227b, 0x38c9,
+ 0x2287, 0x38cf, 0x2292, 0x38d5, 0x229d, 0x38db, 0x22a8, 0x38e0,
+ 0x22b3, 0x38e6, 0x22be, 0x38ec, 0x22ca, 0x38f2, 0x22d5, 0x38f7,
+ 0x22e0, 0x38fd, 0x22eb, 0x3903, 0x22f6, 0x3909, 0x2301, 0x390e,
+ 0x230d, 0x3914, 0x2318, 0x391a, 0x2323, 0x391f, 0x232e, 0x3925,
+ 0x233a, 0x392b, 0x2345, 0x3930, 0x2350, 0x3936, 0x235b, 0x393b,
+ 0x2367, 0x3941, 0x2372, 0x3947, 0x237d, 0x394c, 0x2388, 0x3952,
+ 0x2394, 0x3958, 0x239f, 0x395d, 0x23aa, 0x3963, 0x23b5, 0x3968,
+ 0x23c1, 0x396e, 0x23cc, 0x3973, 0x23d7, 0x3979, 0x23e2, 0x397e,
+ 0x23ee, 0x3984, 0x23f9, 0x3989, 0x2404, 0x398f, 0x2410, 0x3994,
+ 0x241b, 0x399a, 0x2426, 0x399f, 0x2432, 0x39a5, 0x243d, 0x39aa,
+ 0x2448, 0x39b0, 0x2454, 0x39b5, 0x245f, 0x39bb, 0x246a, 0x39c0,
+ 0x2476, 0x39c5, 0x2481, 0x39cb, 0x248c, 0x39d0, 0x2498, 0x39d6,
+ 0x24a3, 0x39db, 0x24ae, 0x39e0, 0x24ba, 0x39e6, 0x24c5, 0x39eb,
+ 0x24d0, 0x39f0, 0x24dc, 0x39f6, 0x24e7, 0x39fb, 0x24f3, 0x3a00,
+ 0x24fe, 0x3a06, 0x2509, 0x3a0b, 0x2515, 0x3a10, 0x2520, 0x3a16,
+ 0x252c, 0x3a1b, 0x2537, 0x3a20, 0x2542, 0x3a25, 0x254e, 0x3a2b,
+ 0x2559, 0x3a30, 0x2565, 0x3a35, 0x2570, 0x3a3a, 0x257c, 0x3a3f,
+ 0x2587, 0x3a45, 0x2592, 0x3a4a, 0x259e, 0x3a4f, 0x25a9, 0x3a54,
+ 0x25b5, 0x3a59, 0x25c0, 0x3a5f, 0x25cc, 0x3a64, 0x25d7, 0x3a69,
+ 0x25e3, 0x3a6e, 0x25ee, 0x3a73, 0x25fa, 0x3a78, 0x2605, 0x3a7d,
+ 0x2611, 0x3a82, 0x261c, 0x3a88, 0x2628, 0x3a8d, 0x2633, 0x3a92,
+ 0x263f, 0x3a97, 0x264a, 0x3a9c, 0x2656, 0x3aa1, 0x2661, 0x3aa6,
+ 0x266d, 0x3aab, 0x2678, 0x3ab0, 0x2684, 0x3ab5, 0x268f, 0x3aba,
+ 0x269b, 0x3abf, 0x26a6, 0x3ac4, 0x26b2, 0x3ac9, 0x26bd, 0x3ace,
+ 0x26c9, 0x3ad3, 0x26d4, 0x3ad8, 0x26e0, 0x3add, 0x26ec, 0x3ae2,
+ 0x26f7, 0x3ae6, 0x2703, 0x3aeb, 0x270e, 0x3af0, 0x271a, 0x3af5,
+ 0x2725, 0x3afa, 0x2731, 0x3aff, 0x273d, 0x3b04, 0x2748, 0x3b09,
+ 0x2754, 0x3b0e, 0x275f, 0x3b12, 0x276b, 0x3b17, 0x2777, 0x3b1c,
+ 0x2782, 0x3b21, 0x278e, 0x3b26, 0x2799, 0x3b2a, 0x27a5, 0x3b2f,
+ 0x27b1, 0x3b34, 0x27bc, 0x3b39, 0x27c8, 0x3b3e, 0x27d3, 0x3b42,
+ 0x27df, 0x3b47, 0x27eb, 0x3b4c, 0x27f6, 0x3b50, 0x2802, 0x3b55,
+ 0x280e, 0x3b5a, 0x2819, 0x3b5f, 0x2825, 0x3b63, 0x2831, 0x3b68,
+ 0x283c, 0x3b6d, 0x2848, 0x3b71, 0x2854, 0x3b76, 0x285f, 0x3b7b,
+ 0x286b, 0x3b7f, 0x2877, 0x3b84, 0x2882, 0x3b88, 0x288e, 0x3b8d,
+ 0x289a, 0x3b92, 0x28a5, 0x3b96, 0x28b1, 0x3b9b, 0x28bd, 0x3b9f,
+ 0x28c9, 0x3ba4, 0x28d4, 0x3ba9, 0x28e0, 0x3bad, 0x28ec, 0x3bb2,
+ 0x28f7, 0x3bb6, 0x2903, 0x3bbb, 0x290f, 0x3bbf, 0x291b, 0x3bc4,
+ 0x2926, 0x3bc8, 0x2932, 0x3bcd, 0x293e, 0x3bd1, 0x294a, 0x3bd6,
+ 0x2955, 0x3bda, 0x2961, 0x3bde, 0x296d, 0x3be3, 0x2979, 0x3be7,
+ 0x2984, 0x3bec, 0x2990, 0x3bf0, 0x299c, 0x3bf5, 0x29a8, 0x3bf9,
+ 0x29b4, 0x3bfd, 0x29bf, 0x3c02, 0x29cb, 0x3c06, 0x29d7, 0x3c0a,
+ 0x29e3, 0x3c0f, 0x29ee, 0x3c13, 0x29fa, 0x3c17, 0x2a06, 0x3c1c,
+ 0x2a12, 0x3c20, 0x2a1e, 0x3c24, 0x2a29, 0x3c29, 0x2a35, 0x3c2d,
+ 0x2a41, 0x3c31, 0x2a4d, 0x3c36, 0x2a59, 0x3c3a, 0x2a65, 0x3c3e,
+ 0x2a70, 0x3c42, 0x2a7c, 0x3c46, 0x2a88, 0x3c4b, 0x2a94, 0x3c4f,
+ 0x2aa0, 0x3c53, 0x2aac, 0x3c57, 0x2ab7, 0x3c5b, 0x2ac3, 0x3c60,
+ 0x2acf, 0x3c64, 0x2adb, 0x3c68, 0x2ae7, 0x3c6c, 0x2af3, 0x3c70,
+ 0x2aff, 0x3c74, 0x2b0a, 0x3c79, 0x2b16, 0x3c7d, 0x2b22, 0x3c81,
+ 0x2b2e, 0x3c85, 0x2b3a, 0x3c89, 0x2b46, 0x3c8d, 0x2b52, 0x3c91,
+ 0x2b5e, 0x3c95, 0x2b6a, 0x3c99, 0x2b75, 0x3c9d, 0x2b81, 0x3ca1,
+ 0x2b8d, 0x3ca5, 0x2b99, 0x3ca9, 0x2ba5, 0x3cad, 0x2bb1, 0x3cb1,
+ 0x2bbd, 0x3cb5, 0x2bc9, 0x3cb9, 0x2bd5, 0x3cbd, 0x2be1, 0x3cc1,
+ 0x2bed, 0x3cc5, 0x2bf9, 0x3cc9, 0x2c05, 0x3ccd, 0x2c10, 0x3cd1,
+ 0x2c1c, 0x3cd5, 0x2c28, 0x3cd9, 0x2c34, 0x3cdd, 0x2c40, 0x3ce0,
+ 0x2c4c, 0x3ce4, 0x2c58, 0x3ce8, 0x2c64, 0x3cec, 0x2c70, 0x3cf0,
+ 0x2c7c, 0x3cf4, 0x2c88, 0x3cf8, 0x2c94, 0x3cfb, 0x2ca0, 0x3cff,
+ 0x2cac, 0x3d03, 0x2cb8, 0x3d07, 0x2cc4, 0x3d0b, 0x2cd0, 0x3d0e,
+ 0x2cdc, 0x3d12, 0x2ce8, 0x3d16, 0x2cf4, 0x3d1a, 0x2d00, 0x3d1d,
+ 0x2d0c, 0x3d21, 0x2d18, 0x3d25, 0x2d24, 0x3d28, 0x2d30, 0x3d2c,
+ 0x2d3c, 0x3d30, 0x2d48, 0x3d34, 0x2d54, 0x3d37, 0x2d60, 0x3d3b,
+ 0x2d6c, 0x3d3f, 0x2d78, 0x3d42, 0x2d84, 0x3d46, 0x2d90, 0x3d49,
+ 0x2d9c, 0x3d4d, 0x2da8, 0x3d51, 0x2db4, 0x3d54, 0x2dc0, 0x3d58,
+ 0x2dcc, 0x3d5b, 0x2dd8, 0x3d5f, 0x2de4, 0x3d63, 0x2df0, 0x3d66,
+ 0x2dfc, 0x3d6a, 0x2e09, 0x3d6d, 0x2e15, 0x3d71, 0x2e21, 0x3d74,
+ 0x2e2d, 0x3d78, 0x2e39, 0x3d7b, 0x2e45, 0x3d7f, 0x2e51, 0x3d82,
+ 0x2e5d, 0x3d86, 0x2e69, 0x3d89, 0x2e75, 0x3d8d, 0x2e81, 0x3d90,
+ 0x2e8d, 0x3d93, 0x2e99, 0x3d97, 0x2ea6, 0x3d9a, 0x2eb2, 0x3d9e,
+ 0x2ebe, 0x3da1, 0x2eca, 0x3da4, 0x2ed6, 0x3da8, 0x2ee2, 0x3dab,
+ 0x2eee, 0x3daf, 0x2efa, 0x3db2, 0x2f06, 0x3db5, 0x2f13, 0x3db9,
+ 0x2f1f, 0x3dbc, 0x2f2b, 0x3dbf, 0x2f37, 0x3dc2, 0x2f43, 0x3dc6,
+ 0x2f4f, 0x3dc9, 0x2f5b, 0x3dcc, 0x2f67, 0x3dd0, 0x2f74, 0x3dd3,
+ 0x2f80, 0x3dd6, 0x2f8c, 0x3dd9, 0x2f98, 0x3ddd, 0x2fa4, 0x3de0,
+ 0x2fb0, 0x3de3, 0x2fbc, 0x3de6, 0x2fc9, 0x3de9, 0x2fd5, 0x3ded,
+ 0x2fe1, 0x3df0, 0x2fed, 0x3df3, 0x2ff9, 0x3df6, 0x3005, 0x3df9,
+ 0x3012, 0x3dfc, 0x301e, 0x3dff, 0x302a, 0x3e03, 0x3036, 0x3e06,
+ 0x3042, 0x3e09, 0x304e, 0x3e0c, 0x305b, 0x3e0f, 0x3067, 0x3e12,
+ 0x3073, 0x3e15, 0x307f, 0x3e18, 0x308b, 0x3e1b, 0x3098, 0x3e1e,
+ 0x30a4, 0x3e21, 0x30b0, 0x3e24, 0x30bc, 0x3e27, 0x30c8, 0x3e2a,
+ 0x30d5, 0x3e2d, 0x30e1, 0x3e30, 0x30ed, 0x3e33, 0x30f9, 0x3e36,
+ 0x3105, 0x3e39, 0x3112, 0x3e3c, 0x311e, 0x3e3f, 0x312a, 0x3e42,
+ 0x3136, 0x3e45, 0x3143, 0x3e48, 0x314f, 0x3e4a, 0x315b, 0x3e4d,
+ 0x3167, 0x3e50, 0x3174, 0x3e53, 0x3180, 0x3e56, 0x318c, 0x3e59,
+ 0x3198, 0x3e5c, 0x31a4, 0x3e5e, 0x31b1, 0x3e61, 0x31bd, 0x3e64,
+ 0x31c9, 0x3e67, 0x31d5, 0x3e6a, 0x31e2, 0x3e6c, 0x31ee, 0x3e6f,
+ 0x31fa, 0x3e72, 0x3207, 0x3e75, 0x3213, 0x3e77, 0x321f, 0x3e7a,
+ 0x322b, 0x3e7d, 0x3238, 0x3e80, 0x3244, 0x3e82, 0x3250, 0x3e85,
+ 0x325c, 0x3e88, 0x3269, 0x3e8a, 0x3275, 0x3e8d, 0x3281, 0x3e90,
+ 0x328e, 0x3e92, 0x329a, 0x3e95, 0x32a6, 0x3e98, 0x32b2, 0x3e9a,
+ 0x32bf, 0x3e9d, 0x32cb, 0x3e9f, 0x32d7, 0x3ea2, 0x32e4, 0x3ea5,
+ 0x32f0, 0x3ea7, 0x32fc, 0x3eaa, 0x3308, 0x3eac, 0x3315, 0x3eaf,
+ 0x3321, 0x3eb1, 0x332d, 0x3eb4, 0x333a, 0x3eb6, 0x3346, 0x3eb9,
+ 0x3352, 0x3ebb, 0x335f, 0x3ebe, 0x336b, 0x3ec0, 0x3377, 0x3ec3,
+ 0x3384, 0x3ec5, 0x3390, 0x3ec8, 0x339c, 0x3eca, 0x33a9, 0x3ecc,
+ 0x33b5, 0x3ecf, 0x33c1, 0x3ed1, 0x33ce, 0x3ed4, 0x33da, 0x3ed6,
+ 0x33e6, 0x3ed8, 0x33f3, 0x3edb, 0x33ff, 0x3edd, 0x340b, 0x3ee0,
+ 0x3418, 0x3ee2, 0x3424, 0x3ee4, 0x3430, 0x3ee7, 0x343d, 0x3ee9,
+ 0x3449, 0x3eeb, 0x3455, 0x3eed, 0x3462, 0x3ef0, 0x346e, 0x3ef2,
+ 0x347b, 0x3ef4, 0x3487, 0x3ef7, 0x3493, 0x3ef9, 0x34a0, 0x3efb,
+ 0x34ac, 0x3efd, 0x34b8, 0x3f00, 0x34c5, 0x3f02, 0x34d1, 0x3f04,
+ 0x34dd, 0x3f06, 0x34ea, 0x3f08, 0x34f6, 0x3f0a, 0x3503, 0x3f0d,
+ 0x350f, 0x3f0f, 0x351b, 0x3f11, 0x3528, 0x3f13, 0x3534, 0x3f15,
+ 0x3540, 0x3f17, 0x354d, 0x3f19, 0x3559, 0x3f1c, 0x3566, 0x3f1e,
+ 0x3572, 0x3f20, 0x357e, 0x3f22, 0x358b, 0x3f24, 0x3597, 0x3f26,
+ 0x35a4, 0x3f28, 0x35b0, 0x3f2a, 0x35bc, 0x3f2c, 0x35c9, 0x3f2e,
+ 0x35d5, 0x3f30, 0x35e2, 0x3f32, 0x35ee, 0x3f34, 0x35fa, 0x3f36,
+ 0x3607, 0x3f38, 0x3613, 0x3f3a, 0x3620, 0x3f3c, 0x362c, 0x3f3e,
+ 0x3639, 0x3f40, 0x3645, 0x3f42, 0x3651, 0x3f43, 0x365e, 0x3f45,
+ 0x366a, 0x3f47, 0x3677, 0x3f49, 0x3683, 0x3f4b, 0x3690, 0x3f4d,
+ 0x369c, 0x3f4f, 0x36a8, 0x3f51, 0x36b5, 0x3f52, 0x36c1, 0x3f54,
+ 0x36ce, 0x3f56, 0x36da, 0x3f58, 0x36e7, 0x3f5a, 0x36f3, 0x3f5b,
+ 0x36ff, 0x3f5d, 0x370c, 0x3f5f, 0x3718, 0x3f61, 0x3725, 0x3f62,
+ 0x3731, 0x3f64, 0x373e, 0x3f66, 0x374a, 0x3f68, 0x3757, 0x3f69,
+ 0x3763, 0x3f6b, 0x376f, 0x3f6d, 0x377c, 0x3f6e, 0x3788, 0x3f70,
+ 0x3795, 0x3f72, 0x37a1, 0x3f73, 0x37ae, 0x3f75, 0x37ba, 0x3f77,
+ 0x37c7, 0x3f78, 0x37d3, 0x3f7a, 0x37e0, 0x3f7b, 0x37ec, 0x3f7d,
+ 0x37f9, 0x3f7f, 0x3805, 0x3f80, 0x3811, 0x3f82, 0x381e, 0x3f83,
+ 0x382a, 0x3f85, 0x3837, 0x3f86, 0x3843, 0x3f88, 0x3850, 0x3f89,
+ 0x385c, 0x3f8b, 0x3869, 0x3f8c, 0x3875, 0x3f8e, 0x3882, 0x3f8f,
+ 0x388e, 0x3f91, 0x389b, 0x3f92, 0x38a7, 0x3f94, 0x38b4, 0x3f95,
+ 0x38c0, 0x3f97, 0x38cd, 0x3f98, 0x38d9, 0x3f99, 0x38e6, 0x3f9b,
+ 0x38f2, 0x3f9c, 0x38ff, 0x3f9e, 0x390b, 0x3f9f, 0x3918, 0x3fa0,
+ 0x3924, 0x3fa2, 0x3931, 0x3fa3, 0x393d, 0x3fa4, 0x394a, 0x3fa6,
+ 0x3956, 0x3fa7, 0x3963, 0x3fa8, 0x396f, 0x3faa, 0x397c, 0x3fab,
+ 0x3988, 0x3fac, 0x3995, 0x3fad, 0x39a1, 0x3faf, 0x39ae, 0x3fb0,
+ 0x39ba, 0x3fb1, 0x39c7, 0x3fb2, 0x39d3, 0x3fb4, 0x39e0, 0x3fb5,
+ 0x39ec, 0x3fb6, 0x39f9, 0x3fb7, 0x3a05, 0x3fb8, 0x3a12, 0x3fb9,
+ 0x3a1e, 0x3fbb, 0x3a2b, 0x3fbc, 0x3a37, 0x3fbd, 0x3a44, 0x3fbe,
+ 0x3a50, 0x3fbf, 0x3a5d, 0x3fc0, 0x3a69, 0x3fc1, 0x3a76, 0x3fc3,
+ 0x3a82, 0x3fc4, 0x3a8f, 0x3fc5, 0x3a9b, 0x3fc6, 0x3aa8, 0x3fc7,
+ 0x3ab4, 0x3fc8, 0x3ac1, 0x3fc9, 0x3acd, 0x3fca, 0x3ada, 0x3fcb,
+ 0x3ae6, 0x3fcc, 0x3af3, 0x3fcd, 0x3b00, 0x3fce, 0x3b0c, 0x3fcf,
+ 0x3b19, 0x3fd0, 0x3b25, 0x3fd1, 0x3b32, 0x3fd2, 0x3b3e, 0x3fd3,
+ 0x3b4b, 0x3fd4, 0x3b57, 0x3fd5, 0x3b64, 0x3fd5, 0x3b70, 0x3fd6,
+ 0x3b7d, 0x3fd7, 0x3b89, 0x3fd8, 0x3b96, 0x3fd9, 0x3ba2, 0x3fda,
+ 0x3baf, 0x3fdb, 0x3bbc, 0x3fdc, 0x3bc8, 0x3fdc, 0x3bd5, 0x3fdd,
+ 0x3be1, 0x3fde, 0x3bee, 0x3fdf, 0x3bfa, 0x3fe0, 0x3c07, 0x3fe0,
+ 0x3c13, 0x3fe1, 0x3c20, 0x3fe2, 0x3c2c, 0x3fe3, 0x3c39, 0x3fe3,
+ 0x3c45, 0x3fe4, 0x3c52, 0x3fe5, 0x3c5f, 0x3fe6, 0x3c6b, 0x3fe6,
+ 0x3c78, 0x3fe7, 0x3c84, 0x3fe8, 0x3c91, 0x3fe8, 0x3c9d, 0x3fe9,
+ 0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,
+ 0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,
+ 0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,
+ 0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,
+ 0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,
+ 0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,
+ 0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,
+ 0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,
+ 0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,
+ 0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,
+ 0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,
+ 0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,
+ 0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,
+ 0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,
+ 0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,
+ 0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,
+ 0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,
+};
+
+/**
+* \par
+* Generation of real_CoefB array:
+* \par
+* n = 4096
+* for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }
+* \par
+* Convert to fixed point Q15 format
+* round(pBTable[i] * pow(2, 15))
+*
+*/
+static const q15_t ALIGN4 realCoefBQ15[8192] = {
+ 0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,
+ 0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,
+ 0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,
+ 0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,
+ 0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,
+ 0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,
+ 0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,
+ 0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,
+ 0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,
+ 0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,
+ 0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,
+ 0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,
+ 0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,
+ 0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,
+ 0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,
+ 0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,
+ 0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,
+ 0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,
+ 0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,
+ 0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,
+ 0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,
+ 0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,
+ 0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,
+ 0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,
+ 0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,
+ 0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,
+ 0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,
+ 0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,
+ 0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,
+ 0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,
+ 0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,
+ 0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,
+ 0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,
+ 0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,
+ 0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,
+ 0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,
+ 0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,
+ 0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,
+ 0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,
+ 0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,
+ 0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,
+ 0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,
+ 0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,
+ 0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,
+ 0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,
+ 0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,
+ 0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,
+ 0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,
+ 0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,
+ 0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,
+ 0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,
+ 0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,
+ 0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,
+ 0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,
+ 0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,
+ 0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,
+ 0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,
+ 0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,
+ 0x4b54, 0x3efd, 0x4b60, 0x3efb, 0x4b6d, 0x3ef9, 0x4b79, 0x3ef7,
+ 0x4b85, 0x3ef4, 0x4b92, 0x3ef2, 0x4b9e, 0x3ef0, 0x4bab, 0x3eed,
+ 0x4bb7, 0x3eeb, 0x4bc3, 0x3ee9, 0x4bd0, 0x3ee7, 0x4bdc, 0x3ee4,
+ 0x4be8, 0x3ee2, 0x4bf5, 0x3ee0, 0x4c01, 0x3edd, 0x4c0d, 0x3edb,
+ 0x4c1a, 0x3ed8, 0x4c26, 0x3ed6, 0x4c32, 0x3ed4, 0x4c3f, 0x3ed1,
+ 0x4c4b, 0x3ecf, 0x4c57, 0x3ecc, 0x4c64, 0x3eca, 0x4c70, 0x3ec8,
+ 0x4c7c, 0x3ec5, 0x4c89, 0x3ec3, 0x4c95, 0x3ec0, 0x4ca1, 0x3ebe,
+ 0x4cae, 0x3ebb, 0x4cba, 0x3eb9, 0x4cc6, 0x3eb6, 0x4cd3, 0x3eb4,
+ 0x4cdf, 0x3eb1, 0x4ceb, 0x3eaf, 0x4cf8, 0x3eac, 0x4d04, 0x3eaa,
+ 0x4d10, 0x3ea7, 0x4d1c, 0x3ea5, 0x4d29, 0x3ea2, 0x4d35, 0x3e9f,
+ 0x4d41, 0x3e9d, 0x4d4e, 0x3e9a, 0x4d5a, 0x3e98, 0x4d66, 0x3e95,
+ 0x4d72, 0x3e92, 0x4d7f, 0x3e90, 0x4d8b, 0x3e8d, 0x4d97, 0x3e8a,
+ 0x4da4, 0x3e88, 0x4db0, 0x3e85, 0x4dbc, 0x3e82, 0x4dc8, 0x3e80,
+ 0x4dd5, 0x3e7d, 0x4de1, 0x3e7a, 0x4ded, 0x3e77, 0x4df9, 0x3e75,
+ 0x4e06, 0x3e72, 0x4e12, 0x3e6f, 0x4e1e, 0x3e6c, 0x4e2b, 0x3e6a,
+ 0x4e37, 0x3e67, 0x4e43, 0x3e64, 0x4e4f, 0x3e61, 0x4e5c, 0x3e5e,
+ 0x4e68, 0x3e5c, 0x4e74, 0x3e59, 0x4e80, 0x3e56, 0x4e8c, 0x3e53,
+ 0x4e99, 0x3e50, 0x4ea5, 0x3e4d, 0x4eb1, 0x3e4a, 0x4ebd, 0x3e48,
+ 0x4eca, 0x3e45, 0x4ed6, 0x3e42, 0x4ee2, 0x3e3f, 0x4eee, 0x3e3c,
+ 0x4efb, 0x3e39, 0x4f07, 0x3e36, 0x4f13, 0x3e33, 0x4f1f, 0x3e30,
+ 0x4f2b, 0x3e2d, 0x4f38, 0x3e2a, 0x4f44, 0x3e27, 0x4f50, 0x3e24,
+ 0x4f5c, 0x3e21, 0x4f68, 0x3e1e, 0x4f75, 0x3e1b, 0x4f81, 0x3e18,
+ 0x4f8d, 0x3e15, 0x4f99, 0x3e12, 0x4fa5, 0x3e0f, 0x4fb2, 0x3e0c,
+ 0x4fbe, 0x3e09, 0x4fca, 0x3e06, 0x4fd6, 0x3e03, 0x4fe2, 0x3dff,
+ 0x4fee, 0x3dfc, 0x4ffb, 0x3df9, 0x5007, 0x3df6, 0x5013, 0x3df3,
+ 0x501f, 0x3df0, 0x502b, 0x3ded, 0x5037, 0x3de9, 0x5044, 0x3de6,
+ 0x5050, 0x3de3, 0x505c, 0x3de0, 0x5068, 0x3ddd, 0x5074, 0x3dd9,
+ 0x5080, 0x3dd6, 0x508c, 0x3dd3, 0x5099, 0x3dd0, 0x50a5, 0x3dcc,
+ 0x50b1, 0x3dc9, 0x50bd, 0x3dc6, 0x50c9, 0x3dc2, 0x50d5, 0x3dbf,
+ 0x50e1, 0x3dbc, 0x50ed, 0x3db9, 0x50fa, 0x3db5, 0x5106, 0x3db2,
+ 0x5112, 0x3daf, 0x511e, 0x3dab, 0x512a, 0x3da8, 0x5136, 0x3da4,
+ 0x5142, 0x3da1, 0x514e, 0x3d9e, 0x515a, 0x3d9a, 0x5167, 0x3d97,
+ 0x5173, 0x3d93, 0x517f, 0x3d90, 0x518b, 0x3d8d, 0x5197, 0x3d89,
+ 0x51a3, 0x3d86, 0x51af, 0x3d82, 0x51bb, 0x3d7f, 0x51c7, 0x3d7b,
+ 0x51d3, 0x3d78, 0x51df, 0x3d74, 0x51eb, 0x3d71, 0x51f7, 0x3d6d,
+ 0x5204, 0x3d6a, 0x5210, 0x3d66, 0x521c, 0x3d63, 0x5228, 0x3d5f,
+ 0x5234, 0x3d5b, 0x5240, 0x3d58, 0x524c, 0x3d54, 0x5258, 0x3d51,
+ 0x5264, 0x3d4d, 0x5270, 0x3d49, 0x527c, 0x3d46, 0x5288, 0x3d42,
+ 0x5294, 0x3d3f, 0x52a0, 0x3d3b, 0x52ac, 0x3d37, 0x52b8, 0x3d34,
+ 0x52c4, 0x3d30, 0x52d0, 0x3d2c, 0x52dc, 0x3d28, 0x52e8, 0x3d25,
+ 0x52f4, 0x3d21, 0x5300, 0x3d1d, 0x530c, 0x3d1a, 0x5318, 0x3d16,
+ 0x5324, 0x3d12, 0x5330, 0x3d0e, 0x533c, 0x3d0b, 0x5348, 0x3d07,
+ 0x5354, 0x3d03, 0x5360, 0x3cff, 0x536c, 0x3cfb, 0x5378, 0x3cf8,
+ 0x5384, 0x3cf4, 0x5390, 0x3cf0, 0x539c, 0x3cec, 0x53a8, 0x3ce8,
+ 0x53b4, 0x3ce4, 0x53c0, 0x3ce0, 0x53cc, 0x3cdd, 0x53d8, 0x3cd9,
+ 0x53e4, 0x3cd5, 0x53f0, 0x3cd1, 0x53fb, 0x3ccd, 0x5407, 0x3cc9,
+ 0x5413, 0x3cc5, 0x541f, 0x3cc1, 0x542b, 0x3cbd, 0x5437, 0x3cb9,
+ 0x5443, 0x3cb5, 0x544f, 0x3cb1, 0x545b, 0x3cad, 0x5467, 0x3ca9,
+ 0x5473, 0x3ca5, 0x547f, 0x3ca1, 0x548b, 0x3c9d, 0x5496, 0x3c99,
+ 0x54a2, 0x3c95, 0x54ae, 0x3c91, 0x54ba, 0x3c8d, 0x54c6, 0x3c89,
+ 0x54d2, 0x3c85, 0x54de, 0x3c81, 0x54ea, 0x3c7d, 0x54f6, 0x3c79,
+ 0x5501, 0x3c74, 0x550d, 0x3c70, 0x5519, 0x3c6c, 0x5525, 0x3c68,
+ 0x5531, 0x3c64, 0x553d, 0x3c60, 0x5549, 0x3c5b, 0x5554, 0x3c57,
+ 0x5560, 0x3c53, 0x556c, 0x3c4f, 0x5578, 0x3c4b, 0x5584, 0x3c46,
+ 0x5590, 0x3c42, 0x559b, 0x3c3e, 0x55a7, 0x3c3a, 0x55b3, 0x3c36,
+ 0x55bf, 0x3c31, 0x55cb, 0x3c2d, 0x55d7, 0x3c29, 0x55e2, 0x3c24,
+ 0x55ee, 0x3c20, 0x55fa, 0x3c1c, 0x5606, 0x3c17, 0x5612, 0x3c13,
+ 0x561d, 0x3c0f, 0x5629, 0x3c0a, 0x5635, 0x3c06, 0x5641, 0x3c02,
+ 0x564c, 0x3bfd, 0x5658, 0x3bf9, 0x5664, 0x3bf5, 0x5670, 0x3bf0,
+ 0x567c, 0x3bec, 0x5687, 0x3be7, 0x5693, 0x3be3, 0x569f, 0x3bde,
+ 0x56ab, 0x3bda, 0x56b6, 0x3bd6, 0x56c2, 0x3bd1, 0x56ce, 0x3bcd,
+ 0x56da, 0x3bc8, 0x56e5, 0x3bc4, 0x56f1, 0x3bbf, 0x56fd, 0x3bbb,
+ 0x5709, 0x3bb6, 0x5714, 0x3bb2, 0x5720, 0x3bad, 0x572c, 0x3ba9,
+ 0x5737, 0x3ba4, 0x5743, 0x3b9f, 0x574f, 0x3b9b, 0x575b, 0x3b96,
+ 0x5766, 0x3b92, 0x5772, 0x3b8d, 0x577e, 0x3b88, 0x5789, 0x3b84,
+ 0x5795, 0x3b7f, 0x57a1, 0x3b7b, 0x57ac, 0x3b76, 0x57b8, 0x3b71,
+ 0x57c4, 0x3b6d, 0x57cf, 0x3b68, 0x57db, 0x3b63, 0x57e7, 0x3b5f,
+ 0x57f2, 0x3b5a, 0x57fe, 0x3b55, 0x580a, 0x3b50, 0x5815, 0x3b4c,
+ 0x5821, 0x3b47, 0x582d, 0x3b42, 0x5838, 0x3b3e, 0x5844, 0x3b39,
+ 0x584f, 0x3b34, 0x585b, 0x3b2f, 0x5867, 0x3b2a, 0x5872, 0x3b26,
+ 0x587e, 0x3b21, 0x5889, 0x3b1c, 0x5895, 0x3b17, 0x58a1, 0x3b12,
+ 0x58ac, 0x3b0e, 0x58b8, 0x3b09, 0x58c3, 0x3b04, 0x58cf, 0x3aff,
+ 0x58db, 0x3afa, 0x58e6, 0x3af5, 0x58f2, 0x3af0, 0x58fd, 0x3aeb,
+ 0x5909, 0x3ae6, 0x5914, 0x3ae2, 0x5920, 0x3add, 0x592c, 0x3ad8,
+ 0x5937, 0x3ad3, 0x5943, 0x3ace, 0x594e, 0x3ac9, 0x595a, 0x3ac4,
+ 0x5965, 0x3abf, 0x5971, 0x3aba, 0x597c, 0x3ab5, 0x5988, 0x3ab0,
+ 0x5993, 0x3aab, 0x599f, 0x3aa6, 0x59aa, 0x3aa1, 0x59b6, 0x3a9c,
+ 0x59c1, 0x3a97, 0x59cd, 0x3a92, 0x59d8, 0x3a8d, 0x59e4, 0x3a88,
+ 0x59ef, 0x3a82, 0x59fb, 0x3a7d, 0x5a06, 0x3a78, 0x5a12, 0x3a73,
+ 0x5a1d, 0x3a6e, 0x5a29, 0x3a69, 0x5a34, 0x3a64, 0x5a40, 0x3a5f,
+ 0x5a4b, 0x3a59, 0x5a57, 0x3a54, 0x5a62, 0x3a4f, 0x5a6e, 0x3a4a,
+ 0x5a79, 0x3a45, 0x5a84, 0x3a3f, 0x5a90, 0x3a3a, 0x5a9b, 0x3a35,
+ 0x5aa7, 0x3a30, 0x5ab2, 0x3a2b, 0x5abe, 0x3a25, 0x5ac9, 0x3a20,
+ 0x5ad4, 0x3a1b, 0x5ae0, 0x3a16, 0x5aeb, 0x3a10, 0x5af7, 0x3a0b,
+ 0x5b02, 0x3a06, 0x5b0d, 0x3a00, 0x5b19, 0x39fb, 0x5b24, 0x39f6,
+ 0x5b30, 0x39f0, 0x5b3b, 0x39eb, 0x5b46, 0x39e6, 0x5b52, 0x39e0,
+ 0x5b5d, 0x39db, 0x5b68, 0x39d6, 0x5b74, 0x39d0, 0x5b7f, 0x39cb,
+ 0x5b8a, 0x39c5, 0x5b96, 0x39c0, 0x5ba1, 0x39bb, 0x5bac, 0x39b5,
+ 0x5bb8, 0x39b0, 0x5bc3, 0x39aa, 0x5bce, 0x39a5, 0x5bda, 0x399f,
+ 0x5be5, 0x399a, 0x5bf0, 0x3994, 0x5bfc, 0x398f, 0x5c07, 0x3989,
+ 0x5c12, 0x3984, 0x5c1e, 0x397e, 0x5c29, 0x3979, 0x5c34, 0x3973,
+ 0x5c3f, 0x396e, 0x5c4b, 0x3968, 0x5c56, 0x3963, 0x5c61, 0x395d,
+ 0x5c6c, 0x3958, 0x5c78, 0x3952, 0x5c83, 0x394c, 0x5c8e, 0x3947,
+ 0x5c99, 0x3941, 0x5ca5, 0x393b, 0x5cb0, 0x3936, 0x5cbb, 0x3930,
+ 0x5cc6, 0x392b, 0x5cd2, 0x3925, 0x5cdd, 0x391f, 0x5ce8, 0x391a,
+ 0x5cf3, 0x3914, 0x5cff, 0x390e, 0x5d0a, 0x3909, 0x5d15, 0x3903,
+ 0x5d20, 0x38fd, 0x5d2b, 0x38f7, 0x5d36, 0x38f2, 0x5d42, 0x38ec,
+ 0x5d4d, 0x38e6, 0x5d58, 0x38e0, 0x5d63, 0x38db, 0x5d6e, 0x38d5,
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+ 0x75c1, 0x22bc, 0x75c8, 0x22b2, 0x75ce, 0x22a7, 0x75d5, 0x229d,
+ 0x75dc, 0x2292, 0x75e3, 0x2288, 0x75ea, 0x227d, 0x75f0, 0x2272,
+ 0x75f7, 0x2268, 0x75fe, 0x225d, 0x7605, 0x2253, 0x760b, 0x2248,
+ 0x7612, 0x223d, 0x7619, 0x2233, 0x7620, 0x2228, 0x7626, 0x221e,
+ 0x762d, 0x2213, 0x7634, 0x2208, 0x763a, 0x21fe, 0x7641, 0x21f3,
+ 0x7648, 0x21e8, 0x764e, 0x21de, 0x7655, 0x21d3, 0x765c, 0x21c8,
+ 0x7662, 0x21be, 0x7669, 0x21b3, 0x766f, 0x21a8, 0x7676, 0x219e,
+ 0x767d, 0x2193, 0x7683, 0x2188, 0x768a, 0x217d, 0x7690, 0x2173,
+ 0x7697, 0x2168, 0x769d, 0x215d, 0x76a4, 0x2153, 0x76ab, 0x2148,
+ 0x76b1, 0x213d, 0x76b8, 0x2132, 0x76be, 0x2128, 0x76c5, 0x211d,
+ 0x76cb, 0x2112, 0x76d2, 0x2107, 0x76d8, 0x20fd, 0x76df, 0x20f2,
+ 0x76e5, 0x20e7, 0x76eb, 0x20dc, 0x76f2, 0x20d1, 0x76f8, 0x20c7,
+ 0x76ff, 0x20bc, 0x7705, 0x20b1, 0x770c, 0x20a6, 0x7712, 0x209b,
+ 0x7718, 0x2091, 0x771f, 0x2086, 0x7725, 0x207b, 0x772c, 0x2070,
+ 0x7732, 0x2065, 0x7738, 0x205b, 0x773f, 0x2050, 0x7745, 0x2045,
+ 0x774b, 0x203a, 0x7752, 0x202f, 0x7758, 0x2024, 0x775e, 0x2019,
+ 0x7765, 0x200f, 0x776b, 0x2004, 0x7771, 0x1ff9, 0x7777, 0x1fee,
+ 0x777e, 0x1fe3, 0x7784, 0x1fd8, 0x778a, 0x1fcd, 0x7790, 0x1fc2,
+ 0x7797, 0x1fb7, 0x779d, 0x1fac, 0x77a3, 0x1fa2, 0x77a9, 0x1f97,
+ 0x77b0, 0x1f8c, 0x77b6, 0x1f81, 0x77bc, 0x1f76, 0x77c2, 0x1f6b,
+ 0x77c8, 0x1f60, 0x77ce, 0x1f55, 0x77d5, 0x1f4a, 0x77db, 0x1f3f,
+ 0x77e1, 0x1f34, 0x77e7, 0x1f29, 0x77ed, 0x1f1e, 0x77f3, 0x1f13,
+ 0x77f9, 0x1f08, 0x77ff, 0x1efd, 0x7805, 0x1ef2, 0x780b, 0x1ee7,
+ 0x7812, 0x1edc, 0x7818, 0x1ed1, 0x781e, 0x1ec6, 0x7824, 0x1ebb,
+ 0x782a, 0x1eb0, 0x7830, 0x1ea5, 0x7836, 0x1e9a, 0x783c, 0x1e8f,
+ 0x7842, 0x1e84, 0x7848, 0x1e79, 0x784e, 0x1e6e, 0x7854, 0x1e63,
+ 0x785a, 0x1e58, 0x7860, 0x1e4d, 0x7866, 0x1e42, 0x786b, 0x1e36,
+ 0x7871, 0x1e2b, 0x7877, 0x1e20, 0x787d, 0x1e15, 0x7883, 0x1e0a,
+ 0x7889, 0x1dff, 0x788f, 0x1df4, 0x7895, 0x1de9, 0x789b, 0x1dde,
+ 0x78a1, 0x1dd3, 0x78a6, 0x1dc7, 0x78ac, 0x1dbc, 0x78b2, 0x1db1,
+ 0x78b8, 0x1da6, 0x78be, 0x1d9b, 0x78c3, 0x1d90, 0x78c9, 0x1d85,
+ 0x78cf, 0x1d79, 0x78d5, 0x1d6e, 0x78db, 0x1d63, 0x78e0, 0x1d58,
+ 0x78e6, 0x1d4d, 0x78ec, 0x1d42, 0x78f2, 0x1d36, 0x78f7, 0x1d2b,
+ 0x78fd, 0x1d20, 0x7903, 0x1d15, 0x7909, 0x1d0a, 0x790e, 0x1cff,
+ 0x7914, 0x1cf3, 0x791a, 0x1ce8, 0x791f, 0x1cdd, 0x7925, 0x1cd2,
+ 0x792b, 0x1cc6, 0x7930, 0x1cbb, 0x7936, 0x1cb0, 0x793b, 0x1ca5,
+ 0x7941, 0x1c99, 0x7947, 0x1c8e, 0x794c, 0x1c83, 0x7952, 0x1c78,
+ 0x7958, 0x1c6c, 0x795d, 0x1c61, 0x7963, 0x1c56, 0x7968, 0x1c4b,
+ 0x796e, 0x1c3f, 0x7973, 0x1c34, 0x7979, 0x1c29, 0x797e, 0x1c1e,
+ 0x7984, 0x1c12, 0x7989, 0x1c07, 0x798f, 0x1bfc, 0x7994, 0x1bf0,
+ 0x799a, 0x1be5, 0x799f, 0x1bda, 0x79a5, 0x1bce, 0x79aa, 0x1bc3,
+ 0x79b0, 0x1bb8, 0x79b5, 0x1bac, 0x79bb, 0x1ba1, 0x79c0, 0x1b96,
+ 0x79c5, 0x1b8a, 0x79cb, 0x1b7f, 0x79d0, 0x1b74, 0x79d6, 0x1b68,
+ 0x79db, 0x1b5d, 0x79e0, 0x1b52, 0x79e6, 0x1b46, 0x79eb, 0x1b3b,
+ 0x79f0, 0x1b30, 0x79f6, 0x1b24, 0x79fb, 0x1b19, 0x7a00, 0x1b0d,
+ 0x7a06, 0x1b02, 0x7a0b, 0x1af7, 0x7a10, 0x1aeb, 0x7a16, 0x1ae0,
+ 0x7a1b, 0x1ad4, 0x7a20, 0x1ac9, 0x7a25, 0x1abe, 0x7a2b, 0x1ab2,
+ 0x7a30, 0x1aa7, 0x7a35, 0x1a9b, 0x7a3a, 0x1a90, 0x7a3f, 0x1a84,
+ 0x7a45, 0x1a79, 0x7a4a, 0x1a6e, 0x7a4f, 0x1a62, 0x7a54, 0x1a57,
+ 0x7a59, 0x1a4b, 0x7a5f, 0x1a40, 0x7a64, 0x1a34, 0x7a69, 0x1a29,
+ 0x7a6e, 0x1a1d, 0x7a73, 0x1a12, 0x7a78, 0x1a06, 0x7a7d, 0x19fb,
+ 0x7a82, 0x19ef, 0x7a88, 0x19e4, 0x7a8d, 0x19d8, 0x7a92, 0x19cd,
+ 0x7a97, 0x19c1, 0x7a9c, 0x19b6, 0x7aa1, 0x19aa, 0x7aa6, 0x199f,
+ 0x7aab, 0x1993, 0x7ab0, 0x1988, 0x7ab5, 0x197c, 0x7aba, 0x1971,
+ 0x7abf, 0x1965, 0x7ac4, 0x195a, 0x7ac9, 0x194e, 0x7ace, 0x1943,
+ 0x7ad3, 0x1937, 0x7ad8, 0x192c, 0x7add, 0x1920, 0x7ae2, 0x1914,
+ 0x7ae6, 0x1909, 0x7aeb, 0x18fd, 0x7af0, 0x18f2, 0x7af5, 0x18e6,
+ 0x7afa, 0x18db, 0x7aff, 0x18cf, 0x7b04, 0x18c3, 0x7b09, 0x18b8,
+ 0x7b0e, 0x18ac, 0x7b12, 0x18a1, 0x7b17, 0x1895, 0x7b1c, 0x1889,
+ 0x7b21, 0x187e, 0x7b26, 0x1872, 0x7b2a, 0x1867, 0x7b2f, 0x185b,
+ 0x7b34, 0x184f, 0x7b39, 0x1844, 0x7b3e, 0x1838, 0x7b42, 0x182d,
+ 0x7b47, 0x1821, 0x7b4c, 0x1815, 0x7b50, 0x180a, 0x7b55, 0x17fe,
+ 0x7b5a, 0x17f2, 0x7b5f, 0x17e7, 0x7b63, 0x17db, 0x7b68, 0x17cf,
+ 0x7b6d, 0x17c4, 0x7b71, 0x17b8, 0x7b76, 0x17ac, 0x7b7b, 0x17a1,
+ 0x7b7f, 0x1795, 0x7b84, 0x1789, 0x7b88, 0x177e, 0x7b8d, 0x1772,
+ 0x7b92, 0x1766, 0x7b96, 0x175b, 0x7b9b, 0x174f, 0x7b9f, 0x1743,
+ 0x7ba4, 0x1737, 0x7ba9, 0x172c, 0x7bad, 0x1720, 0x7bb2, 0x1714,
+ 0x7bb6, 0x1709, 0x7bbb, 0x16fd, 0x7bbf, 0x16f1, 0x7bc4, 0x16e5,
+ 0x7bc8, 0x16da, 0x7bcd, 0x16ce, 0x7bd1, 0x16c2, 0x7bd6, 0x16b6,
+ 0x7bda, 0x16ab, 0x7bde, 0x169f, 0x7be3, 0x1693, 0x7be7, 0x1687,
+ 0x7bec, 0x167c, 0x7bf0, 0x1670, 0x7bf5, 0x1664, 0x7bf9, 0x1658,
+ 0x7bfd, 0x164c, 0x7c02, 0x1641, 0x7c06, 0x1635, 0x7c0a, 0x1629,
+ 0x7c0f, 0x161d, 0x7c13, 0x1612, 0x7c17, 0x1606, 0x7c1c, 0x15fa,
+ 0x7c20, 0x15ee, 0x7c24, 0x15e2, 0x7c29, 0x15d7, 0x7c2d, 0x15cb,
+ 0x7c31, 0x15bf, 0x7c36, 0x15b3, 0x7c3a, 0x15a7, 0x7c3e, 0x159b,
+ 0x7c42, 0x1590, 0x7c46, 0x1584, 0x7c4b, 0x1578, 0x7c4f, 0x156c,
+ 0x7c53, 0x1560, 0x7c57, 0x1554, 0x7c5b, 0x1549, 0x7c60, 0x153d,
+ 0x7c64, 0x1531, 0x7c68, 0x1525, 0x7c6c, 0x1519, 0x7c70, 0x150d,
+ 0x7c74, 0x1501, 0x7c79, 0x14f6, 0x7c7d, 0x14ea, 0x7c81, 0x14de,
+ 0x7c85, 0x14d2, 0x7c89, 0x14c6, 0x7c8d, 0x14ba, 0x7c91, 0x14ae,
+ 0x7c95, 0x14a2, 0x7c99, 0x1496, 0x7c9d, 0x148b, 0x7ca1, 0x147f,
+ 0x7ca5, 0x1473, 0x7ca9, 0x1467, 0x7cad, 0x145b, 0x7cb1, 0x144f,
+ 0x7cb5, 0x1443, 0x7cb9, 0x1437, 0x7cbd, 0x142b, 0x7cc1, 0x141f,
+ 0x7cc5, 0x1413, 0x7cc9, 0x1407, 0x7ccd, 0x13fb, 0x7cd1, 0x13f0,
+ 0x7cd5, 0x13e4, 0x7cd9, 0x13d8, 0x7cdd, 0x13cc, 0x7ce0, 0x13c0,
+ 0x7ce4, 0x13b4, 0x7ce8, 0x13a8, 0x7cec, 0x139c, 0x7cf0, 0x1390,
+ 0x7cf4, 0x1384, 0x7cf8, 0x1378, 0x7cfb, 0x136c, 0x7cff, 0x1360,
+ 0x7d03, 0x1354, 0x7d07, 0x1348, 0x7d0b, 0x133c, 0x7d0e, 0x1330,
+ 0x7d12, 0x1324, 0x7d16, 0x1318, 0x7d1a, 0x130c, 0x7d1d, 0x1300,
+ 0x7d21, 0x12f4, 0x7d25, 0x12e8, 0x7d28, 0x12dc, 0x7d2c, 0x12d0,
+ 0x7d30, 0x12c4, 0x7d34, 0x12b8, 0x7d37, 0x12ac, 0x7d3b, 0x12a0,
+ 0x7d3f, 0x1294, 0x7d42, 0x1288, 0x7d46, 0x127c, 0x7d49, 0x1270,
+ 0x7d4d, 0x1264, 0x7d51, 0x1258, 0x7d54, 0x124c, 0x7d58, 0x1240,
+ 0x7d5b, 0x1234, 0x7d5f, 0x1228, 0x7d63, 0x121c, 0x7d66, 0x1210,
+ 0x7d6a, 0x1204, 0x7d6d, 0x11f7, 0x7d71, 0x11eb, 0x7d74, 0x11df,
+ 0x7d78, 0x11d3, 0x7d7b, 0x11c7, 0x7d7f, 0x11bb, 0x7d82, 0x11af,
+ 0x7d86, 0x11a3, 0x7d89, 0x1197, 0x7d8d, 0x118b, 0x7d90, 0x117f,
+ 0x7d93, 0x1173, 0x7d97, 0x1167, 0x7d9a, 0x115a, 0x7d9e, 0x114e,
+ 0x7da1, 0x1142, 0x7da4, 0x1136, 0x7da8, 0x112a, 0x7dab, 0x111e,
+ 0x7daf, 0x1112, 0x7db2, 0x1106, 0x7db5, 0x10fa, 0x7db9, 0x10ed,
+ 0x7dbc, 0x10e1, 0x7dbf, 0x10d5, 0x7dc2, 0x10c9, 0x7dc6, 0x10bd,
+ 0x7dc9, 0x10b1, 0x7dcc, 0x10a5, 0x7dd0, 0x1099, 0x7dd3, 0x108c,
+ 0x7dd6, 0x1080, 0x7dd9, 0x1074, 0x7ddd, 0x1068, 0x7de0, 0x105c,
+ 0x7de3, 0x1050, 0x7de6, 0x1044, 0x7de9, 0x1037, 0x7ded, 0x102b,
+ 0x7df0, 0x101f, 0x7df3, 0x1013, 0x7df6, 0x1007, 0x7df9, 0xffb,
+ 0x7dfc, 0xfee, 0x7dff, 0xfe2, 0x7e03, 0xfd6, 0x7e06, 0xfca,
+ 0x7e09, 0xfbe, 0x7e0c, 0xfb2, 0x7e0f, 0xfa5, 0x7e12, 0xf99,
+ 0x7e15, 0xf8d, 0x7e18, 0xf81, 0x7e1b, 0xf75, 0x7e1e, 0xf68,
+ 0x7e21, 0xf5c, 0x7e24, 0xf50, 0x7e27, 0xf44, 0x7e2a, 0xf38,
+ 0x7e2d, 0xf2b, 0x7e30, 0xf1f, 0x7e33, 0xf13, 0x7e36, 0xf07,
+ 0x7e39, 0xefb, 0x7e3c, 0xeee, 0x7e3f, 0xee2, 0x7e42, 0xed6,
+ 0x7e45, 0xeca, 0x7e48, 0xebd, 0x7e4a, 0xeb1, 0x7e4d, 0xea5,
+ 0x7e50, 0xe99, 0x7e53, 0xe8c, 0x7e56, 0xe80, 0x7e59, 0xe74,
+ 0x7e5c, 0xe68, 0x7e5e, 0xe5c, 0x7e61, 0xe4f, 0x7e64, 0xe43,
+ 0x7e67, 0xe37, 0x7e6a, 0xe2b, 0x7e6c, 0xe1e, 0x7e6f, 0xe12,
+ 0x7e72, 0xe06, 0x7e75, 0xdf9, 0x7e77, 0xded, 0x7e7a, 0xde1,
+ 0x7e7d, 0xdd5, 0x7e80, 0xdc8, 0x7e82, 0xdbc, 0x7e85, 0xdb0,
+ 0x7e88, 0xda4, 0x7e8a, 0xd97, 0x7e8d, 0xd8b, 0x7e90, 0xd7f,
+ 0x7e92, 0xd72, 0x7e95, 0xd66, 0x7e98, 0xd5a, 0x7e9a, 0xd4e,
+ 0x7e9d, 0xd41, 0x7e9f, 0xd35, 0x7ea2, 0xd29, 0x7ea5, 0xd1c,
+ 0x7ea7, 0xd10, 0x7eaa, 0xd04, 0x7eac, 0xcf8, 0x7eaf, 0xceb,
+ 0x7eb1, 0xcdf, 0x7eb4, 0xcd3, 0x7eb6, 0xcc6, 0x7eb9, 0xcba,
+ 0x7ebb, 0xcae, 0x7ebe, 0xca1, 0x7ec0, 0xc95, 0x7ec3, 0xc89,
+ 0x7ec5, 0xc7c, 0x7ec8, 0xc70, 0x7eca, 0xc64, 0x7ecc, 0xc57,
+ 0x7ecf, 0xc4b, 0x7ed1, 0xc3f, 0x7ed4, 0xc32, 0x7ed6, 0xc26,
+ 0x7ed8, 0xc1a, 0x7edb, 0xc0d, 0x7edd, 0xc01, 0x7ee0, 0xbf5,
+ 0x7ee2, 0xbe8, 0x7ee4, 0xbdc, 0x7ee7, 0xbd0, 0x7ee9, 0xbc3,
+ 0x7eeb, 0xbb7, 0x7eed, 0xbab, 0x7ef0, 0xb9e, 0x7ef2, 0xb92,
+ 0x7ef4, 0xb85, 0x7ef7, 0xb79, 0x7ef9, 0xb6d, 0x7efb, 0xb60,
+ 0x7efd, 0xb54, 0x7f00, 0xb48, 0x7f02, 0xb3b, 0x7f04, 0xb2f,
+ 0x7f06, 0xb23, 0x7f08, 0xb16, 0x7f0a, 0xb0a, 0x7f0d, 0xafd,
+ 0x7f0f, 0xaf1, 0x7f11, 0xae5, 0x7f13, 0xad8, 0x7f15, 0xacc,
+ 0x7f17, 0xac0, 0x7f19, 0xab3, 0x7f1c, 0xaa7, 0x7f1e, 0xa9a,
+ 0x7f20, 0xa8e, 0x7f22, 0xa82, 0x7f24, 0xa75, 0x7f26, 0xa69,
+ 0x7f28, 0xa5c, 0x7f2a, 0xa50, 0x7f2c, 0xa44, 0x7f2e, 0xa37,
+ 0x7f30, 0xa2b, 0x7f32, 0xa1e, 0x7f34, 0xa12, 0x7f36, 0xa06,
+ 0x7f38, 0x9f9, 0x7f3a, 0x9ed, 0x7f3c, 0x9e0, 0x7f3e, 0x9d4,
+ 0x7f40, 0x9c7, 0x7f42, 0x9bb, 0x7f43, 0x9af, 0x7f45, 0x9a2,
+ 0x7f47, 0x996, 0x7f49, 0x989, 0x7f4b, 0x97d, 0x7f4d, 0x970,
+ 0x7f4f, 0x964, 0x7f51, 0x958, 0x7f52, 0x94b, 0x7f54, 0x93f,
+ 0x7f56, 0x932, 0x7f58, 0x926, 0x7f5a, 0x919, 0x7f5b, 0x90d,
+ 0x7f5d, 0x901, 0x7f5f, 0x8f4, 0x7f61, 0x8e8, 0x7f62, 0x8db,
+ 0x7f64, 0x8cf, 0x7f66, 0x8c2, 0x7f68, 0x8b6, 0x7f69, 0x8a9,
+ 0x7f6b, 0x89d, 0x7f6d, 0x891, 0x7f6e, 0x884, 0x7f70, 0x878,
+ 0x7f72, 0x86b, 0x7f73, 0x85f, 0x7f75, 0x852, 0x7f77, 0x846,
+ 0x7f78, 0x839, 0x7f7a, 0x82d, 0x7f7b, 0x820, 0x7f7d, 0x814,
+ 0x7f7f, 0x807, 0x7f80, 0x7fb, 0x7f82, 0x7ef, 0x7f83, 0x7e2,
+ 0x7f85, 0x7d6, 0x7f86, 0x7c9, 0x7f88, 0x7bd, 0x7f89, 0x7b0,
+ 0x7f8b, 0x7a4, 0x7f8c, 0x797, 0x7f8e, 0x78b, 0x7f8f, 0x77e,
+ 0x7f91, 0x772, 0x7f92, 0x765, 0x7f94, 0x759, 0x7f95, 0x74c,
+ 0x7f97, 0x740, 0x7f98, 0x733, 0x7f99, 0x727, 0x7f9b, 0x71a,
+ 0x7f9c, 0x70e, 0x7f9e, 0x701, 0x7f9f, 0x6f5, 0x7fa0, 0x6e8,
+ 0x7fa2, 0x6dc, 0x7fa3, 0x6cf, 0x7fa4, 0x6c3, 0x7fa6, 0x6b6,
+ 0x7fa7, 0x6aa, 0x7fa8, 0x69d, 0x7faa, 0x691, 0x7fab, 0x684,
+ 0x7fac, 0x678, 0x7fad, 0x66b, 0x7faf, 0x65f, 0x7fb0, 0x652,
+ 0x7fb1, 0x646, 0x7fb2, 0x639, 0x7fb4, 0x62d, 0x7fb5, 0x620,
+ 0x7fb6, 0x614, 0x7fb7, 0x607, 0x7fb8, 0x5fb, 0x7fb9, 0x5ee,
+ 0x7fbb, 0x5e2, 0x7fbc, 0x5d5, 0x7fbd, 0x5c9, 0x7fbe, 0x5bc,
+ 0x7fbf, 0x5b0, 0x7fc0, 0x5a3, 0x7fc1, 0x597, 0x7fc3, 0x58a,
+ 0x7fc4, 0x57e, 0x7fc5, 0x571, 0x7fc6, 0x565, 0x7fc7, 0x558,
+ 0x7fc8, 0x54c, 0x7fc9, 0x53f, 0x7fca, 0x533, 0x7fcb, 0x526,
+ 0x7fcc, 0x51a, 0x7fcd, 0x50d, 0x7fce, 0x500, 0x7fcf, 0x4f4,
+ 0x7fd0, 0x4e7, 0x7fd1, 0x4db, 0x7fd2, 0x4ce, 0x7fd3, 0x4c2,
+ 0x7fd4, 0x4b5, 0x7fd5, 0x4a9, 0x7fd5, 0x49c, 0x7fd6, 0x490,
+ 0x7fd7, 0x483, 0x7fd8, 0x477, 0x7fd9, 0x46a, 0x7fda, 0x45e,
+ 0x7fdb, 0x451, 0x7fdc, 0x444, 0x7fdc, 0x438, 0x7fdd, 0x42b,
+ 0x7fde, 0x41f, 0x7fdf, 0x412, 0x7fe0, 0x406, 0x7fe0, 0x3f9,
+ 0x7fe1, 0x3ed, 0x7fe2, 0x3e0, 0x7fe3, 0x3d4, 0x7fe3, 0x3c7,
+ 0x7fe4, 0x3bb, 0x7fe5, 0x3ae, 0x7fe6, 0x3a1, 0x7fe6, 0x395,
+ 0x7fe7, 0x388, 0x7fe8, 0x37c, 0x7fe8, 0x36f, 0x7fe9, 0x363,
+ 0x7fea, 0x356, 0x7fea, 0x34a, 0x7feb, 0x33d, 0x7fec, 0x330,
+ 0x7fec, 0x324, 0x7fed, 0x317, 0x7fed, 0x30b, 0x7fee, 0x2fe,
+ 0x7fef, 0x2f2, 0x7fef, 0x2e5, 0x7ff0, 0x2d9, 0x7ff0, 0x2cc,
+ 0x7ff1, 0x2c0, 0x7ff1, 0x2b3, 0x7ff2, 0x2a6, 0x7ff2, 0x29a,
+ 0x7ff3, 0x28d, 0x7ff3, 0x281, 0x7ff4, 0x274, 0x7ff4, 0x268,
+ 0x7ff5, 0x25b, 0x7ff5, 0x24e, 0x7ff6, 0x242, 0x7ff6, 0x235,
+ 0x7ff7, 0x229, 0x7ff7, 0x21c, 0x7ff7, 0x210, 0x7ff8, 0x203,
+ 0x7ff8, 0x1f7, 0x7ff9, 0x1ea, 0x7ff9, 0x1dd, 0x7ff9, 0x1d1,
+ 0x7ffa, 0x1c4, 0x7ffa, 0x1b8, 0x7ffa, 0x1ab, 0x7ffb, 0x19f,
+ 0x7ffb, 0x192, 0x7ffb, 0x186, 0x7ffc, 0x179, 0x7ffc, 0x16c,
+ 0x7ffc, 0x160, 0x7ffc, 0x153, 0x7ffd, 0x147, 0x7ffd, 0x13a,
+ 0x7ffd, 0x12e, 0x7ffd, 0x121, 0x7ffe, 0x114, 0x7ffe, 0x108,
+ 0x7ffe, 0xfb, 0x7ffe, 0xef, 0x7ffe, 0xe2, 0x7fff, 0xd6,
+ 0x7fff, 0xc9, 0x7fff, 0xbc, 0x7fff, 0xb0, 0x7fff, 0xa3,
+ 0x7fff, 0x97, 0x7fff, 0x8a, 0x7fff, 0x7e, 0x7fff, 0x71,
+ 0x7fff, 0x65, 0x7fff, 0x58, 0x7fff, 0x4b, 0x7fff, 0x3f,
+ 0x7fff, 0x32, 0x7fff, 0x26, 0x7fff, 0x19, 0x7fff, 0xd,
+ 0x7fff, 0x0, 0x7fff, 0xfff3, 0x7fff, 0xffe7, 0x7fff, 0xffda,
+ 0x7fff, 0xffce, 0x7fff, 0xffc1, 0x7fff, 0xffb5, 0x7fff, 0xffa8,
+ 0x7fff, 0xff9b, 0x7fff, 0xff8f, 0x7fff, 0xff82, 0x7fff, 0xff76,
+ 0x7fff, 0xff69, 0x7fff, 0xff5d, 0x7fff, 0xff50, 0x7fff, 0xff44,
+ 0x7fff, 0xff37, 0x7fff, 0xff2a, 0x7ffe, 0xff1e, 0x7ffe, 0xff11,
+ 0x7ffe, 0xff05, 0x7ffe, 0xfef8, 0x7ffe, 0xfeec, 0x7ffd, 0xfedf,
+ 0x7ffd, 0xfed2, 0x7ffd, 0xfec6, 0x7ffd, 0xfeb9, 0x7ffc, 0xfead,
+ 0x7ffc, 0xfea0, 0x7ffc, 0xfe94, 0x7ffc, 0xfe87, 0x7ffb, 0xfe7a,
+ 0x7ffb, 0xfe6e, 0x7ffb, 0xfe61, 0x7ffa, 0xfe55, 0x7ffa, 0xfe48,
+ 0x7ffa, 0xfe3c, 0x7ff9, 0xfe2f, 0x7ff9, 0xfe23, 0x7ff9, 0xfe16,
+ 0x7ff8, 0xfe09, 0x7ff8, 0xfdfd, 0x7ff7, 0xfdf0, 0x7ff7, 0xfde4,
+ 0x7ff7, 0xfdd7, 0x7ff6, 0xfdcb, 0x7ff6, 0xfdbe, 0x7ff5, 0xfdb2,
+ 0x7ff5, 0xfda5, 0x7ff4, 0xfd98, 0x7ff4, 0xfd8c, 0x7ff3, 0xfd7f,
+ 0x7ff3, 0xfd73, 0x7ff2, 0xfd66, 0x7ff2, 0xfd5a, 0x7ff1, 0xfd4d,
+ 0x7ff1, 0xfd40, 0x7ff0, 0xfd34, 0x7ff0, 0xfd27, 0x7fef, 0xfd1b,
+ 0x7fef, 0xfd0e, 0x7fee, 0xfd02, 0x7fed, 0xfcf5, 0x7fed, 0xfce9,
+ 0x7fec, 0xfcdc, 0x7fec, 0xfcd0, 0x7feb, 0xfcc3, 0x7fea, 0xfcb6,
+ 0x7fea, 0xfcaa, 0x7fe9, 0xfc9d, 0x7fe8, 0xfc91, 0x7fe8, 0xfc84,
+ 0x7fe7, 0xfc78, 0x7fe6, 0xfc6b, 0x7fe6, 0xfc5f, 0x7fe5, 0xfc52,
+ 0x7fe4, 0xfc45, 0x7fe3, 0xfc39, 0x7fe3, 0xfc2c, 0x7fe2, 0xfc20,
+ 0x7fe1, 0xfc13, 0x7fe0, 0xfc07, 0x7fe0, 0xfbfa, 0x7fdf, 0xfbee,
+ 0x7fde, 0xfbe1, 0x7fdd, 0xfbd5, 0x7fdc, 0xfbc8, 0x7fdc, 0xfbbc,
+ 0x7fdb, 0xfbaf, 0x7fda, 0xfba2, 0x7fd9, 0xfb96, 0x7fd8, 0xfb89,
+ 0x7fd7, 0xfb7d, 0x7fd6, 0xfb70, 0x7fd5, 0xfb64, 0x7fd5, 0xfb57,
+ 0x7fd4, 0xfb4b, 0x7fd3, 0xfb3e, 0x7fd2, 0xfb32, 0x7fd1, 0xfb25,
+ 0x7fd0, 0xfb19, 0x7fcf, 0xfb0c, 0x7fce, 0xfb00, 0x7fcd, 0xfaf3,
+ 0x7fcc, 0xfae6, 0x7fcb, 0xfada, 0x7fca, 0xfacd, 0x7fc9, 0xfac1,
+ 0x7fc8, 0xfab4, 0x7fc7, 0xfaa8, 0x7fc6, 0xfa9b, 0x7fc5, 0xfa8f,
+ 0x7fc4, 0xfa82, 0x7fc3, 0xfa76, 0x7fc1, 0xfa69, 0x7fc0, 0xfa5d,
+ 0x7fbf, 0xfa50, 0x7fbe, 0xfa44, 0x7fbd, 0xfa37, 0x7fbc, 0xfa2b,
+ 0x7fbb, 0xfa1e, 0x7fb9, 0xfa12, 0x7fb8, 0xfa05, 0x7fb7, 0xf9f9,
+ 0x7fb6, 0xf9ec, 0x7fb5, 0xf9e0, 0x7fb4, 0xf9d3, 0x7fb2, 0xf9c7,
+ 0x7fb1, 0xf9ba, 0x7fb0, 0xf9ae, 0x7faf, 0xf9a1, 0x7fad, 0xf995,
+ 0x7fac, 0xf988, 0x7fab, 0xf97c, 0x7faa, 0xf96f, 0x7fa8, 0xf963,
+ 0x7fa7, 0xf956, 0x7fa6, 0xf94a, 0x7fa4, 0xf93d, 0x7fa3, 0xf931,
+ 0x7fa2, 0xf924, 0x7fa0, 0xf918, 0x7f9f, 0xf90b, 0x7f9e, 0xf8ff,
+ 0x7f9c, 0xf8f2, 0x7f9b, 0xf8e6, 0x7f99, 0xf8d9, 0x7f98, 0xf8cd,
+ 0x7f97, 0xf8c0, 0x7f95, 0xf8b4, 0x7f94, 0xf8a7, 0x7f92, 0xf89b,
+ 0x7f91, 0xf88e, 0x7f8f, 0xf882, 0x7f8e, 0xf875, 0x7f8c, 0xf869,
+ 0x7f8b, 0xf85c, 0x7f89, 0xf850, 0x7f88, 0xf843, 0x7f86, 0xf837,
+ 0x7f85, 0xf82a, 0x7f83, 0xf81e, 0x7f82, 0xf811, 0x7f80, 0xf805,
+ 0x7f7f, 0xf7f9, 0x7f7d, 0xf7ec, 0x7f7b, 0xf7e0, 0x7f7a, 0xf7d3,
+ 0x7f78, 0xf7c7, 0x7f77, 0xf7ba, 0x7f75, 0xf7ae, 0x7f73, 0xf7a1,
+ 0x7f72, 0xf795, 0x7f70, 0xf788, 0x7f6e, 0xf77c, 0x7f6d, 0xf76f,
+ 0x7f6b, 0xf763, 0x7f69, 0xf757, 0x7f68, 0xf74a, 0x7f66, 0xf73e,
+ 0x7f64, 0xf731, 0x7f62, 0xf725, 0x7f61, 0xf718, 0x7f5f, 0xf70c,
+ 0x7f5d, 0xf6ff, 0x7f5b, 0xf6f3, 0x7f5a, 0xf6e7, 0x7f58, 0xf6da,
+ 0x7f56, 0xf6ce, 0x7f54, 0xf6c1, 0x7f52, 0xf6b5, 0x7f51, 0xf6a8,
+ 0x7f4f, 0xf69c, 0x7f4d, 0xf690, 0x7f4b, 0xf683, 0x7f49, 0xf677,
+ 0x7f47, 0xf66a, 0x7f45, 0xf65e, 0x7f43, 0xf651, 0x7f42, 0xf645,
+ 0x7f40, 0xf639, 0x7f3e, 0xf62c, 0x7f3c, 0xf620, 0x7f3a, 0xf613,
+ 0x7f38, 0xf607, 0x7f36, 0xf5fa, 0x7f34, 0xf5ee, 0x7f32, 0xf5e2,
+ 0x7f30, 0xf5d5, 0x7f2e, 0xf5c9, 0x7f2c, 0xf5bc, 0x7f2a, 0xf5b0,
+ 0x7f28, 0xf5a4, 0x7f26, 0xf597, 0x7f24, 0xf58b, 0x7f22, 0xf57e,
+ 0x7f20, 0xf572, 0x7f1e, 0xf566, 0x7f1c, 0xf559, 0x7f19, 0xf54d,
+ 0x7f17, 0xf540, 0x7f15, 0xf534, 0x7f13, 0xf528, 0x7f11, 0xf51b,
+ 0x7f0f, 0xf50f, 0x7f0d, 0xf503, 0x7f0a, 0xf4f6, 0x7f08, 0xf4ea,
+ 0x7f06, 0xf4dd, 0x7f04, 0xf4d1, 0x7f02, 0xf4c5, 0x7f00, 0xf4b8,
+ 0x7efd, 0xf4ac, 0x7efb, 0xf4a0, 0x7ef9, 0xf493, 0x7ef7, 0xf487,
+ 0x7ef4, 0xf47b, 0x7ef2, 0xf46e, 0x7ef0, 0xf462, 0x7eed, 0xf455,
+ 0x7eeb, 0xf449, 0x7ee9, 0xf43d, 0x7ee7, 0xf430, 0x7ee4, 0xf424,
+ 0x7ee2, 0xf418, 0x7ee0, 0xf40b, 0x7edd, 0xf3ff, 0x7edb, 0xf3f3,
+ 0x7ed8, 0xf3e6, 0x7ed6, 0xf3da, 0x7ed4, 0xf3ce, 0x7ed1, 0xf3c1,
+ 0x7ecf, 0xf3b5, 0x7ecc, 0xf3a9, 0x7eca, 0xf39c, 0x7ec8, 0xf390,
+ 0x7ec5, 0xf384, 0x7ec3, 0xf377, 0x7ec0, 0xf36b, 0x7ebe, 0xf35f,
+ 0x7ebb, 0xf352, 0x7eb9, 0xf346, 0x7eb6, 0xf33a, 0x7eb4, 0xf32d,
+ 0x7eb1, 0xf321, 0x7eaf, 0xf315, 0x7eac, 0xf308, 0x7eaa, 0xf2fc,
+ 0x7ea7, 0xf2f0, 0x7ea5, 0xf2e4, 0x7ea2, 0xf2d7, 0x7e9f, 0xf2cb,
+ 0x7e9d, 0xf2bf, 0x7e9a, 0xf2b2, 0x7e98, 0xf2a6, 0x7e95, 0xf29a,
+ 0x7e92, 0xf28e, 0x7e90, 0xf281, 0x7e8d, 0xf275, 0x7e8a, 0xf269,
+ 0x7e88, 0xf25c, 0x7e85, 0xf250, 0x7e82, 0xf244, 0x7e80, 0xf238,
+ 0x7e7d, 0xf22b, 0x7e7a, 0xf21f, 0x7e77, 0xf213, 0x7e75, 0xf207,
+ 0x7e72, 0xf1fa, 0x7e6f, 0xf1ee, 0x7e6c, 0xf1e2, 0x7e6a, 0xf1d5,
+ 0x7e67, 0xf1c9, 0x7e64, 0xf1bd, 0x7e61, 0xf1b1, 0x7e5e, 0xf1a4,
+ 0x7e5c, 0xf198, 0x7e59, 0xf18c, 0x7e56, 0xf180, 0x7e53, 0xf174,
+ 0x7e50, 0xf167, 0x7e4d, 0xf15b, 0x7e4a, 0xf14f, 0x7e48, 0xf143,
+ 0x7e45, 0xf136, 0x7e42, 0xf12a, 0x7e3f, 0xf11e, 0x7e3c, 0xf112,
+ 0x7e39, 0xf105, 0x7e36, 0xf0f9, 0x7e33, 0xf0ed, 0x7e30, 0xf0e1,
+ 0x7e2d, 0xf0d5, 0x7e2a, 0xf0c8, 0x7e27, 0xf0bc, 0x7e24, 0xf0b0,
+ 0x7e21, 0xf0a4, 0x7e1e, 0xf098, 0x7e1b, 0xf08b, 0x7e18, 0xf07f,
+ 0x7e15, 0xf073, 0x7e12, 0xf067, 0x7e0f, 0xf05b, 0x7e0c, 0xf04e,
+ 0x7e09, 0xf042, 0x7e06, 0xf036, 0x7e03, 0xf02a, 0x7dff, 0xf01e,
+ 0x7dfc, 0xf012, 0x7df9, 0xf005, 0x7df6, 0xeff9, 0x7df3, 0xefed,
+ 0x7df0, 0xefe1, 0x7ded, 0xefd5, 0x7de9, 0xefc9, 0x7de6, 0xefbc,
+ 0x7de3, 0xefb0, 0x7de0, 0xefa4, 0x7ddd, 0xef98, 0x7dd9, 0xef8c,
+ 0x7dd6, 0xef80, 0x7dd3, 0xef74, 0x7dd0, 0xef67, 0x7dcc, 0xef5b,
+ 0x7dc9, 0xef4f, 0x7dc6, 0xef43, 0x7dc2, 0xef37, 0x7dbf, 0xef2b,
+ 0x7dbc, 0xef1f, 0x7db9, 0xef13, 0x7db5, 0xef06, 0x7db2, 0xeefa,
+ 0x7daf, 0xeeee, 0x7dab, 0xeee2, 0x7da8, 0xeed6, 0x7da4, 0xeeca,
+ 0x7da1, 0xeebe, 0x7d9e, 0xeeb2, 0x7d9a, 0xeea6, 0x7d97, 0xee99,
+ 0x7d93, 0xee8d, 0x7d90, 0xee81, 0x7d8d, 0xee75, 0x7d89, 0xee69,
+ 0x7d86, 0xee5d, 0x7d82, 0xee51, 0x7d7f, 0xee45, 0x7d7b, 0xee39,
+ 0x7d78, 0xee2d, 0x7d74, 0xee21, 0x7d71, 0xee15, 0x7d6d, 0xee09,
+ 0x7d6a, 0xedfc, 0x7d66, 0xedf0, 0x7d63, 0xede4, 0x7d5f, 0xedd8,
+ 0x7d5b, 0xedcc, 0x7d58, 0xedc0, 0x7d54, 0xedb4, 0x7d51, 0xeda8,
+ 0x7d4d, 0xed9c, 0x7d49, 0xed90, 0x7d46, 0xed84, 0x7d42, 0xed78,
+ 0x7d3f, 0xed6c, 0x7d3b, 0xed60, 0x7d37, 0xed54, 0x7d34, 0xed48,
+ 0x7d30, 0xed3c, 0x7d2c, 0xed30, 0x7d28, 0xed24, 0x7d25, 0xed18,
+ 0x7d21, 0xed0c, 0x7d1d, 0xed00, 0x7d1a, 0xecf4, 0x7d16, 0xece8,
+ 0x7d12, 0xecdc, 0x7d0e, 0xecd0, 0x7d0b, 0xecc4, 0x7d07, 0xecb8,
+ 0x7d03, 0xecac, 0x7cff, 0xeca0, 0x7cfb, 0xec94, 0x7cf8, 0xec88,
+ 0x7cf4, 0xec7c, 0x7cf0, 0xec70, 0x7cec, 0xec64, 0x7ce8, 0xec58,
+ 0x7ce4, 0xec4c, 0x7ce0, 0xec40, 0x7cdd, 0xec34, 0x7cd9, 0xec28,
+ 0x7cd5, 0xec1c, 0x7cd1, 0xec10, 0x7ccd, 0xec05, 0x7cc9, 0xebf9,
+ 0x7cc5, 0xebed, 0x7cc1, 0xebe1, 0x7cbd, 0xebd5, 0x7cb9, 0xebc9,
+ 0x7cb5, 0xebbd, 0x7cb1, 0xebb1, 0x7cad, 0xeba5, 0x7ca9, 0xeb99,
+ 0x7ca5, 0xeb8d, 0x7ca1, 0xeb81, 0x7c9d, 0xeb75, 0x7c99, 0xeb6a,
+ 0x7c95, 0xeb5e, 0x7c91, 0xeb52, 0x7c8d, 0xeb46, 0x7c89, 0xeb3a,
+ 0x7c85, 0xeb2e, 0x7c81, 0xeb22, 0x7c7d, 0xeb16, 0x7c79, 0xeb0a,
+ 0x7c74, 0xeaff, 0x7c70, 0xeaf3, 0x7c6c, 0xeae7, 0x7c68, 0xeadb,
+ 0x7c64, 0xeacf, 0x7c60, 0xeac3, 0x7c5b, 0xeab7, 0x7c57, 0xeaac,
+ 0x7c53, 0xeaa0, 0x7c4f, 0xea94, 0x7c4b, 0xea88, 0x7c46, 0xea7c,
+ 0x7c42, 0xea70, 0x7c3e, 0xea65, 0x7c3a, 0xea59, 0x7c36, 0xea4d,
+ 0x7c31, 0xea41, 0x7c2d, 0xea35, 0x7c29, 0xea29, 0x7c24, 0xea1e,
+ 0x7c20, 0xea12, 0x7c1c, 0xea06, 0x7c17, 0xe9fa, 0x7c13, 0xe9ee,
+ 0x7c0f, 0xe9e3, 0x7c0a, 0xe9d7, 0x7c06, 0xe9cb, 0x7c02, 0xe9bf,
+ 0x7bfd, 0xe9b4, 0x7bf9, 0xe9a8, 0x7bf5, 0xe99c, 0x7bf0, 0xe990,
+ 0x7bec, 0xe984, 0x7be7, 0xe979, 0x7be3, 0xe96d, 0x7bde, 0xe961,
+ 0x7bda, 0xe955, 0x7bd6, 0xe94a, 0x7bd1, 0xe93e, 0x7bcd, 0xe932,
+ 0x7bc8, 0xe926, 0x7bc4, 0xe91b, 0x7bbf, 0xe90f, 0x7bbb, 0xe903,
+ 0x7bb6, 0xe8f7, 0x7bb2, 0xe8ec, 0x7bad, 0xe8e0, 0x7ba9, 0xe8d4,
+ 0x7ba4, 0xe8c9, 0x7b9f, 0xe8bd, 0x7b9b, 0xe8b1, 0x7b96, 0xe8a5,
+ 0x7b92, 0xe89a, 0x7b8d, 0xe88e, 0x7b88, 0xe882, 0x7b84, 0xe877,
+ 0x7b7f, 0xe86b, 0x7b7b, 0xe85f, 0x7b76, 0xe854, 0x7b71, 0xe848,
+ 0x7b6d, 0xe83c, 0x7b68, 0xe831, 0x7b63, 0xe825, 0x7b5f, 0xe819,
+ 0x7b5a, 0xe80e, 0x7b55, 0xe802, 0x7b50, 0xe7f6, 0x7b4c, 0xe7eb,
+ 0x7b47, 0xe7df, 0x7b42, 0xe7d3, 0x7b3e, 0xe7c8, 0x7b39, 0xe7bc,
+ 0x7b34, 0xe7b1, 0x7b2f, 0xe7a5, 0x7b2a, 0xe799, 0x7b26, 0xe78e,
+ 0x7b21, 0xe782, 0x7b1c, 0xe777, 0x7b17, 0xe76b, 0x7b12, 0xe75f,
+ 0x7b0e, 0xe754, 0x7b09, 0xe748, 0x7b04, 0xe73d, 0x7aff, 0xe731,
+ 0x7afa, 0xe725, 0x7af5, 0xe71a, 0x7af0, 0xe70e, 0x7aeb, 0xe703,
+ 0x7ae6, 0xe6f7, 0x7ae2, 0xe6ec, 0x7add, 0xe6e0, 0x7ad8, 0xe6d4,
+ 0x7ad3, 0xe6c9, 0x7ace, 0xe6bd, 0x7ac9, 0xe6b2, 0x7ac4, 0xe6a6,
+ 0x7abf, 0xe69b, 0x7aba, 0xe68f, 0x7ab5, 0xe684, 0x7ab0, 0xe678,
+ 0x7aab, 0xe66d, 0x7aa6, 0xe661, 0x7aa1, 0xe656, 0x7a9c, 0xe64a,
+ 0x7a97, 0xe63f, 0x7a92, 0xe633, 0x7a8d, 0xe628, 0x7a88, 0xe61c,
+ 0x7a82, 0xe611, 0x7a7d, 0xe605, 0x7a78, 0xe5fa, 0x7a73, 0xe5ee,
+ 0x7a6e, 0xe5e3, 0x7a69, 0xe5d7, 0x7a64, 0xe5cc, 0x7a5f, 0xe5c0,
+ 0x7a59, 0xe5b5, 0x7a54, 0xe5a9, 0x7a4f, 0xe59e, 0x7a4a, 0xe592,
+ 0x7a45, 0xe587, 0x7a3f, 0xe57c, 0x7a3a, 0xe570, 0x7a35, 0xe565,
+ 0x7a30, 0xe559, 0x7a2b, 0xe54e, 0x7a25, 0xe542, 0x7a20, 0xe537,
+ 0x7a1b, 0xe52c, 0x7a16, 0xe520, 0x7a10, 0xe515, 0x7a0b, 0xe509,
+ 0x7a06, 0xe4fe, 0x7a00, 0xe4f3, 0x79fb, 0xe4e7, 0x79f6, 0xe4dc,
+ 0x79f0, 0xe4d0, 0x79eb, 0xe4c5, 0x79e6, 0xe4ba, 0x79e0, 0xe4ae,
+ 0x79db, 0xe4a3, 0x79d6, 0xe498, 0x79d0, 0xe48c, 0x79cb, 0xe481,
+ 0x79c5, 0xe476, 0x79c0, 0xe46a, 0x79bb, 0xe45f, 0x79b5, 0xe454,
+ 0x79b0, 0xe448, 0x79aa, 0xe43d, 0x79a5, 0xe432, 0x799f, 0xe426,
+ 0x799a, 0xe41b, 0x7994, 0xe410, 0x798f, 0xe404, 0x7989, 0xe3f9,
+ 0x7984, 0xe3ee, 0x797e, 0xe3e2, 0x7979, 0xe3d7, 0x7973, 0xe3cc,
+ 0x796e, 0xe3c1, 0x7968, 0xe3b5, 0x7963, 0xe3aa, 0x795d, 0xe39f,
+ 0x7958, 0xe394, 0x7952, 0xe388, 0x794c, 0xe37d, 0x7947, 0xe372,
+ 0x7941, 0xe367, 0x793b, 0xe35b, 0x7936, 0xe350, 0x7930, 0xe345,
+ 0x792b, 0xe33a, 0x7925, 0xe32e, 0x791f, 0xe323, 0x791a, 0xe318,
+ 0x7914, 0xe30d, 0x790e, 0xe301, 0x7909, 0xe2f6, 0x7903, 0xe2eb,
+ 0x78fd, 0xe2e0, 0x78f7, 0xe2d5, 0x78f2, 0xe2ca, 0x78ec, 0xe2be,
+ 0x78e6, 0xe2b3, 0x78e0, 0xe2a8, 0x78db, 0xe29d, 0x78d5, 0xe292,
+ 0x78cf, 0xe287, 0x78c9, 0xe27b, 0x78c3, 0xe270, 0x78be, 0xe265,
+ 0x78b8, 0xe25a, 0x78b2, 0xe24f, 0x78ac, 0xe244, 0x78a6, 0xe239,
+ 0x78a1, 0xe22d, 0x789b, 0xe222, 0x7895, 0xe217, 0x788f, 0xe20c,
+ 0x7889, 0xe201, 0x7883, 0xe1f6, 0x787d, 0xe1eb, 0x7877, 0xe1e0,
+ 0x7871, 0xe1d5, 0x786b, 0xe1ca, 0x7866, 0xe1be, 0x7860, 0xe1b3,
+ 0x785a, 0xe1a8, 0x7854, 0xe19d, 0x784e, 0xe192, 0x7848, 0xe187,
+ 0x7842, 0xe17c, 0x783c, 0xe171, 0x7836, 0xe166, 0x7830, 0xe15b,
+ 0x782a, 0xe150, 0x7824, 0xe145, 0x781e, 0xe13a, 0x7818, 0xe12f,
+ 0x7812, 0xe124, 0x780b, 0xe119, 0x7805, 0xe10e, 0x77ff, 0xe103,
+ 0x77f9, 0xe0f8, 0x77f3, 0xe0ed, 0x77ed, 0xe0e2, 0x77e7, 0xe0d7,
+ 0x77e1, 0xe0cc, 0x77db, 0xe0c1, 0x77d5, 0xe0b6, 0x77ce, 0xe0ab,
+ 0x77c8, 0xe0a0, 0x77c2, 0xe095, 0x77bc, 0xe08a, 0x77b6, 0xe07f,
+ 0x77b0, 0xe074, 0x77a9, 0xe069, 0x77a3, 0xe05e, 0x779d, 0xe054,
+ 0x7797, 0xe049, 0x7790, 0xe03e, 0x778a, 0xe033, 0x7784, 0xe028,
+ 0x777e, 0xe01d, 0x7777, 0xe012, 0x7771, 0xe007, 0x776b, 0xdffc,
+ 0x7765, 0xdff1, 0x775e, 0xdfe7, 0x7758, 0xdfdc, 0x7752, 0xdfd1,
+ 0x774b, 0xdfc6, 0x7745, 0xdfbb, 0x773f, 0xdfb0, 0x7738, 0xdfa5,
+ 0x7732, 0xdf9b, 0x772c, 0xdf90, 0x7725, 0xdf85, 0x771f, 0xdf7a,
+ 0x7718, 0xdf6f, 0x7712, 0xdf65, 0x770c, 0xdf5a, 0x7705, 0xdf4f,
+ 0x76ff, 0xdf44, 0x76f8, 0xdf39, 0x76f2, 0xdf2f, 0x76eb, 0xdf24,
+ 0x76e5, 0xdf19, 0x76df, 0xdf0e, 0x76d8, 0xdf03, 0x76d2, 0xdef9,
+ 0x76cb, 0xdeee, 0x76c5, 0xdee3, 0x76be, 0xded8, 0x76b8, 0xdece,
+ 0x76b1, 0xdec3, 0x76ab, 0xdeb8, 0x76a4, 0xdead, 0x769d, 0xdea3,
+ 0x7697, 0xde98, 0x7690, 0xde8d, 0x768a, 0xde83, 0x7683, 0xde78,
+ 0x767d, 0xde6d, 0x7676, 0xde62, 0x766f, 0xde58, 0x7669, 0xde4d,
+ 0x7662, 0xde42, 0x765c, 0xde38, 0x7655, 0xde2d, 0x764e, 0xde22,
+ 0x7648, 0xde18, 0x7641, 0xde0d, 0x763a, 0xde02, 0x7634, 0xddf8,
+ 0x762d, 0xdded, 0x7626, 0xdde2, 0x7620, 0xddd8, 0x7619, 0xddcd,
+ 0x7612, 0xddc3, 0x760b, 0xddb8, 0x7605, 0xddad, 0x75fe, 0xdda3,
+ 0x75f7, 0xdd98, 0x75f0, 0xdd8e, 0x75ea, 0xdd83, 0x75e3, 0xdd78,
+ 0x75dc, 0xdd6e, 0x75d5, 0xdd63, 0x75ce, 0xdd59, 0x75c8, 0xdd4e,
+ 0x75c1, 0xdd44, 0x75ba, 0xdd39, 0x75b3, 0xdd2e, 0x75ac, 0xdd24,
+ 0x75a5, 0xdd19, 0x759f, 0xdd0f, 0x7598, 0xdd04, 0x7591, 0xdcfa,
+ 0x758a, 0xdcef, 0x7583, 0xdce5, 0x757c, 0xdcda, 0x7575, 0xdcd0,
+ 0x756e, 0xdcc5, 0x7567, 0xdcbb, 0x7561, 0xdcb0, 0x755a, 0xdca6,
+ 0x7553, 0xdc9b, 0x754c, 0xdc91, 0x7545, 0xdc86, 0x753e, 0xdc7c,
+ 0x7537, 0xdc72, 0x7530, 0xdc67, 0x7529, 0xdc5d, 0x7522, 0xdc52,
+ 0x751b, 0xdc48, 0x7514, 0xdc3d, 0x750d, 0xdc33, 0x7506, 0xdc29,
+ 0x74ff, 0xdc1e, 0x74f8, 0xdc14, 0x74f1, 0xdc09, 0x74ea, 0xdbff,
+ 0x74e2, 0xdbf5, 0x74db, 0xdbea, 0x74d4, 0xdbe0, 0x74cd, 0xdbd5,
+ 0x74c6, 0xdbcb, 0x74bf, 0xdbc1, 0x74b8, 0xdbb6, 0x74b1, 0xdbac,
+ 0x74aa, 0xdba2, 0x74a2, 0xdb97, 0x749b, 0xdb8d, 0x7494, 0xdb83,
+ 0x748d, 0xdb78, 0x7486, 0xdb6e, 0x747f, 0xdb64, 0x7477, 0xdb59,
+ 0x7470, 0xdb4f, 0x7469, 0xdb45, 0x7462, 0xdb3b, 0x745b, 0xdb30,
+ 0x7453, 0xdb26, 0x744c, 0xdb1c, 0x7445, 0xdb11, 0x743e, 0xdb07,
+ 0x7436, 0xdafd, 0x742f, 0xdaf3, 0x7428, 0xdae8, 0x7420, 0xdade,
+ 0x7419, 0xdad4, 0x7412, 0xdaca, 0x740b, 0xdabf, 0x7403, 0xdab5,
+ 0x73fc, 0xdaab, 0x73f5, 0xdaa1, 0x73ed, 0xda97, 0x73e6, 0xda8c,
+ 0x73df, 0xda82, 0x73d7, 0xda78, 0x73d0, 0xda6e, 0x73c8, 0xda64,
+ 0x73c1, 0xda5a, 0x73ba, 0xda4f, 0x73b2, 0xda45, 0x73ab, 0xda3b,
+ 0x73a3, 0xda31, 0x739c, 0xda27, 0x7395, 0xda1d, 0x738d, 0xda13,
+ 0x7386, 0xda08, 0x737e, 0xd9fe, 0x7377, 0xd9f4, 0x736f, 0xd9ea,
+ 0x7368, 0xd9e0, 0x7360, 0xd9d6, 0x7359, 0xd9cc, 0x7351, 0xd9c2,
+ 0x734a, 0xd9b8, 0x7342, 0xd9ae, 0x733b, 0xd9a4, 0x7333, 0xd99a,
+ 0x732c, 0xd98f, 0x7324, 0xd985, 0x731d, 0xd97b, 0x7315, 0xd971,
+ 0x730d, 0xd967, 0x7306, 0xd95d, 0x72fe, 0xd953, 0x72f7, 0xd949,
+ 0x72ef, 0xd93f, 0x72e7, 0xd935, 0x72e0, 0xd92b, 0x72d8, 0xd921,
+ 0x72d0, 0xd917, 0x72c9, 0xd90d, 0x72c1, 0xd903, 0x72ba, 0xd8f9,
+ 0x72b2, 0xd8ef, 0x72aa, 0xd8e6, 0x72a3, 0xd8dc, 0x729b, 0xd8d2,
+ 0x7293, 0xd8c8, 0x728b, 0xd8be, 0x7284, 0xd8b4, 0x727c, 0xd8aa,
+ 0x7274, 0xd8a0, 0x726d, 0xd896, 0x7265, 0xd88c, 0x725d, 0xd882,
+ 0x7255, 0xd878, 0x724e, 0xd86f, 0x7246, 0xd865, 0x723e, 0xd85b,
+ 0x7236, 0xd851, 0x722e, 0xd847, 0x7227, 0xd83d, 0x721f, 0xd833,
+ 0x7217, 0xd82a, 0x720f, 0xd820, 0x7207, 0xd816, 0x71ff, 0xd80c,
+ 0x71f8, 0xd802, 0x71f0, 0xd7f8, 0x71e8, 0xd7ef, 0x71e0, 0xd7e5,
+ 0x71d8, 0xd7db, 0x71d0, 0xd7d1, 0x71c8, 0xd7c8, 0x71c0, 0xd7be,
+ 0x71b9, 0xd7b4, 0x71b1, 0xd7aa, 0x71a9, 0xd7a0, 0x71a1, 0xd797,
+ 0x7199, 0xd78d, 0x7191, 0xd783, 0x7189, 0xd77a, 0x7181, 0xd770,
+ 0x7179, 0xd766, 0x7171, 0xd75c, 0x7169, 0xd753, 0x7161, 0xd749,
+ 0x7159, 0xd73f, 0x7151, 0xd736, 0x7149, 0xd72c, 0x7141, 0xd722,
+ 0x7139, 0xd719, 0x7131, 0xd70f, 0x7129, 0xd705, 0x7121, 0xd6fc,
+ 0x7119, 0xd6f2, 0x7111, 0xd6e8, 0x7109, 0xd6df, 0x7101, 0xd6d5,
+ 0x70f9, 0xd6cb, 0x70f0, 0xd6c2, 0x70e8, 0xd6b8, 0x70e0, 0xd6af,
+ 0x70d8, 0xd6a5, 0x70d0, 0xd69b, 0x70c8, 0xd692, 0x70c0, 0xd688,
+ 0x70b8, 0xd67f, 0x70af, 0xd675, 0x70a7, 0xd66c, 0x709f, 0xd662,
+ 0x7097, 0xd659, 0x708f, 0xd64f, 0x7087, 0xd645, 0x707e, 0xd63c,
+ 0x7076, 0xd632, 0x706e, 0xd629, 0x7066, 0xd61f, 0x705d, 0xd616,
+ 0x7055, 0xd60c, 0x704d, 0xd603, 0x7045, 0xd5f9, 0x703c, 0xd5f0,
+ 0x7034, 0xd5e6, 0x702c, 0xd5dd, 0x7024, 0xd5d4, 0x701b, 0xd5ca,
+ 0x7013, 0xd5c1, 0x700b, 0xd5b7, 0x7002, 0xd5ae, 0x6ffa, 0xd5a4,
+ 0x6ff2, 0xd59b, 0x6fea, 0xd592, 0x6fe1, 0xd588, 0x6fd9, 0xd57f,
+ 0x6fd0, 0xd575, 0x6fc8, 0xd56c, 0x6fc0, 0xd563, 0x6fb7, 0xd559,
+ 0x6faf, 0xd550, 0x6fa7, 0xd547, 0x6f9e, 0xd53d, 0x6f96, 0xd534,
+ 0x6f8d, 0xd52a, 0x6f85, 0xd521, 0x6f7d, 0xd518, 0x6f74, 0xd50e,
+ 0x6f6c, 0xd505, 0x6f63, 0xd4fc, 0x6f5b, 0xd4f3, 0x6f52, 0xd4e9,
+ 0x6f4a, 0xd4e0, 0x6f41, 0xd4d7, 0x6f39, 0xd4cd, 0x6f30, 0xd4c4,
+ 0x6f28, 0xd4bb, 0x6f20, 0xd4b2, 0x6f17, 0xd4a8, 0x6f0e, 0xd49f,
+ 0x6f06, 0xd496, 0x6efd, 0xd48d, 0x6ef5, 0xd483, 0x6eec, 0xd47a,
+ 0x6ee4, 0xd471, 0x6edb, 0xd468, 0x6ed3, 0xd45f, 0x6eca, 0xd455,
+ 0x6ec2, 0xd44c, 0x6eb9, 0xd443, 0x6eb0, 0xd43a, 0x6ea8, 0xd431,
+ 0x6e9f, 0xd428, 0x6e97, 0xd41e, 0x6e8e, 0xd415, 0x6e85, 0xd40c,
+ 0x6e7d, 0xd403, 0x6e74, 0xd3fa, 0x6e6b, 0xd3f1, 0x6e63, 0xd3e8,
+ 0x6e5a, 0xd3df, 0x6e51, 0xd3d5, 0x6e49, 0xd3cc, 0x6e40, 0xd3c3,
+ 0x6e37, 0xd3ba, 0x6e2f, 0xd3b1, 0x6e26, 0xd3a8, 0x6e1d, 0xd39f,
+ 0x6e15, 0xd396, 0x6e0c, 0xd38d, 0x6e03, 0xd384, 0x6dfa, 0xd37b,
+ 0x6df2, 0xd372, 0x6de9, 0xd369, 0x6de0, 0xd360, 0x6dd7, 0xd357,
+ 0x6dcf, 0xd34e, 0x6dc6, 0xd345, 0x6dbd, 0xd33c, 0x6db4, 0xd333,
+ 0x6dab, 0xd32a, 0x6da3, 0xd321, 0x6d9a, 0xd318, 0x6d91, 0xd30f,
+ 0x6d88, 0xd306, 0x6d7f, 0xd2fd, 0x6d76, 0xd2f4, 0x6d6e, 0xd2eb,
+ 0x6d65, 0xd2e2, 0x6d5c, 0xd2d9, 0x6d53, 0xd2d1, 0x6d4a, 0xd2c8,
+ 0x6d41, 0xd2bf, 0x6d38, 0xd2b6, 0x6d2f, 0xd2ad, 0x6d27, 0xd2a4,
+ 0x6d1e, 0xd29b, 0x6d15, 0xd292, 0x6d0c, 0xd28a, 0x6d03, 0xd281,
+ 0x6cfa, 0xd278, 0x6cf1, 0xd26f, 0x6ce8, 0xd266, 0x6cdf, 0xd25d,
+ 0x6cd6, 0xd255, 0x6ccd, 0xd24c, 0x6cc4, 0xd243, 0x6cbb, 0xd23a,
+ 0x6cb2, 0xd231, 0x6ca9, 0xd229, 0x6ca0, 0xd220, 0x6c97, 0xd217,
+ 0x6c8e, 0xd20e, 0x6c85, 0xd206, 0x6c7c, 0xd1fd, 0x6c73, 0xd1f4,
+ 0x6c6a, 0xd1eb, 0x6c61, 0xd1e3, 0x6c58, 0xd1da, 0x6c4f, 0xd1d1,
+ 0x6c46, 0xd1c9, 0x6c3d, 0xd1c0, 0x6c34, 0xd1b7, 0x6c2b, 0xd1af,
+ 0x6c21, 0xd1a6, 0x6c18, 0xd19d, 0x6c0f, 0xd195, 0x6c06, 0xd18c,
+ 0x6bfd, 0xd183, 0x6bf4, 0xd17b, 0x6beb, 0xd172, 0x6be2, 0xd169,
+ 0x6bd8, 0xd161, 0x6bcf, 0xd158, 0x6bc6, 0xd150, 0x6bbd, 0xd147,
+ 0x6bb4, 0xd13e, 0x6bab, 0xd136, 0x6ba1, 0xd12d, 0x6b98, 0xd125,
+ 0x6b8f, 0xd11c, 0x6b86, 0xd114, 0x6b7d, 0xd10b, 0x6b73, 0xd103,
+ 0x6b6a, 0xd0fa, 0x6b61, 0xd0f2, 0x6b58, 0xd0e9, 0x6b4e, 0xd0e0,
+ 0x6b45, 0xd0d8, 0x6b3c, 0xd0d0, 0x6b33, 0xd0c7, 0x6b29, 0xd0bf,
+ 0x6b20, 0xd0b6, 0x6b17, 0xd0ae, 0x6b0d, 0xd0a5, 0x6b04, 0xd09d,
+ 0x6afb, 0xd094, 0x6af2, 0xd08c, 0x6ae8, 0xd083, 0x6adf, 0xd07b,
+ 0x6ad6, 0xd073, 0x6acc, 0xd06a, 0x6ac3, 0xd062, 0x6ab9, 0xd059,
+ 0x6ab0, 0xd051, 0x6aa7, 0xd049, 0x6a9d, 0xd040, 0x6a94, 0xd038,
+ 0x6a8b, 0xd030, 0x6a81, 0xd027, 0x6a78, 0xd01f, 0x6a6e, 0xd016,
+ 0x6a65, 0xd00e, 0x6a5c, 0xd006, 0x6a52, 0xcffe, 0x6a49, 0xcff5,
+ 0x6a3f, 0xcfed, 0x6a36, 0xcfe5, 0x6a2c, 0xcfdc, 0x6a23, 0xcfd4,
+ 0x6a1a, 0xcfcc, 0x6a10, 0xcfc4, 0x6a07, 0xcfbb, 0x69fd, 0xcfb3,
+ 0x69f4, 0xcfab, 0x69ea, 0xcfa3, 0x69e1, 0xcf9a, 0x69d7, 0xcf92,
+ 0x69ce, 0xcf8a, 0x69c4, 0xcf82, 0x69bb, 0xcf79, 0x69b1, 0xcf71,
+ 0x69a7, 0xcf69, 0x699e, 0xcf61, 0x6994, 0xcf59, 0x698b, 0xcf51,
+ 0x6981, 0xcf48, 0x6978, 0xcf40, 0x696e, 0xcf38, 0x6965, 0xcf30,
+ 0x695b, 0xcf28, 0x6951, 0xcf20, 0x6948, 0xcf18, 0x693e, 0xcf10,
+ 0x6935, 0xcf07, 0x692b, 0xceff, 0x6921, 0xcef7, 0x6918, 0xceef,
+ 0x690e, 0xcee7, 0x6904, 0xcedf, 0x68fb, 0xced7, 0x68f1, 0xcecf,
+ 0x68e7, 0xcec7, 0x68de, 0xcebf, 0x68d4, 0xceb7, 0x68ca, 0xceaf,
+ 0x68c1, 0xcea7, 0x68b7, 0xce9f, 0x68ad, 0xce97, 0x68a4, 0xce8f,
+ 0x689a, 0xce87, 0x6890, 0xce7f, 0x6886, 0xce77, 0x687d, 0xce6f,
+ 0x6873, 0xce67, 0x6869, 0xce5f, 0x6860, 0xce57, 0x6856, 0xce4f,
+ 0x684c, 0xce47, 0x6842, 0xce40, 0x6838, 0xce38, 0x682f, 0xce30,
+ 0x6825, 0xce28, 0x681b, 0xce20, 0x6811, 0xce18, 0x6808, 0xce10,
+ 0x67fe, 0xce08, 0x67f4, 0xce01, 0x67ea, 0xcdf9, 0x67e0, 0xcdf1,
+ 0x67d6, 0xcde9, 0x67cd, 0xcde1, 0x67c3, 0xcdd9, 0x67b9, 0xcdd2,
+ 0x67af, 0xcdca, 0x67a5, 0xcdc2, 0x679b, 0xcdba, 0x6791, 0xcdb2,
+ 0x6788, 0xcdab, 0x677e, 0xcda3, 0x6774, 0xcd9b, 0x676a, 0xcd93,
+ 0x6760, 0xcd8c, 0x6756, 0xcd84, 0x674c, 0xcd7c, 0x6742, 0xcd75,
+ 0x6738, 0xcd6d, 0x672e, 0xcd65, 0x6724, 0xcd5d, 0x671a, 0xcd56,
+ 0x6711, 0xcd4e, 0x6707, 0xcd46, 0x66fd, 0xcd3f, 0x66f3, 0xcd37,
+ 0x66e9, 0xcd30, 0x66df, 0xcd28, 0x66d5, 0xcd20, 0x66cb, 0xcd19,
+ 0x66c1, 0xcd11, 0x66b7, 0xcd09, 0x66ad, 0xcd02, 0x66a3, 0xccfa,
+ 0x6699, 0xccf3, 0x668f, 0xcceb, 0x6685, 0xcce3, 0x667b, 0xccdc,
+ 0x6671, 0xccd4, 0x6666, 0xcccd, 0x665c, 0xccc5, 0x6652, 0xccbe,
+ 0x6648, 0xccb6, 0x663e, 0xccaf, 0x6634, 0xcca7, 0x662a, 0xcca0,
+ 0x6620, 0xcc98, 0x6616, 0xcc91, 0x660c, 0xcc89, 0x6602, 0xcc82,
+ 0x65f8, 0xcc7a, 0x65ed, 0xcc73, 0x65e3, 0xcc6b, 0x65d9, 0xcc64,
+ 0x65cf, 0xcc5d, 0x65c5, 0xcc55, 0x65bb, 0xcc4e, 0x65b1, 0xcc46,
+ 0x65a6, 0xcc3f, 0x659c, 0xcc38, 0x6592, 0xcc30, 0x6588, 0xcc29,
+ 0x657e, 0xcc21, 0x6574, 0xcc1a, 0x6569, 0xcc13, 0x655f, 0xcc0b,
+ 0x6555, 0xcc04, 0x654b, 0xcbfd, 0x6541, 0xcbf5, 0x6536, 0xcbee,
+ 0x652c, 0xcbe7, 0x6522, 0xcbe0, 0x6518, 0xcbd8, 0x650d, 0xcbd1,
+ 0x6503, 0xcbca, 0x64f9, 0xcbc2, 0x64ef, 0xcbbb, 0x64e4, 0xcbb4,
+ 0x64da, 0xcbad, 0x64d0, 0xcba5, 0x64c5, 0xcb9e, 0x64bb, 0xcb97,
+ 0x64b1, 0xcb90, 0x64a7, 0xcb89, 0x649c, 0xcb81, 0x6492, 0xcb7a,
+ 0x6488, 0xcb73, 0x647d, 0xcb6c, 0x6473, 0xcb65, 0x6469, 0xcb5e,
+ 0x645e, 0xcb56, 0x6454, 0xcb4f, 0x644a, 0xcb48, 0x643f, 0xcb41,
+ 0x6435, 0xcb3a, 0x642b, 0xcb33, 0x6420, 0xcb2c, 0x6416, 0xcb25,
+ 0x640b, 0xcb1e, 0x6401, 0xcb16, 0x63f7, 0xcb0f, 0x63ec, 0xcb08,
+ 0x63e2, 0xcb01, 0x63d7, 0xcafa, 0x63cd, 0xcaf3, 0x63c3, 0xcaec,
+ 0x63b8, 0xcae5, 0x63ae, 0xcade, 0x63a3, 0xcad7, 0x6399, 0xcad0,
+ 0x638e, 0xcac9, 0x6384, 0xcac2, 0x637a, 0xcabb, 0x636f, 0xcab4,
+ 0x6365, 0xcaad, 0x635a, 0xcaa6, 0x6350, 0xca9f, 0x6345, 0xca99,
+ 0x633b, 0xca92, 0x6330, 0xca8b, 0x6326, 0xca84, 0x631b, 0xca7d,
+ 0x6311, 0xca76, 0x6306, 0xca6f, 0x62fc, 0xca68, 0x62f1, 0xca61,
+ 0x62e7, 0xca5b, 0x62dc, 0xca54, 0x62d2, 0xca4d, 0x62c7, 0xca46,
+ 0x62bc, 0xca3f, 0x62b2, 0xca38, 0x62a7, 0xca32, 0x629d, 0xca2b,
+ 0x6292, 0xca24, 0x6288, 0xca1d, 0x627d, 0xca16, 0x6272, 0xca10,
+ 0x6268, 0xca09, 0x625d, 0xca02, 0x6253, 0xc9fb, 0x6248, 0xc9f5,
+ 0x623d, 0xc9ee, 0x6233, 0xc9e7, 0x6228, 0xc9e0, 0x621e, 0xc9da,
+ 0x6213, 0xc9d3, 0x6208, 0xc9cc, 0x61fe, 0xc9c6, 0x61f3, 0xc9bf,
+ 0x61e8, 0xc9b8, 0x61de, 0xc9b2, 0x61d3, 0xc9ab, 0x61c8, 0xc9a4,
+ 0x61be, 0xc99e, 0x61b3, 0xc997, 0x61a8, 0xc991, 0x619e, 0xc98a,
+ 0x6193, 0xc983, 0x6188, 0xc97d, 0x617d, 0xc976, 0x6173, 0xc970,
+ 0x6168, 0xc969, 0x615d, 0xc963, 0x6153, 0xc95c, 0x6148, 0xc955,
+ 0x613d, 0xc94f, 0x6132, 0xc948, 0x6128, 0xc942, 0x611d, 0xc93b,
+ 0x6112, 0xc935, 0x6107, 0xc92e, 0x60fd, 0xc928, 0x60f2, 0xc921,
+ 0x60e7, 0xc91b, 0x60dc, 0xc915, 0x60d1, 0xc90e, 0x60c7, 0xc908,
+ 0x60bc, 0xc901, 0x60b1, 0xc8fb, 0x60a6, 0xc8f4, 0x609b, 0xc8ee,
+ 0x6091, 0xc8e8, 0x6086, 0xc8e1, 0x607b, 0xc8db, 0x6070, 0xc8d4,
+ 0x6065, 0xc8ce, 0x605b, 0xc8c8, 0x6050, 0xc8c1, 0x6045, 0xc8bb,
+ 0x603a, 0xc8b5, 0x602f, 0xc8ae, 0x6024, 0xc8a8, 0x6019, 0xc8a2,
+ 0x600f, 0xc89b, 0x6004, 0xc895, 0x5ff9, 0xc88f, 0x5fee, 0xc889,
+ 0x5fe3, 0xc882, 0x5fd8, 0xc87c, 0x5fcd, 0xc876, 0x5fc2, 0xc870,
+ 0x5fb7, 0xc869, 0x5fac, 0xc863, 0x5fa2, 0xc85d, 0x5f97, 0xc857,
+ 0x5f8c, 0xc850, 0x5f81, 0xc84a, 0x5f76, 0xc844, 0x5f6b, 0xc83e,
+ 0x5f60, 0xc838, 0x5f55, 0xc832, 0x5f4a, 0xc82b, 0x5f3f, 0xc825,
+ 0x5f34, 0xc81f, 0x5f29, 0xc819, 0x5f1e, 0xc813, 0x5f13, 0xc80d,
+ 0x5f08, 0xc807, 0x5efd, 0xc801, 0x5ef2, 0xc7fb, 0x5ee7, 0xc7f5,
+ 0x5edc, 0xc7ee, 0x5ed1, 0xc7e8, 0x5ec6, 0xc7e2, 0x5ebb, 0xc7dc,
+ 0x5eb0, 0xc7d6, 0x5ea5, 0xc7d0, 0x5e9a, 0xc7ca, 0x5e8f, 0xc7c4,
+ 0x5e84, 0xc7be, 0x5e79, 0xc7b8, 0x5e6e, 0xc7b2, 0x5e63, 0xc7ac,
+ 0x5e58, 0xc7a6, 0x5e4d, 0xc7a0, 0x5e42, 0xc79a, 0x5e36, 0xc795,
+ 0x5e2b, 0xc78f, 0x5e20, 0xc789, 0x5e15, 0xc783, 0x5e0a, 0xc77d,
+ 0x5dff, 0xc777, 0x5df4, 0xc771, 0x5de9, 0xc76b, 0x5dde, 0xc765,
+ 0x5dd3, 0xc75f, 0x5dc7, 0xc75a, 0x5dbc, 0xc754, 0x5db1, 0xc74e,
+ 0x5da6, 0xc748, 0x5d9b, 0xc742, 0x5d90, 0xc73d, 0x5d85, 0xc737,
+ 0x5d79, 0xc731, 0x5d6e, 0xc72b, 0x5d63, 0xc725, 0x5d58, 0xc720,
+ 0x5d4d, 0xc71a, 0x5d42, 0xc714, 0x5d36, 0xc70e, 0x5d2b, 0xc709,
+ 0x5d20, 0xc703, 0x5d15, 0xc6fd, 0x5d0a, 0xc6f7, 0x5cff, 0xc6f2,
+ 0x5cf3, 0xc6ec, 0x5ce8, 0xc6e6, 0x5cdd, 0xc6e1, 0x5cd2, 0xc6db,
+ 0x5cc6, 0xc6d5, 0x5cbb, 0xc6d0, 0x5cb0, 0xc6ca, 0x5ca5, 0xc6c5,
+ 0x5c99, 0xc6bf, 0x5c8e, 0xc6b9, 0x5c83, 0xc6b4, 0x5c78, 0xc6ae,
+ 0x5c6c, 0xc6a8, 0x5c61, 0xc6a3, 0x5c56, 0xc69d, 0x5c4b, 0xc698,
+ 0x5c3f, 0xc692, 0x5c34, 0xc68d, 0x5c29, 0xc687, 0x5c1e, 0xc682,
+ 0x5c12, 0xc67c, 0x5c07, 0xc677, 0x5bfc, 0xc671, 0x5bf0, 0xc66c,
+ 0x5be5, 0xc666, 0x5bda, 0xc661, 0x5bce, 0xc65b, 0x5bc3, 0xc656,
+ 0x5bb8, 0xc650, 0x5bac, 0xc64b, 0x5ba1, 0xc645, 0x5b96, 0xc640,
+ 0x5b8a, 0xc63b, 0x5b7f, 0xc635, 0x5b74, 0xc630, 0x5b68, 0xc62a,
+ 0x5b5d, 0xc625, 0x5b52, 0xc620, 0x5b46, 0xc61a, 0x5b3b, 0xc615,
+ 0x5b30, 0xc610, 0x5b24, 0xc60a, 0x5b19, 0xc605, 0x5b0d, 0xc600,
+ 0x5b02, 0xc5fa, 0x5af7, 0xc5f5, 0x5aeb, 0xc5f0, 0x5ae0, 0xc5ea,
+ 0x5ad4, 0xc5e5, 0x5ac9, 0xc5e0, 0x5abe, 0xc5db, 0x5ab2, 0xc5d5,
+ 0x5aa7, 0xc5d0, 0x5a9b, 0xc5cb, 0x5a90, 0xc5c6, 0x5a84, 0xc5c1,
+ 0x5a79, 0xc5bb, 0x5a6e, 0xc5b6, 0x5a62, 0xc5b1, 0x5a57, 0xc5ac,
+ 0x5a4b, 0xc5a7, 0x5a40, 0xc5a1, 0x5a34, 0xc59c, 0x5a29, 0xc597,
+ 0x5a1d, 0xc592, 0x5a12, 0xc58d, 0x5a06, 0xc588, 0x59fb, 0xc583,
+ 0x59ef, 0xc57e, 0x59e4, 0xc578, 0x59d8, 0xc573, 0x59cd, 0xc56e,
+ 0x59c1, 0xc569, 0x59b6, 0xc564, 0x59aa, 0xc55f, 0x599f, 0xc55a,
+ 0x5993, 0xc555, 0x5988, 0xc550, 0x597c, 0xc54b, 0x5971, 0xc546,
+ 0x5965, 0xc541, 0x595a, 0xc53c, 0x594e, 0xc537, 0x5943, 0xc532,
+ 0x5937, 0xc52d, 0x592c, 0xc528, 0x5920, 0xc523, 0x5914, 0xc51e,
+ 0x5909, 0xc51a, 0x58fd, 0xc515, 0x58f2, 0xc510, 0x58e6, 0xc50b,
+ 0x58db, 0xc506, 0x58cf, 0xc501, 0x58c3, 0xc4fc, 0x58b8, 0xc4f7,
+ 0x58ac, 0xc4f2, 0x58a1, 0xc4ee, 0x5895, 0xc4e9, 0x5889, 0xc4e4,
+ 0x587e, 0xc4df, 0x5872, 0xc4da, 0x5867, 0xc4d6, 0x585b, 0xc4d1,
+ 0x584f, 0xc4cc, 0x5844, 0xc4c7, 0x5838, 0xc4c2, 0x582d, 0xc4be,
+ 0x5821, 0xc4b9, 0x5815, 0xc4b4, 0x580a, 0xc4b0, 0x57fe, 0xc4ab,
+ 0x57f2, 0xc4a6, 0x57e7, 0xc4a1, 0x57db, 0xc49d, 0x57cf, 0xc498,
+ 0x57c4, 0xc493, 0x57b8, 0xc48f, 0x57ac, 0xc48a, 0x57a1, 0xc485,
+ 0x5795, 0xc481, 0x5789, 0xc47c, 0x577e, 0xc478, 0x5772, 0xc473,
+ 0x5766, 0xc46e, 0x575b, 0xc46a, 0x574f, 0xc465, 0x5743, 0xc461,
+ 0x5737, 0xc45c, 0x572c, 0xc457, 0x5720, 0xc453, 0x5714, 0xc44e,
+ 0x5709, 0xc44a, 0x56fd, 0xc445, 0x56f1, 0xc441, 0x56e5, 0xc43c,
+ 0x56da, 0xc438, 0x56ce, 0xc433, 0x56c2, 0xc42f, 0x56b6, 0xc42a,
+ 0x56ab, 0xc426, 0x569f, 0xc422, 0x5693, 0xc41d, 0x5687, 0xc419,
+ 0x567c, 0xc414, 0x5670, 0xc410, 0x5664, 0xc40b, 0x5658, 0xc407,
+ 0x564c, 0xc403, 0x5641, 0xc3fe, 0x5635, 0xc3fa, 0x5629, 0xc3f6,
+ 0x561d, 0xc3f1, 0x5612, 0xc3ed, 0x5606, 0xc3e9, 0x55fa, 0xc3e4,
+ 0x55ee, 0xc3e0, 0x55e2, 0xc3dc, 0x55d7, 0xc3d7, 0x55cb, 0xc3d3,
+ 0x55bf, 0xc3cf, 0x55b3, 0xc3ca, 0x55a7, 0xc3c6, 0x559b, 0xc3c2,
+ 0x5590, 0xc3be, 0x5584, 0xc3ba, 0x5578, 0xc3b5, 0x556c, 0xc3b1,
+ 0x5560, 0xc3ad, 0x5554, 0xc3a9, 0x5549, 0xc3a5, 0x553d, 0xc3a0,
+ 0x5531, 0xc39c, 0x5525, 0xc398, 0x5519, 0xc394, 0x550d, 0xc390,
+ 0x5501, 0xc38c, 0x54f6, 0xc387, 0x54ea, 0xc383, 0x54de, 0xc37f,
+ 0x54d2, 0xc37b, 0x54c6, 0xc377, 0x54ba, 0xc373, 0x54ae, 0xc36f,
+ 0x54a2, 0xc36b, 0x5496, 0xc367, 0x548b, 0xc363, 0x547f, 0xc35f,
+ 0x5473, 0xc35b, 0x5467, 0xc357, 0x545b, 0xc353, 0x544f, 0xc34f,
+ 0x5443, 0xc34b, 0x5437, 0xc347, 0x542b, 0xc343, 0x541f, 0xc33f,
+ 0x5413, 0xc33b, 0x5407, 0xc337, 0x53fb, 0xc333, 0x53f0, 0xc32f,
+ 0x53e4, 0xc32b, 0x53d8, 0xc327, 0x53cc, 0xc323, 0x53c0, 0xc320,
+ 0x53b4, 0xc31c, 0x53a8, 0xc318, 0x539c, 0xc314, 0x5390, 0xc310,
+ 0x5384, 0xc30c, 0x5378, 0xc308, 0x536c, 0xc305, 0x5360, 0xc301,
+ 0x5354, 0xc2fd, 0x5348, 0xc2f9, 0x533c, 0xc2f5, 0x5330, 0xc2f2,
+ 0x5324, 0xc2ee, 0x5318, 0xc2ea, 0x530c, 0xc2e6, 0x5300, 0xc2e3,
+ 0x52f4, 0xc2df, 0x52e8, 0xc2db, 0x52dc, 0xc2d8, 0x52d0, 0xc2d4,
+ 0x52c4, 0xc2d0, 0x52b8, 0xc2cc, 0x52ac, 0xc2c9, 0x52a0, 0xc2c5,
+ 0x5294, 0xc2c1, 0x5288, 0xc2be, 0x527c, 0xc2ba, 0x5270, 0xc2b7,
+ 0x5264, 0xc2b3, 0x5258, 0xc2af, 0x524c, 0xc2ac, 0x5240, 0xc2a8,
+ 0x5234, 0xc2a5, 0x5228, 0xc2a1, 0x521c, 0xc29d, 0x5210, 0xc29a,
+ 0x5204, 0xc296, 0x51f7, 0xc293, 0x51eb, 0xc28f, 0x51df, 0xc28c,
+ 0x51d3, 0xc288, 0x51c7, 0xc285, 0x51bb, 0xc281, 0x51af, 0xc27e,
+ 0x51a3, 0xc27a, 0x5197, 0xc277, 0x518b, 0xc273, 0x517f, 0xc270,
+ 0x5173, 0xc26d, 0x5167, 0xc269, 0x515a, 0xc266, 0x514e, 0xc262,
+ 0x5142, 0xc25f, 0x5136, 0xc25c, 0x512a, 0xc258, 0x511e, 0xc255,
+ 0x5112, 0xc251, 0x5106, 0xc24e, 0x50fa, 0xc24b, 0x50ed, 0xc247,
+ 0x50e1, 0xc244, 0x50d5, 0xc241, 0x50c9, 0xc23e, 0x50bd, 0xc23a,
+ 0x50b1, 0xc237, 0x50a5, 0xc234, 0x5099, 0xc230, 0x508c, 0xc22d,
+ 0x5080, 0xc22a, 0x5074, 0xc227, 0x5068, 0xc223, 0x505c, 0xc220,
+ 0x5050, 0xc21d, 0x5044, 0xc21a, 0x5037, 0xc217, 0x502b, 0xc213,
+ 0x501f, 0xc210, 0x5013, 0xc20d, 0x5007, 0xc20a, 0x4ffb, 0xc207,
+ 0x4fee, 0xc204, 0x4fe2, 0xc201, 0x4fd6, 0xc1fd, 0x4fca, 0xc1fa,
+ 0x4fbe, 0xc1f7, 0x4fb2, 0xc1f4, 0x4fa5, 0xc1f1, 0x4f99, 0xc1ee,
+ 0x4f8d, 0xc1eb, 0x4f81, 0xc1e8, 0x4f75, 0xc1e5, 0x4f68, 0xc1e2,
+ 0x4f5c, 0xc1df, 0x4f50, 0xc1dc, 0x4f44, 0xc1d9, 0x4f38, 0xc1d6,
+ 0x4f2b, 0xc1d3, 0x4f1f, 0xc1d0, 0x4f13, 0xc1cd, 0x4f07, 0xc1ca,
+ 0x4efb, 0xc1c7, 0x4eee, 0xc1c4, 0x4ee2, 0xc1c1, 0x4ed6, 0xc1be,
+ 0x4eca, 0xc1bb, 0x4ebd, 0xc1b8, 0x4eb1, 0xc1b6, 0x4ea5, 0xc1b3,
+ 0x4e99, 0xc1b0, 0x4e8c, 0xc1ad, 0x4e80, 0xc1aa, 0x4e74, 0xc1a7,
+ 0x4e68, 0xc1a4, 0x4e5c, 0xc1a2, 0x4e4f, 0xc19f, 0x4e43, 0xc19c,
+ 0x4e37, 0xc199, 0x4e2b, 0xc196, 0x4e1e, 0xc194, 0x4e12, 0xc191,
+ 0x4e06, 0xc18e, 0x4df9, 0xc18b, 0x4ded, 0xc189, 0x4de1, 0xc186,
+ 0x4dd5, 0xc183, 0x4dc8, 0xc180, 0x4dbc, 0xc17e, 0x4db0, 0xc17b,
+ 0x4da4, 0xc178, 0x4d97, 0xc176, 0x4d8b, 0xc173, 0x4d7f, 0xc170,
+ 0x4d72, 0xc16e, 0x4d66, 0xc16b, 0x4d5a, 0xc168, 0x4d4e, 0xc166,
+ 0x4d41, 0xc163, 0x4d35, 0xc161, 0x4d29, 0xc15e, 0x4d1c, 0xc15b,
+ 0x4d10, 0xc159, 0x4d04, 0xc156, 0x4cf8, 0xc154, 0x4ceb, 0xc151,
+ 0x4cdf, 0xc14f, 0x4cd3, 0xc14c, 0x4cc6, 0xc14a, 0x4cba, 0xc147,
+ 0x4cae, 0xc145, 0x4ca1, 0xc142, 0x4c95, 0xc140, 0x4c89, 0xc13d,
+ 0x4c7c, 0xc13b, 0x4c70, 0xc138, 0x4c64, 0xc136, 0x4c57, 0xc134,
+ 0x4c4b, 0xc131, 0x4c3f, 0xc12f, 0x4c32, 0xc12c, 0x4c26, 0xc12a,
+ 0x4c1a, 0xc128, 0x4c0d, 0xc125, 0x4c01, 0xc123, 0x4bf5, 0xc120,
+ 0x4be8, 0xc11e, 0x4bdc, 0xc11c, 0x4bd0, 0xc119, 0x4bc3, 0xc117,
+ 0x4bb7, 0xc115, 0x4bab, 0xc113, 0x4b9e, 0xc110, 0x4b92, 0xc10e,
+ 0x4b85, 0xc10c, 0x4b79, 0xc109, 0x4b6d, 0xc107, 0x4b60, 0xc105,
+ 0x4b54, 0xc103, 0x4b48, 0xc100, 0x4b3b, 0xc0fe, 0x4b2f, 0xc0fc,
+ 0x4b23, 0xc0fa, 0x4b16, 0xc0f8, 0x4b0a, 0xc0f6, 0x4afd, 0xc0f3,
+ 0x4af1, 0xc0f1, 0x4ae5, 0xc0ef, 0x4ad8, 0xc0ed, 0x4acc, 0xc0eb,
+ 0x4ac0, 0xc0e9, 0x4ab3, 0xc0e7, 0x4aa7, 0xc0e4, 0x4a9a, 0xc0e2,
+ 0x4a8e, 0xc0e0, 0x4a82, 0xc0de, 0x4a75, 0xc0dc, 0x4a69, 0xc0da,
+ 0x4a5c, 0xc0d8, 0x4a50, 0xc0d6, 0x4a44, 0xc0d4, 0x4a37, 0xc0d2,
+ 0x4a2b, 0xc0d0, 0x4a1e, 0xc0ce, 0x4a12, 0xc0cc, 0x4a06, 0xc0ca,
+ 0x49f9, 0xc0c8, 0x49ed, 0xc0c6, 0x49e0, 0xc0c4, 0x49d4, 0xc0c2,
+ 0x49c7, 0xc0c0, 0x49bb, 0xc0be, 0x49af, 0xc0bd, 0x49a2, 0xc0bb,
+ 0x4996, 0xc0b9, 0x4989, 0xc0b7, 0x497d, 0xc0b5, 0x4970, 0xc0b3,
+ 0x4964, 0xc0b1, 0x4958, 0xc0af, 0x494b, 0xc0ae, 0x493f, 0xc0ac,
+ 0x4932, 0xc0aa, 0x4926, 0xc0a8, 0x4919, 0xc0a6, 0x490d, 0xc0a5,
+ 0x4901, 0xc0a3, 0x48f4, 0xc0a1, 0x48e8, 0xc09f, 0x48db, 0xc09e,
+ 0x48cf, 0xc09c, 0x48c2, 0xc09a, 0x48b6, 0xc098, 0x48a9, 0xc097,
+ 0x489d, 0xc095, 0x4891, 0xc093, 0x4884, 0xc092, 0x4878, 0xc090,
+ 0x486b, 0xc08e, 0x485f, 0xc08d, 0x4852, 0xc08b, 0x4846, 0xc089,
+ 0x4839, 0xc088, 0x482d, 0xc086, 0x4820, 0xc085, 0x4814, 0xc083,
+ 0x4807, 0xc081, 0x47fb, 0xc080, 0x47ef, 0xc07e, 0x47e2, 0xc07d,
+ 0x47d6, 0xc07b, 0x47c9, 0xc07a, 0x47bd, 0xc078, 0x47b0, 0xc077,
+ 0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,
+ 0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,
+ 0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,
+ 0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,
+ 0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,
+ 0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,
+ 0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,
+ 0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,
+ 0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,
+ 0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,
+ 0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,
+ 0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,
+ 0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,
+ 0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,
+ 0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,
+ 0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,
+ 0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,
+ 0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,
+ 0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,
+ 0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,
+ 0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,
+ 0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,
+ 0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,
+ 0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,
+ 0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,
+ 0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,
+ 0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,
+ 0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,
+ 0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,
+ 0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,
+ 0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,
+ 0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,
+ 0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,
+ 0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,
+ 0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,
+ 0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,
+ 0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,
+ 0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,
+ 0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,
+};
+
+/**
+* @brief Initialization function for the Q15 RFFT/RIFFT.
+* @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.
+* \par
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initialization of coef modifier depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ case 8192u:
+ S->twidCoefRModifier = 1u;
+ S->pCfft = &arm_cfft_sR_q15_len4096;
+ break;
+ case 4096u:
+ S->twidCoefRModifier = 2u;
+ S->pCfft = &arm_cfft_sR_q15_len2048;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ S->pCfft = &arm_cfft_sR_q15_len1024;
+ break;
+ case 1024u:
+ S->twidCoefRModifier = 8u;
+ S->pCfft = &arm_cfft_sR_q15_len512;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ S->pCfft = &arm_cfft_sR_q15_len256;
+ break;
+ case 256u:
+ S->twidCoefRModifier = 32u;
+ S->pCfft = &arm_cfft_sR_q15_len128;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ S->pCfft = &arm_cfft_sR_q15_len64;
+ break;
+ case 64u:
+ S->twidCoefRModifier = 128u;
+ S->pCfft = &arm_cfft_sR_q15_len32;
+ break;
+ case 32u:
+ S->twidCoefRModifier = 256u;
+ S->pCfft = &arm_cfft_sR_q15_len16;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+}
+
+/**
+* @} end of RealFFT group
+*/
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,4285 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_q31.c
+*
+* Description: RFFT & RIFFT Q31 initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_const_structs.h"
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* \par
+* Generation fixed-point realCoefAQ31 array in Q31 format:
+* \par
+* n = 4096
+* for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }
+* \par
+* Convert to fixed point Q31 format
+* round(pATable[i] * pow(2, 31))
+*/
+
+
+static const q31_t realCoefAQ31[8192] = {
+ 0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,
+ 0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,
+ 0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,
+ 0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,
+ 0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,
+ 0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,
+ 0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,
+ 0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,
+ 0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,
+ 0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,
+ 0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,
+ 0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,
+ 0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,
+ 0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,
+ 0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,
+ 0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,
+ 0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,
+ 0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,
+ 0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,
+ 0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,
+ 0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,
+ 0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,
+ 0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,
+ 0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,
+ 0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,
+ 0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,
+ 0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,
+ 0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,
+ 0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,
+ 0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,
+ 0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,
+ 0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,
+ 0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,
+ 0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,
+ 0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,
+ 0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,
+ 0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,
+ 0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,
+ 0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,
+ 0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,
+ 0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,
+ 0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,
+ 0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,
+ 0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,
+ 0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,
+ 0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,
+ 0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,
+ 0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,
+ 0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,
+ 0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,
+ 0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,
+ 0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,
+ 0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,
+ 0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,
+ 0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,
+ 0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,
+ 0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,
+ 0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,
+ 0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,
+ 0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,
+ 0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,
+ 0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,
+ 0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,
+ 0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,
+ 0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,
+ 0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,
+ 0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,
+ 0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,
+ 0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,
+ 0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,
+ 0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,
+ 0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,
+ 0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,
+ 0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,
+ 0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,
+ 0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,
+ 0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,
+ 0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,
+ 0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,
+ 0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,
+ 0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,
+ 0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,
+ 0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,
+ 0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,
+ 0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,
+ 0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,
+ 0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,
+ 0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,
+ 0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,
+ 0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,
+ 0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,
+ 0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,
+ 0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,
+ 0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,
+ 0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,
+ 0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,
+ 0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,
+ 0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,
+ 0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,
+ 0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,
+ 0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,
+ 0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,
+ 0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,
+ 0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,
+ 0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,
+ 0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,
+ 0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,
+ 0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,
+ 0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,
+ 0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,
+ 0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,
+ 0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,
+ 0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,
+ 0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,
+ 0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,
+ 0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,
+ 0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,
+ 0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,
+ 0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,
+ 0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,
+ 0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,
+ 0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,
+ 0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,
+ 0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,
+ 0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,
+ 0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,
+ 0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,
+ 0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,
+ 0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,
+ 0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,
+ 0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,
+ 0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,
+ 0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,
+ 0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,
+ 0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,
+ 0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,
+ 0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,
+ 0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,
+ 0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,
+ 0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,
+ 0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,
+ 0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,
+ 0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,
+ 0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,
+ 0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,
+ 0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,
+ 0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,
+ 0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,
+ 0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,
+ 0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,
+ 0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,
+ 0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,
+ 0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,
+ 0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,
+ 0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,
+ 0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,
+ 0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,
+ 0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,
+ 0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,
+ 0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,
+ 0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,
+ 0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,
+ 0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,
+ 0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,
+ 0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,
+ 0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,
+ 0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,
+ 0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,
+ 0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,
+ 0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,
+ 0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,
+ 0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,
+ 0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,
+ 0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,
+ 0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,
+ 0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,
+ 0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,
+ 0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,
+ 0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,
+ 0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,
+ 0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,
+ 0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,
+ 0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,
+ 0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,
+ 0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,
+ 0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,
+ 0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,
+ 0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,
+ 0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,
+ 0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,
+ 0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,
+ 0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,
+ 0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,
+ 0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,
+ 0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,
+ 0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,
+ 0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,
+ 0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,
+ 0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,
+ 0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,
+ 0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,
+ 0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,
+ 0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,
+ 0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,
+ 0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,
+ 0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,
+ 0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,
+ 0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,
+ 0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,
+ 0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,
+ 0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,
+ 0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,
+ 0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,
+ 0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,
+ 0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,
+ 0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,
+ 0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,
+ 0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,
+ 0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,
+ 0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,
+ 0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,
+ 0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,
+ 0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,
+ 0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,
+ 0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,
+ 0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,
+ 0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,
+ 0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,
+ 0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,
+ 0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,
+ 0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,
+ 0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,
+ 0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,
+ 0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,
+ 0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,
+ 0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,
+ 0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,
+ 0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,
+ 0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,
+ 0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,
+ 0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,
+ 0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,
+ 0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,
+ 0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,
+ 0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,
+ 0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,
+ 0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,
+ 0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,
+ 0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,
+ 0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,
+ 0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,
+ 0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,
+ 0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,
+ 0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,
+ 0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,
+ 0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,
+ 0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,
+ 0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,
+ 0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,
+ 0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,
+ 0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,
+ 0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,
+ 0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,
+ 0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,
+ 0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,
+ 0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,
+ 0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,
+ 0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,
+ 0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,
+ 0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,
+ 0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,
+ 0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,
+ 0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,
+ 0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,
+ 0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,
+ 0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,
+ 0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,
+ 0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,
+ 0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,
+ 0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,
+ 0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,
+ 0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,
+ 0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,
+ 0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,
+ 0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,
+ 0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,
+ 0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,
+ 0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,
+ 0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,
+ 0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,
+ 0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,
+ 0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,
+ 0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,
+ 0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,
+ 0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,
+ 0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,
+ 0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,
+ 0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,
+ 0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,
+ 0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,
+ 0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,
+ 0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,
+ 0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,
+ 0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,
+ 0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,
+ 0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,
+ 0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,
+ 0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,
+ 0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,
+ 0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,
+ 0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,
+ 0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,
+ 0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,
+ 0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,
+ 0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,
+ 0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,
+ 0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,
+ 0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,
+ 0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,
+ 0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,
+ 0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,
+ 0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,
+ 0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,
+ 0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,
+ 0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,
+ 0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,
+ 0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,
+ 0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,
+ 0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,
+ 0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,
+ 0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,
+ 0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,
+ 0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,
+ 0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,
+ 0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,
+ 0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,
+ 0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,
+ 0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,
+ 0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,
+ 0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,
+ 0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,
+ 0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,
+ 0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,
+ 0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,
+ 0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,
+ 0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,
+ 0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,
+ 0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,
+ 0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,
+ 0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,
+ 0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,
+ 0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,
+ 0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,
+ 0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,
+ 0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,
+ 0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,
+ 0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,
+ 0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,
+ 0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,
+ 0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,
+ 0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,
+ 0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,
+ 0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,
+ 0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,
+ 0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,
+ 0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,
+ 0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,
+ 0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,
+ 0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,
+ 0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,
+ 0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,
+ 0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,
+ 0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,
+ 0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,
+ 0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,
+ 0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,
+ 0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,
+ 0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,
+ 0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,
+ 0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,
+ 0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,
+ 0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,
+ 0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,
+ 0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,
+ 0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,
+ 0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,
+ 0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,
+ 0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,
+ 0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,
+ 0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,
+ 0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,
+ 0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,
+ 0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,
+ 0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,
+ 0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,
+ 0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,
+ 0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,
+ 0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,
+ 0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,
+ 0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,
+ 0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,
+ 0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,
+ 0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,
+ 0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,
+ 0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,
+ 0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,
+ 0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,
+ 0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,
+ 0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,
+ 0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,
+ 0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,
+ 0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,
+ 0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,
+ 0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,
+ 0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,
+ 0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,
+ 0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,
+ 0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,
+ 0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,
+ 0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,
+ 0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,
+ 0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,
+ 0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,
+ 0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,
+ 0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,
+ 0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,
+ 0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,
+ 0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,
+ 0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,
+ 0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,
+ 0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,
+ 0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,
+ 0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,
+ 0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,
+ 0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,
+ 0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,
+ 0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,
+ 0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,
+ 0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,
+ 0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,
+ 0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,
+ 0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,
+ 0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,
+ 0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,
+ 0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,
+ 0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,
+ 0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,
+ 0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,
+ 0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,
+ 0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,
+ 0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,
+ 0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,
+ 0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,
+ 0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,
+ 0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,
+ 0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,
+ 0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,
+ 0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,
+ 0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,
+ 0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,
+ 0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,
+ 0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,
+ 0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,
+ 0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,
+ 0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,
+ 0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,
+ 0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,
+ 0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,
+ 0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,
+ 0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,
+ 0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,
+ 0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,
+ 0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,
+ 0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,
+ 0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,
+ 0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,
+ 0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,
+ 0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,
+ 0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,
+ 0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,
+ 0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,
+ 0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,
+ 0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,
+ 0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,
+ 0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,
+ 0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,
+ 0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,
+ 0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,
+ 0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,
+ 0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,
+ 0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,
+ 0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,
+ 0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,
+ 0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,
+ 0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,
+ 0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,
+ 0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,
+ 0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,
+ 0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,
+ 0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,
+ 0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,
+ 0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,
+ 0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,
+ 0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,
+ 0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,
+ 0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,
+ 0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,
+ 0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,
+ 0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,
+ 0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,
+ 0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,
+ 0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,
+ 0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,
+ 0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,
+ 0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,
+ 0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,
+ 0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,
+ 0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,
+ 0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,
+ 0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,
+ 0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,
+ 0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,
+ 0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,
+ 0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,
+ 0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,
+ 0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,
+ 0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,
+ 0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,
+ 0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,
+ 0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,
+ 0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,
+ 0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,
+ 0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,
+ 0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,
+ 0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,
+ 0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,
+ 0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,
+ 0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,
+ 0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,
+ 0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,
+ 0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,
+ 0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,
+ 0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,
+ 0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,
+ 0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,
+ 0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,
+ 0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,
+ 0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,
+ 0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,
+ 0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,
+ 0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,
+ 0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,
+ 0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,
+ 0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,
+ 0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,
+ 0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,
+ 0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,
+ 0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,
+ 0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,
+ 0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,
+ 0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,
+ 0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,
+ 0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,
+ 0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,
+ 0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,
+ 0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,
+ 0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,
+ 0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,
+ 0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,
+ 0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,
+ 0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,
+ 0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,
+ 0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,
+ 0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,
+ 0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,
+ 0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,
+ 0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,
+ 0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,
+ 0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,
+ 0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,
+ 0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,
+ 0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,
+ 0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,
+ 0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,
+ 0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,
+ 0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,
+ 0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,
+ 0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,
+ 0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,
+ 0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,
+ 0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,
+ 0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,
+ 0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,
+ 0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,
+ 0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,
+ 0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,
+ 0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,
+ 0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,
+ 0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,
+ 0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,
+ 0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,
+ 0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,
+ 0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,
+ 0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,
+ 0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,
+ 0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,
+ 0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,
+ 0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,
+ 0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,
+ 0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,
+ 0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,
+ 0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,
+ 0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,
+ 0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,
+ 0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,
+ 0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,
+ 0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,
+ 0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,
+ 0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,
+ 0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,
+ 0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,
+ 0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,
+ 0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,
+ 0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,
+ 0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,
+ 0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,
+ 0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,
+ 0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,
+ 0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,
+ 0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,
+ 0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,
+ 0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,
+ 0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,
+ 0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,
+ 0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,
+ 0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,
+ 0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,
+ 0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,
+ 0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,
+ 0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,
+ 0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,
+ 0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,
+ 0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,
+ 0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,
+ 0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,
+ 0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,
+ 0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,
+ 0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,
+ 0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,
+ 0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,
+ 0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,
+ 0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,
+ 0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,
+ 0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,
+ 0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,
+ 0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,
+ 0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,
+ 0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,
+ 0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,
+ 0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,
+ 0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,
+ 0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,
+ 0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,
+ 0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,
+ 0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,
+ 0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,
+ 0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,
+ 0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,
+ 0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,
+ 0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,
+ 0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,
+ 0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,
+ 0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,
+ 0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,
+ 0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,
+ 0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,
+ 0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,
+ 0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,
+ 0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,
+ 0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,
+ 0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,
+ 0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,
+ 0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,
+ 0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,
+ 0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,
+ 0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,
+ 0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,
+ 0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,
+ 0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,
+ 0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,
+ 0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,
+ 0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,
+ 0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,
+ 0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,
+ 0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,
+ 0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,
+ 0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,
+ 0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,
+ 0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,
+ 0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,
+ 0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,
+ 0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,
+ 0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,
+ 0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,
+ 0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,
+ 0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,
+ 0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,
+ 0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,
+ 0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,
+ 0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,
+ 0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,
+ 0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,
+ 0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,
+ 0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,
+ 0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,
+ 0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,
+ 0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,
+ 0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,
+ 0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,
+ 0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,
+ 0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,
+ 0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,
+ 0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,
+ 0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,
+ 0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,
+ 0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,
+ 0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,
+ 0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,
+ 0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,
+ 0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,
+ 0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,
+ 0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,
+ 0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,
+ 0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,
+ 0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,
+ 0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,
+ 0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,
+ 0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,
+ 0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,
+ 0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,
+ 0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,
+ 0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,
+ 0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,
+ 0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,
+ 0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,
+ 0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,
+ 0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,
+ 0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,
+ 0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,
+ 0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,
+ 0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,
+ 0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,
+ 0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,
+ 0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,
+ 0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,
+ 0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,
+ 0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,
+ 0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,
+ 0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,
+ 0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,
+ 0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,
+ 0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,
+ 0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,
+ 0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,
+ 0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,
+ 0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,
+ 0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,
+ 0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,
+ 0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,
+ 0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,
+ 0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,
+ 0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,
+ 0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,
+ 0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,
+ 0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,
+ 0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,
+ 0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,
+ 0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,
+ 0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,
+ 0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,
+ 0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,
+ 0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,
+ 0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,
+ 0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,
+ 0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,
+ 0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,
+ 0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,
+ 0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,
+ 0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,
+ 0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,
+ 0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,
+ 0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,
+ 0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,
+ 0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,
+ 0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,
+ 0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,
+ 0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,
+ 0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,
+ 0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,
+ 0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,
+ 0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,
+ 0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,
+ 0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,
+ 0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,
+ 0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,
+ 0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,
+ 0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,
+ 0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,
+ 0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,
+ 0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,
+ 0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,
+ 0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,
+ 0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,
+ 0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,
+ 0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,
+ 0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,
+ 0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,
+ 0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,
+ 0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,
+ 0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,
+ 0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,
+ 0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,
+ 0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,
+ 0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,
+ 0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,
+ 0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,
+ 0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,
+ 0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,
+ 0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,
+ 0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,
+ 0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,
+ 0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,
+ 0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,
+ 0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,
+ 0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,
+ 0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,
+ 0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,
+ 0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,
+ 0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,
+ 0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,
+ 0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,
+ 0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,
+ 0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,
+ 0x2737922, 0xee75323c, 0x270088e, 0xee81485c,
+ 0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,
+ 0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,
+ 0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,
+ 0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,
+ 0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,
+ 0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,
+ 0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,
+ 0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,
+ 0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,
+ 0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,
+ 0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,
+ 0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,
+ 0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,
+ 0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,
+ 0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,
+ 0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,
+ 0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,
+ 0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,
+ 0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,
+ 0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,
+ 0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,
+ 0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,
+ 0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,
+ 0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,
+ 0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,
+ 0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,
+ 0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,
+ 0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,
+ 0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,
+ 0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,
+ 0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,
+ 0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,
+ 0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,
+ 0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,
+ 0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,
+ 0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,
+ 0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,
+ 0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,
+ 0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,
+ 0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,
+ 0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,
+ 0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,
+ 0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,
+ 0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,
+ 0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,
+ 0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,
+ 0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,
+ 0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,
+ 0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,
+ 0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,
+ 0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,
+ 0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,
+ 0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,
+ 0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,
+ 0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,
+ 0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,
+ 0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,
+ 0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,
+ 0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,
+ 0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,
+ 0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,
+ 0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,
+ 0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,
+ 0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,
+ 0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,
+ 0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,
+ 0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,
+ 0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,
+ 0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,
+ 0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,
+ 0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,
+ 0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,
+ 0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,
+ 0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,
+ 0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,
+ 0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,
+ 0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,
+ 0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,
+ 0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,
+ 0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,
+ 0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,
+ 0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,
+ 0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,
+ 0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,
+ 0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,
+ 0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,
+ 0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,
+ 0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,
+ 0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,
+ 0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,
+ 0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,
+ 0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,
+ 0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,
+ 0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,
+ 0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,
+ 0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,
+ 0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,
+ 0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,
+ 0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,
+ 0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,
+ 0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,
+ 0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,
+ 0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,
+ 0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,
+ 0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,
+ 0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,
+ 0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,
+ 0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,
+ 0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,
+ 0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,
+ 0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,
+ 0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,
+ 0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,
+ 0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,
+ 0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,
+ 0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,
+ 0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,
+ 0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,
+ 0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,
+ 0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,
+ 0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,
+ 0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,
+ 0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,
+ 0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,
+ 0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,
+ 0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,
+ 0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,
+ 0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,
+ 0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,
+ 0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,
+ 0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,
+ 0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,
+ 0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,
+ 0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,
+ 0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,
+ 0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,
+ 0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,
+ 0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,
+ 0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,
+ 0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,
+ 0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,
+ 0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,
+ 0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,
+ 0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,
+ 0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,
+ 0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,
+ 0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,
+ 0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,
+ 0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,
+ 0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,
+ 0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,
+ 0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,
+ 0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,
+ 0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,
+ 0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,
+ 0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,
+ 0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,
+ 0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,
+ 0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,
+ 0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,
+ 0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,
+ 0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,
+ 0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,
+ 0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,
+ 0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,
+ 0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,
+ 0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,
+ 0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,
+ 0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,
+ 0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,
+ 0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,
+ 0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,
+ 0x13bd3, 0xff36f170, 0x11594, 0xff438234,
+ 0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,
+ 0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,
+ 0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,
+ 0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,
+ 0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,
+ 0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,
+ 0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,
+ 0x0, 0x0, 0x13c, 0xc90fe,
+ 0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,
+ 0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,
+ 0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,
+ 0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,
+ 0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,
+ 0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,
+ 0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,
+ 0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,
+ 0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,
+ 0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,
+ 0x25519, 0x1147271, 0x28c9c, 0x12102f4,
+ 0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,
+ 0x341f4, 0x146b438, 0x38356, 0x153448c,
+ 0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,
+ 0x45648, 0x178f536, 0x4a188, 0x1858552,
+ 0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,
+ 0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,
+ 0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,
+ 0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,
+ 0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,
+ 0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,
+ 0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,
+ 0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,
+ 0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,
+ 0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,
+ 0xd077c, 0x28d472e, 0xd88fd, 0x299d590,
+ 0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,
+ 0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,
+ 0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,
+ 0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,
+ 0x128574, 0x30ad245, 0x131f9b, 0x3175f91,
+ 0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,
+ 0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,
+ 0x164757, 0x3562038, 0x16f047, 0x362acc5,
+ 0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,
+ 0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,
+ 0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,
+ 0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,
+ 0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,
+ 0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,
+ 0x2064ab, 0x405c361, 0x213018, 0x4124dee,
+ 0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,
+ 0x23a124, 0x437eca4, 0x24766a, 0x444768d,
+ 0x254e27, 0x451004d, 0x262859, 0x45d89e2,
+ 0x270502, 0x46a134c, 0x27e421, 0x4769c8b,
+ 0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,
+ 0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,
+ 0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,
+ 0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,
+ 0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,
+ 0x321ce0, 0x5007674, 0x331986, 0x50cfd82,
+ 0x3418a2, 0x519845e, 0x351a33, 0x5260b08,
+ 0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,
+ 0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,
+ 0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,
+ 0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,
+ 0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,
+ 0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,
+ 0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,
+ 0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,
+ 0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,
+ 0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,
+ 0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,
+ 0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,
+ 0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,
+ 0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,
+ 0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,
+ 0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,
+ 0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,
+ 0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,
+ 0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,
+ 0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,
+ 0x669e18, 0x726dbae, 0x6806ce, 0x7335862,
+ 0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,
+ 0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,
+ 0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,
+ 0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,
+ 0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,
+ 0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,
+ 0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,
+ 0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,
+ 0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,
+ 0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,
+ 0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,
+ 0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,
+ 0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,
+ 0x91b01d, 0x884104b, 0x935d64, 0x8908483,
+ 0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,
+ 0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,
+ 0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,
+ 0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,
+ 0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,
+ 0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,
+ 0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,
+ 0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,
+ 0xb15502, 0x9640837, 0xb32e42, 0x9707635,
+ 0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,
+ 0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,
+ 0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,
+ 0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,
+ 0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,
+ 0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,
+ 0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,
+ 0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,
+ 0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,
+ 0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,
+ 0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,
+ 0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,
+ 0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,
+ 0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,
+ 0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,
+ 0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,
+ 0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,
+ 0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,
+ 0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,
+ 0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,
+ 0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,
+ 0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,
+ 0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,
+ 0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,
+ 0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,
+ 0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,
+ 0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,
+ 0x1278104, 0xc19b374, 0x129e276, 0xc260a31,
+ 0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,
+ 0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,
+ 0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,
+ 0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,
+ 0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,
+ 0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,
+ 0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,
+ 0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,
+ 0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,
+ 0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,
+ 0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,
+ 0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,
+ 0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,
+ 0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,
+ 0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,
+ 0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,
+ 0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,
+ 0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,
+ 0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,
+ 0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,
+ 0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,
+ 0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,
+ 0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,
+ 0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,
+ 0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,
+ 0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,
+ 0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,
+ 0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,
+ 0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,
+ 0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,
+ 0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,
+ 0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,
+ 0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,
+ 0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,
+ 0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,
+ 0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,
+ 0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,
+ 0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,
+ 0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,
+ 0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,
+ 0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,
+ 0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,
+ 0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,
+ 0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,
+ 0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,
+ 0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,
+ 0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,
+ 0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,
+ 0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,
+ 0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,
+ 0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,
+ 0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,
+ 0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,
+ 0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,
+ 0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,
+ 0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,
+ 0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,
+ 0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,
+ 0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,
+ 0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,
+ 0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,
+ 0x296615d, 0x12038584, 0x299ec05, 0x120f941a,
+ 0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,
+ 0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,
+ 0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,
+ 0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,
+ 0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,
+ 0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,
+ 0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,
+ 0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,
+ 0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,
+ 0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,
+ 0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,
+ 0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,
+ 0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,
+ 0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,
+ 0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,
+ 0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,
+ 0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,
+ 0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,
+ 0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,
+ 0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,
+ 0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,
+ 0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,
+ 0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,
+ 0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,
+ 0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,
+ 0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,
+ 0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,
+ 0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,
+ 0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,
+ 0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,
+ 0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,
+ 0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,
+ 0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,
+ 0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,
+ 0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,
+ 0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,
+ 0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,
+ 0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,
+ 0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,
+ 0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,
+ 0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,
+ 0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,
+ 0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,
+ 0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,
+ 0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,
+ 0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,
+ 0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,
+ 0x414392b, 0x167b949d, 0x418a46d, 0x16875823,
+ 0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,
+ 0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,
+ 0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,
+ 0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,
+ 0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,
+ 0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,
+ 0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,
+ 0x45c0219, 0x173763c9, 0x460923b, 0x17431933,
+ 0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,
+ 0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,
+ 0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,
+ 0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,
+ 0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,
+ 0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,
+ 0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,
+ 0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,
+ 0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,
+ 0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,
+ 0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,
+ 0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,
+ 0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,
+ 0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,
+ 0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,
+ 0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,
+ 0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,
+ 0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,
+ 0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,
+ 0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,
+ 0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,
+ 0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,
+ 0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,
+ 0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,
+ 0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,
+ 0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,
+ 0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,
+ 0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,
+ 0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,
+ 0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,
+ 0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,
+ 0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,
+ 0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,
+ 0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,
+ 0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,
+ 0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,
+ 0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,
+ 0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,
+ 0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,
+ 0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,
+ 0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,
+ 0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,
+ 0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,
+ 0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,
+ 0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,
+ 0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,
+ 0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,
+ 0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,
+ 0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,
+ 0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,
+ 0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,
+ 0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,
+ 0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,
+ 0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,
+ 0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,
+ 0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,
+ 0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,
+ 0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,
+ 0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,
+ 0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,
+ 0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,
+ 0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,
+ 0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,
+ 0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,
+ 0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,
+ 0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,
+ 0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,
+ 0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,
+ 0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,
+ 0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,
+ 0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,
+ 0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,
+ 0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,
+ 0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,
+ 0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,
+ 0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,
+ 0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,
+ 0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,
+ 0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,
+ 0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,
+ 0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,
+ 0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,
+ 0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,
+ 0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,
+ 0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,
+ 0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,
+ 0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,
+ 0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,
+ 0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,
+ 0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,
+ 0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,
+ 0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,
+ 0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,
+ 0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,
+ 0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,
+ 0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,
+ 0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,
+ 0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,
+ 0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,
+ 0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,
+ 0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,
+ 0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,
+ 0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,
+ 0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,
+ 0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,
+ 0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,
+ 0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,
+ 0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,
+ 0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,
+ 0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,
+ 0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,
+ 0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,
+ 0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,
+ 0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,
+ 0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,
+ 0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,
+ 0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,
+ 0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,
+ 0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,
+ 0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,
+ 0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,
+ 0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,
+ 0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,
+ 0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,
+ 0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,
+ 0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,
+ 0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,
+ 0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,
+ 0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,
+ 0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,
+ 0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,
+ 0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,
+ 0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,
+ 0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,
+ 0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,
+ 0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,
+ 0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,
+ 0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,
+ 0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,
+ 0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,
+ 0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,
+ 0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,
+ 0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,
+ 0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,
+ 0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,
+ 0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,
+ 0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,
+ 0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,
+ 0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,
+ 0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,
+ 0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,
+ 0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,
+ 0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,
+ 0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,
+ 0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,
+ 0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,
+ 0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,
+ 0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,
+ 0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,
+ 0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,
+ 0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,
+ 0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,
+ 0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,
+ 0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,
+ 0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,
+ 0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,
+ 0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,
+ 0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,
+ 0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,
+ 0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,
+ 0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,
+ 0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,
+ 0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,
+ 0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,
+ 0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,
+ 0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,
+ 0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,
+ 0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,
+ 0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,
+ 0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,
+ 0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,
+ 0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,
+ 0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,
+ 0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,
+ 0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,
+ 0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,
+ 0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,
+ 0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,
+ 0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,
+ 0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,
+ 0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,
+ 0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,
+ 0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,
+ 0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,
+ 0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,
+ 0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,
+ 0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,
+ 0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,
+ 0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,
+ 0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,
+ 0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,
+ 0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,
+ 0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,
+ 0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,
+ 0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,
+ 0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,
+ 0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,
+ 0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,
+ 0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,
+ 0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,
+ 0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,
+ 0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,
+ 0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,
+ 0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,
+ 0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,
+ 0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,
+ 0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,
+ 0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,
+ 0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,
+ 0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,
+ 0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,
+ 0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,
+ 0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,
+ 0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,
+ 0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,
+ 0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,
+ 0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,
+ 0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,
+ 0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,
+ 0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,
+ 0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,
+ 0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,
+ 0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,
+ 0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,
+ 0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,
+ 0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,
+ 0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,
+ 0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,
+ 0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,
+ 0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,
+ 0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,
+ 0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,
+ 0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,
+ 0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,
+ 0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,
+ 0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,
+ 0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,
+ 0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,
+ 0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,
+ 0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,
+ 0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,
+ 0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,
+ 0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,
+ 0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,
+ 0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,
+ 0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,
+ 0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,
+ 0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,
+ 0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,
+ 0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,
+ 0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,
+ 0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,
+ 0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,
+ 0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,
+ 0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,
+ 0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,
+ 0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,
+ 0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,
+ 0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,
+ 0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,
+ 0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,
+ 0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,
+ 0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,
+ 0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,
+ 0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,
+ 0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,
+ 0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,
+ 0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,
+ 0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,
+ 0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,
+ 0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,
+ 0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,
+ 0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,
+ 0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,
+ 0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,
+ 0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,
+ 0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,
+ 0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,
+ 0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,
+ 0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,
+ 0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,
+ 0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,
+ 0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,
+ 0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,
+ 0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,
+ 0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,
+ 0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,
+ 0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,
+ 0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,
+ 0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,
+ 0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,
+ 0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,
+ 0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,
+ 0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,
+ 0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,
+ 0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,
+ 0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,
+ 0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,
+ 0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,
+ 0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,
+ 0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,
+ 0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,
+ 0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,
+ 0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,
+ 0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,
+ 0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,
+ 0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,
+ 0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,
+ 0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,
+ 0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,
+ 0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,
+ 0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,
+ 0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,
+ 0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,
+ 0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,
+ 0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,
+ 0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,
+ 0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,
+ 0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,
+ 0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,
+ 0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,
+ 0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,
+ 0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,
+ 0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,
+ 0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,
+ 0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,
+ 0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,
+ 0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,
+ 0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,
+ 0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,
+ 0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,
+ 0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,
+ 0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,
+ 0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,
+ 0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,
+ 0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,
+ 0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,
+ 0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,
+ 0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,
+ 0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,
+ 0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,
+ 0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,
+ 0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,
+ 0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,
+ 0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,
+ 0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,
+ 0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,
+ 0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,
+ 0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,
+ 0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,
+ 0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,
+ 0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,
+ 0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,
+ 0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,
+ 0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,
+ 0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,
+ 0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,
+ 0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,
+ 0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,
+ 0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,
+ 0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,
+ 0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,
+ 0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,
+ 0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,
+ 0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,
+ 0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,
+ 0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,
+ 0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,
+ 0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,
+ 0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,
+ 0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,
+ 0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,
+ 0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,
+ 0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,
+ 0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,
+ 0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,
+ 0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,
+ 0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,
+ 0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,
+ 0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,
+ 0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,
+ 0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,
+ 0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,
+ 0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,
+ 0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,
+ 0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,
+ 0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,
+ 0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,
+ 0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,
+ 0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,
+ 0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,
+ 0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,
+ 0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,
+ 0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,
+ 0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,
+ 0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,
+ 0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,
+ 0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,
+ 0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,
+ 0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,
+ 0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,
+ 0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,
+ 0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,
+ 0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,
+ 0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,
+ 0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,
+ 0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,
+ 0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,
+ 0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,
+ 0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,
+ 0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,
+ 0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,
+ 0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,
+ 0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,
+ 0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,
+ 0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,
+ 0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,
+ 0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,
+ 0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,
+ 0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,
+ 0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,
+ 0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,
+ 0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,
+ 0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,
+ 0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,
+ 0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,
+ 0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,
+ 0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,
+ 0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,
+ 0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,
+ 0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,
+ 0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,
+ 0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,
+ 0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,
+ 0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,
+ 0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,
+ 0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,
+ 0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,
+ 0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,
+ 0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,
+ 0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,
+ 0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,
+ 0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,
+ 0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,
+ 0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,
+ 0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,
+ 0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,
+ 0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,
+ 0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,
+ 0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,
+ 0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,
+ 0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,
+ 0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,
+ 0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,
+ 0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,
+ 0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,
+ 0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,
+ 0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,
+ 0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,
+ 0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,
+ 0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,
+ 0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,
+ 0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,
+ 0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,
+ 0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,
+ 0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,
+ 0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,
+ 0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,
+ 0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,
+ 0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,
+ 0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,
+ 0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,
+ 0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,
+ 0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,
+ 0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,
+ 0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,
+ 0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,
+ 0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,
+ 0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,
+ 0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,
+ 0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,
+ 0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,
+ 0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,
+ 0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,
+ 0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,
+ 0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,
+ 0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,
+ 0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,
+ 0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,
+ 0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,
+ 0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,
+ 0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,
+ 0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,
+ 0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,
+ 0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,
+ 0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,
+ 0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,
+ 0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,
+ 0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,
+ 0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,
+ 0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,
+ 0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,
+ 0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,
+ 0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,
+ 0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,
+ 0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,
+ 0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,
+ 0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,
+ 0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,
+ 0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,
+ 0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,
+ 0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,
+ 0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,
+ 0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,
+ 0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,
+ 0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,
+ 0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,
+ 0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,
+ 0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,
+ 0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,
+ 0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,
+ 0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,
+ 0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,
+ 0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,
+ 0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,
+ 0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,
+ 0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,
+ 0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,
+ 0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,
+ 0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,
+ 0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,
+ 0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,
+ 0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,
+ 0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,
+ 0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,
+ 0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,
+ 0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,
+ 0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,
+ 0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,
+ 0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,
+ 0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,
+ 0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,
+ 0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,
+ 0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,
+ 0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,
+ 0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,
+ 0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,
+ 0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,
+ 0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,
+ 0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,
+ 0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,
+ 0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,
+ 0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,
+ 0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,
+ 0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,
+ 0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,
+ 0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,
+ 0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,
+ 0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,
+ 0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,
+ 0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,
+ 0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,
+ 0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,
+ 0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,
+ 0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,
+ 0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,
+ 0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,
+ 0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,
+ 0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,
+ 0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,
+ 0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,
+ 0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,
+ 0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,
+ 0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,
+ 0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,
+ 0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,
+ 0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,
+ 0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,
+ 0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,
+ 0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,
+ 0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,
+ 0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,
+ 0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,
+ 0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,
+ 0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,
+ 0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,
+ 0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,
+ 0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,
+ 0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,
+ 0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,
+ 0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,
+ 0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,
+ 0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,
+ 0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,
+ 0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,
+ 0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,
+ 0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,
+ 0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,
+ 0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,
+ 0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,
+ 0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,
+ 0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,
+ 0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,
+ 0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,
+ 0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,
+ 0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,
+ 0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,
+ 0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,
+ 0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,
+ 0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,
+ 0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,
+ 0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,
+ 0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,
+ 0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,
+ 0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,
+ 0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,
+ 0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,
+ 0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,
+ 0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,
+ 0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,
+ 0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,
+ 0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,
+ 0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,
+ 0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,
+ 0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,
+ 0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,
+ 0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,
+ 0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,
+ 0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,
+ 0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,
+ 0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,
+ 0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,
+ 0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,
+ 0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,
+ 0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,
+ 0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,
+ 0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,
+ 0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,
+ 0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,
+ 0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,
+ 0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,
+ 0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,
+ 0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,
+ 0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,
+ 0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,
+ 0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,
+ 0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,
+ 0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,
+ 0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,
+ 0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,
+ 0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,
+ 0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,
+ 0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,
+ 0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,
+ 0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,
+ 0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,
+ 0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,
+ 0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,
+ 0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,
+ 0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,
+ 0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,
+ 0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,
+ 0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,
+ 0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,
+ 0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,
+ 0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,
+ 0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,
+ 0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,
+ 0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,
+ 0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,
+ 0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,
+ 0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,
+ 0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,
+ 0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,
+ 0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,
+ 0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,
+ 0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,
+ 0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,
+ 0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,
+ 0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,
+ 0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,
+ 0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,
+ 0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,
+ 0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,
+ 0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,
+ 0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,
+ 0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,
+ 0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,
+ 0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,
+ 0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,
+ 0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,
+ 0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,
+ 0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,
+ 0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,
+ 0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,
+ 0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,
+ 0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,
+ 0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,
+ 0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,
+ 0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,
+ 0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,
+ 0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,
+ 0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,
+ 0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,
+ 0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,
+ 0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,
+ 0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,
+ 0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,
+ 0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,
+ 0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,
+ 0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,
+ 0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,
+ 0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,
+ 0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,
+ 0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,
+ 0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,
+ 0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,
+ 0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,
+ 0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,
+ 0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,
+ 0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,
+ 0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,
+ 0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,
+ 0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,
+ 0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,
+ 0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,
+ 0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,
+ 0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,
+ 0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,
+ 0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,
+ 0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,
+ 0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,
+ 0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,
+ 0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,
+ 0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,
+ 0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,
+ 0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,
+ 0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,
+ 0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,
+ 0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,
+ 0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,
+ 0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,
+ 0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,
+ 0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,
+ 0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,
+ 0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,
+ 0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,
+ 0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,
+ 0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,
+ 0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,
+ 0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,
+ 0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,
+ 0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,
+ 0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,
+ 0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,
+ 0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,
+ 0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,
+ 0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,
+ 0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,
+ 0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,
+ 0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,
+ 0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,
+ 0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,
+ 0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,
+ 0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,
+ 0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,
+ 0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,
+ 0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,
+ 0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,
+ 0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,
+ 0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,
+};
+
+
+/**
+* \par
+* Generation of realCoefBQ31 array:
+* \par
+* n = 4096
+* for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }
+* \par
+* Convert to fixed point Q31 format
+* round(pBTable[i] * pow(2, 31))
+*
+*/
+
+static const q31_t realCoefBQ31[8192] = {
+ 0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,
+ 0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,
+ 0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,
+ 0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,
+ 0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,
+ 0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,
+ 0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,
+ 0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,
+ 0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,
+ 0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,
+ 0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,
+ 0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,
+ 0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,
+ 0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,
+ 0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,
+ 0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,
+ 0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,
+ 0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,
+ 0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,
+ 0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,
+ 0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,
+ 0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,
+ 0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,
+ 0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,
+ 0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,
+ 0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,
+ 0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,
+ 0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,
+ 0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,
+ 0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,
+ 0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,
+ 0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,
+ 0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,
+ 0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,
+ 0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,
+ 0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,
+ 0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,
+ 0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,
+ 0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,
+ 0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,
+ 0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,
+ 0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,
+ 0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,
+ 0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,
+ 0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,
+ 0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,
+ 0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,
+ 0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,
+ 0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,
+ 0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,
+ 0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,
+ 0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,
+ 0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,
+ 0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,
+ 0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,
+ 0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,
+ 0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,
+ 0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,
+ 0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,
+ 0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,
+ 0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,
+ 0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,
+ 0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,
+ 0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,
+ 0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,
+ 0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,
+ 0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,
+ 0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,
+ 0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,
+ 0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,
+ 0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,
+ 0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,
+ 0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,
+ 0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,
+ 0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,
+ 0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,
+ 0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,
+ 0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,
+ 0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,
+ 0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,
+ 0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,
+ 0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,
+ 0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,
+ 0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,
+ 0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,
+ 0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,
+ 0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,
+ 0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,
+ 0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,
+ 0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,
+ 0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,
+ 0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,
+ 0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,
+ 0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,
+ 0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,
+ 0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,
+ 0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,
+ 0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,
+ 0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,
+ 0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,
+ 0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,
+ 0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,
+ 0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,
+ 0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,
+ 0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,
+ 0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,
+ 0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,
+ 0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,
+ 0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,
+ 0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,
+ 0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,
+ 0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,
+ 0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,
+ 0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,
+ 0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,
+ 0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,
+ 0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,
+ 0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,
+ 0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,
+ 0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,
+ 0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,
+ 0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,
+ 0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,
+ 0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,
+ 0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,
+ 0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,
+ 0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,
+ 0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,
+ 0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,
+ 0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,
+ 0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,
+ 0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,
+ 0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,
+ 0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,
+ 0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,
+ 0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,
+ 0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,
+ 0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,
+ 0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,
+ 0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,
+ 0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,
+ 0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,
+ 0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,
+ 0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,
+ 0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,
+ 0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,
+ 0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,
+ 0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,
+ 0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,
+ 0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,
+ 0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,
+ 0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,
+ 0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,
+ 0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,
+ 0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,
+ 0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,
+ 0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,
+ 0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,
+ 0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,
+ 0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,
+ 0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,
+ 0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,
+ 0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,
+ 0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,
+ 0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,
+ 0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,
+ 0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,
+ 0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,
+ 0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,
+ 0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,
+ 0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,
+ 0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,
+ 0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,
+ 0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,
+ 0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,
+ 0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,
+ 0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,
+ 0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,
+ 0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,
+ 0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,
+ 0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,
+ 0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,
+ 0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,
+ 0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,
+ 0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,
+ 0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,
+ 0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,
+ 0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,
+ 0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,
+ 0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,
+ 0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,
+ 0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,
+ 0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,
+ 0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,
+ 0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,
+ 0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,
+ 0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,
+ 0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,
+ 0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,
+ 0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,
+ 0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,
+ 0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,
+ 0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,
+ 0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,
+ 0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,
+ 0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,
+ 0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,
+ 0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,
+ 0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,
+ 0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,
+ 0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,
+ 0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,
+ 0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,
+ 0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,
+ 0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,
+ 0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,
+ 0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,
+ 0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,
+ 0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,
+ 0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,
+ 0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,
+ 0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,
+ 0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,
+ 0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,
+ 0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,
+ 0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,
+ 0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,
+ 0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,
+ 0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,
+ 0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,
+ 0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,
+ 0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,
+ 0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,
+ 0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,
+ 0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,
+ 0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,
+ 0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,
+ 0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,
+ 0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,
+ 0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,
+ 0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,
+ 0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,
+ 0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,
+ 0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,
+ 0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,
+ 0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,
+ 0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,
+ 0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,
+ 0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,
+ 0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,
+ 0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,
+ 0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,
+ 0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,
+ 0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,
+ 0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,
+ 0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,
+ 0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,
+ 0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,
+ 0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,
+ 0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,
+ 0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,
+ 0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,
+ 0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,
+ 0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,
+ 0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,
+ 0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,
+ 0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,
+ 0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,
+ 0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,
+ 0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,
+ 0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,
+ 0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,
+ 0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,
+ 0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,
+ 0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,
+ 0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,
+ 0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,
+ 0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,
+ 0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,
+ 0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,
+ 0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,
+ 0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,
+ 0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,
+ 0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,
+ 0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,
+ 0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,
+ 0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,
+ 0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,
+ 0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,
+ 0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,
+ 0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,
+ 0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,
+ 0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,
+ 0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,
+ 0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,
+ 0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,
+ 0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,
+ 0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,
+ 0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,
+ 0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,
+ 0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,
+ 0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,
+ 0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,
+ 0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,
+ 0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,
+ 0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,
+ 0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,
+ 0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,
+ 0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,
+ 0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,
+ 0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,
+ 0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,
+ 0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,
+ 0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,
+ 0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,
+ 0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,
+ 0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,
+ 0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,
+ 0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,
+ 0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,
+ 0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,
+ 0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,
+ 0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,
+ 0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,
+ 0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,
+ 0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,
+ 0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,
+ 0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,
+ 0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,
+ 0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,
+ 0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,
+ 0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,
+ 0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,
+ 0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,
+ 0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,
+ 0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,
+ 0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,
+ 0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,
+ 0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,
+ 0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,
+ 0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,
+ 0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,
+ 0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,
+ 0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,
+ 0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,
+ 0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,
+ 0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,
+ 0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,
+ 0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,
+ 0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,
+ 0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,
+ 0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,
+ 0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,
+ 0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,
+ 0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,
+ 0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,
+ 0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,
+ 0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,
+ 0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,
+ 0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,
+ 0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,
+ 0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,
+ 0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,
+ 0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,
+ 0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,
+ 0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,
+ 0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,
+ 0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,
+ 0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,
+ 0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,
+ 0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,
+ 0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,
+ 0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,
+ 0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,
+ 0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,
+ 0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,
+ 0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,
+ 0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,
+ 0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,
+ 0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,
+ 0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,
+ 0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,
+ 0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,
+ 0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,
+ 0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,
+ 0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,
+ 0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,
+ 0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,
+ 0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,
+ 0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,
+ 0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,
+ 0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,
+ 0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,
+ 0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,
+ 0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,
+ 0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,
+ 0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,
+ 0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,
+ 0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,
+ 0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,
+ 0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,
+ 0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,
+ 0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,
+ 0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,
+ 0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,
+ 0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,
+ 0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,
+ 0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,
+ 0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,
+ 0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,
+ 0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,
+ 0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,
+ 0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,
+ 0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,
+ 0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,
+ 0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,
+ 0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,
+ 0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,
+ 0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,
+ 0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,
+ 0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,
+ 0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,
+ 0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,
+ 0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,
+ 0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,
+ 0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,
+ 0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,
+ 0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,
+ 0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,
+ 0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,
+ 0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,
+ 0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,
+ 0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,
+ 0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,
+ 0x67878893, 0x32554840, 0x679169d5, 0x324d8450,
+ 0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,
+ 0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,
+ 0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,
+ 0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,
+ 0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,
+ 0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,
+ 0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,
+ 0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,
+ 0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,
+ 0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,
+ 0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,
+ 0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,
+ 0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,
+ 0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,
+ 0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,
+ 0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,
+ 0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,
+ 0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,
+ 0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,
+ 0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,
+ 0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,
+ 0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,
+ 0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,
+ 0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,
+ 0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,
+ 0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,
+ 0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,
+ 0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,
+ 0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,
+ 0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,
+ 0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,
+ 0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,
+ 0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,
+ 0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,
+ 0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,
+ 0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,
+ 0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,
+ 0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,
+ 0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,
+ 0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,
+ 0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,
+ 0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,
+ 0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,
+ 0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,
+ 0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,
+ 0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,
+ 0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,
+ 0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,
+ 0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,
+ 0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,
+ 0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,
+ 0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,
+ 0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,
+ 0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,
+ 0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,
+ 0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,
+ 0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,
+ 0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,
+ 0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,
+ 0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,
+ 0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,
+ 0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,
+ 0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,
+ 0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,
+ 0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,
+ 0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,
+ 0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,
+ 0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,
+ 0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,
+ 0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,
+ 0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,
+ 0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,
+ 0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,
+ 0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,
+ 0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,
+ 0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,
+ 0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,
+ 0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,
+ 0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,
+ 0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,
+ 0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,
+ 0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,
+ 0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,
+ 0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,
+ 0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,
+ 0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,
+ 0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,
+ 0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,
+ 0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,
+ 0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,
+ 0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,
+ 0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,
+ 0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,
+ 0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,
+ 0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,
+ 0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,
+ 0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,
+ 0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,
+ 0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,
+ 0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,
+ 0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,
+ 0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,
+ 0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,
+ 0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,
+ 0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,
+ 0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,
+ 0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,
+ 0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,
+ 0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,
+ 0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,
+ 0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,
+ 0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,
+ 0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,
+ 0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,
+ 0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,
+ 0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,
+ 0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,
+ 0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,
+ 0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,
+ 0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,
+ 0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,
+ 0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,
+ 0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,
+ 0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,
+ 0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,
+ 0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,
+ 0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,
+ 0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,
+ 0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,
+ 0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,
+ 0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,
+ 0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,
+ 0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,
+ 0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,
+ 0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,
+ 0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,
+ 0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,
+ 0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,
+ 0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,
+ 0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,
+ 0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,
+ 0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,
+ 0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,
+ 0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,
+ 0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,
+ 0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,
+ 0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,
+ 0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,
+ 0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,
+ 0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,
+ 0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,
+ 0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,
+ 0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,
+ 0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,
+ 0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,
+ 0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,
+ 0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,
+ 0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,
+ 0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,
+ 0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,
+ 0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,
+ 0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,
+ 0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,
+ 0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,
+ 0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,
+ 0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,
+ 0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,
+ 0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,
+ 0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,
+ 0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,
+ 0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,
+ 0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,
+ 0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,
+ 0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,
+ 0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,
+ 0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,
+ 0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,
+ 0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,
+ 0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,
+ 0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,
+ 0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,
+ 0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,
+ 0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,
+ 0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,
+ 0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,
+ 0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,
+ 0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,
+ 0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,
+ 0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,
+ 0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,
+ 0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,
+ 0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,
+ 0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,
+ 0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,
+ 0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,
+ 0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,
+ 0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,
+ 0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,
+ 0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,
+ 0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,
+ 0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,
+ 0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,
+ 0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,
+ 0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,
+ 0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,
+ 0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,
+ 0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,
+ 0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,
+ 0x75608af1, 0x234facda, 0x756778d9, 0x23453125,
+ 0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,
+ 0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,
+ 0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,
+ 0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,
+ 0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,
+ 0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,
+ 0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,
+ 0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,
+ 0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,
+ 0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,
+ 0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,
+ 0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,
+ 0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,
+ 0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,
+ 0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,
+ 0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,
+ 0x76479a8e, 0x21e84d76, 0x764e41e2, 0x21dda46a,
+ 0x7654e71d, 0x21d2fa0f, 0x765b8a41, 0x21c84e67,
+ 0x76622b4c, 0x21bda171, 0x7668ca3e, 0x21b2f32e,
+ 0x766f6717, 0x21a8439e, 0x767601d7, 0x219d92c2,
+ 0x767c9a7e, 0x2192e09b, 0x7683310b, 0x21882d28,
+ 0x7689c57d, 0x217d786a, 0x769057d6, 0x2172c262,
+ 0x7696e814, 0x21680b0f, 0x769d7637, 0x215d5273,
+ 0x76a4023f, 0x2152988d, 0x76aa8c2c, 0x2147dd5f,
+ 0x76b113fd, 0x213d20e8, 0x76b799b3, 0x21326329,
+ 0x76be1d4c, 0x2127a423, 0x76c49ec9, 0x211ce3d5,
+ 0x76cb1e2a, 0x21122240, 0x76d19b6e, 0x21075f65,
+ 0x76d81695, 0x20fc9b44, 0x76de8f9e, 0x20f1d5de,
+ 0x76e5068a, 0x20e70f32, 0x76eb7b58, 0x20dc4742,
+ 0x76f1ee09, 0x20d17e0d, 0x76f85e9a, 0x20c6b395,
+ 0x76fecd0e, 0x20bbe7d8, 0x77053962, 0x20b11ad9,
+ 0x770ba398, 0x20a64c97, 0x77120bae, 0x209b7d13,
+ 0x771871a5, 0x2090ac4d, 0x771ed57c, 0x2085da46,
+ 0x77253733, 0x207b06fe, 0x772b96ca, 0x20703275,
+ 0x7731f440, 0x20655cac, 0x77384f95, 0x205a85a3,
+ 0x773ea8ca, 0x204fad5b, 0x7744ffdd, 0x2044d3d4,
+ 0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,
+ 0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,
+ 0x77649341, 0x200e8190, 0x776add88, 0x2003a099,
+ 0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,
+ 0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,
+ 0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,
+ 0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,
+ 0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,
+ 0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,
+ 0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,
+ 0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,
+ 0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,
+ 0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,
+ 0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,
+ 0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,
+ 0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,
+ 0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,
+ 0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,
+ 0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,
+ 0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,
+ 0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,
+ 0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,
+ 0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,
+ 0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,
+ 0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,
+ 0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,
+ 0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,
+ 0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,
+ 0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,
+ 0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,
+ 0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,
+ 0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,
+ 0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,
+ 0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,
+ 0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,
+ 0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,
+ 0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,
+ 0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,
+ 0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,
+ 0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,
+ 0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,
+ 0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,
+ 0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,
+ 0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,
+ 0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,
+ 0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,
+ 0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,
+ 0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,
+ 0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,
+ 0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,
+ 0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,
+ 0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,
+ 0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,
+ 0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,
+ 0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,
+ 0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,
+ 0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,
+ 0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,
+ 0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,
+ 0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,
+ 0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,
+ 0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,
+ 0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,
+ 0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,
+ 0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,
+ 0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,
+ 0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,
+ 0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,
+ 0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,
+ 0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,
+ 0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,
+ 0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,
+ 0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,
+ 0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,
+ 0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,
+ 0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,
+ 0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,
+ 0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,
+ 0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,
+ 0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,
+ 0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,
+ 0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,
+ 0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,
+ 0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,
+ 0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,
+ 0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,
+ 0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,
+ 0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,
+ 0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,
+ 0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,
+ 0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,
+ 0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,
+ 0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,
+ 0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,
+ 0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,
+ 0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,
+ 0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,
+ 0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,
+ 0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,
+ 0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,
+ 0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,
+ 0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,
+ 0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,
+ 0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,
+ 0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,
+ 0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,
+ 0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,
+ 0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,
+ 0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,
+ 0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,
+ 0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,
+ 0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,
+ 0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,
+ 0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,
+ 0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,
+ 0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,
+ 0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,
+ 0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,
+ 0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,
+ 0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,
+ 0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,
+ 0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,
+ 0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,
+ 0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,
+ 0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,
+ 0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,
+ 0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,
+ 0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,
+ 0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,
+ 0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,
+ 0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,
+ 0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,
+ 0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,
+ 0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,
+ 0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,
+ 0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,
+ 0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,
+ 0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,
+ 0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,
+ 0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,
+ 0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,
+ 0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,
+ 0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,
+ 0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,
+ 0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,
+ 0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,
+ 0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,
+ 0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,
+ 0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,
+ 0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,
+ 0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,
+ 0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,
+ 0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,
+ 0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,
+ 0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,
+ 0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,
+ 0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,
+ 0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,
+ 0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,
+ 0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,
+ 0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,
+ 0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,
+ 0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,
+ 0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,
+ 0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,
+ 0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,
+ 0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,
+ 0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,
+ 0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,
+ 0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,
+ 0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,
+ 0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,
+ 0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,
+ 0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,
+ 0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,
+ 0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,
+ 0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,
+ 0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,
+ 0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,
+ 0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,
+ 0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,
+ 0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,
+ 0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,
+ 0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,
+ 0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,
+ 0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,
+ 0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,
+ 0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,
+ 0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,
+ 0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,
+ 0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,
+ 0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,
+ 0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,
+ 0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,
+ 0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,
+ 0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,
+ 0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,
+ 0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,
+ 0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,
+ 0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,
+ 0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,
+ 0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,
+ 0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,
+ 0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,
+ 0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,
+ 0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,
+ 0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,
+ 0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,
+ 0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,
+ 0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,
+ 0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,
+ 0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,
+ 0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,
+ 0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,
+ 0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,
+ 0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,
+ 0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,
+ 0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,
+ 0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,
+ 0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,
+ 0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,
+ 0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,
+ 0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,
+ 0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,
+ 0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,
+ 0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,
+ 0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,
+ 0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,
+ 0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,
+ 0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,
+ 0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,
+ 0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,
+ 0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,
+ 0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,
+ 0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,
+ 0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,
+ 0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,
+ 0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,
+ 0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,
+ 0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,
+ 0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,
+ 0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,
+ 0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,
+ 0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,
+ 0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,
+ 0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,
+ 0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,
+ 0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,
+ 0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,
+ 0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,
+ 0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,
+ 0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,
+ 0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,
+ 0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,
+ 0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,
+ 0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,
+ 0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,
+ 0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,
+ 0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,
+ 0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,
+ 0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,
+ 0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,
+ 0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,
+ 0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,
+ 0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,
+ 0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,
+ 0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,
+ 0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,
+ 0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,
+ 0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,
+ 0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,
+ 0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,
+ 0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,
+ 0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,
+ 0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,
+ 0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,
+ 0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,
+ 0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,
+ 0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,
+ 0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,
+ 0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,
+ 0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,
+ 0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,
+ 0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,
+ 0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,
+ 0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,
+ 0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,
+ 0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,
+ 0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,
+ 0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,
+ 0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,
+ 0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,
+ 0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,
+ 0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,
+ 0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,
+ 0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,
+ 0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,
+ 0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,
+ 0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,
+ 0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,
+ 0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,
+ 0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,
+ 0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,
+ 0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,
+ 0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,
+ 0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,
+ 0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,
+ 0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,
+ 0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,
+ 0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,
+ 0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,
+ 0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,
+ 0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,
+ 0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,
+ 0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,
+ 0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,
+ 0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,
+ 0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,
+ 0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,
+ 0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,
+ 0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,
+ 0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,
+ 0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,
+ 0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,
+ 0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,
+ 0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,
+ 0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,
+ 0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,
+ 0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,
+ 0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,
+ 0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,
+ 0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,
+ 0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,
+ 0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,
+ 0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,
+ 0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,
+ 0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,
+ 0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,
+ 0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,
+ 0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,
+ 0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,
+ 0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,
+ 0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,
+ 0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,
+ 0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,
+ 0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,
+ 0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,
+ 0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,
+ 0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,
+ 0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,
+ 0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,
+ 0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,
+ 0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,
+ 0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,
+ 0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,
+ 0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,
+ 0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,
+ 0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,
+ 0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,
+ 0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,
+ 0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,
+ 0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,
+ 0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,
+ 0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,
+ 0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,
+ 0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,
+ 0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,
+ 0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,
+ 0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,
+ 0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,
+ 0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,
+ 0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,
+ 0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,
+ 0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,
+ 0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,
+ 0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,
+ 0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,
+ 0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,
+ 0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,
+ 0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,
+ 0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,
+ 0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,
+ 0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,
+ 0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,
+ 0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,
+ 0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,
+ 0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,
+ 0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,
+ 0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,
+ 0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,
+ 0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,
+ 0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,
+ 0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,
+ 0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,
+ 0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,
+ 0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,
+ 0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,
+ 0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,
+ 0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,
+ 0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,
+ 0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,
+ 0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,
+ 0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,
+ 0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,
+ 0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,
+ 0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,
+ 0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,
+ 0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,
+ 0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,
+ 0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,
+ 0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,
+ 0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,
+ 0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,
+ 0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,
+ 0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,
+ 0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,
+ 0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,
+ 0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,
+ 0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,
+ 0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,
+ 0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,
+ 0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,
+ 0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,
+ 0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,
+ 0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,
+ 0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,
+ 0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,
+ 0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,
+ 0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,
+ 0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,
+ 0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,
+ 0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,
+ 0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,
+ 0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,
+ 0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,
+ 0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,
+ 0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,
+ 0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,
+ 0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,
+ 0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,
+ 0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,
+ 0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,
+ 0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,
+ 0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,
+ 0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,
+ 0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,
+ 0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,
+ 0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,
+ 0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,
+ 0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,
+ 0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,
+ 0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,
+ 0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,
+ 0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,
+ 0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,
+ 0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,
+ 0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,
+ 0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,
+ 0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,
+ 0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,
+ 0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,
+ 0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,
+ 0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,
+ 0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,
+ 0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,
+ 0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,
+ 0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,
+ 0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,
+ 0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,
+ 0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,
+ 0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,
+ 0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,
+ 0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,
+ 0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,
+ 0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,
+ 0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,
+ 0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,
+ 0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,
+ 0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,
+ 0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,
+ 0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,
+ 0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,
+ 0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,
+ 0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,
+ 0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,
+ 0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,
+ 0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,
+ 0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,
+ 0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,
+ 0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,
+ 0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,
+ 0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,
+ 0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,
+ 0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,
+ 0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,
+ 0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,
+ 0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,
+ 0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,
+ 0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,
+ 0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,
+ 0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,
+ 0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,
+ 0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,
+ 0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,
+ 0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,
+ 0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,
+ 0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,
+ 0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,
+ 0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,
+ 0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,
+ 0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,
+ 0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,
+ 0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,
+ 0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,
+ 0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,
+ 0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,
+ 0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,
+ 0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,
+ 0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,
+ 0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,
+ 0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,
+ 0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,
+ 0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,
+ 0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,
+ 0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,
+ 0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,
+ 0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,
+ 0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,
+ 0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,
+ 0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,
+ 0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,
+ 0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,
+ 0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,
+ 0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,
+ 0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,
+ 0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,
+ 0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,
+ 0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,
+ 0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,
+ 0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,
+ 0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,
+ 0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,
+ 0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,
+ 0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,
+ 0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,
+ 0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,
+ 0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,
+ 0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,
+ 0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,
+ 0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,
+ 0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,
+ 0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,
+ 0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,
+ 0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,
+ 0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,
+ 0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,
+ 0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,
+ 0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,
+ 0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,
+ 0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,
+ 0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,
+ 0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,
+ 0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,
+ 0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,
+ 0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,
+ 0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,
+ 0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,
+ 0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,
+ 0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,
+ 0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,
+ 0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,
+ 0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,
+ 0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,
+ 0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,
+ 0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,
+ 0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,
+ 0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,
+ 0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,
+ 0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,
+ 0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,
+ 0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,
+ 0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,
+ 0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,
+ 0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,
+ 0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,
+ 0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,
+ 0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,
+ 0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,
+ 0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,
+ 0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,
+ 0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,
+ 0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,
+ 0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,
+ 0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,
+ 0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,
+ 0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,
+ 0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,
+ 0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,
+ 0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,
+ 0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,
+ 0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,
+ 0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,
+ 0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,
+ 0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,
+ 0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,
+ 0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,
+ 0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,
+ 0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,
+ 0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,
+ 0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,
+ 0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,
+ 0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,
+ 0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,
+ 0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,
+ 0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,
+ 0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,
+ 0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,
+ 0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,
+ 0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,
+ 0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,
+ 0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,
+ 0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,
+ 0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,
+ 0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,
+ 0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,
+ 0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,
+ 0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,
+ 0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,
+ 0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,
+ 0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,
+ 0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,
+ 0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,
+ 0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,
+ 0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,
+ 0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,
+ 0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,
+ 0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,
+ 0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,
+ 0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,
+ 0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,
+ 0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,
+ 0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,
+ 0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,
+ 0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,
+ 0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,
+ 0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,
+ 0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,
+ 0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,
+ 0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,
+ 0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,
+ 0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,
+ 0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,
+ 0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,
+ 0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,
+ 0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,
+ 0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,
+ 0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,
+ 0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,
+ 0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,
+ 0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,
+ 0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,
+ 0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,
+ 0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,
+ 0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,
+ 0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,
+ 0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,
+ 0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,
+ 0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,
+ 0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,
+ 0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,
+ 0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,
+ 0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,
+ 0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,
+ 0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,
+ 0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,
+ 0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,
+ 0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,
+ 0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,
+ 0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,
+ 0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,
+ 0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,
+ 0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,
+ 0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,
+ 0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,
+ 0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,
+ 0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,
+ 0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,
+ 0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,
+ 0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,
+ 0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,
+ 0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,
+ 0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,
+ 0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,
+ 0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,
+ 0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,
+ 0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,
+ 0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,
+ 0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,
+ 0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,
+ 0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,
+ 0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,
+ 0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,
+ 0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,
+ 0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,
+ 0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,
+ 0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,
+ 0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,
+ 0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,
+ 0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,
+ 0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,
+ 0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,
+ 0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,
+ 0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,
+ 0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,
+ 0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,
+ 0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,
+ 0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,
+ 0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,
+ 0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,
+ 0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,
+ 0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,
+ 0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,
+ 0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,
+ 0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,
+ 0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,
+ 0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,
+ 0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,
+ 0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,
+ 0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,
+ 0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,
+ 0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,
+ 0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,
+ 0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,
+ 0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,
+ 0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,
+ 0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,
+ 0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,
+ 0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,
+ 0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,
+ 0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,
+ 0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,
+ 0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,
+ 0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,
+ 0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,
+ 0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,
+ 0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,
+ 0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,
+ 0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,
+ 0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,
+ 0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,
+ 0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,
+ 0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,
+ 0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,
+ 0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,
+ 0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,
+ 0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,
+ 0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,
+ 0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,
+ 0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,
+ 0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,
+ 0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,
+ 0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,
+ 0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,
+ 0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,
+ 0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,
+ 0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,
+ 0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,
+ 0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,
+ 0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,
+ 0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,
+ 0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,
+ 0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,
+ 0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,
+ 0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,
+ 0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,
+ 0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,
+ 0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,
+ 0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,
+ 0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,
+ 0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,
+ 0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,
+ 0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,
+ 0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,
+ 0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,
+ 0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,
+ 0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,
+ 0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,
+ 0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,
+ 0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,
+ 0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,
+ 0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,
+ 0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,
+ 0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,
+ 0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,
+ 0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,
+ 0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,
+ 0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,
+ 0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,
+ 0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,
+ 0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,
+ 0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,
+ 0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,
+ 0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,
+ 0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,
+ 0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,
+ 0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,
+ 0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,
+ 0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,
+ 0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,
+ 0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,
+ 0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,
+ 0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,
+ 0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,
+ 0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,
+ 0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,
+ 0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,
+ 0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,
+ 0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,
+ 0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,
+ 0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,
+ 0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,
+ 0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,
+ 0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,
+ 0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,
+ 0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,
+ 0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,
+ 0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,
+ 0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,
+ 0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,
+ 0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,
+ 0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,
+ 0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,
+ 0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,
+ 0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,
+ 0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,
+ 0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,
+ 0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,
+ 0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,
+ 0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,
+ 0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,
+ 0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,
+ 0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,
+ 0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,
+ 0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,
+ 0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,
+ 0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,
+ 0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,
+ 0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,
+ 0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,
+ 0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,
+ 0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,
+ 0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,
+ 0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,
+ 0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,
+ 0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,
+ 0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,
+ 0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,
+ 0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,
+ 0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,
+ 0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,
+ 0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,
+ 0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,
+ 0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,
+ 0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,
+ 0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,
+ 0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,
+ 0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,
+ 0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,
+ 0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,
+ 0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,
+ 0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,
+ 0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,
+ 0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,
+ 0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,
+ 0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,
+ 0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,
+ 0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,
+ 0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,
+ 0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,
+ 0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,
+ 0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,
+ 0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,
+ 0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,
+ 0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,
+ 0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,
+ 0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,
+ 0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,
+ 0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,
+ 0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,
+ 0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,
+ 0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,
+ 0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,
+ 0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,
+ 0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,
+ 0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,
+ 0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,
+ 0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,
+ 0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,
+ 0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,
+ 0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,
+ 0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,
+ 0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,
+ 0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,
+ 0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,
+ 0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,
+ 0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,
+ 0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,
+ 0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,
+ 0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,
+ 0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,
+ 0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,
+ 0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,
+ 0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,
+ 0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,
+ 0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,
+ 0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,
+ 0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,
+ 0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,
+ 0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,
+ 0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,
+ 0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,
+ 0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,
+ 0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,
+ 0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,
+ 0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,
+ 0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,
+ 0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,
+ 0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,
+ 0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,
+ 0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,
+ 0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,
+ 0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,
+ 0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,
+ 0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,
+ 0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,
+ 0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,
+ 0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,
+ 0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,
+ 0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,
+ 0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,
+ 0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,
+ 0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,
+ 0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,
+ 0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,
+ 0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,
+ 0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,
+ 0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,
+ 0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,
+ 0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,
+ 0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,
+ 0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,
+ 0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,
+ 0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,
+ 0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,
+ 0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,
+ 0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,
+ 0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,
+ 0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,
+ 0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,
+ 0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,
+ 0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,
+ 0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,
+ 0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,
+ 0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,
+ 0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,
+ 0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,
+ 0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,
+ 0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,
+ 0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,
+ 0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,
+ 0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,
+ 0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,
+ 0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,
+ 0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,
+ 0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,
+ 0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,
+ 0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,
+ 0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,
+ 0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,
+ 0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,
+ 0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,
+ 0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,
+ 0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,
+ 0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,
+ 0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,
+ 0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,
+ 0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,
+ 0x634facda, 0xca9f750f, 0x63453125, 0xca988727,
+ 0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,
+ 0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,
+ 0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,
+ 0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,
+ 0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,
+ 0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,
+ 0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,
+ 0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,
+ 0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,
+ 0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,
+ 0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,
+ 0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,
+ 0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,
+ 0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,
+ 0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,
+ 0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,
+ 0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,
+ 0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,
+ 0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,
+ 0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,
+ 0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,
+ 0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,
+ 0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,
+ 0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,
+ 0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,
+ 0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,
+ 0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,
+ 0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,
+ 0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,
+ 0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,
+ 0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,
+ 0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,
+ 0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,
+ 0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,
+ 0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,
+ 0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,
+ 0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,
+ 0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,
+ 0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,
+ 0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,
+ 0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,
+ 0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,
+ 0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,
+ 0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,
+ 0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,
+ 0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,
+ 0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,
+ 0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,
+ 0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,
+ 0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,
+ 0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,
+ 0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,
+ 0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,
+ 0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,
+ 0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,
+ 0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,
+ 0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,
+ 0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,
+ 0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,
+ 0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,
+ 0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,
+ 0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,
+ 0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,
+ 0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,
+ 0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,
+ 0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,
+ 0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,
+ 0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,
+ 0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,
+ 0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,
+ 0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,
+ 0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,
+ 0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,
+ 0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,
+ 0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,
+ 0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,
+ 0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,
+ 0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,
+ 0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,
+ 0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,
+ 0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,
+ 0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,
+ 0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,
+ 0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,
+ 0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,
+ 0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,
+ 0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,
+ 0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,
+ 0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,
+ 0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,
+ 0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,
+ 0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,
+ 0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,
+ 0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,
+ 0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,
+ 0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,
+ 0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,
+ 0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,
+ 0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,
+ 0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,
+ 0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,
+ 0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,
+ 0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,
+ 0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,
+ 0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,
+ 0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,
+ 0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,
+ 0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,
+ 0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,
+ 0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,
+ 0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,
+ 0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,
+ 0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,
+ 0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,
+ 0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,
+ 0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,
+ 0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,
+ 0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,
+ 0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,
+ 0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,
+ 0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,
+ 0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,
+ 0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,
+ 0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,
+ 0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,
+ 0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,
+ 0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,
+ 0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,
+ 0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,
+ 0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,
+ 0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,
+ 0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,
+ 0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,
+ 0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,
+ 0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,
+ 0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,
+ 0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,
+ 0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,
+ 0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,
+ 0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,
+ 0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,
+ 0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,
+ 0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,
+ 0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,
+ 0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,
+ 0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,
+ 0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,
+ 0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,
+ 0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,
+ 0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,
+ 0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,
+ 0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,
+ 0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,
+ 0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,
+ 0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,
+ 0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,
+ 0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,
+ 0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,
+ 0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,
+ 0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,
+ 0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,
+ 0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,
+ 0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,
+ 0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,
+ 0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,
+ 0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,
+ 0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,
+ 0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,
+ 0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,
+ 0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,
+ 0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,
+ 0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,
+ 0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,
+ 0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,
+ 0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,
+ 0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,
+ 0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,
+ 0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,
+ 0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,
+ 0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,
+ 0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,
+ 0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,
+ 0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,
+ 0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,
+ 0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,
+ 0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,
+ 0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,
+ 0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,
+ 0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,
+ 0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,
+ 0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,
+ 0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,
+ 0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,
+ 0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,
+ 0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,
+ 0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,
+ 0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,
+ 0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,
+ 0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,
+ 0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,
+ 0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,
+ 0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,
+ 0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,
+ 0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,
+ 0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,
+ 0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,
+ 0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,
+ 0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,
+ 0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,
+ 0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,
+ 0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,
+ 0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,
+ 0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,
+ 0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,
+ 0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,
+ 0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,
+ 0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,
+ 0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,
+ 0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,
+ 0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,
+ 0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,
+ 0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,
+ 0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,
+ 0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,
+ 0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,
+ 0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,
+ 0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,
+ 0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,
+ 0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,
+ 0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,
+ 0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,
+ 0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,
+ 0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,
+ 0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,
+ 0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,
+ 0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,
+ 0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,
+ 0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,
+ 0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,
+ 0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,
+ 0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,
+ 0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,
+ 0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,
+ 0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,
+ 0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,
+ 0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,
+ 0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,
+ 0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,
+ 0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,
+ 0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,
+ 0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,
+ 0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,
+ 0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,
+ 0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,
+ 0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,
+ 0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,
+ 0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,
+ 0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,
+ 0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,
+ 0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,
+ 0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,
+ 0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,
+ 0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,
+ 0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,
+ 0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,
+ 0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,
+ 0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,
+ 0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,
+ 0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,
+ 0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,
+ 0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,
+ 0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,
+ 0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,
+ 0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,
+ 0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,
+ 0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,
+ 0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,
+ 0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,
+ 0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,
+ 0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,
+ 0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,
+ 0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,
+ 0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,
+ 0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,
+ 0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,
+ 0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,
+ 0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,
+ 0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,
+ 0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,
+ 0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,
+ 0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,
+ 0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,
+ 0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,
+ 0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,
+ 0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,
+ 0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,
+ 0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,
+ 0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,
+ 0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,
+ 0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,
+ 0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,
+ 0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,
+ 0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,
+ 0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,
+ 0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,
+ 0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,
+ 0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,
+ 0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,
+ 0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,
+ 0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,
+ 0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,
+ 0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,
+ 0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,
+ 0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,
+ 0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,
+ 0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,
+ 0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,
+ 0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,
+ 0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,
+ 0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,
+ 0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,
+ 0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,
+ 0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,
+ 0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,
+ 0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,
+ 0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,
+ 0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,
+ 0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,
+ 0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,
+ 0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,
+ 0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,
+ 0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,
+ 0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,
+ 0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,
+ 0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,
+ 0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,
+ 0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,
+ 0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,
+ 0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,
+ 0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,
+ 0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,
+ 0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,
+ 0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,
+ 0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,
+ 0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,
+ 0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,
+ 0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,
+ 0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,
+ 0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,
+ 0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,
+ 0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,
+ 0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,
+ 0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,
+ 0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,
+ 0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,
+ 0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,
+ 0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,
+ 0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,
+ 0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,
+ 0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,
+ 0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,
+ 0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,
+ 0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,
+ 0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,
+ 0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,
+ 0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,
+ 0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,
+ 0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,
+ 0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,
+ 0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,
+ 0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,
+ 0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,
+ 0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,
+ 0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,
+ 0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,
+ 0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,
+ 0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,
+ 0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,
+ 0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,
+ 0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,
+};
+
+/**
+* @brief Initialization function for the Q31 RFFT/RIFFT.
+* @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.
+* \par
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par 7
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initialization of coef modifier depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ case 8192u:
+ S->twidCoefRModifier = 1u;
+ S->pCfft = &arm_cfft_sR_q31_len4096;
+ break;
+ case 4096u:
+ S->twidCoefRModifier = 2u;
+ S->pCfft = &arm_cfft_sR_q31_len2048;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ S->pCfft = &arm_cfft_sR_q31_len1024;
+ break;
+ case 1024u:
+ S->twidCoefRModifier = 8u;
+ S->pCfft = &arm_cfft_sR_q31_len512;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ S->pCfft = &arm_cfft_sR_q31_len256;
+ break;
+ case 256u:
+ S->twidCoefRModifier = 32u;
+ S->pCfft = &arm_cfft_sR_q31_len128;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ S->pCfft = &arm_cfft_sR_q31_len64;
+ break;
+ case 64u:
+ S->twidCoefRModifier = 128u;
+ S->pCfft = &arm_cfft_sR_q31_len32;
+ break;
+ case 32u:
+ S->twidCoefRModifier = 256u;
+ S->pCfft = &arm_cfft_sR_q31_len16;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+}
+
+/**
+* @} end of RealFFT group
+*/
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,439 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_q15.c
+*
+* Description: RFFT & RIFFT Q15 process function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------
+* Internal functions prototypes
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier);
+
+void arm_split_rifft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier);
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the Q15 RFFT/RIFFT.
+* @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
+* @param[in] *pSrc points to the input buffer.
+* @param[out] *pDst points to the output buffer.
+* @return none.
+*
+* \par Input an output formats:
+* \par
+* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+* Hence the output format is different for different RFFT sizes.
+* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+* \par
+* \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"
+* \par
+* \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"
+*/
+
+void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst)
+{
+ const arm_cfft_instance_q15 *S_CFFT = S->pCfft;
+ uint32_t i;
+ uint32_t L2 = S->fftLenReal >> 1;
+
+ /* Calculation of RIFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_q15(pSrc, L2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+ /* Complex IFFT process */
+ arm_cfft_q15(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
+
+ for(i=0;ifftLenReal;i++)
+ {
+ pDst[i] = pDst[i] << 1;
+ }
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+
+ /* Complex FFT process */
+ arm_cfft_q15(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
+
+ /* Real FFT core process */
+ arm_split_rfft_q15(pSrc, L2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+}
+
+/**
+* @} end of RealFFT group
+*/
+
+/**
+* @brief Core Real FFT process
+* @param *pSrc points to the input buffer.
+* @param fftLen length of FFT.
+* @param *pATable points to the A twiddle Coef buffer.
+* @param *pBTable points to the B twiddle Coef buffer.
+* @param *pDst points to the output buffer.
+* @param modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+* The function implements a Real FFT
+*/
+
+void arm_split_rfft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q15_t *pSrc1, *pSrc2;
+#ifndef ARM_MATH_CM0_FAMILY
+ q15_t *pD1, *pD2;
+#endif
+
+ // pSrc[2u * fftLen] = pSrc[0];
+ // pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ pSrc1 = &pSrc[2];
+ pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ i = 1u;
+ pD1 = pDst + 2;
+ pD2 = pDst + (4u * fftLen) - 2;
+
+ for(i = fftLen - 1; i > 0; i--)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+ outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+ /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+ outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+ outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 16u;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+ outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+ outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+ /* write output */
+ *pD1++ = (q15_t) outR;
+ *pD1++ = outI >> 16u;
+
+ /* write complex conjugate output */
+ pD2[0] = (q15_t) outR;
+ pD2[1] = -(outI >> 16u);
+ pD2 -= 2;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+ }
+
+ pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+ pDst[1] = 0;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ i = 1u;
+
+ while(i < fftLen)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ outR = *pSrc1 * *pCoefA;
+ outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+ outR = outR + (*pSrc2 * *pCoefB);
+ outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16;
+
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ outI = *pSrc2 * *(pCoefB + 1);
+ outI = outI - (*(pSrc2 + 1) * *pCoefB);
+ outI = outI + (*(pSrc1 + 1) * *pCoefA);
+ outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+ /* update input pointers */
+ pSrc1 += 2u;
+ pSrc2 -= 2u;
+
+ /* write output */
+ pDst[2u * i] = (q15_t) outR;
+ pDst[(2u * i) + 1u] = outI >> 16u;
+
+ /* write complex conjugate output */
+ pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+ pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 16u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i++;
+ }
+
+ pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+ pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+
+/**
+* @brief Core Real IFFT process
+* @param[in] *pSrc points to the input buffer.
+* @param[in] fftLen length of FFT.
+* @param[in] *pATable points to the twiddle Coef A buffer.
+* @param[in] *pBTable points to the twiddle Coef B buffer.
+* @param[out] *pDst points to the output buffer.
+* @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+* The function implements a Real IFFT
+*/
+void arm_split_rifft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q15_t *pSrc1, *pSrc2;
+ q15_t *pDst1 = &pDst[0];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ pSrc1 = &pSrc[0];
+ pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ i = fftLen;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+ outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+ /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+ outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] */
+ outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 16u;
+
+ /*
+ -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+ /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+ outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 16u), 16);
+
+#else
+
+ *__SIMD32(pDst1)++ = __PKHBT((outI >> 16u), outR, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i--;
+ }
+#else
+ /* Run the below code for Cortex-M0 */
+ i = fftLen;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ outR = *pSrc2 * *pCoefB;
+ outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+ outR = outR + (*pSrc1 * *pCoefA);
+ outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16;
+
+ /*
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ outI = *(pSrc1 + 1) * *pCoefA;
+ outI = outI - (*pSrc1 * *(pCoefA + 1));
+ outI = outI - (*pSrc2 * *(pCoefB + 1));
+ outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+ /* update input pointers */
+ pSrc1 += 2u;
+ pSrc2 -= 2u;
+
+ /* write output */
+ *pDst1++ = (q15_t) outR;
+ *pDst1++ = (q15_t) (outI >> 16);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i--;
+ }
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
diff --git a/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,296 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_q31.c
+*
+* Description: RFFT & RIFFT Q31 process function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------
+* Internal functions prototypes
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier);
+
+void arm_split_rifft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier);
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the Q31 RFFT/RIFFT.
+* @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
+* @param[in] *pSrc points to the input buffer.
+* @param[out] *pDst points to the output buffer.
+* @return none.
+*
+* \par Input an output formats:
+* \par
+* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+* Hence the output format is different for different RFFT sizes.
+* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+* \par
+* \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"
+*
+* \par
+* \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"
+*/
+void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst)
+{
+ const arm_cfft_instance_q31 *S_CFFT = S->pCfft;
+ uint32_t i;
+ uint32_t L2 = S->fftLenReal >> 1;
+
+ /* Calculation of RIFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_q31(pSrc, L2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+ /* Complex IFFT process */
+ arm_cfft_q31(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
+
+ for(i=0;ifftLenReal;i++)
+ {
+ pDst[i] = pDst[i] << 1;
+ }
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+
+ /* Complex FFT process */
+ arm_cfft_q31(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
+
+ /* Real FFT core process */
+ arm_split_rfft_q31(pSrc, L2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+}
+
+/**
+* @} end of RealFFT group
+*/
+
+/**
+* @brief Core Real FFT process
+* @param[in] *pSrc points to the input buffer.
+* @param[in] fftLen length of FFT.
+* @param[in] *pATable points to the twiddle Coef A buffer.
+* @param[in] *pBTable points to the twiddle Coef B buffer.
+* @param[out] *pDst points to the output buffer.
+* @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+void arm_split_rfft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+ q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+ /* Init coefficient pointers */
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ i = fftLen - 1u;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pSrc[2 * i] * pATable[2 * i] */
+ mult_32x32_keep32_R(outR, *pIn1, CoefA1);
+
+ /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+ mult_32x32_keep32_R(outI, *pIn1++, CoefA2);
+
+ /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+ multSub_32x32_keep32_R(outR, *pIn1, CoefA2);
+
+ /* (pIn[2 * i + 1] * pATable[2 * i] */
+ multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
+
+ /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */
+ multSub_32x32_keep32_R(outR, *pIn2, CoefA2);
+ CoefB1 = *pCoefB;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+ multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
+
+ /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+ multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ multSub_32x32_keep32_R(outI, *pIn2--, CoefA2);
+
+ /* write output */
+ *pOut1++ = outR;
+ *pOut1++ = outI;
+
+ /* write complex conjugate output */
+ *pOut2-- = -outI;
+ *pOut2-- = outR;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ i--;
+ }
+ pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
+ pDst[1] = 0;
+}
+
+/**
+* @brief Core Real IFFT process
+* @param[in] *pSrc points to the input buffer.
+* @param[in] fftLen length of FFT.
+* @param[in] *pATable points to the twiddle Coef A buffer.
+* @param[in] *pBTable points to the twiddle Coef B buffer.
+* @param[out] *pDst points to the output buffer.
+* @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+void arm_split_rifft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier)
+{
+ q31_t outR, outI; /* Temporary variables for output */
+ q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ while(fftLen > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pIn[2 * i] * pATable[2 * i] */
+ mult_32x32_keep32_R(outR, *pIn1, CoefA1);
+
+ /* - pIn[2 * i] * pATable[2 * i + 1] */
+ mult_32x32_keep32_R(outI, *pIn1++, -CoefA2);
+
+ /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+ multAcc_32x32_keep32_R(outR, *pIn1, CoefA2);
+
+ /* pIn[2 * i + 1] * pATable[2 * i] */
+ multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+ multAcc_32x32_keep32_R(outR, *pIn2, CoefA2);
+ CoefB1 = *pCoefB;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+ multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+ multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ multAcc_32x32_keep32_R(outI, *pIn2--, CoefA2);
+
+ /* write output */
+ *pDst++ = outR;
+ *pDst++ = outI;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ /* Decrement loop count */
+ fftLen--;
+ }
+}
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h b/drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h
@@ -0,0 +1,4936 @@
+/**
+ ******************************************************************************
+ * @file stm32f301x8.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f301x8
+ * @{
+ */
+
+#ifndef __STM32F301x8_H
+#define __STM32F301x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F301x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F301x8 devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F301x8 devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F301x8 devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f302x8
+ * @{
+ */
+
+#ifndef __STM32F302x8_H
+#define __STM32F302x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F302x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F302x8 devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F302x8 devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F302x8 devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f302xc
+ * @{
+ */
+
+#ifndef __STM32F302xC_H
+#define __STM32F302xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F302xC devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F302xC devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F302xC devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F302xC devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ COMP1_2_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt via EXTI Line21 and 22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f302xe
+ * @{
+ */
+
+#ifndef __STM32F302xE_H
+#define __STM32F302xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F302xE devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F302xE devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F302xE devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F302xE devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ COMP1_2_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt via EXTI Line21 and 22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f303x8
+ * @{
+ */
+
+#ifndef __STM32F303x8_H
+#define __STM32F303x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F303x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F303x8 devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F303x8 devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F303x8 devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
+ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f303xc
+ * @{
+ */
+
+#ifndef __STM32F303xC_H
+#define __STM32F303xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F303xC devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F303xC devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F303xC devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F303xC devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f303xe
+ * @{
+ */
+
+#ifndef __STM32F303xE_H
+#define __STM32F303xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F303xE devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F303xE devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
+ TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
+ TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
+ TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f318xx
+ * @{
+ */
+
+#ifndef __STM32F318xx_H
+#define __STM32F318xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F318xx devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F318xx devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F318xx devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F318xx devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f328xx
+ * @{
+ */
+
+#ifndef __STM32F328xx_H
+#define __STM32F328xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F328xx devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F328xx devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F328xx devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F328xx devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
+ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f334x8
+ * @{
+ */
+
+#ifndef __STM32F334x8_H
+#define __STM32F334x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F334x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F334x8 devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
+ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
+ HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
+ HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
+ HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
+ HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
+ HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
+ HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f358xx
+ * @{
+ */
+
+#ifndef __STM32F358xx_H
+#define __STM32F358xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F358xx devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F358xx devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f373xc
+ * @{
+ */
+
+#ifndef __STM32F373xC_H
+#define __STM32F373xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F373xC devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F373xC devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F373xC devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F373xC devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM15_IRQn = 24, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 25, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 26, /*!< TIM17 global Interrupt */
+ TIM18_DAC2_IRQn = 27, /*!< TIM18 global Interrupt and DAC2 underrun Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ CEC_IRQn = 42, /*!< CEC Interrupt & EXTI Line27 Interrupt (CEC wakeup) */
+ TIM12_IRQn = 43, /*!< TIM12 global interrupt */
+ TIM13_IRQn = 44, /*!< TIM13 global interrupt */
+ TIM14_IRQn = 45, /*!< TIM14 global interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ SDADC1_IRQn = 61, /*!< ADC Sigma Delta 1 global Interrupt */
+ SDADC2_IRQn = 62, /*!< ADC Sigma Delta 2 global Interrupt */
+ SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */
+ COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_IRQn = 76, /*!< USB Wakeup Interrupt */
+ TIM19_IRQn = 78, /*!< TIM19 global Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
+} COMP1_2_TypeDef;
+
+typedef struct
+{
+ __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f378xx
+ * @{
+ */
+
+#ifndef __STM32F378xx_H
+#define __STM32F378xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F378xx devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F378xx devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F378xx devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F378xx devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM15_IRQn = 24, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 25, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 26, /*!< TIM17 global Interrupt */
+ TIM18_DAC2_IRQn = 27, /*!< TIM18 global Interrupt and DAC2 underrun Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ CEC_IRQn = 42, /*!< CEC Interrupt & EXTI Line27 Interrupt (CEC wakeup) */
+ TIM12_IRQn = 43, /*!< TIM12 global interrupt */
+ TIM13_IRQn = 44, /*!< TIM13 global interrupt */
+ TIM14_IRQn = 45, /*!< TIM14 global interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ SDADC1_IRQn = 61, /*!< ADC Sigma Delta 1 global Interrupt */
+ SDADC2_IRQn = 62, /*!< ADC Sigma Delta 2 global Interrupt */
+ SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */
+ COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */
+ TIM19_IRQn = 78, /*!< TIM19 global Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
+} COMP1_2_TypeDef;
+
+typedef struct
+{
+ __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f398xx
+ * @{
+ */
+
+#ifndef __STM32F398xx_H
+#define __STM32F398xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F398xx devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F398xx devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F398xx devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F398xx devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
+ TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
+ TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
+ TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f3xx
+ * @{
+ */
+
+#ifndef __STM32F3xx_H
+#define __STM32F3xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F3)
+#define STM32F3
+#endif /* STM32F3 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
+ !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
+ !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
+ !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
+ !defined (STM32F373xC) && !defined (STM32F378xx)
+
+ /* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
+ STM32F301R6 and STM32F301R8 Devices */
+ /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
+ STM32F302R6 and STM32F302R8 Devices */
+ /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC,
+ STM32F302VB and STM32F302VC Devices */
+ /* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
+ STM32F302VD and STM32F302ZD Devices */
+ /* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
+ STM32F303R6 and STM32F303R8 Devices */
+ /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
+ STM32F303VB and STM32F303VC Devices */
+ /* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD,
+ STM32F303VD and STM32F303ZD Devices */
+ /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC,
+ STM32F373R8, STM32F373RB, STM32F373RC,
+ STM32F373V8, STM32F373VB and STM32F373VC Devices */
+ /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8,
+ STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
+ /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
+ /* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
+ /* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
+ /* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
+ /* #define STM32F398xx */ /*!< STM32F398CE, STM32F398RE, STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.2.0
+ */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F301x8)
+ #include "stm32f301x8.h"
+#elif defined(STM32F302x8)
+ #include "stm32f302x8.h"
+#elif defined(STM32F302xC)
+ #include "stm32f302xc.h"
+#elif defined(STM32F302xE)
+ #include "stm32f302xe.h"
+#elif defined(STM32F303x8)
+ #include "stm32f303x8.h"
+#elif defined(STM32F303xC)
+ #include "stm32f303xc.h"
+#elif defined(STM32F303xE)
+ #include "stm32f303xe.h"
+#elif defined(STM32F373xC)
+ #include "stm32f373xc.h"
+#elif defined(STM32F334x8)
+ #include "stm32f334x8.h"
+#elif defined(STM32F318xx)
+ #include "stm32f318xx.h"
+#elif defined(STM32F328xx)
+ #include "stm32f328xx.h"
+#elif defined(STM32F358xx)
+ #include "stm32f358xx.h"
+#elif defined(STM32F378xx)
+ #include "stm32f378xx.h"
+#elif defined(STM32F398xx)
+ #include "stm32f398xx.h"
+#else
+ #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f3xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F3xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h b/drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f3xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f3xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F3XX_H
+#define __SYSTEM_STM32F3XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F3xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F3xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F3XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f301x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f301x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f301x8.s
@@ -0,0 +1,361 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f301x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F301x6/x8 devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD 0 ; Reserved
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT COMP2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+COMP2_IRQHandler
+COMP4_6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302x8.s
@@ -0,0 +1,377 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f302x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F302x6/x8 devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD 0 ; Reserved
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT COMP2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+COMP2_IRQHandler
+COMP4_6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_RMP_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xc.s
@@ -0,0 +1,393 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f302xc.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F302xB/xC devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD 0 ; Reserved
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_IRQHandler ; COMP1 and COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT COMP1_2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP1_2_IRQHandler
+COMP4_6_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_RMP_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xe.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xe.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f302xe.s
@@ -0,0 +1,412 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f302xe.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F302xE devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FMC_IRQHandler ; FMC
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD 0 ; Reserved
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_IRQHandler ; COMP1 and COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD TIM20_BRK_IRQHandler ; TIM20 Break
+ DCD TIM20_UP_IRQHandler ; TIM20 Update
+ DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
+ DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
+ DCD FPU_IRQHandler ; FPU
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI4_IRQHandler ; SPI4
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT COMP1_2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
+ EXPORT TIM20_BRK_IRQHandler [WEAK]
+ EXPORT TIM20_UP_IRQHandler [WEAK]
+ EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM20_CC_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+FMC_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP1_2_IRQHandler
+COMP4_6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_RMP_IRQHandler
+TIM20_BRK_IRQHandler
+TIM20_UP_IRQHandler
+TIM20_TRG_COM_IRQHandler
+TIM20_CC_IRQHandler
+FPU_IRQHandler
+SPI4_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303x8.s
@@ -0,0 +1,363 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f303x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F303x6/x8 devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1 and EXTI Line 25
+ DCD USART2_IRQHandler ; USART2 and EXTI Line 26
+ DCD USART3_IRQHandler ; USART3 and EXTI Line 28
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM6_DAC1_IRQHandler [WEAK]
+ EXPORT TIM7_DAC2_IRQHandler [WEAK]
+ EXPORT COMP2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM6_DAC1_IRQHandler
+TIM7_DAC2_IRQHandler
+COMP2_IRQHandler
+COMP4_6_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xc.s
@@ -0,0 +1,409 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f303xc.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F303xB/xC devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD ADC4_IRQHandler ; ADC4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; COMP7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT ADC4_IRQHandler [WEAK]
+ EXPORT COMP1_2_3_IRQHandler [WEAK]
+ EXPORT COMP4_5_6_IRQHandler [WEAK]
+ EXPORT COMP7_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ADC4_IRQHandler
+COMP1_2_3_IRQHandler
+COMP4_5_6_IRQHandler
+COMP7_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_RMP_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xe.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xe.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f303xe.s
@@ -0,0 +1,428 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f303xe.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F303xE devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FMC_IRQHandler ; FMC
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD ADC4_IRQHandler ; ADC4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; COMP7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD TIM20_BRK_IRQHandler ; TIM20 Break
+ DCD TIM20_UP_IRQHandler ; TIM20 Update
+ DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
+ DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
+ DCD FPU_IRQHandler ; FPU
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI4_IRQHandler ; SPI4
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT ADC4_IRQHandler [WEAK]
+ EXPORT COMP1_2_3_IRQHandler [WEAK]
+ EXPORT COMP4_5_6_IRQHandler [WEAK]
+ EXPORT COMP7_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
+ EXPORT TIM20_BRK_IRQHandler [WEAK]
+ EXPORT TIM20_UP_IRQHandler [WEAK]
+ EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM20_CC_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN_TX_IRQHandler
+USB_LP_CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ADC4_IRQHandler
+COMP1_2_3_IRQHandler
+COMP4_5_6_IRQHandler
+COMP7_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_RMP_IRQHandler
+TIM20_BRK_IRQHandler
+TIM20_UP_IRQHandler
+TIM20_TRG_COM_IRQHandler
+TIM20_CC_IRQHandler
+FPU_IRQHandler
+SPI4_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f318xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f318xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f318xx.s
@@ -0,0 +1,359 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f318xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F318xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD 0 ; Reserved
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT COMP2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+COMP2_IRQHandler
+COMP4_6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f328xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f328xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f328xx.s
@@ -0,0 +1,361 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f328xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F328xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1 and EXTI Line 25
+ DCD USART2_IRQHandler ; USART2 and EXTI Line 26
+ DCD USART3_IRQHandler ; USART3 and EXTI Line 28
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM6_DAC1_IRQHandler [WEAK]
+ EXPORT TIM7_DAC2_IRQHandler [WEAK]
+ EXPORT COMP2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM6_DAC1_IRQHandler
+TIM7_DAC2_IRQHandler
+COMP2_IRQHandler
+COMP4_6_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f334x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f334x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f334x8.s
@@ -0,0 +1,377 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f334x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F334x4/x6/x8 devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1 and EXTI Line 25
+ DCD USART2_IRQHandler ; USART2 and EXTI Line 26
+ DCD USART3_IRQHandler ; USART3 and EXTI Line 28
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM1 timer A
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM1 timer B
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM1 timer C
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM1 timer D
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM1 timer E
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM1 fault
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM6_DAC1_IRQHandler [WEAK]
+ EXPORT TIM7_DAC2_IRQHandler [WEAK]
+ EXPORT COMP2_IRQHandler [WEAK]
+ EXPORT COMP4_6_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM6_DAC1_IRQHandler
+TIM7_DAC2_IRQHandler
+COMP2_IRQHandler
+COMP4_6_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f358xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f358xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f358xx.s
@@ -0,0 +1,400 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f358xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F358xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD ADC4_IRQHandler ; ADC4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; COMP7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT ADC4_IRQHandler [WEAK]
+ EXPORT COMP1_2_3_IRQHandler [WEAK]
+ EXPORT COMP4_5_6_IRQHandler [WEAK]
+ EXPORT COMP7_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ADC4_IRQHandler
+COMP1_2_3_IRQHandler
+COMP4_5_6_IRQHandler
+COMP7_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f373xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f373xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f373xc.s
@@ -0,0 +1,405 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f373xc.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F373xB/xC devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD CEC_IRQHandler ; CEC
+ DCD TIM12_IRQHandler ; TIM12
+ DCD TIM13_IRQHandler ; TIM13
+ DCD TIM14_IRQHandler ; TIM14
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD SDADC1_IRQHandler ; SDADC1
+ DCD SDADC2_IRQHandler ; SDADC2
+ DCD SDADC3_IRQHandler ; SDADC3
+ DCD COMP1_2_IRQHandler ; COMP1 and COMP2 global Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD USBWakeUp_IRQHandler ; USB Wakeup
+ DCD 0 ; Reserved
+ DCD TIM19_IRQHandler ; TIM19
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT TIM18_DAC2_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT TIM12_IRQHandler [WEAK]
+ EXPORT TIM13_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC1_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT SDADC1_IRQHandler [WEAK]
+ EXPORT SDADC2_IRQHandler [WEAK]
+ EXPORT SDADC3_IRQHandler [WEAK]
+ EXPORT COMP1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_IRQHandler [WEAK]
+ EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM19_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+TIM18_DAC2_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC1_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+SDADC1_IRQHandler
+SDADC2_IRQHandler
+SDADC3_IRQHandler
+COMP1_2_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+USBWakeUp_IRQHandler
+TIM19_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f378xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f378xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f378xx.s
@@ -0,0 +1,397 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f378xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F378xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD CEC_IRQHandler ; CEC
+ DCD TIM12_IRQHandler ; TIM12
+ DCD TIM13_IRQHandler ; TIM13
+ DCD TIM14_IRQHandler ; TIM14
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD SDADC1_IRQHandler ; SDADC1
+ DCD SDADC2_IRQHandler ; SDADC2
+ DCD SDADC3_IRQHandler ; SDADC3
+ DCD COMP1_2_IRQHandler ; COMP1 and COMP2 global Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM19_IRQHandler ; TIM19
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT TIM18_DAC2_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT TIM12_IRQHandler [WEAK]
+ EXPORT TIM13_IRQHandler [WEAK]
+ EXPORT TIM14_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT TIM6_DAC1_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT SDADC1_IRQHandler [WEAK]
+ EXPORT SDADC2_IRQHandler [WEAK]
+ EXPORT SDADC3_IRQHandler [WEAK]
+ EXPORT COMP1_2_IRQHandler [WEAK]
+ EXPORT TIM19_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+TIM18_DAC2_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+CEC_IRQHandler
+TIM12_IRQHandler
+TIM13_IRQHandler
+TIM14_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC1_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+SDADC1_IRQHandler
+SDADC2_IRQHandler
+SDADC3_IRQHandler
+COMP1_2_IRQHandler
+TIM19_IRQHandler
+FPU_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f398xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f398xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/arm/startup_stm32f398xx.s
@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f398xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F398xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FMC_IRQHandler ; FMC
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD ADC4_IRQHandler ; ADC4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; COMP7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM20_BRK_IRQHandler ; TIM20 Break
+ DCD TIM20_UP_IRQHandler ; TIM20 Update
+ DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
+ DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
+ DCD FPU_IRQHandler ; FPU
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI4_IRQHandler ; SPI4
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_TSC_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT CAN_TX_IRQHandler [WEAK]
+ EXPORT CAN_RX0_IRQHandler [WEAK]
+ EXPORT CAN_RX1_IRQHandler [WEAK]
+ EXPORT CAN_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
+ EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT ADC4_IRQHandler [WEAK]
+ EXPORT COMP1_2_3_IRQHandler [WEAK]
+ EXPORT COMP4_5_6_IRQHandler [WEAK]
+ EXPORT COMP7_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT TIM20_BRK_IRQHandler [WEAK]
+ EXPORT TIM20_UP_IRQHandler [WEAK]
+ EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM20_CC_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_TSC_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN_TX_IRQHandler
+CAN_RX0_IRQHandler
+CAN_RX1_IRQHandler
+CAN_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ADC4_IRQHandler
+COMP1_2_3_IRQHandler
+COMP4_5_6_IRQHandler
+COMP7_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+TIM20_BRK_IRQHandler
+TIM20_UP_IRQHandler
+TIM20_TRG_COM_IRQHandler
+TIM20_CC_IRQHandler
+FPU_IRQHandler
+SPI4_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f301x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f301x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f301x8.s
@@ -0,0 +1,399 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f301x8.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F301x6/STM32F301x8 devices vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word 0
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word 0
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302x8.S b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302x8.S
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302x8.S
@@ -0,0 +1,423 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f302x8.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F302x6/STM32F302x8 devices vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_CAN_TX_IRQHandler
+ .word USB_LP_CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word 0
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word 0
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_RMP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN_TX_IRQHandler
+ .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_RMP_IRQHandler
+ .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xc.s
@@ -0,0 +1,447 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f302xc.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F302xB/STM32F302xC devices vector table for Atollic
+ * TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN_TX_IRQHandler
+ .word USB_LP_CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word 0
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word COMP1_2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_RMP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN_TX_IRQHandler
+ .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak COMP1_2_IRQHandler
+ .thumb_set COMP1_2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_RMP_IRQHandler
+ .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xe.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xe.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f302xe.s
@@ -0,0 +1,474 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f302xe.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F302xE devices vector table for Atollic
+ * TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN_TX_IRQHandler
+ .word USB_LP_CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FMC_IRQHandler
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word 0
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word COMP1_2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_RMP_IRQHandler
+ .word TIM20_BRK_IRQHandler
+ .word TIM20_UP_IRQHandler
+ .word TIM20_TRG_COM_IRQHandler
+ .word TIM20_CC_IRQHandler
+ .word FPU_IRQHandler
+ .word 0
+ .word 0
+ .word SPI4_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN_TX_IRQHandler
+ .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak COMP1_2_IRQHandler
+ .thumb_set COMP1_2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_RMP_IRQHandler
+ .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+
+ .weak TIM20_BRK_IRQHandler
+ .thumb_set TIM20_BRK_IRQHandler,Default_Handler
+
+ .weak TIM20_UP_IRQHandler
+ .thumb_set TIM20_UP_IRQHandler,Default_Handler
+
+ .weak TIM20_TRG_COM_IRQHandler
+ .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM20_CC_IRQHandler
+ .thumb_set TIM20_CC_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303x8.s
@@ -0,0 +1,402 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f303x8.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F303x6/STM32F303x8 devices vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_DAC2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_DAC2_IRQHandler
+ .thumb_set TIM7_DAC2_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xc.s
@@ -0,0 +1,471 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f303xc.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F303xB/STM32F303xC devices vector table for Atollic
+ * TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN_TX_IRQHandler
+ .word USB_LP_CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ADC4_IRQHandler
+ .word 0
+ .word 0
+ .word COMP1_2_3_IRQHandler
+ .word COMP4_5_6_IRQHandler
+ .word COMP7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_RMP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN_TX_IRQHandler
+ .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ADC4_IRQHandler
+ .thumb_set ADC4_IRQHandler,Default_Handler
+
+ .weak COMP1_2_3_IRQHandler
+ .thumb_set COMP1_2_3_IRQHandler,Default_Handler
+
+ .weak COMP4_5_6_IRQHandler
+ .thumb_set COMP4_5_6_IRQHandler,Default_Handler
+
+ .weak COMP7_IRQHandler
+ .thumb_set COMP7_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_RMP_IRQHandler
+ .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xe.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xe.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f303xe.s
@@ -0,0 +1,498 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f303xe.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F303xE devices vector table for Atollic
+ * TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN_TX_IRQHandler
+ .word USB_LP_CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FMC_IRQHandler
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ADC4_IRQHandler
+ .word 0
+ .word 0
+ .word COMP1_2_3_IRQHandler
+ .word COMP4_5_6_IRQHandler
+ .word COMP7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_RMP_IRQHandler
+ .word TIM20_BRK_IRQHandler
+ .word TIM20_UP_IRQHandler
+ .word TIM20_TRG_COM_IRQHandler
+ .word TIM20_CC_IRQHandler
+ .word FPU_IRQHandler
+ .word 0
+ .word 0
+ .word SPI4_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN_TX_IRQHandler
+ .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN_RX0_IRQHandler
+ .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ADC4_IRQHandler
+ .thumb_set ADC4_IRQHandler,Default_Handler
+
+ .weak COMP1_2_3_IRQHandler
+ .thumb_set COMP1_2_3_IRQHandler,Default_Handler
+
+ .weak COMP4_5_6_IRQHandler
+ .thumb_set COMP4_5_6_IRQHandler,Default_Handler
+
+ .weak COMP7_IRQHandler
+ .thumb_set COMP7_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_RMP_IRQHandler
+ .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
+
+ .weak TIM20_BRK_IRQHandler
+ .thumb_set TIM20_BRK_IRQHandler,Default_Handler
+
+ .weak TIM20_UP_IRQHandler
+ .thumb_set TIM20_UP_IRQHandler,Default_Handler
+
+ .weak TIM20_TRG_COM_IRQHandler
+ .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM20_CC_IRQHandler
+ .thumb_set TIM20_CC_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f318xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f318xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f318xx.s
@@ -0,0 +1,396 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f318xx.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F318xx device vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word 0
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word 0
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word 0
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word TIM6_DAC_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f328xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f328xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f328xx.s
@@ -0,0 +1,399 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f328xx.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F328xx device vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word 0
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_DAC2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_DAC2_IRQHandler
+ .thumb_set TIM7_DAC2_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f334x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f334x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f334x8.s
@@ -0,0 +1,423 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f334x8.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word 0
+ .word 0
+ .word SPI1_IRQHandler
+ .word 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_DAC2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word COMP2_IRQHandler
+ .word COMP4_6_IRQHandler
+ .word 0
+ .word HRTIM1_Master_IRQHandler
+ .word HRTIM1_TIMA_IRQHandler
+ .word HRTIM1_TIMB_IRQHandler
+ .word HRTIM1_TIMC_IRQHandler
+ .word HRTIM1_TIMD_IRQHandler
+ .word HRTIM1_TIME_IRQHandler
+ .word HRTIM1_FLT_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_DAC2_IRQHandler
+ .thumb_set TIM7_DAC2_IRQHandler,Default_Handler
+
+ .weak COMP2_IRQHandler
+ .thumb_set COMP2_IRQHandler,Default_Handler
+
+ .weak COMP4_6_IRQHandler
+ .thumb_set COMP4_6_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f358xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f358xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f358xx.s
@@ -0,0 +1,456 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f358xx.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F358xx device vector table for Atollic
+ * TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word 0
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ADC4_IRQHandler
+ .word 0
+ .word 0
+ .word COMP1_2_3_IRQHandler
+ .word COMP4_5_6_IRQHandler
+ .word COMP7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ADC4_IRQHandler
+ .thumb_set ADC4_IRQHandler,Default_Handler
+
+ .weak COMP1_2_3_IRQHandler
+ .thumb_set COMP1_2_3_IRQHandler,Default_Handler
+
+ .weak COMP4_5_6_IRQHandler
+ .thumb_set COMP4_5_6_IRQHandler,Default_Handler
+
+ .weak COMP7_IRQHandler
+ .thumb_set COMP7_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f373xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f373xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f373xc.s
@@ -0,0 +1,465 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f373xc.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F373xB/STM32F373xC devices vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM15_IRQHandler
+ .word TIM16_IRQHandler
+ .word TIM17_IRQHandler
+ .word TIM18_DAC2_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word CEC_IRQHandler
+ .word TIM12_IRQHandler
+ .word TIM13_IRQHandler
+ .word TIM14_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word SDADC1_IRQHandler
+ .word SDADC2_IRQHandler
+ .word SDADC3_IRQHandler
+ .word COMP1_2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word TIM19_IRQHandler
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak TIM18_DAC2_IRQHandler
+ .thumb_set TIM18_DAC2_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM12_IRQHandler
+ .thumb_set TIM12_IRQHandler,Default_Handler
+
+ .weak TIM13_IRQHandler
+ .thumb_set TIM13_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak SDADC1_IRQHandler
+ .thumb_set SDADC1_IRQHandler,Default_Handler
+
+ .weak SDADC2_IRQHandler
+ .thumb_set SDADC2_IRQHandler,Default_Handler
+
+ .weak SDADC3_IRQHandler
+ .thumb_set SDADC3_IRQHandler,Default_Handler
+
+ .weak COMP1_2_IRQHandler
+ .thumb_set COMP1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM19_IRQHandler
+ .thumb_set TIM19_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f378xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f378xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f378xx.s
@@ -0,0 +1,453 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f378xx.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F378xx device vector table for
+ * Atollic TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word 0
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM15_IRQHandler
+ .word TIM16_IRQHandler
+ .word TIM17_IRQHandler
+ .word TIM18_DAC2_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word CEC_IRQHandler
+ .word TIM12_IRQHandler
+ .word TIM13_IRQHandler
+ .word TIM14_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word 0
+ .word 0
+ .word TIM6_DAC1_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word SDADC1_IRQHandler
+ .word SDADC2_IRQHandler
+ .word SDADC3_IRQHandler
+ .word COMP1_2_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM19_IRQHandler
+ .word 0
+ .word 0
+ .word FPU_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak TIM18_DAC2_IRQHandler
+ .thumb_set TIM18_DAC2_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak TIM12_IRQHandler
+ .thumb_set TIM12_IRQHandler,Default_Handler
+
+ .weak TIM13_IRQHandler
+ .thumb_set TIM13_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC1_IRQHandler
+ .thumb_set TIM6_DAC1_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak SDADC1_IRQHandler
+ .thumb_set SDADC1_IRQHandler,Default_Handler
+
+ .weak SDADC2_IRQHandler
+ .thumb_set SDADC2_IRQHandler,Default_Handler
+
+ .weak SDADC3_IRQHandler
+ .thumb_set SDADC3_IRQHandler,Default_Handler
+
+ .weak COMP1_2_IRQHandler
+ .thumb_set COMP1_2_IRQHandler,Default_Handler
+
+ .weak TIM19_IRQHandler
+ .thumb_set TIM19_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f398xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f398xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/gcc/startup_stm32f398xx.s
@@ -0,0 +1,483 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f398xx.s
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief STM32F398xx devices vector table for Atollic
+ * TrueSTUDIO toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2015 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word 0
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_TSC_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN_TX_IRQHandler
+ .word CAN_RX0_IRQHandler
+ .word CAN_RX1_IRQHandler
+ .word CAN_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word 0
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FMC_IRQHandler
+ .word 0
+ .word 0
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ADC4_IRQHandler
+ .word 0
+ .word 0
+ .word COMP1_2_3_IRQHandler
+ .word COMP4_5_6_IRQHandler
+ .word COMP7_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word TIM20_BRK_IRQHandler
+ .word TIM20_UP_IRQHandler
+ .word TIM20_TRG_COM_IRQHandler
+ .word TIM20_CC_IRQHandler
+ .word FPU_IRQHandler
+ .word 0
+ .word 0
+ .word SPI4_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_TSC_IRQHandler
+ .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN_TX_IRQHandler
+ .thumb_set CAN_TX_IRQHandler,Default_Handler
+
+ .weak CAN_RX0_IRQHandler
+ .thumb_set CAN_RX0_IRQHandler,Default_Handler
+
+ .weak CAN_RX1_IRQHandler
+ .thumb_set CAN_RX1_IRQHandler,Default_Handler
+
+ .weak CAN_SCE_IRQHandler
+ .thumb_set CAN_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ADC4_IRQHandler
+ .thumb_set ADC4_IRQHandler,Default_Handler
+
+ .weak COMP1_2_3_IRQHandler
+ .thumb_set COMP1_2_3_IRQHandler,Default_Handler
+
+ .weak COMP4_5_6_IRQHandler
+ .thumb_set COMP4_5_6_IRQHandler,Default_Handler
+
+ .weak COMP7_IRQHandler
+ .thumb_set COMP7_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak TIM20_BRK_IRQHandler
+ .thumb_set TIM20_BRK_IRQHandler,Default_Handler
+
+ .weak TIM20_UP_IRQHandler
+ .thumb_set TIM20_UP_IRQHandler,Default_Handler
+
+ .weak TIM20_TRG_COM_IRQHandler
+ .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM20_CC_IRQHandler
+ .thumb_set TIM20_CC_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f301x8_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302x8_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xc_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f302xe_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303x8_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xc_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10001FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f303xe_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f318xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f328xx_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f334x8_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f358xx_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10001FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f373xc_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f378xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/linker/stm32f398xx_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f301x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f301x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f301x8.s
@@ -0,0 +1,445 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f301x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F301x6/STM32F301x8 devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD 0 ; Reserved
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK COMP2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP2_IRQHandler
+ B COMP2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302x8.s
@@ -0,0 +1,485 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f302x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F302x6/STM32F302x8 devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD 0 ; Reserved
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK USB_HP_CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_CAN_TX_IRQHandler
+ B USB_HP_CAN_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_CAN_RX0_IRQHandler
+ B USB_LP_CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK COMP2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP2_IRQHandler
+ B COMP2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_RMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_RMP_IRQHandler
+ B USBWakeUp_RMP_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302xc.s
@@ -0,0 +1,525 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f302xc.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F302xB/STM32F302xC devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD 0 ; Reserved
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_IRQHandler ; COMP1 and COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_CAN_TX_IRQHandler
+ B USB_HP_CAN_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_CAN_RX0_IRQHandler
+ B USB_LP_CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK COMP1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_IRQHandler
+ B COMP1_2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_RMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_RMP_IRQHandler
+ B USBWakeUp_RMP_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302xe.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302xe.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f302xe.s
@@ -0,0 +1,569 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f302xe.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F302RE/STM32F302VE/STM32F302ZE devices vector table
+;* for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; 0: Window WatchDog
+ DCD PVD_IRQHandler ; 1: PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; 2: Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; 3: RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; 4: FLASH
+ DCD RCC_IRQHandler ; 5: RCC
+ DCD EXTI0_IRQHandler ; 6: EXTI Line0
+ DCD EXTI1_IRQHandler ; 7: EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; 8: EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; 9: EXTI Line3
+ DCD EXTI4_IRQHandler ; 10: EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; 11: DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; 12: DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; 13: DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; 14: DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; 15: DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; 16: DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; 17: DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; 18: ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; 19: USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; 20: USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; 21: CAN RX1
+ DCD CAN_SCE_IRQHandler ; 22: CAN SCE
+ DCD EXTI9_5_IRQHandler ; 23: External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; 24: TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; 25: TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; 26: TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; 27: TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; 28: TIM2
+ DCD TIM3_IRQHandler ; 29: TIM3
+ DCD TIM4_IRQHandler ; 30: TIM4
+ DCD I2C1_EV_IRQHandler ; 31: I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 32: I2C1 Error
+ DCD I2C2_EV_IRQHandler ; 33: I2C2 Event
+ DCD I2C2_ER_IRQHandler ; 34: I2C2 Error
+ DCD SPI1_IRQHandler ; 35: SPI1
+ DCD SPI2_IRQHandler ; 36: SPI2
+ DCD USART1_IRQHandler ; 37: USART1
+ DCD USART2_IRQHandler ; 38: USART2
+ DCD USART3_IRQHandler ; 39: USART3
+ DCD EXTI15_10_IRQHandler ; 40: External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; 41: RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; 42: USB Wakeup through EXTI line
+ DCD 0 ; 43: Reserved
+ DCD 0 ; 44: Reserved
+ DCD 0 ; 45: Reserved
+ DCD 0 ; 46: Reserved
+ DCD 0 ; 47: Reserved
+ DCD FMC_IRQHandler ; 48: FMC
+ DCD 0 ; 49: Reserved
+ DCD 0 ; 50: Reserved
+ DCD SPI3_IRQHandler ; 51: SPI3
+ DCD UART4_IRQHandler ; 52: UART4
+ DCD UART5_IRQHandler ; 53: UART5
+ DCD TIM6_DAC_IRQHandler ; 54: TIM6 and DAC1&2 underrun errors
+ DCD 0 ; 55: Reserved
+ DCD DMA2_Channel1_IRQHandler ; 56: DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; 57: DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; 58: DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; 59: DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; 60: DMA2 Channel 5
+ DCD 0 ; 61: Reserved
+ DCD 0 ; 62: Reserved
+ DCD 0 ; 63: Reserved
+ DCD COMP1_2_IRQHandler ; 64: COMP1 and COMP2
+ DCD COMP4_6_IRQHandler ; 65: COMP4 and COMP6
+ DCD 0 ; 66: Reserved
+ DCD 0 ; 67: Reserved
+ DCD 0 ; 68: Reserved
+ DCD 0 ; 69: Reserved
+ DCD 0 ; 70: Reserved
+ DCD 0 ; 71: Reserved
+ DCD I2C3_EV_IRQHandler ; 72: I2C3 Event
+ DCD I2C3_ER_IRQHandler ; 73: I2C3 Error
+ DCD USB_HP_IRQHandler ; 74: USB High Priority remap
+ DCD USB_LP_IRQHandler ; 75: USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; 76: USB Wakeup remap through EXTI
+ DCD TIM20_BRK_IRQHandler ; 77: TIM20 Break
+ DCD TIM20_UP_IRQHandler ; 78: TIM20 Update
+ DCD TIM20_TRG_COM_IRQHandler ; 79: TIM20 Trigger and Commutation
+ DCD TIM20_CC_IRQHandler ; 80: TIM20 Capture Compare
+ DCD FPU_IRQHandler ; 81: FPU
+ DCD 0 ; 82: Reserved
+ DCD 0 ; 83: Reserved
+ DCD SPI4_IRQHandler ; 84: SPI4
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_CAN_TX_IRQHandler
+ B USB_HP_CAN_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_CAN_RX0_IRQHandler
+ B USB_LP_CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK COMP1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_IRQHandler
+ B COMP1_2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_RMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_RMP_IRQHandler
+ B USBWakeUp_RMP_IRQHandler
+
+ PUBWEAK TIM20_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_BRK_IRQHandler
+ B TIM20_BRK_IRQHandler
+
+ PUBWEAK TIM20_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_UP_IRQHandler
+ B TIM20_UP_IRQHandler
+
+ PUBWEAK TIM20_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_TRG_COM_IRQHandler
+ B TIM20_TRG_COM_IRQHandler
+
+ PUBWEAK TIM20_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_CC_IRQHandler
+ B TIM20_CC_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303x8.s
@@ -0,0 +1,450 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f303x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F303x6/STM32F303x8 devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM6_DAC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC1_IRQHandler
+ B TIM6_DAC1_IRQHandler
+
+ PUBWEAK TIM7_DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_DAC2_IRQHandler
+ B TIM7_DAC2_IRQHandler
+
+ PUBWEAK COMP2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP2_IRQHandler
+ B COMP2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303xc.s
@@ -0,0 +1,566 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f303xc.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F303xB/STM32F303xC devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD ADC4_IRQHandler ; ADC4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; COMP7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority remap
+ DCD USB_LP_IRQHandler ; USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_CAN_TX_IRQHandler
+ B USB_HP_CAN_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_CAN_RX0_IRQHandler
+ B USB_LP_CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+
+ PUBWEAK ADC4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC4_IRQHandler
+ B ADC4_IRQHandler
+
+ PUBWEAK COMP1_2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_3_IRQHandler
+ B COMP1_2_3_IRQHandler
+
+ PUBWEAK COMP4_5_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_5_6_IRQHandler
+ B COMP4_5_6_IRQHandler
+
+ PUBWEAK COMP7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP7_IRQHandler
+ B COMP7_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_RMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_RMP_IRQHandler
+ B USBWakeUp_RMP_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303xe.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303xe.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f303xe.s
@@ -0,0 +1,610 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f303xe.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table
+;* for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; 0: Window WatchDog
+ DCD PVD_IRQHandler ; 1: PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; 2: Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; 3: RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; 4: FLASH
+ DCD RCC_IRQHandler ; 5: RCC
+ DCD EXTI0_IRQHandler ; 6: EXTI Line0
+ DCD EXTI1_IRQHandler ; 7: EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; 8: EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; 9: EXTI Line3
+ DCD EXTI4_IRQHandler ; 10: EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; 11: DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; 12: DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; 13: DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; 14: DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; 15: DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; 16: DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; 17: DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; 18: ADC1 and ADC2
+ DCD USB_HP_CAN_TX_IRQHandler ; 19: USB Device High Priority or CAN TX
+ DCD USB_LP_CAN_RX0_IRQHandler ; 20: USB Device Low Priority or CAN RX0
+ DCD CAN_RX1_IRQHandler ; 21: CAN RX1
+ DCD CAN_SCE_IRQHandler ; 22: CAN SCE
+ DCD EXTI9_5_IRQHandler ; 23: External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; 24: TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; 25: TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; 26: TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; 27: TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; 28: TIM2
+ DCD TIM3_IRQHandler ; 29: TIM3
+ DCD TIM4_IRQHandler ; 30: TIM4
+ DCD I2C1_EV_IRQHandler ; 31: I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 32: I2C1 Error
+ DCD I2C2_EV_IRQHandler ; 33: I2C2 Event
+ DCD I2C2_ER_IRQHandler ; 34: I2C2 Error
+ DCD SPI1_IRQHandler ; 35: SPI1
+ DCD SPI2_IRQHandler ; 36: SPI2
+ DCD USART1_IRQHandler ; 37: USART1
+ DCD USART2_IRQHandler ; 38: USART2
+ DCD USART3_IRQHandler ; 39: USART3
+ DCD EXTI15_10_IRQHandler ; 40: External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; 41: RTC Alarm (A and B) through EXTI Line
+ DCD USBWakeUp_IRQHandler ; 42: USB Wakeup through EXTI line
+ DCD TIM8_BRK_IRQHandler ; 43: TIM8 Break
+ DCD TIM8_UP_IRQHandler ; 44: TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; 45: TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; 46: TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; 47: ADC3
+ DCD FMC_IRQHandler ; 48: FMC
+ DCD 0 ; 49: Reserved
+ DCD 0 ; 50: Reserved
+ DCD SPI3_IRQHandler ; 51: SPI3
+ DCD UART4_IRQHandler ; 52: UART4
+ DCD UART5_IRQHandler ; 53: UART5
+ DCD TIM6_DAC_IRQHandler ; 54: TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; 55: TIM7
+ DCD DMA2_Channel1_IRQHandler ; 56: DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; 57: DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; 58: DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; 59: DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; 60: DMA2 Channel 5
+ DCD ADC4_IRQHandler ; 61: ADC4
+ DCD 0 ; 62: Reserved
+ DCD 0 ; 63: Reserved
+ DCD COMP1_2_3_IRQHandler ; 64: COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; 65: COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; 66: COMP7
+ DCD 0 ; 67: Reserved
+ DCD 0 ; 68: Reserved
+ DCD 0 ; 69: Reserved
+ DCD 0 ; 70: Reserved
+ DCD 0 ; 71: Reserved
+ DCD I2C3_EV_IRQHandler ; 72: I2C3 Event
+ DCD I2C3_ER_IRQHandler ; 73: I2C3 Error
+ DCD USB_HP_IRQHandler ; 74: USB High Priority remap
+ DCD USB_LP_IRQHandler ; 75: USB Low Priority remap
+ DCD USBWakeUp_RMP_IRQHandler ; 76: USB Wakeup remap through EXTI
+ DCD TIM20_BRK_IRQHandler ; 77: TIM20 Break
+ DCD TIM20_UP_IRQHandler ; 78: TIM20 Update
+ DCD TIM20_TRG_COM_IRQHandler ; 79: TIM20 Trigger and Commutation
+ DCD TIM20_CC_IRQHandler ; 80: TIM20 Capture Compare
+ DCD FPU_IRQHandler ; 81: FPU
+ DCD 0 ; 82: Reserved
+ DCD 0 ; 83: Reserved
+ DCD SPI4_IRQHandler ; 84: SPI4
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_CAN_TX_IRQHandler
+ B USB_HP_CAN_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_CAN_RX0_IRQHandler
+ B USB_LP_CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+
+ PUBWEAK ADC4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC4_IRQHandler
+ B ADC4_IRQHandler
+
+ PUBWEAK COMP1_2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_3_IRQHandler
+ B COMP1_2_3_IRQHandler
+
+ PUBWEAK COMP4_5_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_5_6_IRQHandler
+ B COMP4_5_6_IRQHandler
+
+ PUBWEAK COMP7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP7_IRQHandler
+ B COMP7_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_RMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_RMP_IRQHandler
+ B USBWakeUp_RMP_IRQHandler
+
+ PUBWEAK TIM20_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_BRK_IRQHandler
+ B TIM20_BRK_IRQHandler
+
+ PUBWEAK TIM20_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_UP_IRQHandler
+ B TIM20_UP_IRQHandler
+
+ PUBWEAK TIM20_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_TRG_COM_IRQHandler
+ B TIM20_TRG_COM_IRQHandler
+
+ PUBWEAK TIM20_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_CC_IRQHandler
+ B TIM20_CC_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f318xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f318xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f318xx.s
@@ -0,0 +1,440 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f318xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F318xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD 0 ; Reserved
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C3_EV_IRQHandler ; I2C3 Event
+ DCD I2C3_ER_IRQHandler ; I2C3 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK COMP2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP2_IRQHandler
+ B COMP2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f328xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f328xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f328xx.s
@@ -0,0 +1,445 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f328xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F328xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM6_DAC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC1_IRQHandler
+ B TIM6_DAC1_IRQHandler
+
+ PUBWEAK TIM7_DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_DAC2_IRQHandler
+ B TIM7_DAC2_IRQHandler
+
+ PUBWEAK COMP2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP2_IRQHandler
+ B COMP2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f334x8.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f334x8.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f334x8.s
@@ -0,0 +1,485 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f334x8.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
+ DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP2_IRQHandler ; COMP2
+ DCD COMP4_6_IRQHandler ; COMP4 and COMP6
+ DCD 0 ; Reserved
+ DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM1 timer A
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM1 timer B
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM1 timer C
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM1 timer D
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM1 timer E
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM1 fault
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM6_DAC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC1_IRQHandler
+ B TIM6_DAC1_IRQHandler
+
+ PUBWEAK TIM7_DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_DAC2_IRQHandler
+ B TIM7_DAC2_IRQHandler
+
+ PUBWEAK COMP2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP2_IRQHandler
+ B COMP2_IRQHandler
+
+ PUBWEAK COMP4_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_6_IRQHandler
+ B COMP4_6_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f358xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f358xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f358xx.s
@@ -0,0 +1,541 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f358xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F358xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD ADC4_IRQHandler ; ADC4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; COMP7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+
+ PUBWEAK ADC4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC4_IRQHandler
+ B ADC4_IRQHandler
+
+ PUBWEAK COMP1_2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_3_IRQHandler
+ B COMP1_2_3_IRQHandler
+
+ PUBWEAK COMP4_5_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_5_6_IRQHandler
+ B COMP4_5_6_IRQHandler
+
+ PUBWEAK COMP7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP7_IRQHandler
+ B COMP7_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f373xc.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f373xc.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f373xc.s
@@ -0,0 +1,555 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f373xc.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F373xB/STM32F373xC devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD CEC_IRQHandler ; CEC
+ DCD TIM12_IRQHandler ; TIM12
+ DCD TIM13_IRQHandler ; TIM13
+ DCD TIM14_IRQHandler ; TIM14
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD SDADC1_IRQHandler ; SDADC1
+ DCD SDADC2_IRQHandler ; SDADC2
+ DCD SDADC3_IRQHandler ; SDADC3
+ DCD COMP1_2_IRQHandler ; COMP1 and COMP2 global Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD USB_HP_IRQHandler ; USB High Priority
+ DCD USB_LP_IRQHandler ; USB Low Priority
+ DCD USBWakeUp_IRQHandler ; USB Wakeup
+ DCD 0 ; Reserved
+ DCD TIM19_IRQHandler ; TIM19
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK TIM18_DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM18_DAC2_IRQHandler
+ B TIM18_DAC2_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM12_IRQHandler
+ B TIM12_IRQHandler
+
+ PUBWEAK TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM13_IRQHandler
+ B TIM13_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK TIM6_DAC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC1_IRQHandler
+ B TIM6_DAC1_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK SDADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDADC1_IRQHandler
+ B SDADC1_IRQHandler
+
+ PUBWEAK SDADC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDADC2_IRQHandler
+ B SDADC2_IRQHandler
+
+ PUBWEAK SDADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDADC3_IRQHandler
+ B SDADC3_IRQHandler
+
+ PUBWEAK COMP1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_IRQHandler
+ B COMP1_2_IRQHandler
+
+ PUBWEAK USB_HP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_IRQHandler
+ B USB_HP_IRQHandler
+
+ PUBWEAK USB_LP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_IRQHandler
+ B USB_LP_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM19_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM19_IRQHandler
+ B TIM19_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f378xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f378xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f378xx.s
@@ -0,0 +1,535 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f378xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F378xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_IRQHandler ; ADC1
+ DCD CAN_TX_IRQHandler ; CAN TX
+ DCD CAN_RX0_IRQHandler ; CAN RX0
+ DCD CAN_RX1_IRQHandler ; CAN RX1
+ DCD CAN_SCE_IRQHandler ; CAN SCE
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM15_IRQHandler ; TIM15
+ DCD TIM16_IRQHandler ; TIM16
+ DCD TIM17_IRQHandler ; TIM17
+ DCD TIM18_DAC2_IRQHandler ; TIM18 and DAC2
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD CEC_IRQHandler ; CEC
+ DCD TIM12_IRQHandler ; TIM12
+ DCD TIM13_IRQHandler ; TIM13
+ DCD TIM14_IRQHandler ; TIM14
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 Channel1 & channel2
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD SDADC1_IRQHandler ; SDADC1
+ DCD SDADC2_IRQHandler ; SDADC2
+ DCD SDADC3_IRQHandler ; SDADC3
+ DCD COMP1_2_IRQHandler ; COMP1 and COMP2 global Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM19_IRQHandler ; TIM19
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FPU_IRQHandler ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_IRQHandler
+ B ADC1_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK TIM18_DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM18_DAC2_IRQHandler
+ B TIM18_DAC2_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM12_IRQHandler
+ B TIM12_IRQHandler
+
+ PUBWEAK TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM13_IRQHandler
+ B TIM13_IRQHandler
+
+ PUBWEAK TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+ B TIM14_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK TIM6_DAC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC1_IRQHandler
+ B TIM6_DAC1_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK SDADC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDADC1_IRQHandler
+ B SDADC1_IRQHandler
+
+ PUBWEAK SDADC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDADC2_IRQHandler
+ B SDADC2_IRQHandler
+
+ PUBWEAK SDADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDADC3_IRQHandler
+ B SDADC3_IRQHandler
+
+ PUBWEAK COMP1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_IRQHandler
+ B COMP1_2_IRQHandler
+
+ PUBWEAK TIM19_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM19_IRQHandler
+ B TIM19_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ END
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f398xx.s b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f398xx.s
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/iar/startup_stm32f398xx.s
@@ -0,0 +1,585 @@
+;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name : startup_stm32f398xx.s
+;* Author : MCD Application Team
+;* Version : V2.2.0
+;* Date : 13-November-2015
+;* Description : STM32F398xx devices vector table
+;* for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M4 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* © COPYRIGHT(c) 2015 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;* 1. Redistributions of source code must retain the above copyright notice,
+;* this list of conditions and the following disclaimer.
+;* 2. Redistributions in binary form must reproduce the above copyright notice,
+;* this list of conditions and the following disclaimer in the documentation
+;* and/or other materials provided with the distribution.
+;* 3. Neither the name of STMicroelectronics nor the names of its contributors
+;* may be used to endorse or promote products derived from this software
+;* without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; 0: Window WatchDog
+ DCD 0 ; Reserved
+ DCD TAMP_STAMP_IRQHandler ; 2: Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; 3: RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; 4: FLASH
+ DCD RCC_IRQHandler ; 5: RCC
+ DCD EXTI0_IRQHandler ; 6: EXTI Line0
+ DCD EXTI1_IRQHandler ; 7: EXTI Line1
+ DCD EXTI2_TSC_IRQHandler ; 8: EXTI Line2 and Touch Sense controller
+ DCD EXTI3_IRQHandler ; 9: EXTI Line3
+ DCD EXTI4_IRQHandler ; 10: EXTI Line4
+ DCD DMA1_Channel1_IRQHandler ; 11: DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; 12: DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; 13: DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; 14: DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; 15: DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; 16: DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; 17: DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; 18: ADC1 and ADC2
+ DCD CAN_TX_IRQHandler ; 19: CAN TX
+ DCD CAN_RX0_IRQHandler ; 20: CAN RX0
+ DCD CAN_RX1_IRQHandler ; 21: CAN RX1
+ DCD CAN_SCE_IRQHandler ; 22: CAN SCE
+ DCD EXTI9_5_IRQHandler ; 23: External Line[9:5]s
+ DCD TIM1_BRK_TIM15_IRQHandler ; 24: TIM1 Break and TIM15
+ DCD TIM1_UP_TIM16_IRQHandler ; 25: TIM1 Update and TIM16
+ DCD TIM1_TRG_COM_TIM17_IRQHandler ; 26: TIM1 Trigger and Commutation and TIM17
+ DCD TIM1_CC_IRQHandler ; 27: TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; 28: TIM2
+ DCD TIM3_IRQHandler ; 29: TIM3
+ DCD TIM4_IRQHandler ; 30: TIM4
+ DCD I2C1_EV_IRQHandler ; 31: I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 32: I2C1 Error
+ DCD I2C2_EV_IRQHandler ; 33: I2C2 Event
+ DCD I2C2_ER_IRQHandler ; 34: I2C2 Error
+ DCD SPI1_IRQHandler ; 35: SPI1
+ DCD SPI2_IRQHandler ; 36: SPI2
+ DCD USART1_IRQHandler ; 37: USART1
+ DCD USART2_IRQHandler ; 38: USART2
+ DCD USART3_IRQHandler ; 39: USART3
+ DCD EXTI15_10_IRQHandler ; 40: External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; 41: RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_IRQHandler ; 43: TIM8 Break
+ DCD TIM8_UP_IRQHandler ; 44: TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; 45: TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; 46: TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; 47: ADC3
+ DCD FMC_IRQHandler ; 48: FMC
+ DCD 0 ; 49: Reserved
+ DCD 0 ; 50: Reserved
+ DCD SPI3_IRQHandler ; 51: SPI3
+ DCD UART4_IRQHandler ; 52: UART4
+ DCD UART5_IRQHandler ; 53: UART5
+ DCD TIM6_DAC_IRQHandler ; 54: TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; 55: TIM7
+ DCD DMA2_Channel1_IRQHandler ; 56: DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; 57: DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; 58: DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; 59: DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; 60: DMA2 Channel 5
+ DCD ADC4_IRQHandler ; 61: ADC4
+ DCD 0 ; 62: Reserved
+ DCD 0 ; 63: Reserved
+ DCD COMP1_2_3_IRQHandler ; 64: COMP1, COMP2 and COMP3
+ DCD COMP4_5_6_IRQHandler ; 65: COMP4, COMP5 and COMP6
+ DCD COMP7_IRQHandler ; 66: COMP7
+ DCD 0 ; 67: Reserved
+ DCD 0 ; 68: Reserved
+ DCD 0 ; 69: Reserved
+ DCD 0 ; 70: Reserved
+ DCD 0 ; 71: Reserved
+ DCD I2C3_EV_IRQHandler ; 72: I2C3 Event
+ DCD I2C3_ER_IRQHandler ; 73: I2C3 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM20_BRK_IRQHandler ; 77: TIM20 Break
+ DCD TIM20_UP_IRQHandler ; 78: TIM20 Update
+ DCD TIM20_TRG_COM_IRQHandler ; 79: TIM20 Trigger and Commutation
+ DCD TIM20_CC_IRQHandler ; 80: TIM20 Capture Compare
+ DCD FPU_IRQHandler ; 81: FPU
+ DCD 0 ; 82: Reserved
+ DCD 0 ; 83: Reserved
+ DCD SPI4_IRQHandler ; 84: SPI4
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_TSC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_TSC_IRQHandler
+ B EXTI2_TSC_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_TX_IRQHandler
+ B CAN_TX_IRQHandler
+
+ PUBWEAK CAN_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX0_IRQHandler
+ B CAN_RX0_IRQHandler
+
+ PUBWEAK CAN_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_RX1_IRQHandler
+ B CAN_RX1_IRQHandler
+
+ PUBWEAK CAN_SCE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN_SCE_IRQHandler
+ B CAN_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+ B TIM1_BRK_TIM15_IRQHandler
+
+ PUBWEAK TIM1_UP_TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+ B TIM1_UP_TIM16_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+ B TIM1_TRG_COM_TIM17_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+
+ PUBWEAK ADC4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC4_IRQHandler
+ B ADC4_IRQHandler
+
+ PUBWEAK COMP1_2_3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_2_3_IRQHandler
+ B COMP1_2_3_IRQHandler
+
+ PUBWEAK COMP4_5_6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP4_5_6_IRQHandler
+ B COMP4_5_6_IRQHandler
+
+ PUBWEAK COMP7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP7_IRQHandler
+ B COMP7_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK TIM20_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_BRK_IRQHandler
+ B TIM20_BRK_IRQHandler
+
+ PUBWEAK TIM20_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_UP_IRQHandler
+ B TIM20_UP_IRQHandler
+
+ PUBWEAK TIM20_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_TRG_COM_IRQHandler
+ B TIM20_TRG_COM_IRQHandler
+
+ PUBWEAK TIM20_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM20_CC_IRQHandler
+ B TIM20_CC_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c
@@ -0,0 +1,315 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f3xx.c
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f3xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * Supported STM32F3xx device
+ *-----------------------------------------------------------------------------
+ * System Clock source | HSI
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 8000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 8000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * USB Clock | DISABLE
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f3xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f3xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 8000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F3xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR &= 0xF87FC00C;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+ RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+ }
+ else
+ {
+ /* HSI oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
+ }
+#else
+ if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/CMSIS/Include/arm_common_tables.h b/drivers/CMSIS/Include/arm_common_tables.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/drivers/CMSIS/Include/arm_const_structs.h b/drivers/CMSIS/Include/arm_const_structs.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/drivers/CMSIS/Include/arm_math.h b/drivers/CMSIS/Include/arm_math.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+ #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+#elif defined __GNUC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__ /* Cosmic */
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+#elif defined __TASKING__
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (q15_t) x;
+ s = (q15_t) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+ ((q15_t) (x >> 16) * (q15_t) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+ ((q15_t) (x >> 16) * (q15_t) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+ ((q15_t) x * (q15_t) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+ ((q15_t) x * (q15_t) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+ ((q15_t) x * (q15_t) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+ ((q15_t) x * (q15_t) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+ ((q15_t) x * (q15_t) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ */
+
+
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in >= 0.0f)
+ {
+
+// #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+//Exit low optimization region - place directly after end of function definition
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+//Enter low optimization region - place directly above function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+//Exit low optimization region - place directly after end of function definition
+ #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+ #ifdef ARM_MATH_CM4
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+ #define LOW_OPTIMIZATION_EXIT
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__) // Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__) // TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/drivers/CMSIS/Include/core_cm0.h b/drivers/CMSIS/Include/core_cm0.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cm0.h
@@ -0,0 +1,740 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)(IRQn) < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)(IRQn) < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/drivers/CMSIS/Include/core_cm0plus.h b/drivers/CMSIS/Include/core_cm0plus.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,854 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)(IRQn) < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)(IRQn) < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/drivers/CMSIS/Include/core_cm3.h b/drivers/CMSIS/Include/core_cm3.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1693 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/drivers/CMSIS/Include/core_cm4.h b/drivers/CMSIS/Include/core_cm4.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16 /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/drivers/CMSIS/Include/core_cm7.h b/drivers/CMSIS/Include/core_cm7.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2397 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x07) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16 /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1];
+ __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93];
+ __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15];
+ __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1];
+ __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1];
+ __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6];
+ __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1];
+ __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)IRQn < 0) {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \fn uint32_t SCB_GetFPUType(void)
+ \brief get FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
+ return 2UL; // Double + Single precision FPU
+ } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
+ return 1UL; // Single precision FPU
+ } else {
+ return 0UL; // No FPU
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
+
+
+/** \brief Enable I-Cache
+
+ The function turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; // invalidate I-Cache
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Disable I-Cache
+
+ The function turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
+ SCB->ICIALLU = 0UL; // invalidate I-Cache
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+ The function invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Enable D-Cache
+
+ The function turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Disable D-Cache
+
+ The function turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
+
+ do { // clean & invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+ The function invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Clean D-Cache
+
+ The function cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // clean D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCSW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+ The function cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // clean & invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+ \brief D-Cache Invalidate by address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= (int32_t)linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+ \brief D-Cache Clean by address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= (int32_t)linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+ \brief D-Cache Clean and Invalidate by address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= (int32_t)linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/drivers/CMSIS/Include/core_cmFunc.h b/drivers/CMSIS/Include/core_cmFunc.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/drivers/CMSIS/Include/core_cmInstr.h b/drivers/CMSIS/Include/core_cmInstr.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0)
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0)
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0)
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+ return(result);
+}
+#endif
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function executes a exclusive LDR instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function executes a exclusive LDR instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function executes a exclusive LDR instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function executes a exclusive STR instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function executes a exclusive STR instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function executes a exclusive STR instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Rotate Right with Extend (32 bit)
+
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+#endif
+ return(result);
+}
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function executes a exclusive LDR instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function executes a exclusive LDR instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function executes a exclusive LDR instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function executes a exclusive STR instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function executes a exclusive STR instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function executes a exclusive STR instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Rotate Right with Extend (32 bit)
+
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/drivers/CMSIS/Include/core_cmSimd.h b/drivers/CMSIS/Include/core_cmSimd.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/drivers/CMSIS/Include/core_sc000.h b/drivers/CMSIS/Include/core_sc000.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_sc000.h
@@ -0,0 +1,864 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154];
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)(IRQn) < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)(IRQn) < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/drivers/CMSIS/Include/core_sc300.h b/drivers/CMSIS/Include/core_sc300.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1675 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129];
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/drivers/CMSIS/RTOS/Template/cmsis_os.h b/drivers/CMSIS/RTOS/Template/cmsis_os.h
new file mode 100644
--- /dev/null
+++ b/drivers/CMSIS/RTOS/Template/cmsis_os.h
@@ -0,0 +1,707 @@
+/* ----------------------------------------------------------------------
+ * $Date: 5. February 2013
+ * $Revision: V1.02
+ *
+ * Project: CMSIS-RTOS API
+ * Title: cmsis_os.h template header file
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * Version 0.03
+ * osKernelStart added, optional feature: main started as thread
+ * osSemaphores have standard behavior
+ * osTimerCreate does not start the timer, added osTimerStart
+ * osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ * Support for C++ interface
+ * - const attribute removed from the osXxxxDef_t typedef's
+ * - const attribute added to the osXxxxDef macros
+ * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ * Added: osKernelInitialize
+ * Version 1.02
+ * Control functions for short timeouts in microsecond resolution:
+ * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ * Removed: osSignalGet
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2013 ARM LIMITED
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
+#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0])
+
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
+
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string
+
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available
+#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
+#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
+#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
+#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum {
+ osPriorityIdle = -3, ///< priority: idle (lowest)
+ osPriorityLow = -2, ///< priority: low
+ osPriorityBelowNormal = -1, ///< priority: below normal
+ osPriorityNormal = 0, ///< priority: normal (default)
+ osPriorityAboveNormal = +1, ///< priority: above normal
+ osPriorityHigh = +2, ///< priority: high
+ osPriorityRealtime = +3, ///< priority: realtime (highest)
+ osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+
+/// Timeout value.
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value
+
+/// Status code values returned by CMSIS-RTOS functions.
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum {
+ osOK = 0, ///< function completed; no error or event occurred.
+ osEventSignal = 0x08, ///< function completed; signal event occurred.
+ osEventMessage = 0x10, ///< function completed; message event occurred.
+ osEventMail = 0x20, ///< function completed; mail event occurred.
+ osEventTimeout = 0x40, ///< function completed; timeout occurred.
+ osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+ osErrorResource = 0x81, ///< resource not available: a specified resource was not available.
+ osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period.
+ osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+ osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object.
+ osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority.
+ osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+ osErrorValue = 0x86, ///< value of a parameter is out of range.
+ osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
+ os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
+} osStatus;
+
+
+/// Timer type value for the timer definition.
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum {
+ osTimerOnce = 0, ///< one-shot timer
+ osTimerPeriodic = 1 ///< repeating timer
+} os_timer_type;
+
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument);
+
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument);
+
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_cb *osThreadId;
+
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_cb *osTimerId;
+
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_cb *osMutexId;
+
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_cb *osSemaphoreId;
+
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_cb *osPoolId;
+
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_cb *osMessageQId;
+
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_cb *osMailQId;
+
+
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_def {
+ os_pthread pthread; ///< start address of thread function
+ osPriority tpriority; ///< initial thread priority
+ uint32_t instances; ///< maximum number of instances of that thread function
+ uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_def {
+ os_ptimer ptimer; ///< start address of a timer function
+} osTimerDef_t;
+
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_def {
+ uint32_t dummy; ///< dummy value.
+} osMutexDef_t;
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_def {
+ uint32_t dummy; ///< dummy value.
+} osSemaphoreDef_t;
+
+/// Definition structure for memory block allocation.
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_def {
+ uint32_t pool_sz; ///< number of items (elements) in the pool
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< pointer to memory for pool
+} osPoolDef_t;
+
+/// Definition structure for message queue.
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< memory array for messages
+} osMessageQDef_t;
+
+/// Definition structure for mail queue.
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< memory array for mail
+} osMailQDef_t;
+
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
+/// However the struct may be extended at the end.
+typedef struct {
+ osStatus status; ///< status code: event or error information
+ union {
+ uint32_t v; ///< message as 32-bit value
+ void *p; ///< message or mail as void pointer
+ int32_t signals; ///< signal flags
+ } value; ///< event value
+ union {
+ osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
+ osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
+ } def; ///< event definition
+} osEvent;
+
+
+// ==== Kernel Control Functions ====
+
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
+osStatus osKernelInitialize (void);
+
+/// Start the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+osStatus osKernelStart (void);
+
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+
+#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
+
+/// Get the RTOS kernel system timer counter
+/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
+/// \return RTOS kernel system timer as 32-bit value
+uint32_t osKernelSysTick (void);
+
+/// The RTOS kernel system timer frequency in Hz
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#define osKernelSysTickFrequency 100000000
+
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param microsec time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+
+#endif // System Timer available
+
+// ==== Thread Management ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param name name of the thread function.
+/// \param priority initial priority of the thread function.
+/// \param instances number of possible thread instances.
+/// \param stacksz stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osThreadDef(name, priority, instances, stacksz) \
+extern const osThreadDef_t os_thread_def_##name
+#else // define the object
+#define osThreadDef(name, priority, instances, stacksz) \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz) }
+#endif
+
+/// Access a Thread definition.
+/// \param name name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name) \
+&os_thread_def_##name
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in] thread_def thread definition referenced with \ref osThread.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+
+/// Change priority of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] priority new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+
+/// Get current priority of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+
+
+// ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in] millisec time delay value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+
+#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+osEvent osWait (uint32_t millisec);
+
+#endif // Generic Wait available
+
+
+// ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param name name of the timer object.
+/// \param function name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osTimerDef(name, function) \
+extern const osTimerDef_t os_timer_def_##name
+#else // define the object
+#define osTimerDef(name, function) \
+const osTimerDef_t os_timer_def_##name = \
+{ (function) }
+#endif
+
+/// Access a Timer definition.
+/// \param name name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create a timer.
+/// \param[in] timer_def timer object referenced with \ref osTimer.
+/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in] argument argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \param[in] millisec time delay value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+
+/// Stop the timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+
+/// Delete a timer that was created by \ref osTimerCreate.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
+osStatus osTimerDelete (osTimerId timer_id);
+
+
+// ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+osEvent osSignalWait (int32_t signals, uint32_t millisec);
+
+
+// ==== Mutex Management ====
+
+/// Define a Mutex.
+/// \param name name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osMutexDef(name) \
+extern const osMutexDef_t os_mutex_def_##name
+#else // define the object
+#define osMutexDef(name) \
+const osMutexDef_t os_mutex_def_##name = { 0 }
+#endif
+
+/// Access a Mutex definition.
+/// \param name name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name) \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object.
+/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+
+/// Delete a Mutex that was created by \ref osMutexCreate.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
+osStatus osMutexDelete (osMutexId mutex_id);
+
+
+// ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available
+
+/// Define a Semaphore object.
+/// \param name name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osSemaphoreDef(name) \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else // define the object
+#define osSemaphoreDef(name) \
+const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
+#endif
+
+/// Access a Semaphore definition.
+/// \param name name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name) \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object used for managing resources.
+/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in] count number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+
+/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+
+#endif // Semaphore available
+
+
+// ==== Memory Pool Management Functions ====
+
+#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
+
+/// \brief Define a Memory Pool.
+/// \param name name of the memory pool.
+/// \param no maximum number of blocks (objects) in the memory pool.
+/// \param type data type of a single block (object).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osPoolDef(name, no, type) \
+extern const osPoolDef_t os_pool_def_##name
+#else // define the object
+#define osPoolDef(name, no, type) \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), NULL }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param name name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a memory pool.
+/// \param[in] pool_def memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a memory pool.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a memory pool and set memory block to zero.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a specific memory pool.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in] block address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif // Memory Pool Management available
+
+
+// ==== Message Queue Management Functions ====
+
+#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available
+
+/// \brief Create a Message Queue Definition.
+/// \param name name of the queue.
+/// \param queue_sz maximum number of messages in the queue.
+/// \param type data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osMessageQDef(name, queue_sz, type) \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else // define the object
+#define osMessageQDef(name, queue_sz, type) \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), sizeof (type) }
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param name name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue.
+/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] info message information.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+#endif // Message Queues available
+
+
+// ==== Mail Queue Management Functions ====
+
+#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available
+
+/// \brief Create a Mail Queue Definition.
+/// \param name name of the queue
+/// \param queue_sz maximum number of messages in queue
+/// \param type data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else // define the object
+#define osMailQDef(name, queue_sz, type) \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof (type) }
+#endif
+
+/// \brief Access a Mail Queue Definition.
+/// \param name name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name) \
+&os_mailQ_def_##name
+
+/// Create and Initialize mail queue.
+/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block from a mail.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block from a mail and set memory block to zero.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a mail to a queue.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+
+/// Get a mail from a queue.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec timeout value or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+
+/// Free a memory block from a mail.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+
+#endif // Mail Queues available
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _CMSIS_OS_H
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,2948 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE ((uint32_t)0x00000000)
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F3) || defined(STM32F1)
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F3 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR ((uint32_t)0x00000100)
+#define ETH_MMCRIR ((uint32_t)0x00000104)
+#define ETH_MMCTIR ((uint32_t)0x00000108)
+#define ETH_MMCRIMR ((uint32_t)0x0000010C)
+#define ETH_MMCTIMR ((uint32_t)0x00000110)
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
+#define ETH_MMCTGFCR ((uint32_t)0x00000168)
+#define ETH_MMCRFCECR ((uint32_t)0x00000194)
+#define ETH_MMCRFAECR ((uint32_t)0x00000198)
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#if defined(STM32L0)
+#define RCC_IT_LSECSS RCC_IT_CSSLSE
+#define RCC_IT_CSS RCC_IT_CSSHSE
+#endif
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h
@@ -0,0 +1,915 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_H
+#define __STM32F3xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_conf.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Macros
+ * @{
+ */
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+/** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
+ * @brief SYSCFG registers bit address in the alias region
+ * @{
+ */
+/* ------------ SYSCFG registers bit address in the alias region -------------*/
+#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
+/* --- CFGR2 Register ---*/
+/* Alias word address of BYP_ADDR_PAR bit */
+#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
+#define BYPADDRPAR_BitNumber 0x04
+#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_DMA_RMP)
+/** @defgroup HAL_DMA_Remapping HAL DMA Remapping
+ * Elements values convention: 0xXXYYYYYY
+ * - YYYYYY : Position in the register
+ * - XX : Register index
+ * - 00: CFGR1 register in SYSCFG
+ * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
+ * @{
+ */
+#define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
+#define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap
+ 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
+#define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap
+ 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
+#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
+#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
+#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
+ 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
+#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
+ 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
+#if defined(SYSCFG_CFGR3_DMA_RMP)
+#if !defined(HAL_REMAP_CFGR3_MASK)
+#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
+#endif
+
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 2 */
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 4 */
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 6 */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 3 */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 5 */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 7 */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 7 */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 3 */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 5 */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 11: Map on DMA1 channel 6 */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 01: Map on DMA1 channel 2 */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
+ 10: Map on DMA1 channel 4 */
+#define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap
+ x0: No remap (ADC2 on DMA2)
+ 10: Map on DMA1 channel 2 */
+#define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap
+ 11: Map on DMA1 channel 4 */
+#endif /* SYSCFG_CFGR3_DMA_RMP */
+
+#if defined(SYSCFG_CFGR3_DMA_RMP)
+#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
+ (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
+ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
+ (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
+#else
+#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
+ (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
+ (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
+ (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
+ (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
+ (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
+ (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
+#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_DMA_RMP */
+
+/** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
+ * Elements values convention: 0xXXYYYYYY
+ * - YYYYYY : Position in the register
+ * - XX : Register index
+ * - 00: CFGR1 register in SYSCFG
+ * - 01: CFGR3 register in SYSCFG
+ * @{
+ */
+#define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
+ 0: No remap (DAC trigger is TIM8_TRGO)
+ 1: Remap (DAC trigger is TIM3_TRGO) */
+#define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap
+ 0: No remap
+ 1: Remap (TIM1_TRG3 = TIM17_OC) */
+#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
+#if !defined(HAL_REMAP_CFGR3_MASK)
+#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
+#endif
+#define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
+ 0: Remap (DAC trigger is TIM15_TRGO)
+ 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
+#define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
+ 0: No remap
+ 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
+#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
+ (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
+ (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
+ (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
+#else
+#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
+ (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
+#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
+/**
+ * @}
+ */
+
+#if defined (STM32F302xE)
+/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
+ * @{
+ */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
+ 0: No remap (TIM1_CC3)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
+ 0: No remap (TIM2_CC2)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
+ 0: No remap (TIM4_CC4)
+ 1: Remap (TIM20_CC1) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
+ 0: No remap (TIM6_TRGO)
+ 1: Remap (TIM20_CC2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
+ 0: No remap (TIM3_CC4)
+ 1: Remap (TIM20_CC3) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
+ 0: No remap (TIM2_CC1)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
+ 0: No remap (EXTI line 15)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
+ 0: No remap (TIM3_CC1)
+ 1: Remap (TIM20_CC4) */
+
+#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
+/**
+ * @}
+ */
+#endif /* STM32F302xE */
+
+#if defined (STM32F303xE) || defined (STM32F398xx)
+/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
+ * @{
+ */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
+ 0: No remap (TIM1_CC3)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
+ 0: No remap (TIM2_CC2)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
+ 0: No remap (TIM4_CC4)
+ 1: Remap (TIM20_CC1) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
+ 0: No remap (TIM6_TRGO)
+ 1: Remap (TIM20_CC2) */
+#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
+ 0: No remap (TIM3_CC4)
+ 1: Remap (TIM20_CC3) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
+ 0: No remap (TIM2_CC1)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
+ 0: No remap (EXTI line 15)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
+ 0: No remap (TIM3_CC1)
+ 1: Remap (TIM20_CC4) */
+#define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
+ 0: No remap (EXTI line 2)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
+ 0: No remap (TIM4_CC1)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
+ 0: No remap (TIM2_CC1)
+ 1: Remap (TIM20_CC1) */
+#define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
+ 0: No remap (TIM4_CC3)
+ 1: Remap (TIM20_TRGO) */
+#define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
+ 0: No remap (TIM1_CC3)
+ 1: Remap (TIM20_TRGO2) */
+#define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
+ 0: No remap (TIM7_TRGO)
+ 1: Remap (TIM20_CC2) */
+
+#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+ * @{
+ */
+
+/** @brief Fast-mode Plus driving capability on a specific GPIO
+ */
+#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
+#define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */
+#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
+#define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */
+#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/* CCM-SRAM defined */
+/** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
+ * @{
+ */
+#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
+#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
+#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
+#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
+#if defined(SYSCFG_RCR_PAGE4)
+/* More than 4KB CCM-SRAM defined */
+#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
+#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
+#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
+#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
+#endif /* SYSCFG_RCR_PAGE4 */
+#if defined(SYSCFG_RCR_PAGE8)
+#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
+#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
+#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
+#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
+#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
+#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
+#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
+#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
+#endif /* SYSCFG_RCR_PAGE8 */
+
+#if defined(SYSCFG_RCR_PAGE8)
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0xFFFF))
+#elif defined(SYSCFG_RCR_PAGE4)
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x00FF))
+#else
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x000F))
+#endif /* SYSCFG_RCR_PAGE8 */
+/**
+ * @}
+ */
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
+ * @{
+ */
+#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
+#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
+#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
+#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
+#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
+
+#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
+ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
+
+/** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
+ * @{
+ */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
+#define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
+#define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
+
+#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
+
+#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
+
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
+
+#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
+#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
+#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
+#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
+ * @{
+ */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
+#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
+#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
+#define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
+#define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
+
+#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
+#define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
+#define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
+#endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_MEM_MODE)
+/** @brief Main Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
+#endif /* SYSCFG_CFGR1_MEM_MODE */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_0)
+/** @brief System Flash memory mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
+ }while(0)
+#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
+/** @brief Embedded SRAM mapped at 0x00000000
+ */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
+ }while(0)
+#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
+
+#if defined(SYSCFG_CFGR1_MEM_MODE_2)
+#define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
+ }while(0)
+#endif /* SYSCFG_CFGR1_MEM_MODE_2 */
+/**
+ * @}
+ */
+
+/** @defgroup Encoder_Mode Encoder Mode
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE)
+/** @brief No Encoder mode
+ */
+#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
+#endif /* SYSCFG_CFGR1_ENCODER_MODE */
+
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
+/** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
+ */
+#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
+ }while(0)
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
+
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
+/** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
+ */
+#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
+ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
+ }while(0)
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
+
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
+/** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
+ */
+#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
+ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
+ }while(0)
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Remap_Enable DMA Remap Enable
+ * @{
+ */
+#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
+/** @brief DMA remapping enable/disable macros
+ * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
+ */
+#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
+ }while(0)
+#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
+ }while(0)
+#elif defined(SYSCFG_CFGR1_DMA_RMP)
+/** @brief DMA remapping enable/disable macros
+ * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
+ */
+#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 |= (__DMA_REMAP__); \
+ }while(0)
+#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
+ }while(0)
+#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
+/**
+ * @}
+ */
+
+/** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
+ * @{
+ */
+/** @brief Fast-mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
+ * That you can find above these macros.
+ */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+ }while(0)
+/**
+ * @}
+ */
+
+/** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
+ * @{
+ */
+/** @brief SYSCFG interrupt enable/disable macros
+ * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
+ */
+#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
+ SYSCFG->CFGR1 |= (__INTERRUPT__); \
+ }while(0)
+
+#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
+ SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
+ }while(0)
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_USB_IT_RMP)
+/** @defgroup USB_Interrupt_Remap USB Interrupt Remap
+ * @{
+ */
+/** @brief USB interrupt remapping enable/disable macros
+ */
+#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
+#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_USB_IT_RMP */
+
+#if defined(SYSCFG_CFGR1_VBAT)
+/** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
+ * @{
+ */
+/** @brief SYSCFG interrupt enable/disable macros
+ */
+#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
+#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR1_VBAT */
+
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
+ * @{
+ */
+/** @brief SYSCFG Break Lockup lock
+ * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
+
+#if defined(SYSCFG_CFGR2_PVD_LOCK)
+/** @defgroup PVD_Lock_Enable PVD Lock
+ * @{
+ */
+/** @brief SYSCFG Break PVD lock
+ * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_PVD_LOCK */
+
+#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
+ * @{
+ */
+/** @brief SYSCFG Break SRAM PARITY lock
+ * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
+ * @note The selected configuration is locked and can be unlocked by system reset
+ */
+#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
+ SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
+
+/** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
+ * @{
+ */
+#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
+/** @brief Trigger remapping enable/disable macros
+ * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
+ */
+#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
+ }while(0)
+#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
+ (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
+ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
+ }while(0)
+#else
+/** @brief Trigger remapping enable/disable macros
+ * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
+ */
+#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
+ }while(0)
+#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
+ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
+ }while(0)
+#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
+/**
+ * @}
+ */
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
+/** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
+ * @{
+ */
+/** @brief ADC trigger remapping enable/disable macros
+ * @param __ADCTRIGGER_REMAP__: This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
+ */
+#define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
+ (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
+ }while(0)
+#define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
+ (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
+/** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
+ * @{
+ */
+/**
+ * @brief Parity check on RAM disable macro
+ * @note Disabling the parity check on RAM locks the configuration bit.
+ * To re-enable the parity check on RAM perform a system reset.
+ */
+#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001)
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
+ * @{
+ */
+/** @brief CCM RAM page write protection enable macro
+ * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
+ * @note write protection can only be disabled by a system reset
+ */
+#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
+ SYSCFG->RCR |= (__PAGE_WP__); \
+ }while(0)
+/**
+ * @}
+ */
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+ * @}
+ */
+
+/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h
@@ -0,0 +1,243 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_ADC_H
+#define __STM32F3xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/* Include ADC HAL Extended module */
+/* (include on top of file since ADC structures are defined in extended file) */
+#include "stm32f3xx_hal_adc_ex.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ * @note ADC state machine is managed by bitfields, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Not available on STM32F1 device: Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F1 device: End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master ( */
+
+
+/**
+ * @brief ADC handle Structure definition
+ */
+typedef struct __ADC_HandleTypeDef
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+
+ ADC_InitTypeDef Init; /*!< ADC required parameters */
+
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+}ADC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macro ADC Exported Macros
+ * @{
+ */
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h
@@ -0,0 +1,4047 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file containing functions prototypes of ADC HAL library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_ADC_EX_H
+#define __STM32F3xx_ADC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
+ * @{
+ */
+struct __ADC_HandleTypeDef;
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Structure definition of ADC initialization and regular group
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign,
+ * ScanConvMode, EOCSelection, LowPowerAutoWait.
+ * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun.
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group.
+ * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler.
+ The clock is common for all the ADCs.
+ This parameter can be a value of @ref ADCEx_ClockPrescaler
+ Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
+ AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
+ Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
+ Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
+ uint32_t Resolution; /*!< Configures the ADC resolution.
+ This parameter can be a value of @ref ADCEx_Resolution */
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0) (default setting)
+ or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4, if offset enabled: MSB on register bit 14 and LSB on register bit 3).
+ See reference manual for alignments with other resolutions.
+ This parameter can be a value of @ref ADCEx_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be a value of @ref ADCEx_Scan_mode */
+ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
+ This parameter can be a value of @ref ADCEx_EOCSelection. */
+ uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary.
+ New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
+ This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
+ and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+ Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Regular
+ Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available) */
+ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */
+ uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+ uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved.
+ This parameter is for regular group only.
+ This parameter can be a value of @ref ADCEx_Overrun
+ Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
+ Note: Error reporting in function of conversion mode:
+ - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */
+}ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+ * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
+ * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
+ This parameter can be a value of @ref ADCEx_regular_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
+ uint32_t SingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+ This parameter must be a value of @ref ADCEx_SingleDifferential
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
+ uint32_t OffsetNumber; /*!< Selects the offset number
+ This parameter can be a value of @ref ADCEx_OffsetNumber
+ Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */
+ uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC injected group and ADC channel for injected group
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
+ * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
+ * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group.
+ * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
+ * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Configure the ADC injected channel
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< The rank in the regular group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
+ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+ This parameter must be a value of @ref ADCEx_SingleDifferential
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
+ uint32_t InjectedOffsetNumber; /*!< Selects the offset number
+ This parameter can be a value of @ref ADCEx_OffsetNumber
+ Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
+ This parameter can be set to ENABLE or DISABLE.
+ If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
+ new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'.
+ Caution: This feature request that the sequence is fully configured before injected conversion start.
+ Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
+ If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef;
+
+/**
+ * @brief ADC Injection Configuration
+ */
+typedef struct
+{
+ uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
+ HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+ JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
+}ADC_InjectionConfigTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
+ */
+typedef struct
+{
+ uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog to apply to the selected channel.
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
+ uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
+ For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter.
+ This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
+ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
+ For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
+ Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
+ This parameter can be a value of @ref ADCEx_channels. */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
+}ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC multimode
+ * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'DMAAccessMode')
+ * - For parameter 'DMAAccessMode': ADC enabled without conversion on going on regular group.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
+ This parameter can be a value of @ref ADCEx_Common_mode */
+ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multi ADC mode:
+ selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
+ This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode
+ Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun.
+ Therefore, it is recommended to disable multimode DMA access: each ADC uses its own DMA channel.
+ Refer to device errata sheet for more details. */
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
+ Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits
+ from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits */
+}ADC_MultiModeTypeDef;
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Structure definition of ADC and regular group initialization
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
+ * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
+ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+ This parameter can be a value of @ref ADCEx_Data_align */
+ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
+ Scan direction is upward: from rank1 to rank 'n'.
+ This parameter can be a value of @ref ADCEx_Scan_mode
+ Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
+ or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
+ the last conversion of the sequence. All previous conversions would be overwritten by the last one.
+ Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
+ uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ after the selected trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
+ To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
+ uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */
+}ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC can be either disabled or enabled without conversion on going on regular group.
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
+ This parameter can be a value of @ref ADCEx_regular_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
+}ADC_ChannelConfTypeDef;
+
+/**
+ * @brief ADC Configuration injected Channel structure definition
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
+ * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
+ * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
+ * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
+ This parameter can be a value of @ref ADCEx_channels
+ Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
+ uint32_t InjectedRank; /*!< Rank in the injected group sequencer
+ This parameter must be a value of @ref ADCEx_injected_rank
+ Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
+ This parameter can be a value of @ref ADCEx_sampling_times
+ Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
+ If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
+ If set to external trigger source, triggering is on event rising edge.
+ This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+}ADC_InjectionConfTypeDef;
+
+/**
+ * @brief ADC Configuration analog watchdog definition
+ * @note The setting of these parameters with function is conditioned to ADC state.
+ * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
+ */
+typedef struct
+{
+ uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
+ This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
+ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
+ This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
+ This parameter can be a value of @ref ADCEx_channels. */
+ uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+}ADC_AnalogWDGConfTypeDef;
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup ADCEx_Error_Code ADC Extended Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
+ enable/disable, erroneous state */
+#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */
+/**
+ * @}
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler
+ * @{
+ */
+#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated PLL */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
+#endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Resolution ADC Extended Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */
+#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
+#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
+#define ADC_SCAN_ENABLE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+
+/*!< External triggers of regular group for ADC3&ADC4 only */
+#define ADC_EXTERNALTRIGCONV_T2_CC1 ADC3_4_EXTERNALTRIG_T2_CC1
+#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_4_EXTERNALTRIG_T2_CC3
+#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_4_EXTERNALTRIG_T3_CC1
+#define ADC_EXTERNALTRIGCONV_T4_CC1 ADC3_4_EXTERNALTRIG_T4_CC1
+#define ADC_EXTERNALTRIGCONV_T7_TRGO ADC3_4_EXTERNALTRIG_T7_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_4_EXTERNALTRIG_T8_CC1
+#define ADC_EXTERNALTRIGCONV_EXT_IT2 ADC3_4_EXTERNALTRIG_EXT_IT2
+
+/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+
+#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/* ADC external triggers specific to device STM303xE: mask to differentiate */
+/* standard triggers from specific timer 20, needed for reallocation of */
+/* triggers common to ADC1&2/ADC3&4 and to avoid mixing with standard */
+/* triggers without remap. */
+#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
+
+/*!< List of external triggers specific to device STM303xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */
+#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */
+
+/*!< External triggers of regular group for ADC3&ADC4 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+/* None */
+
+/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15) */
+#define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */
+#define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) */
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+
+#if defined(STM32F302xE)
+/* ADC external triggers specific to device STM302xE: mask to differentiate */
+/* standard triggers from specific timer 20, needed for reallocation of */
+/* triggers common to ADC1&2 and to avoind mixing with standard */
+/* triggers without remap. */
+#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
+
+/*!< List of external triggers specific to device STM302xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
+/* device STM302xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */
+#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */
+#endif /* STM32F302xE */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
+#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
+#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/*!< External triggers of regular group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1
+#define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1
+#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2
+#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO
+#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO
+#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
+#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
+#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Overrun ADC Extended overrun
+ * @{
+ */
+#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) /*!< Default setting, to be used for compatibility with other STM32 devices */
+#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_channels ADC Extended Channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package */
+/* pins. Refer to device datasheet for channels availability. */
+#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
+
+/* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */
+#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_15
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
+#define ADC_CHANNEL_VBAT ADC_CHANNEL_17
+
+/* Note: Vopamp2/3/4 internal channels available on ADC2/3/4 respectively */
+#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17
+#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17
+#define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17
+
+/* Note: VrefInt internal channels available on all ADCs, but only */
+/* one ADC is allowed to be connected to VrefInt at the same time. */
+#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_18)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */
+#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC_SAMPLETIME_61CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 61.5 ADC clock cycles */
+#define ADC_SAMPLETIME_181CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 181.5 ADC clock cycles */
+#define ADC_SAMPLETIME_601CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 601.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
+ * @{
+ */
+#define ADC_SINGLE_ENDED ((uint32_t)0x00000000)
+#define ADC_DIFFERENTIAL_ENDED ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
+ * @{
+ */
+#define ADC_OFFSET_NONE ((uint32_t)0x00)
+#define ADC_OFFSET_1 ((uint32_t)0x01)
+#define ADC_OFFSET_2 ((uint32_t)0x02)
+#define ADC_OFFSET_3 ((uint32_t)0x03)
+#define ADC_OFFSET_4 ((uint32_t)0x04)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
+#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
+#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
+#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
+#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
+#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
+#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
+#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
+#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
+#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
+#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
+#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
+#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
+#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
+#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
+#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/* List of external triggers with generic trigger name, independently of ADC */
+/* target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 only */
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+/* External triggers of injected group for ADC3&ADC4 only */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC3 ADC3_4_EXTERNALTRIGINJEC_T1_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_4_EXTERNALTRIGINJEC_T4_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T4_CC4 ADC3_4_EXTERNALTRIGINJEC_T4_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC3_4_EXTERNALTRIGINJEC_T7_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_4_EXTERNALTRIGINJEC_T8_CC2
+
+/* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/*!< List of external triggers specific to device STM303xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */
+
+/*!< External triggers of injected group for ADC3&ADC4 only, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14) */
+
+/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
+/* device STM303xE: : using Timer20 with ADC trigger input remap */
+/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
+/* ADC3_4 by driver when needed. */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11) */
+#endif /* STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+
+#if defined(STM32F302xE)
+/*!< List of external triggers specific to device STM302xE: using Timer20 */
+/* with ADC trigger input remap. */
+/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
+/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
+
+/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
+/* device STM302xE: : using Timer20 with ADC trigger input remap */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
+#endif /* STM32F302xE */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/*!< List of external triggers with generic trigger name, independently of */
+/* ADC target (caution: applies to other ADCs sharing the same common group), */
+/* sorted by trigger name: */
+
+/* External triggers of injected group for ADC1&ADC2 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2
+#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of injected group for ADC1 */
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15
+
+#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1))
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1))
+#define ADC_DUALMODE_INTERL ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
+#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_3 | ADC12_CCR_MULTI_0))
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
+ * @{
+ */
+#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC will use its own DMA channel */
+#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
+#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
+#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC12_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC12_CCR_DELAY_3))
+#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
+#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
+#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_conversion_group ADC Conversion Group
+ * @{
+ */
+#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
+#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
+#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Event_type ADC Extended Event Type
+ * @{
+ */
+#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) */
+#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) */
+#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) */
+#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /* ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
+ * @{
+ */
+#define ADC_IT_RDY ADC_IER_RDY /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of Sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) */
+#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */
+
+#define ADC_IT_AWD ADC_IT_AWD1 /* ADC Analog watchdog 1 interrupt source: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
+ * @{
+ */
+#define ADC_FLAG_RDY ADC_ISR_ADRD /*!< ADC Ready (ADRDY) flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) */
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) */
+#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
+
+#define ADC_FLAG_AWD ADC_FLAG_AWD1 /* ADC Analog watchdog 1 flag: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_multimode_bits ADC Multimode Bits
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_CCR_MULTI ADC12_CCR_MULTI /*!< Multi ADC mode selection */
+#define ADC_CCR_MULTI_0 ADC12_CCR_MULTI_0 /*!< MULTI bit 0 */
+#define ADC_CCR_MULTI_1 ADC12_CCR_MULTI_1 /*!< MULTI bit 1 */
+#define ADC_CCR_MULTI_2 ADC12_CCR_MULTI_2 /*!< MULTI bit 2 */
+#define ADC_CCR_MULTI_3 ADC12_CCR_MULTI_3 /*!< MULTI bit 3 */
+#define ADC_CCR_MULTI_4 ADC12_CCR_MULTI_4 /*!< MULTI bit 4 */
+#define ADC_CCR_DELAY ADC12_CCR_DELAY /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0 ADC12_CCR_DELAY_0 /*!< DELAY bit 0 */
+#define ADC_CCR_DELAY_1 ADC12_CCR_DELAY_1 /*!< DELAY bit 1 */
+#define ADC_CCR_DELAY_2 ADC12_CCR_DELAY_2 /*!< DELAY bit 2 */
+#define ADC_CCR_DELAY_3 ADC12_CCR_DELAY_3 /*!< DELAY bit 3 */
+#define ADC_CCR_DMACFG ADC12_CCR_DMACFG /*!< DMA configuration for multi-ADC mode */
+#define ADC_CCR_MDMA ADC12_CCR_MDMA /*!< DMA mode for multi-ADC mode */
+#define ADC_CCR_MDMA_0 ADC12_CCR_MDMA_0 /*!< MDMA bit 0 */
+#define ADC_CCR_MDMA_1 ADC12_CCR_MDMA_1 /*!< MDMA bit 1 */
+#define ADC_CCR_CKMODE ADC12_CCR_CKMODE /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0 ADC12_CCR_CKMODE_0 /*!< CKMODE bit 0 */
+#define ADC_CCR_CKMODE_1 ADC12_CCR_CKMODE_1 /*!< CKMODE bit 1 */
+#define ADC_CCR_VREFEN ADC12_CCR_VREFEN /*!< VREFINT enable */
+#define ADC_CCR_TSEN ADC12_CCR_TSEN /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN ADC12_CCR_VBATEN /*!< VBAT enable */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_CCR_MULTI ADC1_CCR_MULTI /*!< Multi ADC mode selection */
+#define ADC_CCR_MULTI_0 ADC1_CCR_MULTI_0 /*!< MULTI bit 0 */
+#define ADC_CCR_MULTI_1 ADC1_CCR_MULTI_1 /*!< MULTI bit 1 */
+#define ADC_CCR_MULTI_2 ADC1_CCR_MULTI_2 /*!< MULTI bit 2 */
+#define ADC_CCR_MULTI_3 ADC1_CCR_MULTI_3 /*!< MULTI bit 3 */
+#define ADC_CCR_MULTI_4 ADC1_CCR_MULTI_4 /*!< MULTI bit 4 */
+#define ADC_CCR_DELAY ADC1_CCR_DELAY /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0 ADC1_CCR_DELAY_0 /*!< DELAY bit 0 */
+#define ADC_CCR_DELAY_1 ADC1_CCR_DELAY_1 /*!< DELAY bit 1 */
+#define ADC_CCR_DELAY_2 ADC1_CCR_DELAY_2 /*!< DELAY bit 2 */
+#define ADC_CCR_DELAY_3 ADC1_CCR_DELAY_3 /*!< DELAY bit 3 */
+#define ADC_CCR_DMACFG ADC1_CCR_DMACFG /*!< DMA configuration for multi-ADC mode */
+#define ADC_CCR_MDMA ADC1_CCR_MDMA /*!< DMA mode for multi-ADC mode */
+#define ADC_CCR_MDMA_0 ADC1_CCR_MDMA_0 /*!< MDMA bit 0 */
+#define ADC_CCR_MDMA_1 ADC1_CCR_MDMA_1 /*!< MDMA bit 1 */
+#define ADC_CCR_CKMODE ADC1_CCR_CKMODE /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0 ADC1_CCR_CKMODE_0 /*!< CKMODE bit 0 */
+#define ADC_CCR_CKMODE_1 ADC1_CCR_CKMODE_1 /*!< CKMODE bit 1 */
+#define ADC_CCR_VREFEN ADC1_CCR_VREFEN /*!< VREFINT enable */
+#define ADC_CCR_TSEN ADC1_CCR_TSEN /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN ADC1_CCR_VBATEN /*!< VBAT enable */
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
+#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
+ * @{
+ */
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
+#define ADC_EXTERNALTRIGCONV_T4_CC2 ADC_EXTERNALTRIG_T4_CC2
+#define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO
+#define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3
+#define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4
+#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
+#define ADC_SOFTWARE_START ADC_SWSTART
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_channels ADC Extended Channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package */
+/* pins. Refer to device datasheet for channels availability. */
+#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
+#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
+#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
+#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
+#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
+#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
+#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))
+
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
+#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
+#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
+#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
+#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
+#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
+#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */
+#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
+#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
+#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
+#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
+#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
+#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
+#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
+#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
+#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
+#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
+#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
+#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
+#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
+#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
+#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
+#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
+#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
+#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
+#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
+ * @{
+ */
+/* External triggers for injected groups of ADC1 */
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
+#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
+#define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2
+#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
+#define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
+#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_conversion_group ADC Conversion Group
+ * @{
+ */
+#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
+#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
+#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Event_type ADC Extended Event Type
+ * @{
+ */
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
+ * @{
+ */
+#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
+ * @{
+ */
+#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
+#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
+#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
+#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
+#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
+
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of regular group for ADC1 & ADC2 */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+
+/* External triggers of regular group for ADC3 & ADC4 */
+#define ADC3_4_EXTERNALTRIG_T3_CC1 ((uint32_t)0x00000000)
+#define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T8_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC3_4_EXTERNALTRIG_EXT_IT2 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T4_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC3_4_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T8_TRGO2 ((uint32_t)ADC_CFGR_EXTSEL_3)
+#define ADC3_4_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC3_4_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC3_4_EXTERNALTRIG_T7_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC3_4_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC3_4_EXTERNALTRIG_T2_CC1 ((uint32_t)ADC_CFGR_EXTSEL)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/* List of external triggers of common group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/* List of external triggers of common group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/* List of external triggers of common group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
+#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_HRTIM_TRG1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_HRTIM_TRG3 ((uint32_t) ADC_CFGR_EXTSEL_3)
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers of regular group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
+#define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
+#define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
+#define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
+#define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
+#define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
+#define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
+#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
+ * @{
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers for injected groups of ADC1 & ADC2 */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+
+/* External triggers for injected groups of ADC3 & ADC4 */
+/* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event). */
+/* JEXT2 is the main trigger, JEXT5 could be redirected to another */
+/* in future devices. */
+/* However, this channel is implemented with a SW offset of 0x10000 for */
+/* differentiation between similar triggers of common groups ADC1&ADC2, */
+/* ADC3&ADC4 (Differentiation processed into macro */
+/* ADC_JSQR_JEXTSEL_SET) */
+#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000)
+#define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#endif /* STM32F303xE || STM32F398xx */
+
+#define ADC3_4_EXTERNALTRIGINJEC_T4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC3_4_EXTERNALTRIGINJEC_T1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/* List of external triggers of group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+/* List of external triggers of group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/* List of external triggers of group ADC1&ADC2: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
+#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
+#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
+#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* List of external triggers of injected group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
+#define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
+#define ADC1_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
+ ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
+ ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
+ ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
+ ADC_FLAG_JQOVF)
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
+ * @{
+ */
+/* List of external triggers of regular group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIG_T19_TRGO ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
+#define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
+#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
+#define ADC_EXTERNALTRIG_T4_CC2 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
+#define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
+ * @{
+ */
+/* List of external triggers of injected group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+
+/* External triggers of injected group for ADC1 */
+#define ADC_EXTERNALTRIGINJEC_T19_CC1 ((uint32_t) 0x00000000)
+#define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
+#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
+#define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels
+ * @{
+ */
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
+ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
+ ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
+ ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
+ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
+ ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
+ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
+ ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
+ ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
+ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
+ ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
+
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
+ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
+ ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
+ ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
+#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
+ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
+ ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
+
+#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
+#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
+#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
+
+/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/**
+ * @brief Enable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @note ADC enable requires a delay for ADC stabilization time
+ * (refer to device datasheet, parameter tSTAB)
+ * @note On STM32F3 devices, some hardware constraints must be strictly
+ * respected before using this macro:
+ * - ADC internal voltage regulator must be preliminarily enabled.
+ * This is performed by function HAL_ADC_Init().
+ * - ADC state requirements: ADC must be disabled, no conversion on
+ * going, no calibration on going.
+ * These checks are performed by functions HAL_ADC_start_xxx().
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) \
+ (SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADEN))
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @note On STM32F3 devices, some hardware constraints must be strictly
+ * respected before using this macro:
+ * - ADC state requirements: ADC must be enabled, no conversion on
+ * going.
+ * These checks are performed by functions HAL_ADC_start_xxx().
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \
+ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
+ } while(0)
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
+ * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
+ * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
+ * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of */
+/* register ISR). */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__)))
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enable the ADC peripheral
+ * @note ADC enable requires a delay for ADC stabilization time
+ * (refer to device datasheet, parameter tSTAB)
+ * @note On STM32F37x devices, if ADC is already enabled this macro trigs
+ * a conversion SW start on regular group.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) \
+ (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
+
+/** @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_STRT: ADC Regular group start flag
+ * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_STRT: ADC Regular group start flag
+ * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @retval None
+ */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Private macro ------------------------------------------------------------*/
+
+/** @addtogroup ADCEx_Private_Macro ADCEx Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/**
+ * @brief Verification of hardware constraints before ADC can be enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
+ */
+#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
+ (( HAL_IS_BIT_CLR((__HANDLE__)->Instance->CR , \
+ (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | \
+ ADC_CR_JADSTART |ADC_CR_ADSTART | ADC_CR_ADDIS | \
+ ADC_CR_ADEN ) ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
+
+/**
+ * @brief Check if no conversion on going on regular and/or injected groups
+ * @param __HANDLE__: ADC handle
+ * @retval SET (conversion is on going) or RESET (no conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \
+ ) ? RESET : SET)
+
+/**
+ * @brief Check if no conversion on going on regular group
+ * @param __HANDLE__: ADC handle
+ * @retval SET (conversion is on going) or RESET (no conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
+ ) ? RESET : SET)
+
+/**
+ * @brief Check if no conversion on going on injected group
+ * @param __HANDLE__: ADC handle
+ * @retval SET (conversion is on going) or RESET (no conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
+ ) ? RESET : SET)
+
+/**
+ * @brief Returns resolution bits in CFGR1 register: RES[1:0].
+ * Returned value is among parameters to @ref ADCEx_Resolution.
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+
+/**
+ * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 1 and 4.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 5 and 9.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 5)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 10 and 14.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 10)))
+
+/**
+ * @brief Set the selected regular Channel rank for rank between 15 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 15)))
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_) +2))
+
+
+/**
+ * @brief Set the Analog Watchdog 1 channel.
+ * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
+ * @retval None
+ */
+#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26)
+
+/**
+ * @brief Configure the channel number into Analog Watchdog 2 or 3.
+ * @param _CHANNEL_: ADC Channel
+ * @retval None
+ */
+#define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_))
+
+/**
+ * @brief Enable automatic conversion of injected group
+ * @param _INJECT_AUTO_CONVERSION_: Injected automatic conversion.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25)
+
+/**
+ * @brief Enable ADC injected context queue
+ * @param _INJECT_CONTEXT_QUEUE_MODE_: Injected context queue mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21)
+
+/**
+ * @brief Enable ADC discontinuous conversion mode for injected group
+ * @param _INJECT_DISCONTINUOUS_MODE_: Injected discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20)
+
+/**
+ * @brief Enable ADC discontinuous conversion mode for regular group
+ * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16)
+
+/**
+ * @brief Configures the number of discontinuous conversions for regular group.
+ * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
+
+/**
+ * @brief Enable the ADC auto delay mode.
+ * @param _AUTOWAIT_: Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14)
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
+
+/**
+ * @brief Enable ADC overrun mode.
+ * @param _OVERRUN_MODE_: Overrun mode.
+ * @retval Overrun bit setting to be programmed into CFGR register
+ */
+/* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
+/* as the default case to be compliant with other STM32 devices. */
+#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
+ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
+ )? (ADC_CFGR_OVRMOD) : (0x00000000) \
+ )
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param _DMACONTREQ_MODE_: DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1)
+
+/**
+ * @brief For devices with 3 ADCs or more: Defines the external trigger source
+ * for regular group according to ADC into common group ADC1&ADC2 or
+ * ADC3&ADC4 (some triggers with same source have different value to
+ * be programmed into ADC EXTSEL bits of CFGR register).
+ * Note: No risk of trigger bits value of common group ADC1&ADC2
+ * misleading to another trigger at same bits value, because the 3
+ * exceptions below are circular and do not point to any other trigger
+ * with direct treatment.
+ * For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
+ * @retval External trigger to be programmed into EXTSEL bits of CFGR register
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T3_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T8_TRGO) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/* Note: Macro including external triggers specific to device STM303xE: using */
+/* Timer20 with ADC trigger input remap. */
+#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T3_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T8_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1 \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T2_CC1) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIG_EXT_IT2) \
+ : \
+ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2 \
+ )? \
+ (ADC3_4_EXTERNALTRIG_T4_CC1) \
+ : \
+ (__EXT_TRIG_CONV__) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
+ )
+#endif /* STM32F303xE || STM32F398xx */
+#else
+#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
+ (__EXT_TRIG_CONV__)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @brief For devices with 3 ADCs or more: Defines the external trigger source
+ * for injected group according to ADC into common group ADC1&ADC2 or
+ * ADC3&ADC4 (some triggers with same source have different value to
+ * be programmed into ADC JEXTSEL bits of JSQR register).
+ * Note: No risk of trigger bits value of common group ADC1&ADC2
+ * misleading to another trigger at same bits value, because the 3
+ * exceptions below are circular and do not point to any other trigger
+ * with direct treatment, except trigger
+ * ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset.
+ * For devices with 2 ADCs or less: this macro makes no change.
+ * @param __HANDLE__: ADC handle
+ * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group
+ * @retval External trigger to be programmed into JEXTSEL bits of JSQR register
+ */
+#if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx)
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ ) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/* Note: Macro including external triggers specific to device STM303xE: using */
+/* Timer20 with ADC trigger input remap. */
+#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
+ )? \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) \
+ == ADC_EXTERNALTRIGINJECCONV_T20_TRGO \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T20_TRGO) \
+ : \
+ ( ( (__EXT_TRIG_INJECTCONV__) \
+ == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 \
+ )? \
+ (ADC3_4_EXTERNALTRIGINJEC_T1_CC3) \
+ : \
+ (__EXT_TRIG_INJECTCONV__) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ : \
+ (__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
+ )
+#endif /* STM32F303xE || STM32F398xx */
+#else
+#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
+ (__EXT_TRIG_INJECTCONV__)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @brief Configure the channel number into offset OFRx register
+ * @param _CHANNEL_: ADC Channel
+ * @retval None
+ */
+#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26)
+
+/**
+ * @brief Configure the channel number into differential mode selection register
+ * @param _CHANNEL_: ADC Channel
+ * @retval None
+ */
+#define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_))
+
+/**
+ * @brief Calibration factor in differential mode to be set into calibration register
+ * @param _Calibration_Factor_: Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16)
+
+/**
+ * @brief Calibration factor in differential mode to be retrieved from calibration register
+ * @param _Calibration_Factor_: Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16)
+
+/**
+ * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+ * @param _Threshold_: Threshold value
+ * @retval None
+ */
+#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
+
+/**
+ * @brief Enable the ADC DMA continuous request for ADC multimode.
+ * @param _DMAContReq_MODE_: DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13)
+
+/**
+ * @brief Verification of hardware constraints before ADC can be disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
+ */
+#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
+ (( ( ((__HANDLE__)->Instance->CR) & \
+ (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
+ ) ? SET : RESET)
+
+
+/**
+ * @brief Shift the offset in function of the selected ADC resolution.
+ * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+ * @param __HANDLE__: ADC handle
+ * @param _Offset_: Value to be shifted
+ * @retval None
+ */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
+ ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
+
+/**
+ * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
+ * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+ * If resolution 12 bits, no shift.
+ * If resolution 10 bits, shift of 2 ranks on the left.
+ * If resolution 8 bits, shift of 4 ranks on the left.
+ * If resolution 6 bits, shift of 6 ranks on the left.
+ * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+ * @param __HANDLE__: ADC handle
+ * @param _Threshold_: Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
+
+/**
+ * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
+ * Thresholds have to be left-aligned on bit 7.
+ * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded)
+ * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded)
+ * If resolution 8 bits, no shift.
+ * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0)
+ * @param __HANDLE__: ADC handle
+ * @param _Threshold_: Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+ ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
+ ((_Threshold_) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
+ (_Threshold_) << 2 )
+
+/**
+ * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE__: ADC handle
+ * @retval Common control register ADC1_2 or ADC3_4
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_MASTER_INSTANCE(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? (ADC1) : (ADC3) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_MASTER_INSTANCE(__HANDLE__) \
+ (ADC1)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_MASTER_INSTANCE(__HANDLE__) \
+ (ADC1)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE__: ADC handle
+ * @retval Common control register ADC1_2 or ADC3_4
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_COMMON_REGISTER(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? (ADC1_2_COMMON) : (ADC3_4_COMMON) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_COMMON_REGISTER(__HANDLE__) \
+ (ADC1_2_COMMON)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_COMMON_REGISTER(__HANDLE__) \
+ (ADC1_COMMON)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? \
+ (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) \
+ : \
+ (ADC3_4_COMMON->CCR & ADC34_CCR_MULTI) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
+ (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
+ (RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
+ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ (!RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle.
+ * @retval None
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
+ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INJECSIMULT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_ALTERTRIG) || \
+ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
+ (!RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle.
+ * @retval None
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
+ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_REGSIMULT) || \
+ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INTERL) || \
+ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
+ (!RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
+ )? \
+ (ADC1->CFGR & ADC_CFGR_JAUTO) \
+ : \
+ (ADC3->CFGR & ADC_CFGR_JAUTO) \
+ )
+#elif defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
+ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
+ )? \
+ (ADC1->CFGR & ADC_CFGR_JAUTO) \
+ : \
+ (RESET) \
+ )
+#else
+#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
+ (RESET)
+#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+
+/**
+ * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE__: ADC handle
+ * @param __HANDLE_OTHER_ADC__: other ADC handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
+ : \
+ ( ( ((__HANDLE__)->Instance == ADC2) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
+ : \
+ ( ( ((__HANDLE__)->Instance == ADC3) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC4) \
+ : \
+ ( ( ((__HANDLE__)->Instance == ADC4) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC3) \
+ : \
+ ((__HANDLE_OTHER_ADC__)->Instance = NULL) \
+ ) \
+ ) \
+ ) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
+ : \
+ ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
+ )
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
+ ((__HANDLE_OTHER_ADC__)->Instance = NULL)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Set handle of the ADC slave associated to the ADC master
+ * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+ * @param __HANDLE_MASTER__: ADC master handle
+ * @param __HANDLE_SLAVE__: ADC slave handle
+ * @retval None
+ */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : \
+ ( ( ((__HANDLE_MASTER__)->Instance == ADC3) \
+ )? \
+ ((__HANDLE_SLAVE__)->Instance = ADC4) \
+ : \
+ ((__HANDLE_SLAVE__)->Instance = NULL) \
+ ) \
+ )
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
+ )? \
+ ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : \
+ ( NULL ) \
+ )
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B) )
+
+#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B) )
+
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_ENABLE) )
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) )
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
+ ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VBAT) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP1) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP2) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP3) || \
+ ((CHANNEL) == ADC_CHANNEL_VOPAMP4) )
+
+#define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_4CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_61CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_181CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_601CYCLES_5) )
+
+#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \
+ ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) )
+
+#define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_1) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_2) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_3) || \
+ ((OFFSET_NUMBER) == ADC_OFFSET_4) )
+
+#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_10) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_11) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_12) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_13) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_14) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_15) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_16) )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+#if defined(STM32F302xE)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F302xE */
+
+#if defined(STM32F302xC)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F302xC */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
+ \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
+ \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+#if defined(STM32F302xE)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F302xE */
+
+#if defined(STM32F302xC)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F302xC */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F303x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F334x8 */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_2) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_3) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_4) )
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
+ ((MODE) == ADC_DUALMODE_REGSIMULT) || \
+ ((MODE) == ADC_DUALMODE_INTERL) || \
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) )
+
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
+ ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \
+ ((MODE) == ADC_DMAACCESSMODE_8_6_BITS) )
+
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
+
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
+ ((CONVERSION) == ADC_INJECTED_GROUP) || \
+ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_AWD2_EVENT) || \
+ ((EVENT) == ADC_AWD3_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT) || \
+ ((EVENT) == ADC_JQOVF_EVENT) )
+
+/** @defgroup ADCEx_range_verification ADC Extended Range Verification
+ * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
+ * @{
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification
+ * @{
+ */
+/**
+ * @brief Calibration factor length verification (7 bits maximum)
+ * @param _Calibration_Factor_: Calibration factor value
+ * @retval None
+ */
+#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Verification of ADC state: enabled or disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Set ADC number of conversions into regular channel sequence length.
+ * @param _NbrOfConversion_: Regular channel sequence length
+ * @retval None
+ */
+#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
+ (((_NbrOfConversion_) - (uint8_t)1) << 20)
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 10 and 18.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
+ ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+
+/**
+ * @brief Set the ADC's sample time for channel numbers between 0 and 9.
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @param _CHANNELNB_: Channel number.
+ * @retval None
+ */
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
+ ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 1 and 6.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 7 and 12.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
+
+/**
+ * @brief Set the selected regular channel rank for rank between 13 and 16.
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @retval None
+ */
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
+ ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
+
+/**
+ * @brief Set the injected sequence length.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
+ (((_JSQR_JL_) -1) << 20)
+
+/**
+ * @brief Set the selected injected channel rank
+ * Note: on STM32F37x devices, channel rank position in JSQR register
+ * is depending on total number of ranks selected into
+ * injected sequencer (ranks sequence starting from 4-JL)
+ * @param _CHANNELNB_: Channel number.
+ * @param _RANKNB_: Rank number.
+ * @param _JSQR_JL_: Sequence length.
+ * @retval None
+ */
+#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
+ ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
+
+/**
+ * @brief Enable ADC continuous conversion mode.
+ * @param _CONTINUOUS_MODE_: Continuous mode.
+ * @retval None
+ */
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
+ ((_CONTINUOUS_MODE_) << 1)
+
+/**
+ * @brief Configures the number of discontinuous conversions for the regular group channels.
+ * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
+ (((_NBR_DISCONTINUOUS_CONV_) - 1) << 13)
+
+/**
+ * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
+ * @param _SCAN_MODE_: Scan conversion mode.
+ * @retval None
+ */
+/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
+/* is equivalent to ADC_SCAN_ENABLE. */
+#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
+ (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
+ )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
+ )
+
+/**
+ * @brief Calibration factor in differential mode to be set into calibration register
+ * @param _Calibration_Factor_: Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \
+ ((_Calibration_Factor_) << 16)
+
+/**
+ * @brief Calibration factor in differential mode to be retrieved from calibration register
+ * @param _Calibration_Factor_: Calibration factor value
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \
+ ((_Calibration_Factor_) >> 16)
+
+
+/**
+ * @brief Get the maximum ADC conversion cycles on all channels.
+ * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
+ * Approximation of sampling time within 4 ranges, returns the highest value:
+ * below 7.5 cycles {1.5 cycle; 7.5 cycles},
+ * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
+ * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
+ * equal to 239.5 cycles
+ * Unit: ADC clock cycles
+ * @param __HANDLE__: ADC handle
+ * @retval ADC conversion cycles on all channels
+ */
+#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
+ \
+ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
+ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
+ : \
+ ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
+ ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
+ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
+ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
+ )
+
+/**
+ * @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler)
+ * from system clock configuration register.
+ * Approximation within 3 ranges, returns the higher value:
+ * total prescaler minimum: 2 (ADC presc 2, APB2 presc 0)
+ * total prescaler 32 (ADC presc 0 and APB2 presc all, or
+ * ADC presc {4, 6, 8} and APB2 presc {0, 2, 4})
+ * total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16})
+ * Unit: none (prescaler factor)
+ * @retval ADC and APB2 prescaler factor
+ */
+#define ADC_CLOCK_PRESCALER_RANGE() \
+ (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \
+ (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32 ) \
+ : \
+ (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128 ) \
+ )
+
+/**
+ * @brief Get the ADC clock prescaler from system clock configuration register.
+ * @retval None
+ */
+#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14) +1)
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
+ ((SCAN_MODE) == ADC_SCAN_ENABLE) )
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VBAT) )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
+
+#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_10) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_11) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_12) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_13) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_14) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_15) || \
+ ((CHANNEL) == ADC_REGULAR_RANK_16) )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
+
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_SOFTWARE_START) )
+
+#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) )
+
+#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2) || \
+ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
+
+#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_2) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_3) || \
+ ((CHANNEL) == ADC_INJECTED_RANK_4) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
+ ((CONVERSION) == ADC_INJECTED_GROUP) || \
+ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
+
+#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
+
+/** @defgroup ADCEx_range_verification ADC Extended Range Verification
+ * For a unique ADC resolution: 12 bits
+ * @{
+ */
+#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
+ * @{
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions *********************************/
+
+/** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+
+/* ADC calibration */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
+uint32_t HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc);
+#endif /* STM32F373xC || STM32F378xx */
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* ADC group regular stop conversion without impacting group injected */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(struct __ADC_HandleTypeDef* hadc);
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(struct __ADC_HandleTypeDef* hadc);
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(struct __ADC_HandleTypeDef* hadc);
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+void HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_LevelOutOfWindow2Callback(struct __ADC_HandleTypeDef* hadc);
+void HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleTypeDef* hadc);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_ADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h
@@ -0,0 +1,812 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_can.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_CAN_H
+#define __STM32F3xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter
+ F3 devices don't support CAN2 interface (Slave). Therefore this parameter
+ is meaningless but it has been kept for compatibility accross STM32 families */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+ uint8_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code
+ This parameter can be a value of @ref HAL_CAN_Error_Code */
+
+}CAN_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_CAN_Error_Code CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */
+#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */
+#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */
+#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */
+#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
+#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
+#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts CAN Interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mailboxes CAN Mailboxes
+* @{
+*/
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__: CAN handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle.
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__: CAN handle.
+ * @param __INTERRUPT__: CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__: CAN handle.
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
+
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __INTERRUPT__: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__: CAN handle.
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__: CAN handle.
+ * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disables the DBG Freeze for CAN.
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @param __NEWSTATE__: new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F302x8 || */
+ /* STM32F373xC || STM32F378xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h
@@ -0,0 +1,656 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cec.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of CEC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CEC_H
+#define __STM32F3xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CEC CEC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CEC_Exported_Types CEC Exported Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
+ It can be one of @ref CEC_Signal_Free_Time
+ and belongs to the set {0,...,7} where
+ 0x0 is the default configuration
+ else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
+
+ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
+ it can be a value of @ref CEC_Tolerance :
+ @arg CEC_STANDARD_TOLERANCE
+ @arg CEC_EXTENDED_TOLERANCE */
+
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ @arg CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ @arg CEC_RX_STOP_ON_BRE: reception is stopped. */
+
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ CEC line upon Bit Rising Error detection.
+ @arg CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ @arg CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
+
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ @arg CEC line upon Long Bit Period Error detection.
+ @arg CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ @arg CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ upon an error detected on a broadcast message.
+
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+
+ @arg 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
+ @arg __ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ @arg __ b) LBPE detection: error-bit generation on the CEC line
+ if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
+
+ @arg 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
+ no error-bit generation in case neither a) nor b) are satisfied. Additionally,
+ there is no error-bit generation in case of Short Bit Period Error detection in
+ a broadcast message while LSTN bit is set. */
+
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ @arg CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
+ @arg CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+
+ uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
+
+ uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+
+ @arg CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ own address (OAR). Messages addressed to different destination are ignored.
+ Broadcast messages are always received.
+
+ @arg CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ address (OAR) with positive acknowledge. Messages addressed to different destination
+ are received, but without interfering with the CEC bus: no acknowledge sent. */
+
+ uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
+
+}CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State structures definition
+ */
+typedef enum
+{
+ HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
+ HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
+ HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
+ HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
+}HAL_CEC_StateTypeDef;
+
+/**
+ * @brief CEC handle Structure definition
+ */
+typedef struct
+{
+ CEC_TypeDef *Instance; /*!< CEC registers base address */
+
+ CEC_InitTypeDef Init; /*!< CEC communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
+
+ uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to CEC Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
+
+ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
+ in case error is reported */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_CEC_StateTypeDef State; /*!< CEC communication state */
+
+}CEC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+ * @{
+ */
+
+/** @defgroup CEC_Error_Code CEC Error Code
+ * @{
+ */
+#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< No error */
+#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
+#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
+#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
+#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
+#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
+#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
+#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
+#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
+#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
+ * @{
+ */
+#define CEC_DEFAULT_SFT ((uint32_t)0x00000000) /*!< Transmission history-based signal free time (ruled by hardware) */
+#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001) /*!< 0.5 nominal data bit period */
+#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002) /*!< 1.5 nominal data bit periods */
+#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003) /*!< 2.5 nominal data bit periods */
+#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004) /*!< 3.5 nominal data bit periods */
+#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005) /*!< 4.5 nominal data bit periods */
+#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006) /*!< 5.5 nominal data bit periods */
+#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007) /*!< 6.5 nominal data bit periods */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Tolerance CEC Receiver Tolerance
+ * @{
+ */
+#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000) /*!< Standard tolerance margin */
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) /*!< Extended Tolerance */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
+ * @{
+ */
+#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000) /*!< CEC reception not stopped by BRE detection */
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) /*!< CEC reception stopped by BRE detection */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
+ * @{
+ */
+#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) /*!< No Error-Bit on CEC line in case of BRE detection */
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) /*!< Error-Bit on CEC line in case of BRE detection */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
+ * @{
+ */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) /*!< No Error-Bit on CEC line in case of LBPE detection */
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) /*!< Error-Bit on CEC line in case of LBPE detection */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
+ * @{
+ */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000) /*!< Error-Bit on CEC line for specific error conditions
+ on a broadcast message (cf Reference Manual) */
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) /*!< No Error-Bit on CEC line for specific error conditions
+ on a broadcast message (cf Reference Manual) */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
+ * @{
+ */
+#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000) /*!< SFT timer starts when TXSOM is set by software */
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) /*!< SFT timer starts automatically at the end of message transmission/reception */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Listening_Mode CEC Listening mode option
+ * @{
+ */
+#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000) /*!< CEC peripheral receives only message addressed to its own address (OAR). */
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) /*!< CEC peripheral receives messages addressed to its own address (OAR) with
+ positive acknowledge. Messages addressed to different destination are
+ received, but without interfering with the CEC bus: no acknowledge sent. */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
+ * @{
+ */
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) /*!< CEC Device Own Address position in CEC CFGR register */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) /*!< CEC Initiator logical address position in message header */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Interrupts_Definitions CEC interrupts definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE /*!< Tx missing acknowledge error interruption */
+#define CEC_IT_TXERR CEC_IER_TXERRIE /*!< Tx error interruption */
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE /*!< Tx underrun interruption */
+#define CEC_IT_TXEND CEC_IER_TXENDIE /*!< Tx end of message interruption */
+#define CEC_IT_TXBR CEC_IER_TXBRIE /*!< Tx byte request interruption */
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE /*!< Arbitration lost interruption */
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE /*!< Rx missing acknowledge error interruption */
+#define CEC_IT_LBPE CEC_IER_LBPEIE /*!< Long bit period error interruption */
+#define CEC_IT_SBPE CEC_IER_SBPEIE /*!< Short bit period error interruption */
+#define CEC_IT_BRE CEC_IER_BREIE /*!< Bit rising error interruption */
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE /*!< Rx overrun interruption */
+#define CEC_IT_RXEND CEC_IER_RXENDIE /*!< End of reception interruption */
+#define CEC_IT_RXBR CEC_IER_RXBRIE /*!< RX byte received interruption */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Flags_Definitions CEC flags definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE /*!< Tx missing acknowledge error flag */
+#define CEC_FLAG_TXERR CEC_ISR_TXERR /*!< Tx error flag */
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR /*!< Tx underrun flag */
+#define CEC_FLAG_TXEND CEC_ISR_TXEND /*!< Tx end of message flag */
+#define CEC_FLAG_TXBR CEC_ISR_TXBR /*!< Tx byte request flag */
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST /*!< Arbitration lost flag */
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE /*!< Rx missing acknowledge error flag */
+#define CEC_FLAG_LBPE CEC_ISR_LBPE /*!< Long bit period error flag */
+#define CEC_FLAG_SBPE CEC_ISR_SBPE /*!< Short bit period error flag */
+#define CEC_FLAG_BRE CEC_ISR_BRE /*!< Bit rising error flag */
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR /*!< Rx overrun flag */
+#define CEC_FLAG_RXEND CEC_ISR_RXEND /*!< End of reception flag */
+#define CEC_FLAG_RXBR CEC_ISR_RXBR /*!< RX byte received flag */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
+ * @{
+ */
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /*!< All Rx or Tx errors flags concatenation */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) /*!< All Rx errors interruptions concatenation */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
+ * @{
+ */
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /*!< All Tx errors interruptions concatenation */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CEC handle state
+ * @param __HANDLE__: CEC handle.
+ * @retval None
+ */
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+
+/** @brief Check whether or not the specified CEC interrupt flag is set.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval IT Status
+ */
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+
+/** @brief Clear the interrupt or status flag when raised (write at 1)
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __FLAG__: specifies the interrupt/status flag to clear.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
+
+/** @brief Enable the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disable the specified CEC interrupt.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Check whether or not the specified CEC interrupt is enabled.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __INTERRUPT__: specifies the CEC interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval Flag Status
+ */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+/** @brief Enable the CEC device.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
+
+/** @brief Disable the CEC device.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
+
+/** @brief Set Transmission Start flag.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
+
+/** @brief Set Transmission End flag.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @note If the CEC message consists of only one byte, TXEOM must be set before TXSOM.
+ * @retval none
+ *
+ */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
+
+/** @brief Get Transmission Start flag.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
+
+/** @brief Get Transmission End flag.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval FlagStatus
+ */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
+
+/** @brief Clear OAR register.
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @retval none
+ */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
+
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode).
+ * @param __HANDLE__: specifies the CEC Handle.
+ * @param __ADDRESS__: own address value (CEC logical address is identified by bit position)
+ * @note To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.
+ * @retval none
+ */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief CEC control functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+ * @{
+ */
+
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+
+#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
+ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
+
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
+
+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
+
+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
+
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+
+#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
+ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
+
+#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
+ ((__MODE__) == CEC_FULL_LISTENING_MODE))
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__: CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__: CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__: CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h
@@ -0,0 +1,294 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_comp.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of COMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_COMP_H
+#define __STM32F3xx_HAL_COMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup COMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+ * @{
+ */
+/**
+ * @brief COMP Init structure definition
+ */
+typedef struct
+{
+
+ uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
+ This parameter can be a value of @ref COMPEx_InvertingInput */
+
+ uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
+ This parameter can be a value of @ref COMPEx_NonInvertingInput
+ Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
+
+ uint32_t Output; /*!< Selects the output redirection of the comparator.
+ This parameter can be a value of @ref COMPEx_Output */
+
+ uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
+ This parameter can be a value of @ref COMP_OutputPolarity */
+
+ uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
+ This parameter can be a value of @ref COMPEx_Hysteresis
+ Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
+
+ uint32_t BlankingSrce; /*!< Selects the output blanking source of the comparator.
+ This parameter can be a value of @ref COMPEx_BlankingSrce
+ Note: Not available on STM32F373xB/C and STM32F378xx devices */
+
+ uint32_t Mode; /*!< Selects the operating consumption mode of the comparator
+ to adjust the speed/consumption.
+ This parameter can be a value of @ref COMPEx_Mode
+ Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
+
+ uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2, 4 or 6 if available).
+ This parameter can be a value of @ref COMPEx_WindowMode */
+
+ uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
+ This parameter can be a value of @ref COMP_TriggerMode */
+
+}COMP_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */
+ HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */
+ HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */
+ HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */
+ HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
+}HAL_COMP_StateTypeDef;
+
+/**
+ * @brief COMP Handle Structure definition
+ */
+typedef struct
+{
+ COMP_TypeDef *Instance; /*!< Register base address */
+ COMP_InitTypeDef Init; /*!< COMP required parameters */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
+}COMP_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_OutputPolarity COMP Output Polarity
+ * @{
+ */
+#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
+#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+ * @{
+ */
+/* When output polarity is not inverted, comparator output is low when
+ the non-inverting input is at a lower voltage than the inverting input*/
+#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
+/* When output polarity is not inverted, comparator output is high when
+ the non-inverting input is at a higher voltage than the inverting input */
+#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
+/**
+ * @}
+ */
+
+/** @defgroup COMP_TriggerMode COMP Trigger Mode
+ * @{
+ */
+#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING ((uint32_t)0x00000010) /*!< Event Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_FALLING ((uint32_t)0x00000020) /*!< Event Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING ((uint32_t)0x00000030) /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_State_Lock COMP State Lock
+ * @{
+ */
+#define COMP_STATE_BIT_LOCK ((uint32_t)0x00000010) /* Lock bit in COMP handle state */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+ * @{
+ */
+
+/** @brief Reset COMP handle state.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Include COMP HAL Extended module */
+#include "stm32f3xx_hal_comp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+ * @{
+ */
+/** @addtogroup COMP_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/* Callback in Interrupt mode */
+void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+ * @{
+ */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/* Peripheral State functions **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+ * @{
+ */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+ * @{
+ */
+
+/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
+ * @{
+ */
+
+#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
+ ((__POL__) == COMP_OUTPUTPOL_INVERTED))
+
+#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h
@@ -0,0 +1,2760 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_comp_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of COMP HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_COMP_EX_H
+#define __STM32F3xx_HAL_COMP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup COMPEx COMPEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMPEx_Exported_Constants COMP Extended Exported Constants
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F302xE/STM32F303xE/STM32F398xx/STM32F302xC/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
+ PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
+ PC0 for COMP7) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO2 COMP_CSR_COMPxINSEL /*!< IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
+ PB15 for COMP6) connected to comparator inverting input */
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
+/**
+ * @}
+ */
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
+ * @{
+ */
+#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2, PB2 for COMP4, PB15 for COMP6)
+ connected to comparator inverting input */
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+/**
+ * @}
+ */
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
+ * @{
+ */
+#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2, PB2 for COMP4, PB15 for COMP6)
+ connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC2_CH1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_CH1_OUT connected to comparator inverting input */
+
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0) /*!< 1/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1) /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0)) /*!< VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2) /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0)) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_IO1 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1)) /*!< IO1 (PA0 for COMP1, PA2 for COMP2) connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_DAC2_CH1 ((uint32_t)COMP_CSR_COMPxINSEL) /*!< DAC2_CH1_OUT connected to comparator inverting input */
+
+/* Aliases for compatibility */
+#define COMP_INVERTINGINPUT_DAC1 COMP_INVERTINGINPUT_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INVERTINGINPUT_DAC1_CH2
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+ PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
+ PA0 for COMP7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_IO2 COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
+ PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+/**
+ * @}
+ */
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
+ connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC ouput connected to comparator COMP2 non inverting input */
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
+ connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+/**
+ * @}
+ */
+#elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+ PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
+ PA0 for COMP7) connected to comparator non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+/**
+ * @}
+ */
+#else
+/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices)
+ * @{
+ */
+#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
+ connected to comparator non inverting input */
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
+ * - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
+#define COMP_OUTPUT_NONE ((uint32_t)0x0000002A) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2_BRK2 ((uint32_t)0x0000082A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
+#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000142A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001802) /*!< COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C02) /*!< COMP2 output connected to TIM1 Input Capture 1 */
+#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002002) /*!< COMP2 output connected to TIM2 Input Capture 4 */
+#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002402) /*!< COMP2 output connected to TIM2 OCREF Clear */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
+#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
+/**
+ * @}
+ */
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F303x8/STM32F334x8/STM32F328xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
+ * - YYYYYY : Applicable comparator instance number (bitmap format: 000010 for COMP2, 100000 for COMP6)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
+#define COMP_OUTPUT_NONE ((uint32_t)0x0000002A) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000082A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+/* Output Redirection common to COMP2 and COMP4 */
+#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C0A) /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001802) /*!< COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C02) /*!< COMP2 output connected to TIM1 Input Capture 1 */
+#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002002) /*!< COMP2 output connected to TIM2 Input Capture 4 */
+#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002402) /*!< COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002802) /*!< COMP2 output connected to TIM3 Input Capture 1 */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
+#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
+#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
+/**
+ * @}
+ */
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F302xC/STM32F302xE Product devices)
+ * Elements value convention on 16 LSB: 00XXXX0000YYYYYYb
+ * - YYYYYY : Applicable comparator instance number (bitmap format: 000001 for COMP1, 100000 for COMP6)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1, COMP2, COMP4, COMP6 */
+#define COMP_OUTPUT_NONE ((uint32_t)0x0000002B) /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2_BRK2 ((uint32_t)0x0000082B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
+#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000142B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+/* Output Redirection common to COMP1 and COMP2 */
+#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001803) /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */
+#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
+#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002403) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */
+/* Output Redirection common to COMP1,COMP2 and COMP4 */
+#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C0B) /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
+#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
+#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */
+#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
+#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */
+/**
+ * @}
+ */
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F303xC/STM32F358xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
+ * - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1...COMP7 */
+#define COMP_OUTPUT_NONE ((uint32_t)0x0000007F) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000047F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000087F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM8BKIN ((uint32_t)0x00000C7F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM8BKIN2 ((uint32_t)0x0000107F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x0000147F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
+/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001847) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2 and COMP3 */
+#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002407) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
+#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C1B) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
+/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_OUTPUT_TIM8OCREFCLR ((uint32_t)0x00001C78) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
+/* Output Redirection common to COMP1 and COMP2 */
+#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */
+#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
+#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */
+/* Output Redirection specific to COMP3 */
+#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x00001C04) /*!< COMP3 output connected to TIM4 Input Capture 1 */
+#define COMP_OUTPUT_TIM3IC2 ((uint32_t)0x00002004) /*!< COMP3 output connected to TIM3 Input Capture 2 */
+#define COMP_OUTPUT_TIM15IC1 ((uint32_t)0x00002804) /*!< COMP3 output connected to TIM15 Input Capture 1 */
+#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x00002C04) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
+#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
+#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */
+#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP5 */
+#define COMP_OUTPUT_TIM2IC1 ((uint32_t)0x00001810) /*!< COMP5 output connected to TIM2 Input Capture 1 */
+#define COMP_OUTPUT_TIM17IC1 ((uint32_t)0x00002010) /*!< COMP5 output connected to TIM17 Input Capture 1 */
+#define COMP_OUTPUT_TIM4IC3 ((uint32_t)0x00002410) /*!< COMP5 output connected to TIM4 Input Capture 3 */
+#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x00002810) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
+#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */
+/* Output Redirection specific to COMP7 */
+#define COMP_OUTPUT_TIM2IC3 ((uint32_t)0x00002040) /*!< COMP7 output connected to TIM2 Input Capture 3 */
+#define COMP_OUTPUT_TIM1IC2 ((uint32_t)0x00002440) /*!< COMP7 output connected to TIM1 Input Capture 2 */
+#define COMP_OUTPUT_TIM17OCREFCLR ((uint32_t)0x00002840) /*!< COMP7 output connected to TIM17 OCREF Clear */
+#define COMP_OUTPUT_TIM17BKIN ((uint32_t)0x00002C40) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
+/**
+ * @}
+ */
+#elif defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F303xE/STM32F398xx Product devices)
+ * Elements value convention on 16 LSB: 00XXXX000YYYYYYYb
+ * - YYYYYYY : Applicable comparator instance number (bitmap format: 0000001 for COMP1, 1000000 for COMP7)
+ * - XXXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1...COMP7 */
+#define COMP_OUTPUT_NONE ((uint32_t)0x0000007F) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000047F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000087F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM8BKIN ((uint32_t)0x00000C7F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM8BKIN2 ((uint32_t)0x0000107F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x0000147F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
+#define COMP_OUTPUT_TIM20BKIN ((uint32_t)0x0000307F) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM20BKIN2 ((uint32_t)0x0000347F) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 ((uint32_t)0x0000387F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2, TIM8 Break Input 2 and TIM20 Break Input 2 */
+/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001847) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2 and COMP3 */
+#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002407) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
+/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
+#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C1B) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
+/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_OUTPUT_TIM8OCREFCLR ((uint32_t)0x00001C78) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
+/* Output Redirection common to COMP1 and COMP2 */
+#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */
+#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
+#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM20OCREFCLR ((uint32_t)0x00003C04) /*!< COMP2 output connected to TIM20 OCREF Clear */
+/* Output Redirection specific to COMP3 */
+#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x00001C04) /*!< COMP3 output connected to TIM4 Input Capture 1 */
+#define COMP_OUTPUT_TIM3IC2 ((uint32_t)0x00002004) /*!< COMP3 output connected to TIM3 Input Capture 2 */
+#define COMP_OUTPUT_TIM15IC1 ((uint32_t)0x00002804) /*!< COMP3 output connected to TIM15 Input Capture 1 */
+#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x00002C04) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
+/* Output Redirection specific to COMP4 */
+#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
+#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
+#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */
+#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+/* Output Redirection specific to COMP5 */
+#define COMP_OUTPUT_TIM2IC1 ((uint32_t)0x00001810) /*!< COMP5 output connected to TIM2 Input Capture 1 */
+#define COMP_OUTPUT_TIM17IC1 ((uint32_t)0x00002010) /*!< COMP5 output connected to TIM17 Input Capture 1 */
+#define COMP_OUTPUT_TIM4IC3 ((uint32_t)0x00002410) /*!< COMP5 output connected to TIM4 Input Capture 3 */
+#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x00002810) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
+/* Output Redirection specific to COMP6 */
+#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
+#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */
+/* Output Redirection specific to COMP7 */
+#define COMP_OUTPUT_TIM2IC3 ((uint32_t)0x00002040) /*!< COMP7 output connected to TIM2 Input Capture 3 */
+#define COMP_OUTPUT_TIM1IC2 ((uint32_t)0x00002440) /*!< COMP7 output connected to TIM1 Input Capture 2 */
+#define COMP_OUTPUT_TIM17OCREFCLR ((uint32_t)0x00002840) /*!< COMP7 output connected to TIM17 OCREF Clear */
+#define COMP_OUTPUT_TIM17BKIN ((uint32_t)0x00002C40) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_Output COMP Extended Output (STM32F373xC/STM32F378xx Product devices)
+ * Elements value convention: 00000XXX000000YYb
+ * - YY : Applicable comparator instance number (bitmap format: 01 for COMP1, 10 for COMP2)
+ * - XXX : COMPxOUTSEL value
+ * @{
+ */
+/* Output Redirection values common to all comparators COMP1 and COMP2 */
+#define COMP_OUTPUT_NONE ((uint32_t)0x0003) /*!< COMP1 or COMP2 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x0403) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
+#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x0503) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
+/* Output Redirection specific to COMP1 */
+#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x0101) /*!< COMP1 output connected to TIM15 Break Input */
+#define COMP_OUTPUT_COMP1_TIM3IC1 ((uint32_t)0x0201) /*!< COMP1 output connected to TIM3 Input Capture 1 */
+#define COMP_OUTPUT_COMP1_TIM3OCREFCLR ((uint32_t)0x0301) /*!< COMP1 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM5IC4 ((uint32_t)0x0601) /*!< COMP1 output connected to TIM5 Input Capture 4 */
+#define COMP_OUTPUT_TIM5OCREFCLR ((uint32_t)0x0701) /*!< COMP1 output connected to TIM5 OCREF Clear */
+/* Output Redirection specific to COMP2 */
+#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x0102) /*!< COMP2 output connected to TIM16 Break Input */
+#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x0202) /*!< COMP2 output connected to TIM4 Input Capture 1 */
+#define COMP_OUTPUT_TIM4OCREFCLR ((uint32_t)0x0302) /*!< COMP2 output connected to TIM4 OCREF Clear */
+#define COMP_OUTPUT_COMP2_TIM3IC1 ((uint32_t)0x0602) /*!< COMP2 output connected to TIM3 Input Capture 1 */
+#define COMP_OUTPUT_COMP2_TIM3OCREFCLR ((uint32_t)0x0702) /*!< COMP2 output connected to TIM3 OCREF Clear */
+/**
+ * @}
+ */
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2,4,6)
+ is connected to the non inverting input of comparator X-1 */
+/**
+ * @}
+ */
+#elif defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2,4,6)
+ is connected to the non inverting input of comparator X-1 */
+/**
+ * @}
+ */
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN) /*!< Window mode enabled: non inverting input of comparator 2
+ is connected to the non inverting input of comparator 1 (PA1) */
+/**
+ * @}
+ */
+#else
+/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (Other Product devices)
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled (not available) */
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+/** @defgroup COMPEx_Mode COMP Extended Mode
+ * @{
+ */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Please refer to the electrical characteristics in the device datasheet for
+ the power consumption values */
+#define COMP_MODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */
+#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
+#define COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1 /*!< Low power mode */
+#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_Hysteresis COMP Extended Hysteresis
+ * @{
+ */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
+#define COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST /*!< Hysteresis level high */
+
+#else
+
+#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F301x8/STM32F302x8/STM32F303x8/STM32F334x8/STM32F318xx/STM32F328xx Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+/* Blanking source for COMP2 */
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP2 */
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP2 */
+#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM3 OC3 selected as blanking source for COMP2 */
+/* Blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
+/* Blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 */
+/**
+ * @}
+ */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) ||\
+ defined(STM32F302xC)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F302xE/STM32F302xC Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM3 OC3 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
+/* Blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP6 */
+#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 */
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F303xE/STM32F398xx/STM32F303xC/STM32F358xx Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1, COMP2, COMP3 and COMP7 */
+/* Blanking source common for COMP1 and COMP2 */
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for COMP1 and COMP2 */
+/* Blanking source common for COMP1, COMP2 and COMP5 */
+#define COMP_BLANKINGSRCE_TIM3OC3 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC3 selected as blanking source for COMP1, COMP2 and COMP5 */
+/* Blanking source common for COMP3 and COMP6 */
+#define COMP_BLANKINGSRCE_TIM2OC4 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM2 OC4 selected as blanking source for COMP3 and COMP6 */
+/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for COMP4, COMP5, COMP6 and COMP7 */
+/* Blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for COMP4 */
+#define COMP_BLANKINGSRCE_TIM15OC1 (COMP_CSR_COMPxBLANKING_0|COMP_CSR_COMPxBLANKING_1) /*!< TIM15 OC1 selected as blanking source for COMP4 */
+/* Blanking source common for COMP6 and COMP7 */
+#define COMP_BLANKINGSRCE_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for COMP6 and COMP7 */
+/**
+ * @}
+ */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup COMPEx_BlankingSrce COMP Extended Blanking Source (STM32F373xC/STM32F378xx Product devices)
+ * @{
+ */
+/* No blanking source can be selected for all comparators */
+#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/** @defgroup COMP_Flag COMP Flag
+ * @{
+ */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK /*!< Lock flag */
+#else
+#define COMP_FLAG_LOCK COMP_CSR_LOCK /*!< Lock flag */
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMPEx_Exported_Macros COMP Extended Exported Macros
+ * @{
+ */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_ENABLE(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
+ } while(0)
+
+/**
+ * @brief Disable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_DISABLE(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
+ } while(0)
+
+/**
+ * @brief Lock a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define __HAL_COMP_LOCK(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift); \
+ } while(0)
+
+/** @brief Check whether the specified COMP flag is set or not.
+ * @param __HANDLE__ COMP Handle.
+ * @param __FLAG__ flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref COMP_FLAG_LOCK lock flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance == COMP1) ? (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) \
+ (((__HANDLE__)->Instance->CSR & (uint32_t)((__FLAG__) << COMP_CSR_COMP2_SHIFT) == (__FLAG__))))
+
+#else
+
+/**
+ * @brief Enable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
+
+/**
+ * @brief Disable the specified comparator.
+ * @param __HANDLE__ COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxEN)
+
+/**
+ * @brief Lock a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_COMPxLOCK)
+
+/** @brief Check whether the specified COMP flag is set or not.
+ * @param __HANDLE__ COMP Handle.
+ * @param __FLAG__ flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref COMP_FLAG_LOCK lock flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Generate a software interrupt on the COMP1 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Check whether the COMP1 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Clear the COMP1 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @brief Enable the COMP2 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP2 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Generate a software interrupt on the COMP2 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Check whether the COMP2 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Clear the COMP2 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+/**
+ * @brief Enable the COMP3 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Enable the COMP3 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Enable the COMP3 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP3 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP3 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Generate a software interrupt on the COMP3 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Enable the COMP3 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Disable the COMP3 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Check whether the COMP3 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP3_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP3)
+
+/**
+ * @brief Clear the COMP3 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP3)
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+/**
+ * @brief Enable the COMP4 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Enable the COMP4 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Enable the COMP4 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP4 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP4 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Generate a software interrupt on the COMP4 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Enable the COMP4 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Disable the COMP4 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Check whether the COMP4 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP4_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP4)
+
+/**
+ * @brief Clear the COMP4 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP4)
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+/**
+ * @brief Enable the COMP5 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Enable the COMP5 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Enable the COMP5 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP5 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP5 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Generate a software interrupt on the COMP5 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Enable the COMP5 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Disable the COMP5 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Check whether the COMP5 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP5_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP5)
+
+/**
+ * @brief Clear the COMP5 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP5)
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+/**
+ * @brief Enable the COMP6 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Enable the COMP6 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Enable the COMP6 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP6 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP6 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Generate a software interrupt on the COMP6 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Enable the COMP6 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Disable the COMP6 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Check whether the COMP6 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP6_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP6)
+
+/**
+ * @brief Clear the COMP6 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP6)
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/**
+ * @brief Enable the COMP7 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Enable the COMP7 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Enable the COMP7 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP7 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP7 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Generate a software interrupt on the COMP7 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Enable the COMP7 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Disable the COMP7 EXTI line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Check whether the COMP7 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP7_EXTI_GET_FLAG() READ_BIT(EXTI->PR2, COMP_EXTI_LINE_COMP7)
+
+/**
+ * @brief Clear the COMP7 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, COMP_EXTI_LINE_COMP7)
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMPEx_Private_Constants COMP Extended Private Constants
+ * @{
+ */
+/** @defgroup COMPEx_ExtiLineEvent COMP Extended EXTI lines
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
+#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
+
+#define COMP_EXTI_LINE_REG2_MASK EXTI_IMR2_MR32 /*!< Mask for External interrupt line control in register xxx2 */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
+#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
+
+#define COMP_EXTI_LINE_REG2_MASK EXTI_IMR2_MR32 /*!< Mask for External interrupt line control in register xxx2 */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+#define COMP_EXTI_LINE_COMP3 EXTI_IMR_MR29 /*!< External interrupt line 29 connected to COMP3 */
+#define COMP_EXTI_LINE_COMP4 EXTI_IMR_MR30 /*!< External interrupt line 30 connected to COMP4 */
+#define COMP_EXTI_LINE_COMP5 EXTI_IMR_MR31 /*!< External interrupt line 31 connected to COMP5 */
+#define COMP_EXTI_LINE_COMP6 EXTI_IMR2_MR32 /*!< External interrupt line 32 connected to COMP6 */
+#define COMP_EXTI_LINE_COMP7 EXTI_IMR2_MR33 /*!< External interrupt line 33 connected to COMP7 */
+
+#define COMP_EXTI_LINE_REG2_MASK (EXTI_IMR2_MR33 | EXTI_IMR2_MR32) /*!< Mask for External interrupt line control in register xxx2 */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define COMP_EXTI_LINE_COMP1 EXTI_IMR_MR21 /*!< External interrupt line 21 connected to COMP1 */
+#define COMP_EXTI_LINE_COMP2 EXTI_IMR_MR22 /*!< External interrupt line 22 connected to COMP2 */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_Misc COMP Extended miscellaneous defines
+ * @{
+ */
+
+/* CSR masks redefinition for internal use */
+#define COMP_CSR_COMPxINSEL_MASK COMP_CSR_COMPxINSEL /*!< COMP_CSR_COMPxINSEL Mask */
+#define COMP_CSR_COMPxOUTSEL_MASK COMP_CSR_COMPxOUTSEL /*!< COMP_CSR_COMPxOUTSEL Mask */
+#define COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL /*!< COMP_CSR_COMPxPOL Mask */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/* CSR register reset value */
+#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+#define COMP_CSR_RESET_PARAMETERS_MASK ((uint32_t)0x00003FFF)
+#define COMP_CSR_UPDATE_PARAMETERS_MASK ((uint32_t)0x00003FFE)
+/* CSR COMP1/COMP2 shift */
+#define COMP_CSR_COMP1_SHIFT 0U
+#define COMP_CSR_COMP2_SHIFT 16U
+#else
+/* CSR register reset value */
+#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP2_CSR_COMP2INPDAC) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define COMP_CSR_COMPxNONINSEL_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxWNDWEN_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMPxNONINSEL | COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
+#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */
+#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
+#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_CSR_COMPxNONINSEL_MASK (COMP_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
+#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
+#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */
+#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */
+#define COMP_CSR_COMPxBLANKING_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMPEx_Private_Macros COMP Extended Private Macros
+ * @{
+ */
+/** @defgroup COMP_GET_EXTI_LINE COMP Extended Private macro to get the EXTI line associated with a comparator handle
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__: specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
+ ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
+ COMP_EXTI_LINE_COMP6)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__: specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
+ ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
+ COMP_EXTI_LINE_COMP6)
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__: specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ ((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
+ ((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 : \
+ ((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 : \
+ ((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 : \
+ ((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 : \
+ COMP_EXTI_LINE_COMP7)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Get the specified EXTI line for a comparator instance
+ * @param __INSTANCE__: specifies the COMP instance.
+ * @retval value of @ref COMPEx_ExtiLineEvent
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ COMP_EXTI_LINE_COMP2)
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_Private_Macros_Misc COMP Extended miscellaneous private macros
+ * @{
+ */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Init a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @note The common output selection is checked versus the COMP instance to set the right output configuration
+ * @retval None.
+ */
+
+#define COMP_INIT(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ uint32_t compoutput = (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ \
+ MODIFY_REG(COMP->CSR, \
+ (COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
+ COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \
+ COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift, \
+ ((__HANDLE__)->Init.InvertingInput | \
+ (__HANDLE__)->Init.NonInvertingInput | \
+ compoutput | \
+ (__HANDLE__)->Init.OutputPol | \
+ (__HANDLE__)->Init.Hysteresis | \
+ (__HANDLE__)->Init.Mode) << regshift); \
+ \
+ if((__HANDLE__)->Init.WindowMode != COMP_WINDOWMODE_DISABLE) \
+ { \
+ COMP->CSR |= COMP_CSR_WNDWEN; \
+ } \
+ } while(0)
+
+/**
+ * @brief DeInit a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define COMP_DEINIT(__HANDLE__) \
+ do { \
+ uint32_t regshift = COMP_CSR_COMP1_SHIFT; \
+ \
+ if((__HANDLE__)->Instance == COMP2) \
+ { \
+ regshift = COMP_CSR_COMP2_SHIFT; \
+ } \
+ MODIFY_REG(COMP->CSR, \
+ COMP_CSR_RESET_PARAMETERS_MASK << regshift, \
+ COMP_CSR_RESET_VALUE << regshift); \
+ } while(0)
+
+
+/**
+ * @brief Enable the Exti Line rising edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_ENABLE(__EXTILINE__) SET_BIT(EXTI->RTSR, (__EXTILINE__))
+
+/**
+ * @brief Disable the Exti Line rising edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->RTSR, (__EXTILINE__))
+
+/**
+ * @brief Enable the Exti Line falling edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) SET_BIT(EXTI->FTSR, (__EXTILINE__))
+
+/**
+ * @brief Disable the Exti Line falling edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) CLEAR_BIT(EXTI->FTSR, (__EXTILINE__))
+
+/**
+ * @brief Enable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_IT(__EXTILINE__) SET_BIT(EXTI->IMR, (__EXTILINE__))
+
+/**
+ * @brief Disable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_IT(__EXTILINE__) CLEAR_BIT(EXTI->IMR, (__EXTILINE__))
+
+/**
+ * @brief Enable the COMP Exti Line event generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) SET_BIT(EXTI->EMR, (__EXTILINE__))
+
+/**
+ * @brief Disable the COMP Exti Line event generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) CLEAR_BIT(EXTI->EMR, (__EXTILINE__))
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __FLAG__: specifies the COMP Exti sources to be checked.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval The state of __FLAG__ (SET or RESET).
+ */
+#define COMP_EXTI_GET_FLAG(__FLAG__) READ_BIT(EXTI->PR, (__FLAG__))
+
+/**
+ * @brief Clear the COMP Exti flags.
+ * @param __FLAG__: specifies the COMP Exti sources to be cleared.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_CLEAR_FLAG(__FLAG__) WRITE_REG(EXTI->PR, (__FLAG__))
+
+#else
+
+/**
+ * @brief Init a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define COMP_INIT(__HANDLE__) \
+ do { \
+ __IO uint32_t csrreg = 0; \
+ \
+ csrreg = READ_REG((__HANDLE__)->Instance->CSR); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxINSEL_MASK, (__HANDLE__)->Init.InvertingInput); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxNONINSEL_MASK, (__HANDLE__)->Init.NonInvertingInput); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxBLANKING_MASK, (__HANDLE__)->Init.BlankingSrce); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxOUTSEL_MASK, (__HANDLE__)->Init.Output & COMP_CSR_COMPxOUTSEL_MASK); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxPOL_MASK, (__HANDLE__)->Init.OutputPol); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxHYST_MASK, (__HANDLE__)->Init.Hysteresis); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxMODE_MASK, (__HANDLE__)->Init.Mode); \
+ MODIFY_REG(csrreg, COMP_CSR_COMPxWNDWEN_MASK, (__HANDLE__)->Init.WindowMode); \
+ WRITE_REG((__HANDLE__)->Instance->CSR, csrreg); \
+ } while(0)
+
+/**
+ * @brief DeInit a comparator instance
+ * @param __HANDLE__ COMP handle
+ * @retval None.
+ */
+#define COMP_DEINIT(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->CSR, COMP_CSR_RESET_VALUE)
+
+/**
+ * @brief Enable the Exti Line rising edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->RTSR2, (__EXTILINE__)) : SET_BIT(EXTI->RTSR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the Exti Line rising edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_RISING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->RTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->RTSR, (__EXTILINE__)))
+
+/**
+ * @brief Enable the Exti Line falling edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_ENABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->FTSR2, (__EXTILINE__)) : SET_BIT(EXTI->FTSR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the Exti Line falling edge trigger.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_FALLING_DISABLE(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->FTSR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->FTSR, (__EXTILINE__)))
+
+/**
+ * @brief Enable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->IMR2, (__EXTILINE__)) : SET_BIT(EXTI->IMR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the COMP Exti Line interrupt generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_IT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->IMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->IMR, (__EXTILINE__)))
+
+/**
+ * @brief Enable the COMP Exti Line event generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_ENABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? SET_BIT(EXTI->EMR2, (__EXTILINE__)) : SET_BIT(EXTI->EMR, (__EXTILINE__)))
+
+/**
+ * @brief Disable the COMP Exti Line event generation.
+ * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_DISABLE_EVENT(__EXTILINE__) ((((__EXTILINE__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? CLEAR_BIT(EXTI->EMR2, (__EXTILINE__)) : CLEAR_BIT(EXTI->EMR, (__EXTILINE__)))
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __FLAG__: specifies the COMP Exti sources to be checked.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval The state of __FLAG__ (SET or RESET).
+ */
+#define COMP_EXTI_GET_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? READ_BIT(EXTI->PR2, (__FLAG__)) : READ_BIT(EXTI->PR, (__FLAG__)))
+
+/**
+ * @brief Clear the COMP Exti flags.
+ * @param __FLAG__: specifies the COMP Exti sources to be cleared.
+ * This parameter can be a value of @ref COMPEx_ExtiLineEvent
+ * @retval None.
+ */
+#define COMP_EXTI_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & COMP_EXTI_LINE_REG2_MASK) != RESET) ? WRITE_REG(EXTI->PR2, (__FLAG__)) : WRITE_REG(EXTI->PR, (__FLAG__)))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup COMPEx_IS_COMP_Definitions COMP Extended Private macros to check input parameters
+ * @{
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F318xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP2) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
+
+#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6/8, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ ((((INSTANCE) == COMP2) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
+
+/*!< Non inverting input not available */
+#define IS_COMP_NONINVERTINGINPUT(INPUT) ((INPUT) == (INPUT)) /*!< Multiple selection not available: check always true */
+
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) ((INPUT) == (INPUT)) /*!< Multiple selection not available: check always true */
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) ((WINDOWMODE) == (WINDOWMODE)) /*!< Not available: check always true */
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6/8, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ ((((INSTANCE) == COMP2) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO2))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F302xB/xC, STM32F303xB/xC, STM32F358xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ ((((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_IO2))))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
+ ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
+ ((MODE) == COMP_MODE_MEDIUMSPEED) || \
+ ((MODE) == COMP_MODE_LOWPOWER) || \
+ ((MODE) == COMP_MODE_ULTRALOWPOWER))
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
+
+#if defined(STM32F302xC)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F302xC */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F303xC || STM32F358xx */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO2))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F302xE/STM32F303xE/STM32F398xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
+ ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
+
+#define IS_COMP_MODE(MODE) ((MODE) == (MODE)) /*!< Not available: check always true */
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) ((HYSTERESIS) == (HYSTERESIS)) /*!< Not available: check always true */
+
+#if defined(STM32F302xE)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_BRK2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F302xB/STM32F302xC/STM32F302xE devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17IC1))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP6_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16OCREFCLR))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC2) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC3) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM17OCREFCLR))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) (((SOURCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC3) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
+ ((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
+
+/* STM32F303xE/STM32F398xx/STM32F303xB/STM32F303xC/STM32F358xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ (((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC3) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP3) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4))) \
+ || \
+ (((INSTANCE) == COMP4) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC1))) \
+ || \
+ (((INSTANCE) == COMP5) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM3OC3))) \
+ || \
+ (((INSTANCE) == COMP6) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM2OC4) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))) \
+ || \
+ (((INSTANCE) == COMP7) && \
+ (((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) || \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
+
+#endif /* STM32F303xE || STM32F398xx */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1_CH2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC2_CH1))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+/* STM32F373xB/xC, STM32F378xx devices comparator instances non inverting source values */
+#define IS_COMP_NONINVERTINGINPUT_INSTANCE(INSTANCE, INPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))) \
+ || \
+ (((INPUT) == COMP_NONINVERTINGINPUT_IO1)))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
+ ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
+ ((MODE) == COMP_MODE_MEDIUMSPEED) || \
+ ((MODE) == COMP_MODE_LOWPOWER) || \
+ ((MODE) == COMP_MODE_ULTRALOWPOWER))
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))
+
+#define IS_COMP_OUTPUT_INSTANCE(INSTANCE, OUTPUT) \
+ ((((INSTANCE) == COMP1) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP1_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM5OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM15BKIN))) \
+ || \
+ (((INSTANCE) == COMP2) && \
+ (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_COMP2_TIM3OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM16BKIN))))
+
+#define IS_COMP_BLANKINGSRCE(SOURCE) ((SOURCE) == (SOURCE)) /*!< Not available: check always true */
+
+/* STM32F373xB/STM32F373xC/STM32F378xx devices comparator instances blanking source values */
+#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
+ ((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2)) && \
+ ((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_COMP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CONF_H
+#define __STM32F3xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_HRTIM_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SDADC_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)40000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief Time out for LSE start up value in ms.
+ */
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
+ * - External clock not generated on EVAL 373
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 1
+#define INSTRUCTION_CACHE_ENABLE 0
+#define DATA_CACHE_ENABLE 0
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/*#define USE_FULL_ASSERT 1*/
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f3xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f3xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f3xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f3xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f3xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f3xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f3xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f3xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f3xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f3xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f3xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f3xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f3xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f3xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f3xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SDADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_sdadc.h"
+#endif /* HAL_SDADC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f3xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f3xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f3xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32f3xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f3xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f3xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h
@@ -0,0 +1,472 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cortex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CORTEX_H
+#define __STM32F3xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+ * @{
+ */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported Macros -----------------------------------------------------------*/
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
+ * @{
+ */
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
+ ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || \
+ ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @brief CORTEX private functions
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU */
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h
@@ -0,0 +1,368 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of CRC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CRC_H
+#define __STM32F3xx_HAL_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRC CRC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+ * @{
+ */
+/**
+ * @brief CRC HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
+}HAL_CRC_StateTypeDef;
+
+
+/**
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+ In that case, there is no need to set GeneratingPolynomial field.
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+ If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
+ If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
+
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
+ e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+ No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
+
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+ Value can be either one of
+ @arg CRC_POLYLENGTH_32B (32-bit CRC),
+ @arg CRC_POLYLENGTH_16B (16-bit CRC),
+ @arg CRC_POLYLENGTH_8B (8-bit CRC),
+ @arg CRC_POLYLENGTH_7B (7-bit CRC). */
+
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+ is set to DEFAULT_INIT_VALUE_ENABLE. */
+
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+ Can be either one of the following values
+ @arg CRC_INPUTDATA_INVERSION_NONE, no input data inversion
+ @arg CRC_INPUTDATA_INVERSION_BYTE, byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+ @arg CRC_INPUTDATA_INVERSION_HALFWORD, halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+ @arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+
+ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+ Can be either
+ @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion,
+ @arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488 */
+}CRC_InitTypeDef;
+
+
+/**
+ * @brief CRC Handle Structure definition
+ */
+typedef struct
+{
+ CRC_TypeDef *Instance; /*!< Register base address */
+
+ CRC_InitTypeDef Init; /*!< CRC configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< CRC Locking object */
+
+ __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
+
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+ Can be either
+ @arg CRC_INPUTDATA_FORMAT_BYTES, input data is a stream of bytes (8-bit data)
+ @arg CRC_INPUTDATA_FORMAT_HALFWORDS, input data is a stream of half-words (16-bit data)
+ @arg CRC_INPUTDATA_FORMAT_WORDS, input data is a stream of words (32-bit data)
+
+ Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+ must occur if InputBufferFormat is not one of the three values listed above */
+}CRC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+ * @{
+ */
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
+ * @{
+ */
+#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF /*!< Initial CRC default value */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
+ * @{
+ */
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) /*!< Enable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) /*!< Disable default generating polynomial 0x04C11DB7 */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
+ * @{
+ */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) /*!< Enable initial CRC default value */
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) /*!< Disable initial CRC default value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
+ * @{
+ */
+#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */
+#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+ * @{
+ */
+#define HAL_CRC_LENGTH_32B 32 /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B 16 /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B 8 /*!< 8-bit long CRC */
+#define HAL_CRC_LENGTH_7B 7 /*!< 7-bit long CRC */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+ * @{
+ */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) /*!< Undefined input data format */
+#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) /*!< Input data in byte format */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) /*!< Input data in word format */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @brief Reset CRC handle state.
+ * @param __HANDLE__: CRC handle.
+ * @retval None
+ */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+ * @brief Reset CRC Data Register.
+ * @param __HANDLE__: CRC handle
+ * @retval None
+ */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+ * @brief Set CRC INIT non-default value
+* @param __HANDLE__: CRC handle
+ * @param __INIT__: 32-bit initial value
+ * @retval None
+ */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+ * @brief Store a 8-bit data in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @param __VALUE__: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+ * @brief Return the 8-bit data stored in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @retval 8-bit value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+ * @}
+ */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup CRC_Private_Macros CRC Private Macros
+ * @{
+ */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+ * @}
+ */
+
+/* Include CRC HAL Extended module */
+#include "stm32f3xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+ /** @defgroup HAL_CRC_Alias_Exported_Functions CRC aliases for Exported Functions
+ * @{
+ */
+/* Aliases for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc_ex.h
@@ -0,0 +1,175 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of CRC HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CRC_EX_H
+#define __STM32F3xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CRCEx CRCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup CRCEx_Input_Data_Inversion CRC Extended Input Data Inversion Modes
+ * @{
+ */
+#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) /*!< No input data inversion */
+#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */
+/**
+ * @}
+ */
+
+/** @defgroup CRCEx_Output_Data_Inversion CRC Extended Output Data Inversion Modes
+ * @{
+ */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) /*!< No output data inversion */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Set CRC output reversal
+ * @param __HANDLE__: CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+ * @brief Unset CRC output reversal
+ * @param __HANDLE__: CRC handle
+ * @retval None.
+ */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+ * @brief Set CRC non-default polynomial
+ * @param __HANDLE__: CRC handle
+ * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
+ * @retval None.
+ */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup CRCEx_Private_Macros CRCEx Private Macros
+ * @{
+ */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration functions.
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac.h
@@ -0,0 +1,452 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of DAC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DAC_H
+#define __STM32F3xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+
+}HAL_DAC_StateTypeDef;
+
+/**
+ * @brief DAC Configuration regular Channel structure definition
+ */
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DACEx_trigger_selection */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer
+ For a given DAC channel, is this paramater applies then DAC_OutputSwitch
+ does not apply */
+
+ uint32_t DAC_OutputSwitch; /*!< Specifies whether the DAC channel output switch is enabled or disabled.
+ This parameter can be a value of @ref DAC_OutputSwitch
+ For a given DAC channel, is this paramater applies then DAC_OutputBuffer
+ does not apply */
+
+}DAC_ChannelConfTypeDef;
+
+/**
+ * @brief DAC handle Structure definition
+ */
+typedef struct __DAC_HandleTypeDef
+{
+ DAC_TypeDef *Instance; /*!< Register base address */
+
+ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
+
+ HAL_LockTypeDef Lock; /*!< DAC locking object */
+
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
+ __IO uint32_t ErrorCode; /*!< DAC Error code */
+
+}DAC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+ * @{
+ */
+#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
+ * @{
+ */
+#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+ * @{
+ */
+#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_switch DAC output switch
+ * @{
+ */
+#define DAC_OUTPUTSWITCH_DISABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement DAC data alignement
+ * @{
+ */
+#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+ * @{
+ */
+#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_interrupts_definition DAC interrupts definition
+ * @{
+ */
+#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __DAC_Channel__: specifies the DAC channel
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __DAC_Channel__: specifies the DAC channel.
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval None
+ */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief Check whether the specified DAC interrupt source is enabled or not
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the DAC flag to get.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+ * @retval None
+ */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the DAC's flag
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __FLAG__: specifies the DAC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+ * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_OUTPUT_SWITCH_STATE(STATE) (((STATE) == DAC_OUTPUTSWITCH_DISABLE) || \
+ ((STATE) == DAC_OUTPUTSWITCH_ENABLE))
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+
+
+/**
+ * @}
+ */
+
+
+/* Include DAC HAL Extended module */
+#include "stm32f3xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h
@@ -0,0 +1,361 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of DAC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DAC_EX_H
+#define __STM32F3xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DACEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+ * @{
+ */
+
+/** @defgroup DACEx_trigger_selection DACEx trigger selection
+ * @{
+ */
+
+#if defined(STM32F301x8) || defined(STM32F318xx)
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F302x8)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F302x8 */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
+#define DAC_TRIGGER_T8_TRGO DAC_TRIGGER_T3_TRGO /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+
+#if defined(STM32F303x8) || defined(STM32F328xx)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F303x8 || STM32F328xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
+#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F334x8)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
+
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
+ Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
+#define DAC_TRIGGER_HRTIM1_DACTRG1 DAC_TRIGGER_T15_TRGO /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
+
+#define DAC_TRIGGER_HRTIM1_DACTRG2 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
+ Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
+#define DAC_TRIGGER_HRTIM1_DACTRG3 DAC_TRIGGER_HRTIM1_DACTRG2 /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
+
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F334x8 */
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_Channel_selection DACEx Channel selection
+ * @{
+ */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+ * @{
+ */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_HAL_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h
@@ -0,0 +1,180 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_def.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DEF
+#define __STM32F3xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00,
+ HAL_ERROR = 0x01,
+ HAL_BUSY = 0x02,
+ HAL_TIMEOUT = 0x03
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00,
+ HAL_LOCKED = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#define HAL_MAX_DELAY 0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
+ (__DMA_HANDLE_).Parent = (__HANDLE__); \
+ } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__: specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+ #error " USE_RTOS should be 0 in the current HAL release "
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+ #define __ALIGN_END __attribute__ ((aligned (4)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+ #define __ALIGN_BEGIN __align(4)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F3xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h
@@ -0,0 +1,454 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dma.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DMA_H
+#define __STM32F3xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+ * @brief DMA Configuration enumeration values definition
+ */
+typedef enum
+{
+ DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
+ DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
+
+} DMA_ControlTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
+ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+}HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Error Code structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+} DMA_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @{
+ */
+ #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+ #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
+ #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Enable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__: DMA handle
+ * @retval None.
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Enables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+ * @brief Disables the specified DMA Channel interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
+
+/**
+ * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @retval The state of DMA_IT (SET or RESET).
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extended module */
+#include "stm32f3xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA private macros
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h
@@ -0,0 +1,259 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_DMA_EX_H
+#define __STM32F3xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
+ * @{
+ */
+/* Interrupt & Flag management */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
+ (DMA1->ISR & (__FLAG__)))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
+ (DMA1->IFCR = (__FLAG__)))
+
+/**
+ * @}
+ */
+
+#else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */
+/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
+ * @{
+ */
+
+/**
+ * @brief Returns the current DMA Channel transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ DMA_FLAG_TC7)
+
+/**
+ * @brief Returns the current DMA Channel half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ DMA_FLAG_HT7)
+
+/**
+ * @brief Returns the current DMA Channel transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ DMA_FLAG_TE7)
+
+/**
+ * @brief Get the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+ * @brief Clears the DMA Channel pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCx: Transfer complete flag
+ * @arg DMA_FLAG_HTx: Half transfer complete flag
+ * @arg DMA_FLAG_TEx: Transfer error flag
+ * Where x can be 1_7 to select the DMA Channel flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* __STM32F3xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h
@@ -0,0 +1,401 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of Flash HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_FLASH_H
+#define __STM32F3xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
+ ((__LATENCY__) == FLASH_LATENCY_1) || \
+ ((__LATENCY__) == FLASH_LATENCY_2))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief FLASH Procedure structure definition
+ */
+typedef enum
+{
+ FLASH_PROC_NONE = 0,
+ FLASH_PROC_PAGEERASE = 1,
+ FLASH_PROC_MASSERASE = 2,
+ FLASH_PROC_PROGRAMHALFWORD = 3,
+ FLASH_PROC_PROGRAMWORD = 4,
+ FLASH_PROC_PROGRAMDOUBLEWORD = 5
+} FLASH_ProcedureTypeDef;
+
+/**
+ * @brief FLASH handle Structure definition
+ */
+typedef struct
+{
+ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
+
+ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
+
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */
+
+ __IO uint32_t ErrorCode; /*!< FLASH error code
+ This parameter can be a value of @ref FLASH_Error_Codes */
+} FLASH_ProcessTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+ * @{
+ */
+
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */
+#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01) /*!< Programming error */
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+ * @{
+ */
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!ACR |= FLASH_ACR_HLFCYA)
+
+/**
+ * @brief Disable the FLASH half cycle access.
+ * @retval None
+ */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_EM_Latency FLASH Latency
+ * @brief macros to handle FLASH Latency
+ * @{
+ */
+
+/**
+ * @brief Set the FLASH Latency.
+ * @param __LATENCY__ FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
+ * @retval None
+ */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
+ * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
+ * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Prefetch FLASH Prefetch
+ * @brief macros to handle FLASH Prefetch buffer
+ * @{
+ */
+/**
+ * @brief Enable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+ * @brief Disable the FLASH prefetch buffer.
+ * @retval None
+ */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts
+ * @brief macros to handle FLASH interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ * @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FLASH interrupt.
+ * @param __INTERRUPT__ FLASH interrupt
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+ * @arg @ref FLASH_IT_ERR Error Interrupt
+ * @retval none
+ */
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
+
+/**
+ * @brief Get the specified FLASH flag status.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref FLASH_FLAG_BSY FLASH Busy flag
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
+ * @retval The new state of __FLAG__ (SET or RESET).
+ */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified FLASH flag.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
+ * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
+ * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
+ * @retval none
+ */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include FLASH HAL Extended module */
+#include "stm32f3xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler function */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+void FLASH_PageErase(uint32_t PageAddress);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h
@@ -0,0 +1,500 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of Flash HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_FLASH_EX_H
+#define __STM32F3xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FLASHEx
+ * @{
+ */
+
+/** @addtogroup FLASHEx_Private_Constants
+ * @{
+ */
+
+#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7CC)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Macros
+ * @{
+ */
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
+ ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+ ((LEVEL) == OB_RDP_LEVEL_2))*/
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+
+#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
+#define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
+ ((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
+#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
+ ((ADDRESS) <= 0x0803FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
+ ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFF))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
+ ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
+ ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF))))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF)))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+ This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
+
+ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+ This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Options bytes program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_OB_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
+ This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
+ This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
+ @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
+ @ref FLASHEx_OB_RAM_Parity_Check_Enable.
+ @if STM32F373xC
+ And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
+ @endif
+ @if STM32F378xx
+ And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
+ @endif
+ */
+
+ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
+ This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+
+ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+} FLASH_OBProgramInitTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+ * @{
+ */
+
+/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
+ * @{
+ */
+#define FLASH_PAGE_SIZE 0x800
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_GPIO_H
+#define __STM32F3xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
+ This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+/** @defgroup GPIO_pins GPIO pins
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode GPIO mode
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed GPIO speed
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 2 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000003) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
+/**
+ * @}
+ */
+
+ /** @defgroup GPIO_pull GPIO pull
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
+#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__: specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line pending flags.
+ * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Check whether the specified EXTI line is asserted or not.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
+
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
+ ((__MODE__) == GPIO_MODE_AF_PP) ||\
+ ((__MODE__) == GPIO_MODE_AF_OD) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_IT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
+ ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH))
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
+ ((__PULL__) == GPIO_PULLUP) || \
+ ((__PULL__) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extended module */
+#include "stm32f3xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_GPIO_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h
@@ -0,0 +1,1540 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of GPIO HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_GPIO_EX_H
+#define __STM32F3xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIOEx GPIOEx
+ * @brief GPIO Extended HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+ * @{
+ */
+
+#if defined (STM32F302xC)
+/*---------------------------------- STM32F302xC ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+
+#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F302xC */
+
+#if defined (STM32F303xC)
+/*---------------------------------- STM32F303xC ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+
+#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F303xC */
+
+#if defined (STM32F303xE)
+/*---------------------------------- STM32F303xE ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F303xE */
+
+#if defined (STM32F302xE)
+/*---------------------------------- STM32F302xE ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F302xE */
+
+#if defined (STM32F398xx)
+/*---------------------------------- STM32F398xx ------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F398xx */
+
+#if defined (STM32F358xx)
+/*---------------------------------- STM32F358xx -------------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F358xx */
+
+#if defined (STM32F373xC)
+/*---------------------------------- STM32F373xC--------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
+#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
+
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F373xC */
+
+
+#if defined (STM32F378xx)
+/*---------------------------------------- STM32F378xx--------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
+#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F378xx */
+
+#if defined (STM32F303x8)
+/*---------------------------------- STM32F303x8--------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F303x8 */
+
+#if defined (STM32F334x8) || defined (STM32F328xx)
+/*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
+#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F334x8 || STM32F328xx */
+
+#if defined (STM32F301x8) || defined (STM32F318xx)
+/*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined (STM32F302x8)
+/*---------------------------------- STM32F302x8------------------------------------------*/
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+/*------------------------------------------------------------------------------------------*/
+#endif /* STM32F302x8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
+* @{
+ */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U : 5U)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U : 5U)
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U : 7U)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_hrtim.h
@@ -0,0 +1,3608 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_hrtim.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of HRTIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_HRTIM_H
+#define __STM32F3xx_HAL_HRTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F334x8)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HRTIM HRTIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
+ * @{
+ */
+/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
+ * @{
+ */
+#define MAX_HRTIM_TIMER 6
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief HRTIM Configuration Structure definition - Time base related parameters
+ */
+typedef struct
+{
+ uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
+ This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
+ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
+ The HRTIM instance can be configured to act as a slave (waiting for a trigger
+ to be synchronized) or a master (generating a synchronization signal) or both.
+ This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
+ uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
+ the HRTIM instance is configured as a slave).
+ This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
+ uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
+ (significant only when the HRTIM instance is configured as a master).
+ This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
+ uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
+ outputs (significant only when the HRTIM instance is configured as a master).
+ This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
+} HRTIM_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_HRTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_HRTIM_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_HRTIM_STATE_TIMEOUT = 0x06, /*!< Timeout state */
+ HAL_HRTIM_STATE_ERROR = 0x07, /*!< Error state */
+} HAL_HRTIM_StateTypeDef;
+
+/**
+ * @brief HRTIM Timer Structure definition
+ */
+typedef struct
+{
+ uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
+ When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
+ When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
+ uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
+ When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
+ When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
+ uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */
+ uint32_t DMARequests; /*!< DMA requests enabled for the timer. */
+ uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */
+ uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */
+ uint32_t DMASize; /*!< Size of the DMA transfer */
+} HRTIM_TimerParamTypeDef;
+
+/**
+ * @brief HRTIM Handle Structure definition
+ */
+typedef struct __HRTIM_HandleTypeDef
+{
+ HRTIM_TypeDef * Instance; /*!< Register base address */
+
+ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
+
+ HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
+
+ DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
+ DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
+} HRTIM_HandleTypeDef;
+
+/**
+ * @brief Simple output compare mode configuration definition
+ */
+typedef struct {
+ uint32_t Period; /*!< Specifies the timer period.
+ The period value must be above 3 periods of the fHRTIM clock.
+ Maximum value is = 0xFFDF */
+ uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
+ This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
+ uint32_t Mode; /*!< Specifies the counter operating mode.
+ This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
+} HRTIM_TimeBaseCfgTypeDef;
+
+/**
+ * @brief Simple output compare mode configuration definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
+ This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+} HRTIM_SimpleOCChannelCfgTypeDef;
+
+/**
+ * @brief Simple PWM output mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+} HRTIM_SimplePWMChannelCfgTypeDef;
+
+/**
+ * @brief Simple capture mode configuration definition
+ */
+typedef struct {
+ uint32_t Event; /*!< Specifies the external event triggering the capture.
+ This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
+ This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_External_Event_Filter */
+} HRTIM_SimpleCaptureChannelCfgTypeDef;
+
+/**
+ * @brief Simple One Pulse mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t OutputPolarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+ uint32_t Event; /*!< Specifies the external event triggering the pulse generation.
+ This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
+ This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_External_Event_Filter */
+} HRTIM_SimpleOnePulseChannelCfgTypeDef;
+
+/**
+ * @brief Timer configuration definition
+ */
+typedef struct {
+ uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies which interrupts requests must enabled for the timer.
+ This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
+ or @ref HRTIM_Timing_Unit_Interrupt_Enable */
+ uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies which DMA requests must be enabled for the timer.
+ This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
+ or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
+ uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies the address of the source address of the DMA transfer */
+ uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies the address of the destination address of the DMA transfer */
+ uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies the size of the DMA transfer */
+ uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not hald mode is enabled
+ This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
+ uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
+ This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
+ uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
+ This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
+ uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master.
+ Indicates whether or not the a DAC synchronization event is generated.
+ This parameter can be any value of @ref HRTIM_DAC_Synchronization */
+ uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not register preload is enabled.
+ This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
+ uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies how the update occurs with respect to a burst DMA transaction or
+ update enable inputs (Slave timers only).
+ This parameter can be any value of @ref HRTIM_Update_Gating */
+ uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies how the timer behaves during a burst mode operation.
+ This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
+ uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master.
+ Specifies whether or not registers update is triggered by the repetition event.
+ This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
+ uint32_t PushPull; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not the push-pull mode is enabled.
+ This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
+ uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E.
+ Specifies which fault channels are enabled for the timer.
+ This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
+ uint32_t FaultLock; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not fault enabling status is write protected.
+ This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
+ uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not dead-time insertion is enabled for the timer.
+ This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
+ uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E.
+ Specifies the delayed protection mode.
+ This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
+ uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E.
+ Specifies source(s) triggering the timer registers update.
+ This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
+ uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E.
+ Specifies source(s) triggering the timer counter reset.
+ This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
+ uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E.
+ Specifies whether or not registers update is triggered when the timer counter is reset.
+ This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
+} HRTIM_TimerCfgTypeDef;
+
+/**
+ * @brief Compare unit configuration definition
+ */
+typedef struct {
+ uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
+ The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
+ The maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
+ uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
+ This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
+ uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
+ CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
+} HRTIM_CompareCfgTypeDef;
+
+/**
+ * @brief Capture unit configuration definition
+ */
+typedef struct {
+ uint32_t Trigger; /*!< Specifies source(s) triggering the capture.
+ This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
+} HRTIM_CaptureCfgTypeDef;
+
+/**
+ * @brief Output configuration definition
+ */
+typedef struct {
+ uint32_t Polarity; /*!< Specifies the output polarity.
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
+ This parameter can be a combination of @ref HRTIM_Output_Set_Source */
+ uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
+ This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
+ uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
+ This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
+ uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
+ This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+ uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
+ This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
+ uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
+ This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
+ uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
+ This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
+} HRTIM_OutputCfgTypeDef;
+
+/**
+ * @brief External event filtering in timing units configuration definition
+ */
+typedef struct {
+ uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
+ This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
+ uint32_t Latch; /*!< Specifies whether or not the signal is latched.
+ This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
+} HRTIM_TimerEventFilteringCfgTypeDef;
+
+/**
+ * @brief Dead time feature configuration definition
+ */
+typedef struct {
+ uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler.
+ This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
+ uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge.
+ This parameter can be a number between 0x0 and 0x1FF */
+ uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge.
+ This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
+ uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
+ uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
+ uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge.
+ This parameter can be a number between 0x0 and 0x1FF */
+ uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge.
+ This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
+ uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
+ uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected.
+ This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
+} HRTIM_DeadTimeCfgTypeDef ;
+
+/**
+ * @brief Chopper mode configuration definition
+ */
+typedef struct {
+ uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
+ This parameter can be a value of @ref HRTIM_Chopper_Frequency */
+ uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
+ This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
+ uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
+ This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
+} HRTIM_ChopperModeCfgTypeDef;
+
+/**
+ * @brief External event channel configuration definition
+ */
+typedef struct {
+ uint32_t Source; /*!< Identifies the source of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sources */
+ uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
+ This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+ uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
+ uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_External_Event_Filter */
+ uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
+ This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
+} HRTIM_EventCfgTypeDef;
+
+/**
+ * @brief Fault channel configuration definition
+ */
+typedef struct {
+ uint32_t Source; /*!< Identifies the source of the fault.
+ This parameter can be a value of @ref HRTIM_Fault_Sources */
+ uint32_t Polarity; /*!< Specifies the polarity of the fault event.
+ This parameter can be a value of @ref HRTIM_Fault_Polarity */
+ uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
+ This parameter can be a value of @ref HRTIM_Fault_Filter */
+ uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected.
+ This parameter can be a value of @ref HRTIM_Fault_Lock */
+} HRTIM_FaultCfgTypeDef;
+
+/**
+ * @brief Burst mode configuration definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the burst mode operating mode.
+ This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
+ uint32_t ClockSource; /*!< Specifies the burst mode clock source.
+ This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
+ uint32_t Prescaler; /*!< Specifies the burst mode prescaler.
+ This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
+ uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
+ This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
+ uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation.
+ This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
+ uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
+ This parameter can be a number between 0x0 and 0xFFFF */
+ uint32_t Period; /*!< Specifies burst mode repetition period.
+ This parameter can be a number between 0x1 and 0xFFFF */
+} HRTIM_BurstModeCfgTypeDef;
+
+/**
+ * @brief ADC trigger configuration definition
+ */
+typedef struct {
+ uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
+ This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
+ uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
+ This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
+} HRTIM_ADCTriggerCfgTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
+ * @{
+ * @brief Constants defining the timer indexes
+ */
+#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index used to access timer A registers */
+#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index used to access timer B registers */
+#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index used to access timer C registers */
+#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index used to access timer D registers */
+#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index used to access timer E registers */
+#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index used to access master registers */
+#define HRTIM_TIMERINDEX_COMMON (uint32_t)0xFF /*!< Index used to access HRTIM common registers */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
+ * @{
+ * @brief Constants defining timer identifiers
+ */
+#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
+#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
+#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
+#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
+#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
+#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
+ * @{
+ * @brief Constants defining compare unit identifiers
+ */
+#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */
+#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */
+#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */
+#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
+ * @{
+ * @brief Constants defining capture unit identifiers
+ */
+#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */
+#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
+ * @{
+ * @brief Constants defining timer output identifiers
+ */
+#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Output 1 identifier */
+#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Output 2 identifier */
+#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Output 1 identifier */
+#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Output 2 identifier */
+#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Output 1 identifier */
+#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Output 2 identifier */
+#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Output 1 identifier */
+#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Output 2 identifier */
+#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Output 1 identifier */
+#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Output 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
+ * @{
+ * @brief Constants defining ADC triggers identifiers
+ */
+#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */
+#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 2 identifier */
+#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 3 identifier */
+#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 4 identifier */
+
+#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
+ (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
+ ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
+ * @{
+ * @brief Constants defining external event channel identifiers
+ */
+#define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */
+#define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */
+#define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */
+#define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */
+#define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */
+#define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */
+#define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */
+#define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */
+#define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */
+#define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */
+#define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
+ * @{
+ * @brief Constants defining fault channel identifiers
+ */
+#define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */
+#define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */
+#define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */
+#define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */
+#define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */
+/**
+ * @}
+ */
+
+
+ /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
+ * @{
+ * @brief Constants defining timer high-resolution clock prescaler ratio.
+ */
+#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
+ * @{
+ * @brief Constants defining timer counter operating mode.
+ */
+#define HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */
+#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */
+#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
+ * @{
+ * @brief Constants defining half mode enabling status.
+ */
+#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */
+#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
+ * @{
+ * @brief Constants defining the timer behavior following the synchronization event
+ */
+#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
+ * @{
+ * @brief Constants defining the timer behavior following the synchronization event
+ */
+#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
+ * @{
+ * @brief Constants defining on which output the DAC synchronization event is sent
+ */
+#define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */
+#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
+ * @{
+ * @brief Constants defining whether a write access into a preloadable
+ * register is done into the active or the preload register.
+ */
+#define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */
+#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
+ * @{
+ * @brief Constants defining how the update occurs relatively to the burst DMA
+ * transaction and the external update request on update enable inputs 1 to 3.
+ */
+#define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */
+#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
+#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
+#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
+#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
+#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
+#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
+#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
+#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
+ * @{
+ * @brief Constants defining how the timer behaves during a burst
+ mode operation.
+ */
+#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
+#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
+ * @{
+ * @brief Constants defining whether registers are updated when the timer
+ * repetition period is completed (either due to roll-over or
+ * reset events)
+ */
+#define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */
+#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
+/**
+ * @}
+ */
+
+
+/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
+ * @{
+ * @brief Constants defining whether or not the puhs-pull mode is enabled for
+ * a timer.
+ */
+#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */
+#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
+ * @{
+ * @brief Constants defining whether a faut channel is enabled for a timer
+ */
+#define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
+ * @{
+ * @brief Constants defining whether or not fault enabling bits are write
+ * protected for a timer
+ */
+#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */
+#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
+ * @{
+ * @brief Constants defining whether or not fault the dead time insertion
+ * feature is enabled for a timer
+ */
+#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */
+#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
+ * @{
+ * @brief Constants defining all possible delayed protection modes
+ * for a timer. Also definethe source and outputs on which the delayed
+ * protection schemes are applied
+ */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
+
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6 */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6 */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6 */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6 */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7 */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7 */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7 */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
+ * @{
+ * @brief Constants defining whether the registers update is done synchronously
+ * with any other timer or master update
+ */
+#define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */
+#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
+#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the reset
+ * of the timer counter
+ */
+#define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */
+#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
+#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */
+#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */
+#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */
+#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */
+#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */
+#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */
+#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */
+#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */
+#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */
+#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
+ * @{
+ * @brief Constants defining whether the register are updated upon Timerx
+ * counter reset or roll-over to 0 after reaching the period value
+ * in continuous mode
+ */
+#define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / roll-over disabled */
+#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
+ * @{
+ * @brief Constants defining whether the compare register is behaving in
+ * regular mode (compare match issued as soon as counter equal compare),
+ * or in auto-delayed mode
+ */
+#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
+ * @{
+ * @brief Constants defining the behavior of the output signal when the timer
+ operates in basic output compare mode
+ */
+#define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /*!< Output toggles when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /*!< Output forced to active level when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /*!< Output forced to inactive level when the timer counter reaches the compare value */
+
+#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
+ (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
+ ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
+ * @{
+ * @brief Constants defining the polarity of a timer output
+ */
+#define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< Output is acitve HIGH */
+#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
+ * @{
+ * @brief Constants defining the events that can be selected to configure the
+ * set crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */
+#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
+#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
+ * @{
+ * @brief Constants defining the events that can be selected to configure the
+ * set crossbar of a timer output
+ */
+#define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */
+#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
+ * @{
+ * @brief Constants defining whether or not the timer output transition to its
+ IDLE state when burst mode is entered
+ */
+#define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */
+#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
+ * @{
+ * @brief Constants defining the output level when output is in IDLE state
+ */
+#define HRTIM_OUTPUTIDLELEVEL_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */
+#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
+ * @{
+ * @brief Constants defining the output level when output is in FAULT state
+ */
+#define HRTIM_OUTPUTFAULTLEVEL_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
+#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
+#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
+#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
+ * @{
+ * @brief Constants defining whether or not chopper mode is enabled for a timer
+ output
+ */
+#define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< Output signal is not altered */
+#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
+ * @{
+ * @brief Constants defining the idle mode entry is delayed by forcing a
+ deadtime insertion before switching the outputs to their idle state
+ */
+#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */
+#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the
+ * capture of the timing unit counter
+ */
+#define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */
+#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
+ * @{
+ * @brief Constants defining the event filtering apploed to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
+ * @{
+ * @brief Constants defining whether or not the external event is
+ * memorized (latched) and generated as soon as the blanking period
+ * is completed or the window ends
+ */
+#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency
+ * (fHRTIM) and the deadtime generator clock (fDTG)
+ */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000) /*!< fDTG = fHRTIM * 8 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative
+ * (overlapping signal) on rising edge
+ */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime (rising sign and
+ * value) is write protected
+ */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime rising sign is write
+ * protected
+ */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative
+ * (overlapping signal) on falling edge
+ */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime (falling sign and
+ * value) is write protected
+ */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
+ * @{
+ * @brief Constants defining whether or not the deadtime falling sign is write
+ * protected
+ */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
+ * @{
+ * @brief Constants defining the frequency of the generated high frequency carrier
+ */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000) /*!< fCHPFRQ = fHRTIM / 16 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
+ /**
+ * @}
+ */
+
+/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
+ * @{
+ * @brief Constants defining the duty cycle of the generated high frequency carrier
+ * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
+ */
+#define HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000) /*!< Only 1st pulse is present */
+#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
+#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
+#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
+#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
+#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
+#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
+#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
+ * @{
+ * @brief Constants defining the pulse width of the first pulse of the generated
+ * high frequency carrier
+ */
+#define HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000) /*!< tSTPW = tHRTIM x 16 */
+#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
+#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
+#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
+#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
+#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
+#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
+#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
+#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
+#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
+#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
+#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
+#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
+#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
+#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
+#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
+ * @{
+ * @brief Constants defining the options for synchronizing multiple HRTIM
+ * instances, as a master unit (generating a synchronization signal)
+ * or as a slave (waiting for a trigger to be synchronized)
+ */
+#define HRTIM_SYNCOPTION_NONE (uint32_t)0x00000000 /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
+#define HRTIM_SYNCOPTION_MASTER (uint32_t)0x00000001 /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
+#define HRTIM_SYNCOPTION_SLAVE (uint32_t)0x00000002 /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
+ * @{
+ * @brief Constants defining defining the synchronization input source
+ */
+#define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
+#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
+#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
+ * @{
+ * @brief Constants defining the source and event to be sent on the
+ * synchronization outputs
+ */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
+ * @{
+ * @brief Constants defining the routing and conditioning of the synchronization output event
+ */
+#define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */
+#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
+#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
+ * @{
+ * @brief Constants defining available sources associated to external events
+ */
+#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
+ * @{
+ * @brief Constants defining the polarity of an external event
+ */
+#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */
+#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
+ * @{
+ * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
+ * of an external event
+ */
+#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */
+#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
+#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
+#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
+ * @{
+ * @brief Constants defining whether or not an external event is programmed in
+ fast mode
+ */
+#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */
+#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
+ * @{
+ * @brief Constants defining the frequency used to sample an external event 6
+ * input and the length (N) of the digital filter applied
+ */
+#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
+#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */
+#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */
+#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */
+#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */
+#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */
+#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */
+#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */
+#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */
+#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */
+#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */
+#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */
+#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */
+#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */
+#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */
+#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency
+ * fHRTIM) and the external event signal sampling clock (fEEVS)
+ * used by the digital filters
+ */
+#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */
+#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */
+#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */
+#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
+ * @{
+ * @brief Constants defining whether a faults is be triggered by any external
+ * or internal fault source
+ */
+#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */
+#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
+ * @{
+ * @brief Constants defining the polarity of a fault event
+ */
+#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */
+#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
+ * @{
+ * @ brief Constants defining the frequency used to sample the fault input and
+ * the length (N) of the digital filter applied
+ */
+#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
+#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
+#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
+#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
+#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
+#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
+#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
+#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
+#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
+#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
+#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
+#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
+#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
+#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
+#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
+#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
+ * @{
+ * @brief Constants defining whether or not the fault programming bits are
+ write protected
+ */
+#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */
+#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
+ * @{
+ * @brief Constants defining the division ratio between the timer clock
+ * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
+ * by the digital filters.
+ */
+#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */
+#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */
+#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */
+#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
+ * @{
+ * @brief Constants defining if the burst mode is entered once or if it is
+ * continuously operating
+ */
+#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */
+#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
+ * @{
+ * @brief Constants defining the clock source for the burst mode counter
+ */
+#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
+ * @{
+ * @brief Constants defining the prescaling ratio of the fHRTIM clock
+ * for the burst mode controller
+ */
+#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */
+#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
+#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
+#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
+#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
+#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
+#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
+#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
+#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
+#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
+#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
+#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
+#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
+#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
+#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
+#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
+ * @{
+ * @brief Constants defining whether or not burst mode registers preload
+ mechanism is enabled, i.e. a write access into a preloadable register
+ (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
+ */
+#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */
+#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
+ * @{
+ * @brief Constants defining the events that can be used tor trig the burst
+ * mode operation
+ */
+#define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000 /*!< No trigger */
+#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
+#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
+#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
+#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
+#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
+ * @{
+ * @brief constants defining the source triggering the update of the
+ HRTIM_ADCxR register (transfer from preload to active register).
+ */
+#define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
+ * @{
+ * @brief constants defining the events triggering ADC conversion.
+ * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
+ * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
+ */
+#define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
+
+#define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
+ * @{
+ * @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_SINGLE_CALIBRATION (uint32_t)0xFFFFFFFF /*!< Non periodic DLL calibration */
+#define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /*!< Periodic DLL calibration: T = 1048576 * tHRTIM (7.3 ms) */
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072 * tHRTIM (910 ms) */
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384 * tHRTIM (114 ms) */
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048 * tHRTIM (14 ms) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
+ * @{
+ * @brief Constants defining the registers that can be written during a burst
+ * DMA operation
+ */
+#define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
+ * @{
+ * @brief Constants used to enable or disable the burst mode controller
+ */
+#define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */
+#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
+ * @{
+ * @brief Constants used to enable or disable a fault channel
+ */
+#define HRTIM_FAULTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Fault channel is disabled */
+#define HRTIM_FAULTMODECTL_ENABLED (uint32_t)0x00000001 /*!< Fault channel is enabled */
+
+#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
+ (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
+ ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
+ * @{
+ * @brief Constants used to force timer registers update
+ */
+#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
+#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
+#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
+#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
+#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
+#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
+ * @{
+ * @brief Constants used to force timer counter reset
+ */
+#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
+#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
+#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
+#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
+#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
+#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_Level HRTIM Output Level
+ * @{
+ * @brief Constants defining the level of a timer output
+ */
+#define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /*!< Forces the output to its active state */
+#define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /*!< Forces the output to its inactive state */
+
+#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
+ (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
+ ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Output_State HRTIM Output State
+ * @{
+ * @brief Constants defining the state of a timer output
+ */
+#define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
+ inactive level as programmed in the crossbar unit */
+#define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
+ outputs are disabled by software or during a burst mode operation */
+#define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
+ FAULTx inputs */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
+ * @{
+ * @brief Constants defining the operating state of the burst mode controller
+ */
+#define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */
+#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
+ * @{
+ * @brief Constants defining on which output the signal is currently applied
+ * in push-pull mode
+ */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
+ * @{
+ * @brief Constants defining on which output the signal was applied, in
+ * push-pull mode balanced fault mode or delayed idle mode, when the
+ * protection was triggered
+ */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
+ * @{
+ */
+#define HRTIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
+#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
+#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
+#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
+#define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */
+#define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */
+#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */
+#define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */
+#define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
+ * @{
+ */
+#define HRTIM_MASTER_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
+#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */
+#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */
+#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */
+#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
+ * @{
+ */
+#define HRTIM_TIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
+#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
+#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
+#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
+#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */
+#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */
+#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */
+#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */
+#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */
+#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */
+#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */
+#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */
+#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */
+#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */
+#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
+ * @{
+ */
+#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
+#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
+#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
+#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
+#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
+#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
+#define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
+#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
+ * @{
+ */
+#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
+#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
+#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
+#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
+ * @{
+ */
+#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
+#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
+#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
+#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
+#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
+#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
+#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */
+#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
+ * @{
+ */
+#define HRTIM_MASTER_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */
+#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */
+#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
+#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
+ * @{
+ */
+#define HRTIM_TIM_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
+#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
+#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
+#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
+#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */
+#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */
+#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */
+#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */
+#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */
+#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */
+#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
+#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */
+#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
+#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */
+#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
+ * @{
+ */
+
+#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
+ (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
+
+#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
+ (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
+ ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
+
+#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFF) == 0x00000000)
+
+#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
+ ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
+
+#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
+ (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
+ ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
+
+#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00) == 0x00000000)
+
+#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
+ ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
+ (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
+ ((OUTPUT) == HRTIM_OUTPUT_TE2))))
+
+#define IS_HRTIM_EVENT(EVENT)\
+ (((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5) || \
+ ((EVENT) == HRTIM_EVENT_6) || \
+ ((EVENT) == HRTIM_EVENT_7) || \
+ ((EVENT) == HRTIM_EVENT_8) || \
+ ((EVENT) == HRTIM_EVENT_9) || \
+ ((EVENT) == HRTIM_EVENT_10))
+
+#define IS_HRTIM_FAULT(FAULT)\
+ (((FAULT) == HRTIM_FAULT_1) || \
+ ((FAULT) == HRTIM_FAULT_2) || \
+ ((FAULT) == HRTIM_FAULT_3) || \
+ ((FAULT) == HRTIM_FAULT_4) || \
+ ((FAULT) == HRTIM_FAULT_5))
+
+#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
+ (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
+ ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
+
+#define IS_HRTIM_MODE(MODE)\
+ (((MODE) == HRTIM_MODE_CONTINUOUS) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+#define IS_HRTIM_MODE_ONEPULSE(MODE)\
+ (((MODE) == HRTIM_MODE_SINGLESHOT) || \
+ ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+
+#define IS_HRTIM_HALFMODE(HALFMODE)\
+ (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
+ ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
+
+#define IS_HRTIM_SYNCSTART(SYNCSTART)\
+ (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
+ ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
+
+#define IS_HRTIM_SYNCRESET(SYNCRESET)\
+ (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
+ ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
+
+#define IS_HHRTIM_DACSYNC(DACSYNC)\
+ (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
+ ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
+
+#define IS_HRTIM_PRELOAD(PRELOAD)\
+ (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
+ ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
+
+#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
+ (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
+
+#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
+ (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
+ ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
+
+#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
+ (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
+ ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
+
+#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
+ (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
+ ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
+
+#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
+ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
+ ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
+
+#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
+
+
+#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
+ (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
+ ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
+ ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
+ ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
+ ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
+ || \
+ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
+ ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
+
+#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
+ ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
+ || \
+ (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
+ ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))
+
+#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
+
+#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
+
+
+#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
+ (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
+ ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
+
+#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
+
+/* Auto delayed mode is only available for compare units 2 and 4 */
+#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
+ ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
+ || \
+ (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
+ (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
+ ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
+
+#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
+ (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
+ ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
+
+#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
+ (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
+
+#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
+ (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
+
+#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
+ (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
+ ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
+
+#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
+ (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
+ ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
+
+#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
+ (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
+ ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
+ ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
+ ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
+
+#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
+ (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
+ ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
+
+#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
+ (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
+ ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
+
+#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
+ (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
+
+#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
+ (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
+ ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
+
+#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
+ (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
+ ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
+
+#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
+ (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
+ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
+ (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
+ ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
+ (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
+ ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
+ (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
+ ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
+ (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
+ ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
+ (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
+ ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
+ (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
+ ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
+
+#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
+ (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
+ ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
+
+#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
+ (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
+ ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
+
+#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
+ (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
+ ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
+
+#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
+ (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
+ ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
+ ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
+
+#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
+ (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
+ ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
+
+#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
+ (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
+ ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
+ ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
+
+#define IS_HRTIM_EVENTSRC(EVENTSRC)\
+ (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
+ ((EVENTSRC) == HRTIM_EVENTSRC_4))
+
+#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
+ ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
+ (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
+ ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
+ || \
+ (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
+
+#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
+ (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
+ ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
+
+#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
+ (((((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5)) && \
+ (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
+ ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
+ || \
+ (((EVENT) == HRTIM_EVENT_6) || \
+ ((EVENT) == HRTIM_EVENT_7) || \
+ ((EVENT) == HRTIM_EVENT_8) || \
+ ((EVENT) == HRTIM_EVENT_9) || \
+ ((EVENT) == HRTIM_EVENT_10)))
+
+
+#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
+ ((((EVENT) == HRTIM_EVENT_1) || \
+ ((EVENT) == HRTIM_EVENT_2) || \
+ ((EVENT) == HRTIM_EVENT_3) || \
+ ((EVENT) == HRTIM_EVENT_4) || \
+ ((EVENT) == HRTIM_EVENT_5)) \
+ || \
+ ((((EVENT) == HRTIM_EVENT_6) || \
+ ((EVENT) == HRTIM_EVENT_7) || \
+ ((EVENT) == HRTIM_EVENT_8) || \
+ ((EVENT) == HRTIM_EVENT_9) || \
+ ((EVENT) == HRTIM_EVENT_10)) && \
+ (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
+ ((FILTER) == HRTIM_EVENTFILTER_1) || \
+ ((FILTER) == HRTIM_EVENTFILTER_2) || \
+ ((FILTER) == HRTIM_EVENTFILTER_3) || \
+ ((FILTER) == HRTIM_EVENTFILTER_4) || \
+ ((FILTER) == HRTIM_EVENTFILTER_5) || \
+ ((FILTER) == HRTIM_EVENTFILTER_6) || \
+ ((FILTER) == HRTIM_EVENTFILTER_7) || \
+ ((FILTER) == HRTIM_EVENTFILTER_8) || \
+ ((FILTER) == HRTIM_EVENTFILTER_9) || \
+ ((FILTER) == HRTIM_EVENTFILTER_10) || \
+ ((FILTER) == HRTIM_EVENTFILTER_11) || \
+ ((FILTER) == HRTIM_EVENTFILTER_12) || \
+ ((FILTER) == HRTIM_EVENTFILTER_13) || \
+ ((FILTER) == HRTIM_EVENTFILTER_14) || \
+ ((FILTER) == HRTIM_EVENTFILTER_15))))
+
+#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
+ (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
+ ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
+#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
+ (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
+ ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
+
+#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
+ (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
+ ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
+
+#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
+ (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
+ ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
+
+#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
+ (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
+ ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
+
+#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
+ (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
+ ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
+
+#define IS_HRTIM_BURSTMODE(BURSTMODE)\
+ (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
+ ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
+
+#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
+ (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
+ ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
+
+#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
+ (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
+ ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
+
+#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
+ (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
+ ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
+
+#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
+ (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
+ ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
+
+#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
+ (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
+ ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
+
+#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
+ (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
+ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
+
+#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
+ ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
+ || \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
+
+#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
+ (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
+ ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
+
+#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
+
+#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
+
+#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0) == 0x00000000)
+
+
+#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80) == 0x00000000)
+
+
+#define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020) == 0x00000000)
+
+
+#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFF) == 0x00000000)
+
+#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFF) == 0x00000000)
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset HRTIM handle state
+ * @param __HANDLE__: HRTIM handle.
+ * @retval None
+ */
+#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
+
+/** @brief Enables or disables the timer counter(s)
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __TIMERS__: timers to enable/disable
+ * This parameter can be any combinations of the following values:
+ * @arg HRTIM_TIMERID_MASTER: Master timer identifier
+ * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
+ * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
+ * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
+ * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
+ * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
+ * @retval None
+ */
+#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
+
+/* The counter of a timing unit is disabled only if all the timer outputs */
+/* are disabled and no capture is configured */
+#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
+#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
+#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
+#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
+#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
+#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
+ do {\
+ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
+ {\
+ if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
+ }\
+ }\
+ } while(0)
+
+/** @brief Enables or disables the specified HRTIM common interrupts.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
+ * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
+ * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
+#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRTIM Master timer interrupts.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
+#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRTIM Timerx interrupts.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __TIMER__: specified the timing unit (Timer A to E)
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
+ * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
+ * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
+ * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
+#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRTIM_IT_FLT3: Fault 3 enable
+ * @arg HRTIM_IT_FLT4: Fault 4 enable
+ * @arg HRTIM_IT_FLT5: Fault 5 enable
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __TIMER__: specified the timing unit (Timer A to E)
+ * @param __INTERRUPT__: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
+ * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
+ * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
+ * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clears the specified HRTIM common pending flag.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
+ * @arg HRTIM_IT_FLT3: Fault 3 clear flag
+ * @arg HRTIM_IT_FLT4: Fault 4 clear flag
+ * @arg HRTIM_IT_FLT5: Fault 5 clear flag
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
+ * @retval None
+ */
+#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
+
+/** @brief Clears the specified HRTIM Master pending flag.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
+ * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
+ * @retval None
+ */
+#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
+
+/** @brief Clears the specified HRTIM Timerx pending flag.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __TIMER__: specified the timing unit (Timer A to E)
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
+ * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
+ * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
+ * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
+ * @retval None
+ */
+#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
+
+/* DMA HANDLING */
+/** @brief Enables or disables the specified HRTIM common interrupts.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
+ * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
+ * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
+ * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+ * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+ * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+ * @retval None
+ */
+#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
+#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
+
+/** @brief Enables or disables the specified HRTIM Master timer DMA requets.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __DMA__: specifies the DMA request to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
+ * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
+ * @retval None
+ */
+#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
+#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
+
+/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
+ * @param __HANDLE__: specifies the HRTIM Handle.
+ * @param __TIMER__: specified the timing unit (Timer A to E)
+ * @param __DMA__: specifies the DMA request to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
+ * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
+ * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
+ * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
+ * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
+ * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
+ * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
+ * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
+ * @retval None
+ */
+#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
+#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
+
+#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
+
+#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
+
+#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
+
+/** @brief Sets the HRTIM timer Counter Register value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __COUNTER__: specifies the Counter Register new value.
+ * @retval None
+ */
+#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
+
+/** @brief Gets the HRTIM timer Counter Register value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval HRTIM timer Counter Register value
+ */
+#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
+
+/** @brief Sets the HRTIM timer Period value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __PERIOD__: specifies the Period Register new value.
+ * @retval None
+ */
+#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
+
+/** @brief Gets the HRTIM timer Period Register value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval timer Period Register
+ */
+#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
+
+/** @brief Sets the HRTIM timer clock prescaler value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __PRESCALER__: specifies the clock prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
+ * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
+ * @retval None
+ */
+#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__PRESCALER__)) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR |= (__PRESCALER__)))
+
+/** @brief Gets the HRTIM timer clock prescaler value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval timer clock prescaler value
+ */
+#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
+
+/** @brief Sets the HRTIM timer Compare Register value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __COMPAREUNIT__: timer compare unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param __COMPARE__: specifies the Compare new value.
+ * @retval None
+ */
+#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
+ : \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
+
+/** @brief Gets the HRTIM timer Compare Register value on runtime
+ * @param __HANDLE__: HRTIM Handle.
+ * @param __TIMER__: HRTIM timer
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param __COMPAREUNIT__: timer compare unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @retval Compare value
+ */
+#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
+ (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
+ ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
+ : \
+ (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
+ ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
+ ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HRTIM_Exported_Functions
+* @{
+*/
+
+/** @addtogroup HRTIM_Exported_Functions_Group1
+* @{
+*/
+
+/* Initialization and Configuration functions ********************************/
+HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
+
+void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
+
+void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t CalibrationRate);
+
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t CalibrationRate);
+
+HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group2
+* @{
+*/
+
+/* Simple time base related functions *****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group3
+* @{
+*/
+/* Simple output compare related functions ************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group4
+* @{
+*/
+/* Simple PWM output related functions ****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group5
+* @{
+*/
+/* Simple capture related functions *******************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group6
+* @{
+*/
+/* Simple one pulse related functions *****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group7
+* @{
+*/
+HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Prescaler);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Fault,
+ HRTIM_FaultCfgTypeDef* pFaultCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Prescaler);
+
+void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Faults,
+ uint32_t Enable);
+
+HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group8
+* @{
+*/
+/* Waveform related functions *************************************************/
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel);
+
+HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate);
+
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t OutputsToStart);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t OutputsToStop);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Enable);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t BurstBufferAddress,
+ uint32_t BurstBufferLength);
+
+HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group9
+* @{
+*/
+/* HRTIM peripheral state functions */
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
+
+uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
+
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Exported_Functions_Group10
+* @{
+*/
+/* IRQ handler */
+void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+
+/* HRTIM events related callback functions */
+void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
+
+/* Timer events related callback functions */
+void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx);
+void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F334x8) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_HRTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h
@@ -0,0 +1,598 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of I2C HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2C_H
+#define __STM32F3xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+ * @{
+ */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+ * @brief I2C Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
+ This parameter calculated by referring to I2C initialization
+ section in Reference manual */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+ This parameter can be a value of @ref I2C_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref I2C_own_address2_masks */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+ * @brief HAL State structure definition
+ * @{
+ */
+
+typedef enum
+{
+ HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
+ HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
+ HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
+ HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
+ HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
+ HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
+ HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_I2C_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+ * @brief I2C Error Code definition
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+ * @brief I2C handle Structure definition
+ * @{
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
+
+}I2C_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+ * @{
+ */
+#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
+#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address2_masks I2C own address2 masks
+ * @{
+ */
+#define I2C_OA2_NOMASK ((uint8_t)0x00)
+#define I2C_OA2_MASK01 ((uint8_t)0x01)
+#define I2C_OA2_MASK02 ((uint8_t)0x02)
+#define I2C_OA2_MASK03 ((uint8_t)0x03)
+#define I2C_OA2_MASK04 ((uint8_t)0x04)
+#define I2C_OA2_MASK05 ((uint8_t)0x05)
+#define I2C_OA2_MASK06 ((uint8_t)0x06)
+#define I2C_OA2_MASK07 ((uint8_t)0x07)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+ * @{
+ */
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+ * @{
+ */
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+ * @{
+ */
+#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
+ * @{
+ */
+#define I2C_RELOAD_MODE I2C_CR2_RELOAD
+#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
+#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
+ * @{
+ */
+#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
+#define I2C_GENERATE_STOP I2C_CR2_STOP
+#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_GENERATE_START_WRITE I2C_CR2_START
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+ * @brief I2C Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define I2C_IT_ERRI I2C_CR1_ERRIE
+#define I2C_IT_TCI I2C_CR1_TCIE
+#define I2C_IT_STOPI I2C_CR1_STOPIE
+#define I2C_IT_NACKI I2C_CR1_NACKIE
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE
+#define I2C_IT_RXI I2C_CR1_RXIE
+#define I2C_IT_TXI I2C_CR1_TXIE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+ * @{
+ */
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_AF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+#define I2C_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2C handle state.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief Enable the specified I2C interrupt.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified I2C interrupt.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified I2C interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __INTERRUPT__: specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_IT_ERRI Errors interrupt enable
+ * @arg @ref I2C_IT_TCI Transfer complete interrupt enable
+ * @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+ * @arg @ref I2C_IT_NACKI NACK received interrupt enable
+ * @arg @ref I2C_IT_ADDRI Address match interrupt enable
+ * @arg @ref I2C_IT_RXI RX interrupt enable
+ * @arg @ref I2C_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified I2C flag is set or not.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty
+ * @arg @ref I2C_FLAG_TXIS Transmit interrupt status
+ * @arg @ref I2C_FLAG_RXNE Receive data register not empty
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag
+ * @arg @ref I2C_FLAG_TC Transfer complete (master mode)
+ * @arg @ref I2C_FLAG_TCR Transfer complete reload
+ * @arg @ref I2C_FLAG_BERR Bus error
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref I2C_FLAG_ALERT SMBus alert
+ * @arg @ref I2C_FLAG_BUSY Bus busy
+ * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref I2C_FLAG_TXE Transmit data register empty
+ * @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref I2C_FLAG_AF Acknowledge failure received flag
+ * @arg @ref I2C_FLAG_STOPF STOP detection flag
+ * @arg @ref I2C_FLAG_BERR Bus error
+ * @arg @ref I2C_FLAG_ARLO Arbitration lost
+ * @arg @ref I2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref I2C_FLAG_PECERR PEC error in reception
+ * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref I2C_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+
+/** @brief Enable the specified I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Disable the specified I2C peripheral.
+ * @param __HANDLE__ specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/**
+ * @}
+ */
+
+/* Include I2C HAL Extended module */
+#include "stm32f3xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions ****************************************************/
+ /******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+ /******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+ /******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral State and Errors functions *************************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+ * @{
+ */
+
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
+ ((MASK) == I2C_OA2_MASK01) || \
+ ((MASK) == I2C_OA2_MASK02) || \
+ ((MASK) == I2C_OA2_MASK03) || \
+ ((MASK) == I2C_OA2_MASK04) || \
+ ((MASK) == I2C_OA2_MASK05) || \
+ ((MASK) == I2C_OA2_MASK06) || \
+ ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
+ ((MODE) == I2C_AUTOEND_MODE) || \
+ ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
+ ((REQUEST) == I2C_GENERATE_START_READ) || \
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f3xx_hal_i2c.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h
@@ -0,0 +1,209 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of I2C HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2C_EX_H
+#define __STM32F3xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2CEx I2CEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+ * @{
+ */
+#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
+#define I2C_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast Mode Plus on PB6 */
+#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
+#define I2C_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast Mode Plus on PB7 */
+#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define I2C_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast Mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define I2C_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast Mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C1_FMP)
+#define I2C_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< Enable Fast Mode Plus on I2C1 pins */
+#endif /* SYSCFG_CFGR1_I2C1_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C2_FMP)
+#define I2C_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< Enable Fast Mode Plus on I2C2 pins */
+#endif /* SYSCFG_CFGR1_I2C2_FMP */
+
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
+#define I2C_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< Enable Fast Mode Plus on I2C3 pins */
+#endif /* SYSCFG_CFGR1_I2C3_FMP */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+ * @{
+ */
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+
+
+#if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
+#elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(SYSCFG_CFGR1_I2C1_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
+#endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_I2C_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s.h
@@ -0,0 +1,488 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of I2S HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2S_H
+#define __STM32F3xx_HAL_I2S_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2S_Exported_Types I2S Exported Types
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+
+ uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
+ This parameter can be a value of @ref I2S_Clock_Source */
+
+ uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
+ This parameter can be a value of @ref I2S_FullDuplex_Mode */
+
+}I2S_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
+}HAL_I2S_StateTypeDef;
+
+/**
+ * @brief I2S handle Structure definition
+ */
+typedef struct
+{
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
+
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received.
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_Error */
+
+}I2S_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+ * @{
+ */
+/** @defgroup I2S_Error I2S Error
+ * @{
+ */
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Source I2S Clock Source
+ * @{
+ */
+#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
+#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)
+
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+ ((CLOCK) == I2S_CLOCK_SYSCLK))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode I2S Mode
+ * @{
+ */
+#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
+#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
+#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
+#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
+
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
+ ((MODE) == I2S_MODE_SLAVE_RX) || \
+ ((MODE) == I2S_MODE_MASTER_TX)|| \
+ ((MODE) == I2S_MODE_MASTER_RX))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard I2S Standard
+ * @{
+ */
+#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
+#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
+#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
+#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
+
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
+ ((STANDARD) == I2S_STANDARD_MSB) || \
+ ((STANDARD) == I2S_STANDARD_LSB) || \
+ ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
+ ((STANDARD) == I2S_STANDARD_PCM_LONG))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format I2S Data Format
+ * @{
+ */
+#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
+#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
+#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
+
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
+ ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((FORMAT) == I2S_DATAFORMAT_24B) || \
+ ((FORMAT) == I2S_DATAFORMAT_32B))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+ * @{
+ */
+#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
+ * @{
+ */
+#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
+#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
+#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
+#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
+#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
+#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
+#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
+#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
+#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
+#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
+ ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
+ ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_FullDuplex_Mode I2S Full Duplex Mode
+ * @{
+ */
+#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
+#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
+
+#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
+ ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+ * @{
+ */
+#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
+
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
+ ((CPOL) == I2S_CPOL_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
+ * @{
+ */
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Flag_definition I2S Flag definition
+ * @{
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
+
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
+
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__: I2S handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
+
+/** @brief Enable or disable the specified I2S interrupts.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
+
+/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2S flag is set or not.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2S OVR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ }while(0)
+/** @brief Clears the I2S UDR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+ __IO uint32_t tmpreg;\
+ tmpreg = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg); \
+ }while(0)
+/**
+ * @}
+ */
+
+/* Include I2S HAL Extended module */
+#include "stm32f3xx_hal_i2s_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_I2S_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2s_ex.h
@@ -0,0 +1,225 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of I2S HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_I2S_EX_H
+#define __STM32F3xx_HAL_I2S_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup I2SEx I2SEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
+
+/** @brief Enable or disable the specified I2SExt peripheral.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
+#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+
+/** @brief Enable or disable the specified I2SExt interrupts.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
+#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
+ * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks whether the specified I2SExt flag is set or not.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clears the I2SExt OVR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
+ (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0)
+/** @brief Clears the I2SExt UDR pending flag.
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+ /**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
+ * @{
+ */
+
+/* Extended features functions ************************************************/
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S I2S
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
+void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral Control and State functions ************************************/
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_I2S_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda.h
@@ -0,0 +1,761 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_irda.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file contains all the functions prototypes for the IRDA
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_IRDA_H
+#define __STM32F3xx_HAL_IRDA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IRDA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Types IRDA Exported Types
+ * @{
+ */
+
+/**
+ * @brief IRDA Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref IRDAEx_Word_Length */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref IRDA_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref IRDA_Transfer_Mode */
+
+ uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
+ to achieve low-power frequency.
+ @note Prescaler value 0 is forbidden */
+
+ uint16_t PowerMode; /*!< Specifies the IRDA power mode.
+ This parameter can be a value of @ref IRDA_Low_Power */
+}IRDA_InitTypeDef;
+
+/**
+ * @brief HAL IRDA State structures definition
+ */
+typedef enum
+{
+ HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
+}HAL_IRDA_StateTypeDef;
+
+/**
+ * @brief IRDA clock sources definition
+ */
+typedef enum
+{
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
+}IRDA_ClockSourceTypeDef;
+
+/**
+ * @brief IRDA handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
+
+ uint16_t Mask; /*!< USART RX RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
+
+ __IO uint32_t ErrorCode; /*!< IRDA Error code
+ This parameter can be a value of @ref IRDA_Error */
+
+}IRDA_HandleTypeDef;
+
+/**
+ * @brief IRDA Configuration enumeration values definition
+ */
+typedef enum
+{
+ IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */
+ IRDA_PARITY = 0x01, /*!< IRDA frame parity */
+ IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */
+ IRDA_MODE = 0x03, /*!< IRDA communication mode */
+ IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */
+ IRDA_POWERMODE = 0x05 /*!< IRDA power mode */
+}IRDA_ControlTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
+ * @{
+ */
+
+/** @defgroup IRDA_Error IRDA Error
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Parity IRDA Parity
+ * @{
+ */
+#define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+ * @{
+ */
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
+ * @{
+ */
+#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
+/**
+ * @}
+ */
+
+ /** @defgroup IRDA_State IRDA State
+ * @{
+ */
+#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */
+#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
+/**
+ * @}
+ */
+
+ /** @defgroup IRDA_Mode IRDA Mode
+ * @{
+ */
+#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
+ * @{
+ */
+#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
+ * @{
+ */
+#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+ * @{
+ */
+#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Flags IRDA Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */
+#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */
+#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */
+#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */
+#define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */
+#define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */
+#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */
+#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */
+#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */
+#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Noise error */
+#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */
+#define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */
+#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */
+
+/** Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ */
+#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */
+
+/** Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ */
+#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */
+#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
+ * @{
+ */
+#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
+ * @{
+ */
+#define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
+ * @{
+ */
+
+/** @brief Reset IRDA handle state.
+ * @param __HANDLE__: IRDA handle.
+ * @retval None
+ */
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+
+/** @brief Flush the IRDA Data registers.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+
+
+/** @brief Clear the specified IRDA pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg IRDA_CLEAR_PEF
+ * @arg IRDA_CLEAR_FEF
+ * @arg IRDA_CLEAR_NEF
+ * @arg IRDA_CLEAR_OREF
+ * @arg IRDA_CLEAR_TCF
+ * @arg IRDA_CLEAR_IDLEF
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief Check whether the specified IRDA flag is set or not.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
+ * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
+ * @arg IRDA_FLAG_BUSY: Busy flag
+ * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
+ * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
+ * @arg IRDA_FLAG_TXE: Transmit data register empty flag
+ * @arg IRDA_FLAG_TC: Transmission Complete flag
+ * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
+ * @arg IRDA_FLAG_IDLE: Idle Line detection flag
+ * @arg IRDA_FLAG_ORE: OverRun Error flag
+ * @arg IRDA_FLAG_NE: Noise Error flag
+ * @arg IRDA_FLAG_FE: Framing Error flag
+ * @arg IRDA_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Enable the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+/** @brief Disable the specified IRDA interrupt.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+
+
+/** @brief Check whether the specified IRDA interrupt has occurred or not.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __IT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_ORE: OverRun Error interrupt
+ * @arg IRDA_IT_NE: Noise Error interrupt
+ * @arg IRDA_IT_FE: Framing Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
+
+/** @brief Check whether the specified IRDA interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __IT__: specifies the IRDA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
+ * @arg IRDA_IT_TC: Transmission complete interrupt
+ * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+ * @arg IRDA_IT_IDLE: Idle line detection interrupt
+ * @arg IRDA_IT_ORE: OverRun Error interrupt
+ * @arg IRDA_IT_NE: Noise Error interrupt
+ * @arg IRDA_IT_FE: Framing Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+
+
+/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
+ * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
+ * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
+ * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+
+/** @brief Set a specific IRDA request flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @param __REQ__: specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
+ * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the IRDA one bit sample method.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the IRDA one bit sample method.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART/USART associated to IRDA Handle.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART/USART associated to IRDA Handle.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+
+/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
+ * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
+
+/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
+ * @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
+ * @retval True or False
+ */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
+
+/**
+ * @brief Ensure that IRDA frame parity is valid.
+ * @param __PARITY__: IRDA frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+ ((__PARITY__) == IRDA_PARITY_EVEN) || \
+ ((__PARITY__) == IRDA_PARITY_ODD))
+
+/**
+ * @brief Ensure that IRDA communication mode is valid.
+ * @param __MODE__: IRDA communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+ * @brief Ensure that IRDA power mode is valid.
+ * @param __MODE__: IRDA power mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+ ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/**
+ * @brief Ensure that IRDA state is valid.
+ * @param __STATE__: IRDA state mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+ ((__STATE__) == IRDA_STATE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA associated UART/USART mode is valid.
+ * @param __MODE__: IRDA associated UART/USART mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
+ ((__MODE__) == IRDA_MODE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA sampling rate is valid.
+ * @param __ONEBIT__: IRDA sampling rate.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA DMA TX mode is valid.
+ * @param __DMATX__: IRDA DMA TX mode.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+ ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that IRDA DMA RX mode is valid.
+ * @param __DMARX__: IRDA DMA RX mode.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+ ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that IRDA request is valid.
+ * @param __PARAM__: IRDA request.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include IRDA HAL Extended module */
+#include "stm32f3xx_hal_irda_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_IRDA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_irda_ex.h
@@ -0,0 +1,432 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_irda_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of IRDA HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_IRDA_EX_H
+#define __STM32F3xx_HAL_IRDA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDAEx IRDAEx
+ * @brief IRDA Extension HAL module driver.
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants
+ * @{
+ */
+
+/** @defgroup IRDAEx_Word_Length IRDA Word Length
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
+#else
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
+ * @{
+ */
+
+/** @brief Report the IRDA clock source.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __CLOCKSOURCE__: output variable.
+ * @retval IRDA clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#else
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+
+
+/** @brief Compute the mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__: specifies the IRDA Handle
+ * @retval None, the mask to apply to IRDA RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F334x8)
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003F ; \
+ } \
+ } \
+} while(0)
+#else
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+} while(0)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F334x8 */
+/**
+ * @brief Ensure that IRDA frame length is valid.
+ * @param __LENGTH__: IRDA frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+#else
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_IRDA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_iwdg.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_iwdg.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_iwdg.h
@@ -0,0 +1,307 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_iwdg.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of IWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_IWDG_H
+#define __STM32F3xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief IWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
+ HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
+ HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
+ HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
+
+}HAL_IWDG_StateTypeDef;
+
+/**
+ * @brief IWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+ uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+ * @brief IWDG Handle Structure definition
+ */
+typedef struct
+{
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< IWDG Locking object */
+
+ __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
+
+}IWDG_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+ * @{
+ */
+#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Window IWDG Window
+ * @{
+ */
+#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @brief Reset IWDG handle state.
+ * @param __HANDLE__: IWDG handle.
+ * @retval None
+ */
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+
+/**
+ * @brief Enable the IWDG peripheral.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+ * @brief Reload IWDG counter with value defined in the reload register.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+ * @brief Get the selected IWDG flag status.
+ * @param __HANDLE__: IWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
+ * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
+ * @arg IWDG_FLAG_WVU: Watchdog counter window value flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE) .
+ */
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup IWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @addtogroup IWDG_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup IWDG_Private_Defines
+ * @{
+ */
+/**
+ * @brief IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */
+
+/**
+ * @brief IWDG Flag definition
+ */
+#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
+#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
+#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macro IWDG Private Macros
+ * @{
+ */
+/**
+ * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__: IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__: IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+
+/**
+ * @brief Check IWDG window value.
+ * @param __WINDOW__: IWDG window value
+ * @retval None
+ */
+#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h
@@ -0,0 +1,306 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nand.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_NAND_H
+#define __STM32F3xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+ #include "stm32f3xx_ll_fmc.h"
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NAND
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @addtogroup NAND_Private_Constants
+ * @{
+ */
+
+#define NAND_DEVICE1 FMC_BANK2
+#define NAND_DEVICE2 FMC_BANK3
+#define NAND_WRITE_TIMEOUT ((uint32_t)1000)
+
+#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
+#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
+#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
+#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
+#define NAND_BUSY ((uint32_t)0x00000000)
+#define NAND_ERROR ((uint32_t)0x00000001)
+#define NAND_READY ((uint32_t)0x00000040)
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Private_Macros
+ * @{
+ */
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__: NAND memory address.
+ * @param __HANDLE__ : NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
+}HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*State = HAL_NAND_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h
@@ -0,0 +1,301 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nor.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_NOR_H
+#define __STM32F3xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+ #include "stm32f3xx_ll_fmc.h"
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NOR
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @addtogroup NOR_Private_Constants
+ * @{
+ */
+
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x10)
+#define CFI2_ADDRESS ((uint16_t)0x11)
+#define CFI3_ADDRESS ((uint16_t)0x12)
+#define CFI4_ADDRESS ((uint16_t)0x13)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B ((uint8_t)0x0)
+#define NOR_MEMORY_16B ((uint8_t)0x1)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1 FMC_BANK1_1
+#define NOR_MEMORY_ADRESS2 FMC_BANK1_2
+#define NOR_MEMORY_ADRESS3 FMC_BANK1_3
+#define NOR_MEMORY_ADRESS4 FMC_BANK1_4
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Private_Macros
+ * @{
+ */
+
+/**
+ * @brief NOR memory address shifting.
+ * @param __NOR_ADDRESS: NOR base address
+ * @param __NOR_MEMORY_WIDTH_: NOR memory width
+ * @param __ADDRESS__: NOR memory address
+ * @retval NOR shifted address value
+ */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param __ADDRESS__: NOR memory address
+ * @param __DATA__: Data to write
+ * @retval None
+ */
+#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FMC NOR Status typedef
+ */
+typedef enum
+{
+ HAL_NOR_STATUS_SUCCESS = 0,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
+
+/**
+ * @brief FMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command. */
+}NOR_IDTypeDef;
+
+/**
+ * @brief FMC NOR CFI typedef
+ */
+typedef struct
+{
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory. */
+}NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+}NOR_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+ * @{
+ */
+
+/** @brief Reset NOR handle state
+ * @param __HANDLE__: NOR handle
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h
@@ -0,0 +1,509 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_opamp.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of OPAMP HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_OPAMP_H
+#define __STM32F3xx_HAL_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
+ * @{
+ */
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the OPAMP mode
+ This parameter must be a value of @ref OPAMP_Mode
+ mode is either Standalone, - Follower or PGA */
+
+ uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & Pga modes
+ - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
+ This parameter must be a value of @ref OPAMP_InvertingInput
+ InvertingInput is either VM0 or VM1
+ - In PGA mode: i.e when mode is OPAMP_PGA_MODE
+ & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
+ This parameter is Not Applicable */
+
+ uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
+ This parameter must be a value of @ref OPAMP_NonInvertingInput
+ NonInvertingInput is either VP0, VP1, VP2 or VP3 */
+
+ uint32_t TimerControlledMuxmode; /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
+ This parameter must be a value of @ref OPAMP_TimerControlledMuxmode */
+
+ uint32_t InvertingInputSecondary; /*!< Specifies the inverting input (secondary) of the opamp when
+ TimerControlledMuxmode is enabled
+ i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
+ - In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
+ This parameter must be a value of @ref OPAMP_InvertingInputSecondary
+ InvertingInputSecondary is either VM0 or VM1
+ - In PGA mode: i.e when mode is OPAMP_PGA_MODE
+ & in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
+ This parameter is Not Applicable */
+
+ uint32_t NonInvertingInputSecondary; /*!< Specifies the non inverting input (secondary) of the opamp when
+ TimerControlledMuxmode is enabled
+ i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
+ This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
+ NonInvertingInput is either VP0, VP1, VP2 or VP3 */
+
+ uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
+ i.e. when mode is OPAMP_PGA_MODE
+ This parameter must be a value of @ref OPAMP_PgaConnect
+ Either: not connected, connected to VM0, connected to VM1
+ (VM0 or VM1 are typically used for external filtering) */
+
+ uint32_t PgaGain; /*!< Specifies the gain in PGA mode
+ i.e. when mode is OPAMP_PGA_MODE.
+ This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */
+
+ uint32_t UserTrimming; /*!< Specifies the trimming mode
+ This parameter must be a value of @ref OPAMP_UserTrimming
+ UserTrimming is either factory or user trimming */
+
+ uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
+ i.e. when UserTrimming is OPAMP_TRIMMING_USER.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+}OPAMP_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+
+typedef enum
+{
+ HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPMAP is not yet Initialized */
+
+ HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */
+ HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
+
+ HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
+ HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005, /*!< OPAMP is locked
+ only system reset allows reconfiguring the opamp. */
+
+}HAL_OPAMP_StateTypeDef;
+
+/**
+ * @brief OPAMP Handle Structure definition to @brief OPAMP Handle Structure definition
+ */
+typedef struct
+{
+ OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
+ OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
+ HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
+
+} OPAMP_HandleTypeDef;
+
+/**
+ * @brief OPAMP_TrimmingValueTypeDef @brief definition
+ */
+
+typedef uint32_t OPAMP_TrimmingValueTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_CSR_INIT OPAMP CSR init register Mask
+ * @{
+ */
+/* Used for Init phase */
+#define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
+ | OPAMP_CSR_USERTRIM | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSSEL \
+ | OPAMP_CSR_VMSSEL | OPAMP_CSR_TCMEN | OPAMP_CSR_VPSEL \
+ | OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Mode OPAMP Mode
+ * @{
+ */
+#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */
+#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
+#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
+
+
+#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
+ ((INPUT) == OPAMP_PGA_MODE) || \
+ ((INPUT) == OPAMP_FOLLOWER_MODE))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL_0 /*!< vp3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == OPAMP_NONINVERTINGINPUT_IO3))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
+ * @{
+ */
+
+#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< inverting input connected to VM0 */
+#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
+
+#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
+ * @{
+ */
+ #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE ((uint32_t)0x00000000) /*!< Timer controlled Mux mode disabled */
+ #define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE OPAMP_CSR_TCMEN /*!< Timer controlled Mux mode enabled */
+
+ #define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \
+ ((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE))
+/**
+ * @}
+ */
+
+ /** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
+ * @{
+ */
+
+#define OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_SEC_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSSEL_0 /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+
+#define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
+ ((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
+ * @{
+ */
+
+#define OPAMP_SEC_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
+ connected to OPAMPx inverting input */
+#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
+ connected to OPAMPx inverting input */
+
+#define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
+ ((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
+ * @{
+ */
+
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the non inverting input is not connected */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
+
+#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
+ ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
+ ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1))
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
+ * @{
+ */
+
+#define OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000) /*!< PGA gain = 2 */
+#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */
+#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */
+#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */
+
+#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
+ ((GAIN) == OPAMP_PGA_GAIN_4) || \
+ ((GAIN) == OPAMP_PGA_GAIN_8) || \
+ ((GAIN) == OPAMP_PGA_GAIN_16))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
+ * @{
+ */
+
+#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
+#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
+ ((TRIMMING) == OPAMP_TRIMMING_USER))
+
+/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
+ * @{
+ */
+
+#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy trimming value */
+
+#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */
+#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */
+
+#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
+ ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_TrimmingValue OPAMP Trimming Value
+ * @{
+ */
+
+#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Input OPAMP Input
+ * @{
+ */
+
+#define OPAMP_INPUT_INVERTING ((uint32_t) 24) /*!< Inverting input */
+#define OPAMP_INPUT_NONINVERTING ((uint32_t) 19) /*!< Non inverting input */
+
+#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
+ ((INPUT) == OPAMP_INPUT_NONINVERTING))
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_VREF OPAMP VREF
+ * @{
+ */
+
+#define OPAMP_VREF_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
+#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
+#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
+#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
+
+#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
+ ((VREF) == OPAMP_VREF_10VDDA) || \
+ ((VREF) == OPAMP_VREF_50VDDA) || \
+ ((VREF) == OPAMP_VREF_90VDDA))
+
+/**
+ * @}
+ */
+
+ /** @defgroup OPAMP_Vref2ADCforCalib OPAMP Vref2ADCforCalib
+ */
+
+#define OPAMP_VREF_NOTCONNECTEDTO_ADC ((uint32_t)0x00000000) /*!< VREF not connected to ADC */
+#define OPAMP_VREF_CONNECTEDTO_ADC ((uint32_t)0x00000001) /*!< VREF not connected to ADC */
+
+#define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \
+ ((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC))
+
+
+ /**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
+ * @{
+ */
+
+/** @brief Reset OPAMP handle state
+ * @param __HANDLE__: OPAMP handle.
+ * @retval None
+ */
+#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Include OPAMP HAL Extended module */
+#include "stm32f3xx_hal_opamp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
+void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* I/O operation functions *****************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* Peripheral State functions **************************************************/
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
+OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_OPAMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp_ex.h
@@ -0,0 +1,117 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_opamp_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of OPAMP HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_OPAMP_EX_H
+#define __STM32F3xx_HAL_OPAMP_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMPEx OPAMPEx
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @{
+ */
+
+/* I/O operation functions *****************************************************/
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_OPAMP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pccard.h
@@ -0,0 +1,251 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pccard.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of PCCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PCCARD_H
+#define __STM32F3xx_HAL_PCCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+ #include "stm32f3xx_ll_fmc.h"
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCCARD
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @addtogroup PCCARD_Private_Constants
+ * @{
+ */
+
+#define PCCARD_DEVICE_ADDRESS FMC_BANK4
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x08000000)) /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x0C000000)) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FMC_BANK4 + 0x0C0001F0)) /* IO space size to @0x9FFF FFFF */
+
+/* Compact Flash-ATA registers description */
+#define ATA_DATA ((uint8_t)0x00) /* Data register */
+#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
+#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
+#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
+#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
+#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
+#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
+#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
+#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
+
+/* Compact Flash-ATA commands */
+#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
+#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
+#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
+#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
+
+/* Compact Flash status */
+#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
+#define PCCARD_BUSY ((uint8_t)0x80)
+#define PCCARD_PROGR ((uint8_t)0x01)
+#define PCCARD_READY ((uint8_t)0x40)
+
+#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */
+
+
+/* Compact Flash redefinition */
+#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
+#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
+#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
+#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
+#define HAL_CF_Reset HAL_PCCARD_Reset
+
+#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
+#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
+
+#define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define CF_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define CF_ERROR HAL_PCCARD_STATUS_ERROR
+#define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+#define HAL_PCCARD_StatusTypeDef HAL_PCCARD_StatusTypeDef
+
+
+#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
+#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
+#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
+
+#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
+#define CF_BUSY PCCARD_BUSY
+#define CF_PROGR PCCARD_PROGR
+#define CF_READY PCCARD_READY
+
+#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL PCCARD State structures definition
+ */
+typedef enum
+{
+ HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
+}HAL_PCCARD_StateTypeDef;
+
+typedef enum
+{
+ HAL_PCCARD_STATUS_SUCCESS = 0,
+ HAL_PCCARD_STATUS_ONGOING,
+ HAL_PCCARD_STATUS_ERROR,
+ HAL_PCCARD_STATUS_TIMEOUT
+}HAL_PCCARD_StatusTypeDef;
+
+/**
+ * @brief FMC_PCCARD handle Structure definition
+ */
+typedef struct
+{
+ FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
+
+ FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
+
+ __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
+
+ HAL_LockTypeDef Lock; /*!< PCCARD Lock */
+
+}PCCARD_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset PCCARD handle state
+ * @param __HANDLE__: specifies the PCCARD handle.
+ * @retval None
+ */
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
+ * @{
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
+void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
+ * @{
+ */
+/* PCCARD State functions *******************************************************/
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_PCCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h
@@ -0,0 +1,857 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of PCD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PCD_H
+#define __STM32F3xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+ * @{
+ */
+
+/**
+ * @brief PCD State structure definition
+ */
+typedef enum
+{
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/**
+ * @brief PCD double buffered endpoint direction
+ */
+typedef enum
+{
+ PCD_EP_DBUF_OUT,
+ PCD_EP_DBUF_IN,
+ PCD_EP_DBUF_ERR,
+}PCD_EP_DBUF_DIR;
+
+/**
+ * @brief PCD endpoint buffer number
+ */
+typedef enum
+{
+ PCD_EP_NOBUF,
+ PCD_EP_BUF0,
+ PCD_EP_BUF1
+}PCD_EP_BUF_NUM;
+
+/**
+ * @brief PCD Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Core_Speed */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
+ This parameter can be any value of @ref PCD_EP0_MPS */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_Core_PHY */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t low_power_enable; /*!< Enable or disable Low Power mode
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+
+}PCD_InitTypeDef;
+
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref PCD_EP_Type */
+
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+
+}PCD_EPTypeDef;
+
+typedef USB_TypeDef PCD_TypeDef;
+
+/**
+ * @brief PCD Handle Structure definition
+ */
+typedef struct
+{
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
+
+} PCD_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Include PCD HAL Extension module */
+#include "stm32f3xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+/** @defgroup PCD_Core_Speed PCD Core Speed
+ * @{
+ */
+#define PCD_SPEED_HIGH 0 /* Not Supported */
+#define PCD_SPEED_FULL 2
+/**
+ * @}
+ */
+
+ /** @defgroup PCD_Core_PHY PCD Core PHY
+ * @{
+ */
+#define PCD_PHY_EMBEDDED 2
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
+
+#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\
+ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
+ } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
+ EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ } while(0)
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
+ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;\
+ } while(0)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+ * @{
+ */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+ * @{
+ */
+#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+/**
+ * @}
+ */
+
+/** @defgroup PCD_EP0_MPS PCD EP0 MPS
+ * @{
+ */
+#define DEP0CTL_MPS_64 0
+#define DEP0CTL_MPS_32 1
+#define DEP0CTL_MPS_16 2
+#define DEP0CTL_MPS_8 3
+
+#define PCD_EP0MPS_64 DEP0CTL_MPS_64
+#define PCD_EP0MPS_32 DEP0CTL_MPS_32
+#define PCD_EP0MPS_16 DEP0CTL_MPS_16
+#define PCD_EP0MPS_08 DEP0CTL_MPS_8
+/**
+ * @}
+ */
+
+/** @defgroup PCD_EP_Type PCD EP Type
+ * @{
+ */
+#define PCD_EP_TYPE_CTRL 0
+#define PCD_EP_TYPE_ISOC 1
+#define PCD_EP_TYPE_BULK 2
+#define PCD_EP_TYPE_INTR 3
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP PCD ENDP
+ * @{
+ */
+#define PCD_ENDP0 ((uint8_t)0)
+#define PCD_ENDP1 ((uint8_t)1)
+#define PCD_ENDP2 ((uint8_t)2)
+#define PCD_ENDP3 ((uint8_t)3)
+#define PCD_ENDP4 ((uint8_t)4)
+#define PCD_ENDP5 ((uint8_t)5)
+#define PCD_ENDP6 ((uint8_t)6)
+#define PCD_ENDP7 ((uint8_t)7)
+/**
+ * @}
+ */
+
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+ * @{
+ */
+#define PCD_SNG_BUF 0
+#define PCD_DBL_BUF 1
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Internal macros -----------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+
+/* GetENDPOINT */
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
+
+
+
+/**
+ * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wType: Endpoint Type.
+ * @retval None
+ */
+#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+
+/**
+ * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint Type
+ */
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+
+
+/**
+ * @brief free buffer used from the application realizing it to the line
+ toggles bit SW_BUF in the double buffered endpoint register
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: Direction
+ * @retval None
+ */
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
+{\
+ if ((bDir) == PCD_EP_DBUF_OUT)\
+ { /* OUT double buffered endpoint */\
+ PCD_TX_DTOG((USBx), (bEpNum));\
+ }\
+ else if ((bDir) == PCD_EP_DBUF_IN)\
+ { /* IN double buffered endpoint */\
+ PCD_RX_DTOG((USBx), (bEpNum));\
+ }\
+}
+
+/**
+ * @brief gets direction of the double buffered endpoint
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval EP_DBUF_OUT, EP_DBUF_IN,
+ * EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+#define PCD_GET_DB_DIR(USBx, bEpNum)\
+{\
+ if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
+ return(PCD_EP_DBUF_OUT);\
+ else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
+ return(PCD_EP_DBUF_IN);\
+ else\
+ return(PCD_EP_DBUF_ERR);\
+}
+
+/**
+ * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state
+ * @retval None
+ */
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wState))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & (wState))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ } /* PCD_SET_EP_TX_STATUS */
+
+/**
+ * @brief sets the status for rx transfer (bits STAT_TX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state
+ * @retval None
+ */
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & (wState))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & (wState))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ } /* PCD_SET_EP_RX_STATUS */
+
+/**
+ * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wStaterx: new state.
+ * @param wStatetx: new state.
+ * @retval None
+ */
+#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
+ /* toggle first bit ? */ \
+ if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ /* toggle first bit ? */ \
+ if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
+ } /* PCD_SET_EP_TXRX_STATUS */
+
+/**
+ * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
+ * /STAT_RX[1:0])
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval status
+ */
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+
+/**
+ * @brief sets directly the VALID tx/rx-status into the endpoint register
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+
+/**
+ * @brief checks stall condition in an endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval TRUE = endpoint in stall condition.
+ */
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
+ == USB_EP_RX_STALL)
+
+/**
+ * @brief set & clear EP_KIND bit.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
+
+/**
+ * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Sets/clears directly EP_KIND bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+
+/**
+ * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+
+/**
+ * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+
+/**
+ * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
+ PCD_RX_DTOG((USBx), (bEpNum))
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
+ PCD_TX_DTOG((USBx), (bEpNum))
+
+/**
+ * @brief Sets address in an endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bAddr: Address.
+ * @retval None
+ */
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
+ USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
+
+/**
+ * @brief Gets address in an endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
+
+/**
+ * @brief sets address of the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wAddr: address to be set (must be word aligned).
+ * @retval None
+ */
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+
+/**
+ * @brief Gets address of the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval address of the buffer.
+ */
+#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Sets counter of rx buffer with no. of blocks.
+ * @param dwReg: Register
+ * @param wCount: Counter.
+ * @param wNBlocks: no. of Blocks.
+ * @retval None
+ */
+#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 5;\
+ if(((wCount) & 0x1f) == 0)\
+ (wNBlocks)--;\
+ *pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\
+ }/* PCD_CALC_BLK32 */
+
+#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
+ (wNBlocks) = (wCount) >> 1;\
+ if(((wCount) & 0x1) != 0)\
+ (wNBlocks)++;\
+ *pdwReg = (uint16_t)((wNBlocks) << 10);\
+ }/* PCD_CALC_BLK2 */
+
+#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
+ uint16_t wNBlocks;\
+ if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\
+ else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\
+ }/* PCD_SET_EP_CNT_RX_REG */
+
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
+ uint32_t *pdwReg = PCD_EP_TX_CNT(USBx, bEpNum); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+ }
+/**
+ * @brief sets counter for the tx/rx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wCount: Counter value.
+ * @retval None
+ */
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
+
+/**
+ * @brief gets counter of the tx buffer.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Counter value
+ */
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
+
+/**
+ * @brief Sets buffer 0/1 address in a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @retval Counter value
+ */
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
+
+/**
+ * @brief Sets addresses in a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: buffer 0 address.
+ * @param wBuf1Addr = buffer 1 address.
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
+ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
+ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
+ } /* PCD_SET_EP_DBUF_ADDR */
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+
+/**
+ * @brief Gets buffer 0/1 address of a double buffer endpoint.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * @param wCount: Counter value
+ * @retval None
+ */
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ /* IN endpoint */ \
+ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } /* SetEPDblBuf0Count*/
+
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
+ if((bDir) == PCD_EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\
+ else if((bDir) == PCD_EP_DBUF_IN)\
+ /* IN endpoint */\
+ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } /* SetEPDblBuf1Count */
+
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
+ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ } /* PCD_SET_EP_DBUF_CNT */
+
+/**
+ * @brief Gets buffer 0/1 rx/tx counter for double buffering.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+
+/** @defgroup PCD_Instance_definition PCD Instance definition
+ * @{
+ */
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/** @addtogroup PCDEx_Private_Functions PCD Extended Private Functions
+ * @{
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h
@@ -0,0 +1,153 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd_ex.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief Header file of PCD HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PCD_EX_H
+#define __STM32F3xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PCDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCDEx_Exported_Macros PCD Extended Exported Macros
+ * @{
+ */
+/**
+ * @brief Gets address in an endpoint register.
+ * @param USBx: USB peripheral instance register address.
+ * @param bEpNum: Endpoint Number.
+ * @retval None
+ */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F373xC)
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8)*2+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+2)*2+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+4)*2+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+6)*2+ ((uint32_t)USBx + 0x400)))
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+ uint32_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+ }
+
+#endif /* STM32F302xC || STM32F303xC || */
+ /* STM32F373xC */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302x8)
+
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8)+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+2)+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+4)+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+6)+ ((uint32_t)USBx + 0x400)))
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
+ uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+ }
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302x8 */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress);
+
+void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h
@@ -0,0 +1,270 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PWR_H
+#define __STM32F3xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Alias_Exported_Constants PWR Alias Exported Constants
+ * @{
+ */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BIT_NUMBER * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BIT_NUMBER * 4))
+
+/* --- CSR Register ---*/
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+/* Alias word address of EWUP1 bit */
+#define EWUP1_BitNumber POSITION_VAL(PWR_CSR_EWUP1)
+#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
+
+/* Alias word address of EWUP2 bit */
+#define EWUP2_BitNumber POSITION_VAL(PWR_CSR_EWUP2)
+#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
+
+/* Alias word address of EWUP3 bit */
+#define EWUP3_BitNumber POSITION_VAL(PWR_CSR_EWUP3)
+#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP3_BitNumber * 4))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+ * @{
+ */
+
+#define PWR_WAKEUP_PIN1 ((uint32_t)0x00) /*!< Wakeup pin 1 */
+#define PWR_WAKEUP_PIN2 ((uint32_t)0x01) /*!< Wakeup pin 2 */
+#define PWR_WAKEUP_PIN3 ((uint32_t)0x02) /*!< Wakeup pin 3 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Voltage regulator on during STOP mode */
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter SLEEP mode */
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter SLEEP mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter STOP mode */
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter STOP mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag PWR Flag
+ * @{
+ */
+#define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */
+#define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */
+#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */
+#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+ * @{
+ */
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+ * was received from the WKUP pin or from the RTC alarm (Alarm A
+ * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+ * An additional wakeup event is detected if the WKUP pin is enabled
+ * (by setting the EWUP bit) when the WKUP pin level is already high.
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * For this reason, this bit is equal to 0 after Standby or reset
+ * until the PVDE bit is set.
+ * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
+ * voltage VREFINT is ready.
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the PWR's pending flags.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+ ((PIN) == PWR_WAKEUP_PIN2) || \
+ ((PIN) == PWR_WAKEUP_PIN3))
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+ * @}
+ */
+
+/* Include PWR HAL Extended module */
+#include "stm32f3xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h
@@ -0,0 +1,340 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of PWR HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_PWR_EX_H
+#define __STM32F3xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
+ This parameter can be a value of @ref PWREx_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWREx_PVD_Mode */
+}PWR_PVDTypeDef;
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */
+#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */
+#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */
+#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+#define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
+ * @{
+ */
+#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_SDADC1EN) /*!< Enable SDADC1 */
+#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_SDADC2EN) /*!< Enable SDADC2 */
+#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_SDADC3EN) /*!< Enable SDADC3 */
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/**
+ * @brief Enable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable interrupt on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Enable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable event on PVD Exti Line 16.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief PVD EXTI line configuration: set falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief PVD EXTI line configuration: set rising edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+ * @retval EXTI PVD Line Status.
+ */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+ * @brief Clear the PVD EXTI flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+ ((MODE) == PWR_PVD_MODE_NORMAL))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \
+ ((SDADC) == PWR_SDADC_ANALOG2) || \
+ ((SDADC) == PWR_SDADC_ANALOG3))
+#endif /* STM32F373xC || STM32F378xx */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
+ * @{
+ */
+/* Peripheral Extended control functions **************************************/
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+void HAL_PWREx_EnableSDADC(uint32_t Analogx);
+void HAL_PWREx_DisableSDADC(uint32_t Analogx);
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h
@@ -0,0 +1,1738 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RCC_H
+#define __STM32F3xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+/** @defgroup RCC_Timeout RCC Timeout
+ * @{
+ */
+
+/* Disable Backup domain write protection state change timeout */
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/* LSE state change timeout */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Register_Offset Register offsets
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define RCC_CR_OFFSET 0x00
+#define RCC_CFGR_OFFSET 0x04
+#define RCC_CIR_OFFSET 0x08
+#define RCC_BDCR_OFFSET 0x20
+#define RCC_CSR_OFFSET 0x24
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
+#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
+#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
+#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
+#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
+
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
+/* Alias word address of HSEON bit */
+#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
+#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
+
+/* Alias word address of RMVF bit */
+#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
+#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
+
+/* --- BDCR Registers ---*/
+/* Alias word address of LSEON bit */
+#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
+#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
+
+/* Alias word address of LSEON bit */
+#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
+#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
+
+/* Alias word address of RTCEN bit */
+#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
+#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
+
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
+#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
+
+/**
+ * @}
+ */
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+
+/* Defines used for Flags */
+#define CR_REG_INDEX ((uint8_t)1)
+#define BDCR_REG_INDEX ((uint8_t)2)
+#define CSR_REG_INDEX ((uint8_t)3)
+#define CFGR_REG_INDEX ((uint8_t)4)
+
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
+#else
+#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
+ ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
+#endif
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
+ ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
+ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
+ ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
+ ((__MUL__) == RCC_PLL_MUL16))
+#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< PLLState: The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
+
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
+
+#endif
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
+ This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */
+
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+} RCC_OscInitTypeDef;
+
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
+
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+} RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+ * @{
+ */
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */
+#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config HSE Config
+ * @{
+ */
+#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
+#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
+#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config LSE Config
+ * @{
+ */
+#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
+#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
+#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config HSI Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
+
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
+#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
+#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
+ * @{
+ */
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */
+#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
+ * @{
+ */
+#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
+#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
+#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
+#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
+#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
+#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
+#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
+#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
+#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
+#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
+#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
+#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
+#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
+#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
+#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
+
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
+ * @{
+ */
+
+#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
+#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
+#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
+#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
+#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
+#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
+#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
+#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
+#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
+#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
+#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
+#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
+#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
+#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
+#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
+#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
+
+/**
+ * @}
+ */
+
+#endif
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+/** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
+ * @{
+ */
+
+#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
+#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
+#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
+#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
+#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
+#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
+#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
+#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
+#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
+#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
+#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
+#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
+#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
+#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
+#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
+#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
+
+/**
+ * @}
+ */
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
+ * @{
+ */
+#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
+#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
+#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
+#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
+ * @{
+ */
+#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
+#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
+#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
+ * @{
+ */
+#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
+#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
+
+/**
+ * @}
+ */
+/** @defgroup RCC_MCO_Index MCO Index
+ * @{
+ */
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt Interrupts
+ * @{
+ */
+#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
+#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
+#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: XXXYYYYYb
+ * - YYYYY : Flag position in the register
+ * - XXX : Register index
+ * - 001: CR register
+ * - 010: BDCR register
+ * - 011: CSR register
+ * - 100: CFGR register
+ * @{
+ */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
+#if defined(RCC_CSR_V18PWRRSTF)
+#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
+#endif /*RCC_CSR_V18PWRRSTF*/
+#if defined(RCC_CSR_VREGRSTF)
+#define RCC_FLAG_VREGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_VREGRSTF)))
+#endif /*RCC_CSR_VREGRSTF*/
+#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_RMVF_BIT_NUMBER)) /*!< Remove reset flag */
+#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
+
+/* Flags in the CFGR register */
+#if defined(RCC_CFGR_MCOF)
+#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */
+#endif /* RCC_CFGR_MCOF */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TSC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
+#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
+#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
+#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
+#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
+#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
+#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
+#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
+#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief EGet the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
+
+#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
+ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+ * @{
+ */
+
+/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+
+/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
+ * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+ * software should wait on HSERDY flag to be set indicating that HSE clock
+ * is stable and can be used to clock the PLL and/or system clock.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the Clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__ specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
+ * 6 HSE oscillator clock cycles.
+ * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
+ * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if ((__STATE__) == RCC_HSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ }while(0)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+ * software should wait on LSERDY flag to be set indicating that LSE clock
+ * is stable and can be used to clock the RTC.
+ * @param __STATE__ specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
+ * 6 LSE oscillator clock cycles.
+ * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
+ * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else if ((__STATE__) == RCC_LSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ }while(0)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the USART1 clock (USART1CLK).
+ * @param __USART1CLKSOURCE__ specifies the USART1 clock source.
+ * This parameter can be one of the following values:
+ @if STM32F302xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F358xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F302xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F398xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F373xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F378xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F301x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F302x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F318xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F303x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F334x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F328xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
+ */
+#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
+
+/** @brief Macro to get the USART1 clock source.
+ * @retval The clock source can be one of the following values:
+ @if STM32F302xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F358xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F302xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F303xE
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F398xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F373xC
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F378xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
+ @endif
+ @if STM32F301x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F302x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F318xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F303x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F334x8
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ @if STM32F328xx
+ * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
+ @endif
+ * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
+ * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
+ */
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
+
+/** @brief Macro to configure the USART2 clock (USART2CLK).
+ * @param __USART2CLKSOURCE__ specifies the USART2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ */
+#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
+
+/** @brief Macro to get the USART2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
+ * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
+ */
+#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
+
+/** @brief Macro to configure the USART3 clock (USART3CLK).
+ * @param __USART3CLKSOURCE__ specifies the USART3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ */
+#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
+
+/** @brief Macro to get the USART3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
+ * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
+ */
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2C1 clock (I2C1CLK).
+ * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
+ */
+#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
+
+/** @brief Macro to get the I2C1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
+ * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
+ */
+#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
+
+/** @brief Macro to enable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+
+/** @brief Macro to disable the main PLL.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ */
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
+
+/** @brief Get oscillator clock selected as PLL input clock
+ * @retval The clock source used for PLL entry. The returned value can be one
+ * of the following:
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
+
+#if defined(RCC_CFGR_MCOPRE)
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
+ * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
+ * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
+ * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
+ * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
+ * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
+ * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
+ * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
+ */
+#else
+/** @brief Macro to configure the MCO clock.
+ * @param __MCOCLKSOURCE__ specifies the MCO clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param __MCODIV__ specifies the MCO clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
+ */
+#endif
+#if defined(RCC_CFGR_MCOPRE)
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+#else
+
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
+
+#endif
+
+/**
+ * @}
+ */
+
+ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
+ * @{
+ */
+
+/** @brief Macro to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is denied to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
+ * a Power On Reset (POR).
+ *
+ * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
+ * the RTC cannot be used in STOP and STANDBY modes.
+ * @note The system must always be configured so as to get a PCLK frequency greater than or
+ * equal to the RTCCLK frequency for a proper operation of the RTC.
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/** @brief Macro to enable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+
+/** @brief Macro to disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
+
+/** @brief Macro to force the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_BDCR register.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+
+/** @brief Macros to release the Backup domain reset.
+ */
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+ * @brief macros to manage the specified RCC Flags and interrupts.
+ * @{
+ */
+
+/** @brief Enable RCC interrupt.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+ */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt
+ * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt
+ */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
+ * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
+ * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
+ * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
+ * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+ * @arg @ref RCC_IT_CSS Clock Security System interrupt
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+ * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
+
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
+ * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
+ * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
+ * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
+ * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
+ * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
+ * @arg @ref RCC_FLAG_PINRST Pin reset.
+ * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
+ * @arg @ref RCC_FLAG_SFTRST Software reset.
+ * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
+ * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
+ * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
+ @if defined(STM32F302xC)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
+ @endif
+ @if defined(STM32F302xE)
+ * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
+ @endif
+ @if defined(STM32F303xC)
+ * @arg @ref RCC_FLAG_VREGRST Voltage regulator reset
+ * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
+ @endif
+ @if defined(STM32F303xE)
+ * @arg @ref RCC_FLAG_VREGRST Voltage regulator reset
+ @endif
+ @if defined(STM32F358xx)
+ * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output
+ @endif
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX) ? RCC->CR : \
+ (((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
+ (((__FLAG__) >> 5) == CFGR_REG_INDEX)? RCC->CFGR : \
+ RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include RCC HAL Extension module */
+#include "stm32f3xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h
@@ -0,0 +1,3915 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RCC_EX_H
+#define __STM32F3xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/** @addtogroup RCCEx_Private_Macros
+ * @{
+ */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F301x8) || defined(STM32F318xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F301x8 || STM32F318xx */
+#if defined(STM32F302x8)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17))
+#endif /* STM32F302x8 */
+#if defined(STM32F302xC)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F302xC */
+#if defined(STM32F303xC)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F303xC */
+#if defined(STM32F302xE)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17))
+#endif /* STM32F302xE */
+#if defined(STM32F303xE)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
+#endif /* STM32F303xE */
+#if defined(STM32F398xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
+ RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
+ RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
+ RCC_PERIPHCLK_TIM20))
+#endif /* STM32F398xx */
+#if defined(STM32F358xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F358xx */
+#if defined(STM32F303x8)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F303x8 */
+#if defined(STM32F334x8)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F334x8 */
+#if defined(STM32F328xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
+#endif /* STM32F328xx */
+#if defined(STM32F373xC)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F373xC */
+#if defined(STM32F378xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
+#endif /* STM32F378xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM15CLK_PLLCLK))
+#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM16CLK_PLLCLK))
+#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM17CLK_PLLCLK))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM2CLK_PLLCLK))
+#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM34CLK_PLLCLK))
+#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM15CLK_PLLCLK))
+#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM16CLK_PLLCLK))
+#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM17CLK_PLLCLK))
+#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM20CLK_PLLCLK))
+#endif /* STM32F303xE || STM32F398xx */
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
+#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM8CLK_PLLCLK))
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+#if defined(STM32F334x8)
+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
+#endif /* STM32F334x8 */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
+ ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
+ ((DIV) == RCC_SDADCSYSCLK_DIV48))
+#endif /* STM32F373xC || STM32F378xx */
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
+ ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+#if defined(RCC_CFGR_MCOPRE)
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
+ ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
+ ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
+#else
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
+#endif /* RCC_CFGR_MCOPRE */
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
+ ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC extended clocks structure definition
+ */
+#if defined(STM32F301x8) || defined(STM32F318xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined(STM32F302x8)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F302x8 */
+
+#if defined(STM32F302xC)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F302xC */
+
+#if defined(STM32F303xC)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F303xC */
+
+#if defined(STM32F302xE)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t Tim20ClockSelection; /*!< TIM20 clock source
+ This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F303xE */
+
+#if defined(STM32F398xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t Tim20ClockSelection; /*!< TIM20 clock source
+ This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F398xx */
+
+#if defined(STM32F358xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F358xx */
+
+#if defined(STM32F303x8)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F303x8 */
+
+#if defined(STM32F334x8)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
+ This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F334x8 */
+
+#if defined(STM32F328xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F328xx */
+
+#if defined(STM32F373xC)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
+ This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F373xC */
+
+#if defined(STM32F378xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t Adc1ClockSelection; /*!< ADC1 clock source
+ This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
+
+ uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
+ This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
+
+ uint32_t CecClockSelection; /*!< HDMI CEC clock source
+ This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F378xx */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
+ * @{
+ */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
+#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
+#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
+#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
+
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
+#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
+#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
+#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
+#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
+#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
+#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F318xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
+
+#endif /* STM32F301x8 || STM32F318xx */
+
+#if defined(STM32F302x8)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
+
+
+#endif /* STM32F302x8 */
+
+#if defined(STM32F302xC)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#endif /* STM32F302xC */
+
+#if defined(STM32F303xC)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#endif /* STM32F303xC */
+
+#if defined(STM32F302xE)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
+
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
+#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
+
+#endif /* STM32F303xE */
+
+#if defined(STM32F398xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
+#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
+
+
+#endif /* STM32F398xx */
+
+#if defined(STM32F358xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+#endif /* STM32F358xx */
+
+#if defined(STM32F303x8)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+#endif /* STM32F303x8 */
+
+#if defined(STM32F334x8)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F328xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+#endif /* STM32F328xx */
+
+#if defined(STM32F373xC)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#endif /* STM32F373xC */
+
+#if defined(STM32F378xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+
+#endif /* STM32F378xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
+ * @{
+ */
+#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
+ * @{
+ */
+#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
+#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
+#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
+#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
+#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
+#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
+#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
+#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
+#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
+#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
+#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
+#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
+#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
+ * @{
+ */
+#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
+#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
+ * @{
+ */
+#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
+#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
+ * @{
+ */
+#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
+#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
+ * @{
+ */
+
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
+#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
+#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
+#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
+#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
+#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
+#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
+#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
+#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
+#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
+#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
+#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
+#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
+
+/**
+ * @}
+ */
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
+ * @{
+ */
+#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
+#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
+#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
+ * @{
+ */
+#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
+#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
+#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
+ * @{
+ */
+#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
+ * @{
+ */
+
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
+#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
+#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
+#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
+#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
+#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
+#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
+#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
+#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
+#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
+#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
+#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
+#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
+ * @{
+ */
+#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
+#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
+ * @{
+ */
+#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
+#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
+ * @{
+ */
+#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
+#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
+ * @{
+ */
+#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
+#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
+ * @{
+ */
+#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
+#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
+ * @{
+ */
+#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
+#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
+#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
+ * @{
+ */
+#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
+#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
+#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
+ * @{
+ */
+#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
+#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
+
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
+ * @{
+ */
+
+/* ADC3 & ADC4 */
+#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
+#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
+#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
+#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
+#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
+#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
+#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
+#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
+#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
+#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
+#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
+#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
+#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
+ * @{
+ */
+#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
+#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
+ * @{
+ */
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
+#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
+#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
+#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
+#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
+#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
+#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
+#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
+#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
+#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
+#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
+#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
+#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
+ * @{
+ */
+#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
+#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
+
+/**
+ * @}
+ */
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
+#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
+#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
+#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
+ * @{
+ */
+
+/* ADC1 */
+#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
+#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
+#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
+#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
+ * @{
+ */
+#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
+#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
+ * @{
+ */
+#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
+#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
+#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
+#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
+#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
+#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
+#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
+#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
+#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
+#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
+#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
+#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
+#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
+#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
+#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
+#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
+#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
+
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
+ * @{
+ */
+
+#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
+#define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+
+/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
+ * @{
+ */
+#if defined(RCC_CFGR_MCOPRE)
+
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+#define RCC_MCODIV_2 ((uint32_t)0x10000000)
+#define RCC_MCODIV_4 ((uint32_t)0x20000000)
+#define RCC_MCODIV_8 ((uint32_t)0x30000000)
+#define RCC_MCODIV_16 ((uint32_t)0x40000000)
+#define RCC_MCODIV_32 ((uint32_t)0x50000000)
+#define RCC_MCODIV_64 ((uint32_t)0x60000000)
+#define RCC_MCODIV_128 ((uint32_t)0x70000000)
+
+#else
+
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+
+#endif /* RCC_CFGR_MCOPRE */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
+ * @{
+ */
+
+#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /*!< Xtal mode lower driving capability */
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
+ * @{
+ */
+
+/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @brief Macro to configure the PLL clock source, multiplication and division factors.
+ * @note This macro must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+ * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
+ * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
+ do { \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
+ } while(0)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+/** @brief Macro to configure the PLL clock source and multiplication factor.
+ * @note This macro must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+ * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
+
+/**
+ * @brief Macro to get prediv1 factor for PLL.
+ */
+#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
+
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+
+/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_ADC34_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
+
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_FMC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_UART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM18_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) \
+ || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define __HAL_RCC_USB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if !defined(STM32F301x8)
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
+#endif /* STM32F301x8*/
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM19_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
+#define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
+#define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
+#define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_TIM20_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
+#endif /* STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
+
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
+
+#define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
+
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
+
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
+
+#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) \
+ || defined(STM32F303xC) || defined(STM32F358xx) \
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
+
+#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if !defined(STM32F301x8)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
+
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
+#endif /* STM32F301x8*/
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
+
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
+#define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
+#define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
+#define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
+
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
+#define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
+#define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
+#define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
+
+#define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
+#endif /* STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
+
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
+
+#define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
+
+#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
+/* Aliases for STM32 F3 compatibility */
+#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
+
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
+
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
+ */
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if !defined(STM32F301x8)
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
+
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
+#endif /* STM32F301x8*/
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
+
+#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
+#define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
+#define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
+#define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
+
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
+#define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
+#define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
+#define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
+
+#define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
+#endif /* STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ * @param __I2C2CLKSource__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
+
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
+ * @param __I2C3CLKSource__ specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
+
+/** @brief Macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM1 clock (TIM1CLK).
+ * @param __TIM1CLKSource__ specifies the TIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
+
+/** @brief Macro to get the TIM1 clock (TIM1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
+
+/** @brief Macro to configure the TIM15 clock (TIM15CLK).
+ * @param __TIM15CLKSource__ specifies the TIM15 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
+
+/** @brief Macro to get the TIM15 clock (TIM15CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
+
+/** @brief Macro to configure the TIM16 clock (TIM16CLK).
+ * @param __TIM16CLKSource__ specifies the TIM16 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
+
+/** @brief Macro to get the TIM16 clock (TIM16CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
+
+/** @brief Macro to configure the TIM17 clock (TIM17CLK).
+ * @param __TIM17CLKSource__ specifies the TIM17 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
+
+/** @brief Macro to get the TIM17 clock (TIM17CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __I2SCLKSource__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
+
+/** @brief Macro to get the I2S clock source (I2SCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC1 clock (ADC1CLK).
+ * @param __ADC1CLKSource__ specifies the ADC1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
+ */
+#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
+
+/** @brief Macro to get the ADC1 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
+ */
+#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
+/**
+ * @}
+ */
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ * @param __I2C2CLKSource__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
+ * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
+
+/** @brief Macro to get the ADC1 & ADC2 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the TIM1 clock (TIM1CLK).
+ * @param __TIM1CLKSource__ specifies the TIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
+
+/** @brief Macro to get the TIM1 clock (TIM1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ * @param __I2SCLKSource__ specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
+
+/** @brief Macro to get the I2S clock source (I2SCLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
+ * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the UART4 clock (UART4CLK).
+ * @param __UART4CLKSource__ specifies the UART4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ */
+#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
+
+/** @brief Macro to get the UART4 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
+ * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
+ */
+#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
+
+/** @brief Macro to configure the UART5 clock (UART5CLK).
+ * @param __UART5CLKSource__ specifies the UART5 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ */
+#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
+
+/** @brief Macro to get the UART5 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
+ * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
+ */
+#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
+ * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
+ */
+#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
+
+/** @brief Macro to get the ADC3 & ADC4 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
+ * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
+ */
+#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the TIM8 clock (TIM8CLK).
+ * @param __TIM8CLKSource__ specifies the TIM8 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
+ * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
+ */
+#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
+
+/** @brief Macro to get the TIM8 clock (TIM8CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
+ * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
+ */
+#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
+
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+
+/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
+ * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
+
+/** @brief Macro to get the ADC1 & ADC2 clock
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
+ * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
+ */
+#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM1 clock (TIM1CLK).
+ * @param __TIM1CLKSource__ specifies the TIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
+
+/** @brief Macro to get the TIM1 clock (TIM1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
+ * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
+ */
+#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
+/**
+ * @}
+ */
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F334x8)
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the HRTIM1 clock.
+ * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
+ * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
+ */
+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
+
+/** @brief Macro to get the HRTIM1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
+ * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
+ */
+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
+/**
+ * @}
+ */
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the I2C2 clock (I2C2CLK).
+ * @param __I2C2CLKSource__ specifies the I2C2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
+
+/** @brief Macro to get the I2C2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
+ * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
+ */
+#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the ADC1 clock (ADC1CLK).
+ * @param __ADC1CLKSource__ specifies the ADC1 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
+ */
+#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
+
+/** @brief Macro to get the ADC1 clock (ADC1CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
+ * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
+ */
+#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
+ * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
+ */
+#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
+
+/** @brief Macro to get the SDADCx clock prescaler.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
+ * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
+ */
+#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the CEC clock.
+ * @param __CECCLKSource__ specifies the CEC clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
+ * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
+ */
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
+
+/** @brief Macro to get the HDMI CEC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
+ * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
+ */
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
+/**
+ * @}
+ */
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+
+/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the USB clock (USBCLK).
+ * @param __USBCLKSource__ specifies the USB clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
+
+/** @brief Macro to get the USB clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
+ * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
+ */
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
+ * @param __I2C3CLKSource__ specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
+
+/** @brief Macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
+ * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM2 clock (TIM2CLK).
+ * @param __TIM2CLKSource__ specifies the TIM2 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
+ * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
+ */
+#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
+
+/** @brief Macro to get the TIM2 clock (TIM2CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
+ * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
+ */
+#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
+
+/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
+ * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
+ * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
+ */
+#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
+
+/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
+ * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
+ */
+#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
+
+/** @brief Macro to configure the TIM15 clock (TIM15CLK).
+ * @param __TIM15CLKSource__ specifies the TIM15 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
+
+/** @brief Macro to get the TIM15 clock (TIM15CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
+ * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
+
+/** @brief Macro to configure the TIM16 clock (TIM16CLK).
+ * @param __TIM16CLKSource__ specifies the TIM16 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
+
+/** @brief Macro to get the TIM16 clock (TIM16CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
+ * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
+
+/** @brief Macro to configure the TIM17 clock (TIM17CLK).
+ * @param __TIM17CLKSource__ specifies the TIM17 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
+
+/** @brief Macro to get the TIM17 clock (TIM17CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
+ * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
+
+/**
+ * @}
+ */
+
+#endif /* STM32f302xE || STM32f303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM20 clock (TIM20CLK).
+ * @param __TIM20CLKSource__ specifies the TIM20 clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
+ * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
+ */
+#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
+
+/** @brief Macro to get the TIM20 clock (TIM20CLK).
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
+ * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
+ */
+#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
+
+/**
+ * @}
+ */
+#endif /* STM32f303xE || STM32F398xx */
+
+/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
+ * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
+ * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
+ * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
+ * @retval None
+ */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
+ RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h
@@ -0,0 +1,839 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of RTC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RTC_H
+#define __STM32F3xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTC RTC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
+
+}HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
+ This parameter can be a value of @ref RTC_Hour_Formats */
+
+ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hour.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity */
+
+ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
+ corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ This parameter corresponds to a time unit range between [0-1] Second
+ with [1 Sec / SecondFraction +1] granularity.
+ This field will be used only by HAL_RTC_GetTime function */
+
+ uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+ This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+ in CR register to store the operation.
+ This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
+ This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+ uint8_t Date; /*!< Specifies the RTC Date.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
+ If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+ If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/**
+ * @brief RTC Handle Structure definition
+ */
+typedef struct
+{
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+ * @{
+ */
+#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12 RTC_CR_FMT
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+ * @{
+ */
+#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+ * @{
+ */
+#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
+#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
+#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
+/**
+ * @}
+ */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
+ * @{
+ */
+#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET RTC_CR_BCK
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
+ * @{
+ */
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+ * @{
+ */
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
+#define RTC_MONTH_MARCH ((uint8_t)0x03)
+#define RTC_MONTH_APRIL ((uint8_t)0x04)
+#define RTC_MONTH_MAY ((uint8_t)0x05)
+#define RTC_MONTH_JUNE ((uint8_t)0x06)
+#define RTC_MONTH_JULY ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+ * @{
+ */
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
+ * @{
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
+/**
+ * @}
+ */
+
+/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
+ * @{
+ */
+#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_NONE | \
+ RTC_ALARMMASK_DATEWEEKDAY | \
+ RTC_ALARMMASK_HOURS | \
+ RTC_ALARMMASK_MINUTES | \
+ RTC_ALARMMASK_SECONDS)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+ * @{
+ */
+#define RTC_ALARM_A RTC_CR_ALRAE
+#define RTC_ALARM_B RTC_CR_ALRBE
+/**
+ * @}
+ */
+
+ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+ * @{
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
+ for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are ignored in Alarm
+ comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are ignored in Alarm
+ comparison. Only SS[1:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] are ignored in Alarm
+ comparison. Only SS[2:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are ignored in Alarm
+ comparison. Only SS[3:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] are ignored in Alarm
+ comparison. Only SS[4:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] are ignored in Alarm
+ comparison. Only SS[5:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] are ignored in Alarm
+ comparison. Only SS[6:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are ignored in Alarm
+ comparison. Only SS[7:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] are ignored in Alarm
+ comparison. Only SS[8:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] are ignored in Alarm
+ comparison. Only SS[9:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] are ignored in Alarm
+ comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] are ignored in Alarm
+ comparison.Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] are ignored in Alarm
+ comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] is don't care in Alarm
+ comparison.Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match to activate alarm. */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+ * @{
+ */
+#define RTC_IT_TS RTC_CR_TSIE
+#define RTC_IT_WUT RTC_CR_WUTIE
+#define RTC_IT_ALRB RTC_CR_ALRBIE
+#define RTC_IT_ALRA RTC_CR_ALRAIE
+#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000) /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000) /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /*only for RTC_ISR flag check*/
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+ * @{
+ */
+#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
+#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
+#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
+#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
+#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
+#define RTC_FLAG_TSF RTC_ISR_TSF
+#define RTC_FLAG_WUTF RTC_ISR_WUTF
+#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
+#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
+#define RTC_FLAG_INITF RTC_ISR_INITF
+#define RTC_FLAG_RSF RTC_ISR_RSF
+#define RTC_FLAG_INITS RTC_ISR_INITS
+#define RTC_FLAG_SHPF RTC_ISR_SHPF
+#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
+#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
+#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @brief Reset RTC handle state
+ * @param __HANDLE__: RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xCA; \
+ (__HANDLE__)->Instance->WPR = 0x53; \
+ } while(0)
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->WPR = 0xFF; \
+ } while(0)
+
+/**
+ * @brief Enable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+ * @brief Disable the RTC ALARMA peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+ * @brief Enable the RTC ALARMB peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+ * @brief Disable the RTC ALARMB peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+ * @brief Enable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Alarm interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @arg RTC_FLAG_ALRAWF
+ * @arg RTC_FLAG_ALRBWF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Clear the RTC Alarm associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
+/**
+ * @}
+ */
+
+/* Include RTC HAL Extended module */
+#include "stm32f3xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ * @{
+ */
+
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ * @{
+ */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
+ RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
+ RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
+ RTC_FLAG_INITF | RTC_FLAG_RSF | \
+ RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19 /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+/**
+ * @}
+ */
+/* Private macros -----------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+ * @{
+ */
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
+ ((PM) == RTC_HOURFORMAT12_PM))
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -------------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t Value);
+uint8_t RTC_Bcd2ToByte(uint8_t Value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc_ex.h
@@ -0,0 +1,1017 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of RTC HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_RTC_EX_H
+#define __STM32F3xx_HAL_RTC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RTCEx RTCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Types RTC Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief RTC Tamper structure definition
+ */
+typedef struct
+{
+ uint32_t Tamper; /*!< Specifies the Tamper Pin.
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+
+ uint32_t Trigger; /*!< Specifies the Tamper Trigger.
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+
+ uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
+ This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
+
+ uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
+ This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
+
+ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+
+ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+
+ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
+ This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
+}RTC_TamperTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Constants RTC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup RTCEx_Output_selection_Definitions RTC Extended Output Selection Definition
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
+#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
+#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
+#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition
+ * @{
+ */
+#if RTC_BKP_NUMBER > 0
+#define RTC_BKP_DR0 ((uint32_t)0x00000000)
+#define RTC_BKP_DR1 ((uint32_t)0x00000001)
+#define RTC_BKP_DR2 ((uint32_t)0x00000002)
+#define RTC_BKP_DR3 ((uint32_t)0x00000003)
+#define RTC_BKP_DR4 ((uint32_t)0x00000004)
+#endif /* RTC_BKP_NUMBER > 0 */
+
+#if RTC_BKP_NUMBER > 5
+#define RTC_BKP_DR5 ((uint32_t)0x00000005)
+#define RTC_BKP_DR6 ((uint32_t)0x00000006)
+#define RTC_BKP_DR7 ((uint32_t)0x00000007)
+#define RTC_BKP_DR8 ((uint32_t)0x00000008)
+#define RTC_BKP_DR9 ((uint32_t)0x00000009)
+#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
+#endif /* RTC_BKP_NUMBER > 5 */
+
+#if RTC_BKP_NUMBER > 16
+#define RTC_BKP_DR16 ((uint32_t)0x00000010)
+#define RTC_BKP_DR17 ((uint32_t)0x00000011)
+#define RTC_BKP_DR18 ((uint32_t)0x00000012)
+#define RTC_BKP_DR19 ((uint32_t)0x00000013)
+#endif /* RTC_BKP_NUMBER > 16 */
+
+#if RTC_BKP_NUMBER > 20
+#define RTC_BKP_DR20 ((uint32_t)0x00000014)
+#define RTC_BKP_DR21 ((uint32_t)0x00000015)
+#define RTC_BKP_DR22 ((uint32_t)0x00000016)
+#define RTC_BKP_DR23 ((uint32_t)0x00000017)
+#define RTC_BKP_DR24 ((uint32_t)0x00000018)
+#define RTC_BKP_DR25 ((uint32_t)0x00000019)
+#define RTC_BKP_DR26 ((uint32_t)0x0000001A)
+#define RTC_BKP_DR27 ((uint32_t)0x0000001B)
+#define RTC_BKP_DR28 ((uint32_t)0x0000001C)
+#define RTC_BKP_DR29 ((uint32_t)0x0000001D)
+#define RTC_BKP_DR30 ((uint32_t)0x0000001E)
+#define RTC_BKP_DR31 ((uint32_t)0x0000001F)
+#endif /* RTC_BKP_NUMBER > 20 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition
+ * @{
+ */
+#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Extended Tamper Pins Definition
+ * @{
+ */
+#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
+#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
+#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E
+/**
+ * @}
+ */
+
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition
+ * @{
+ */
+#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
+#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
+#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definition
+ * @{
+ */
+#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8
+ consecutive samples at the active level. */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definition
+ * @{
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definition
+ * @{
+ */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Extended Tamper TimeStampOnTamperDetection Definition
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definition
+ * @{
+ */
+#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definition
+ * @{
+ */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (RTC_CR_WUCKSEL_2)
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definition
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 32s, else 2exp20 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibation
+ period is 8s, else 2exp18 RTCCLK seconds */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definition
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+/**
+ * @}
+ */
+
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definition
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
+#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definition
+ * @{
+ */
+#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Macros RTC Extended Exported Macros
+ * @{
+ */
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC Extended WakeUp Timer
+ * @{
+ */
+/**
+ * @brief Enable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
+
+/**
+ * @brief Disable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/* WAKE-UP TIMER EXTI */
+/* ------------------ */
+/**
+ * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the RTC WakeUp Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+/**
+ * @}
+ */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Extended Timestamp
+ * @{
+ */
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
+
+/**
+ * @brief Disable the RTC TimeStamp peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
+
+/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TAMPER------------------------------------*/
+/** @defgroup RTCEx_Tamper RTC Extended Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Disable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Enable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
+
+/**
+ * @brief Disable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
+
+/**
+ * @brief Enable the RTC Tamper3 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
+
+/**
+ * @brief Disable the RTC Tamper3 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
+
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+ /**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP3F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP3F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+
+/**
+ * @}
+ */
+
+/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Extended Tamper Timestamp EXTI
+ * @{
+ */
+
+/* TAMPER TIMESTAMP EXTI */
+/* --------------------- */
+/**
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+/**
+ * @}
+ */
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Extended Calibration
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
+
+/**
+ * @brief Disable the calibration output.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
+
+/**
+ * @brief Enable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
+
+/**
+ * @brief Disable the clock reference detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
+
+/**
+ * @brief Get the selected RTC shift operation's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
+ * @retval None
+ */
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+ * @{
+ */
+
+/* RTC TimeStamp and Tamper functions *****************************************/
+/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
+
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* RTC Wake-up functions ******************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Extended Control functions ************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @{
+ */
+
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
+/**
+ * @}
+ */
+
+/* Extended RTC features functions *******************************************/
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+ * @{
+ */
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+
+
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_RTC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h
@@ -0,0 +1,706 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sdadc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file contains all the functions prototypes for the SDADC
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_SDADC_H
+#define __STM32F3xx_SDADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SDADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SDADC_Exported_Types SDADC Exported Types
+ * @{
+ */
+
+
+/**
+ * @brief HAL SDADC States definition
+ */
+typedef enum
+{
+ HAL_SDADC_STATE_RESET = 0x00, /*!< SDADC not initialized */
+ HAL_SDADC_STATE_READY = 0x01, /*!< SDADC initialized and ready for use */
+ HAL_SDADC_STATE_CALIB = 0x02, /*!< SDADC calibration in progress */
+ HAL_SDADC_STATE_REG = 0x03, /*!< SDADC regular conversion in progress */
+ HAL_SDADC_STATE_INJ = 0x04, /*!< SDADC injected conversion in progress */
+ HAL_SDADC_STATE_REG_INJ = 0x05, /*!< SDADC regular and injected conversions in progress */
+ HAL_SDADC_STATE_ERROR = 0xFF, /*!< SDADC state error */
+}HAL_SDADC_StateTypeDef;
+
+/**
+ * @brief SDADC Init Structure definition
+ */
+typedef struct
+{
+ uint32_t IdleLowPowerMode; /*!< Specifies if SDADC can enter in power down or standby when idle.
+ This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
+ uint32_t FastConversionMode; /*!< Specifies if Fast conversion mode is enabled or not.
+ This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
+ uint32_t SlowClockMode; /*!< Specifies if slow clock mode is enabled or not.
+ This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
+ uint32_t ReferenceVoltage; /*!< Specifies the reference voltage.
+ Note: This parameter is common to all SDADC instances.
+ This parameter can be a value of @ref SDADC_Reference_Voltage */
+}SDADC_InitTypeDef;
+
+/**
+ * @brief SDADC handle Structure definition
+ */
+typedef struct
+{
+ SDADC_TypeDef *Instance; /*!< SDADC registers base address */
+ SDADC_InitTypeDef Init; /*!< SDADC init parameters */
+ DMA_HandleTypeDef *hdma; /*!< SDADC DMA Handle parameters */
+ uint32_t RegularContMode; /*!< Regular conversion continuous mode */
+ uint32_t InjectedContMode; /*!< Injected conversion continuous mode */
+ uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
+ uint32_t InjConvRemaining; /*!< Injected conversion remaining */
+ uint32_t RegularTrigger; /*!< Current trigger used for regular conversion */
+ uint32_t InjectedTrigger; /*!< Current trigger used for injected conversion */
+ uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
+ uint32_t RegularMultimode; /*!< current type of regular multimode */
+ uint32_t InjectedMultimode; /*!< Current type of injected multimode */
+ HAL_SDADC_StateTypeDef State; /*!< SDADC state */
+ uint32_t ErrorCode; /*!< SDADC Error code */
+}SDADC_HandleTypeDef;
+
+/**
+ * @brief SDADC Configuration Register Parameter Structure
+ */
+typedef struct
+{
+ uint32_t InputMode; /*!< Specifies the input mode (single ended, differential...)
+ This parameter can be any value of @ref SDADC_InputMode */
+ uint32_t Gain; /*!< Specifies the gain setting.
+ This parameter can be any value of @ref SDADC_Gain */
+ uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2).
+ This parameter can be any value of @ref SDADC_CommonMode */
+ uint32_t Offset; /*!< Specifies the 12-bit offset value.
+ This parameter can be any value lower or equal to 0x00000FFF */
+}SDADC_ConfParamTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDADC_Exported_Constants SDADC Exported Constants
+ * @{
+ */
+
+/** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
+ * @{
+ */
+#define SDADC_LOWPOWER_NONE ((uint32_t)0x00000000)
+#define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
+#define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
+ * @{
+ */
+#define SDADC_FAST_CONV_DISABLE ((uint32_t)0x00000000)
+#define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
+ * @{
+ */
+#define SDADC_SLOW_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
+ * @{
+ */
+#define SDADC_VREF_EXT ((uint32_t)0x00000000) /*!< The reference voltage is forced externally using VREF pin */
+#define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */
+#define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */
+#define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ConfIndex SDADC Configuration Index
+ * @{
+ */
+
+#define SDADC_CONF_INDEX_0 ((uint32_t)0x00000000) /*!< Configuration 0 Register selected */
+#define SDADC_CONF_INDEX_1 ((uint32_t)0x00000001) /*!< Configuration 1 Register selected */
+#define SDADC_CONF_INDEX_2 ((uint32_t)0x00000002) /*!< Configuration 2 Register selected */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_InputMode SDADC Input Mode
+ * @{
+ */
+#define SDADC_INPUT_MODE_DIFF ((uint32_t)0x00000000) /*!< Conversions are executed in differential mode */
+#define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */
+#define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Gain SDADC Gain
+ * @{
+ */
+#define SDADC_GAIN_1 ((uint32_t)0x00000000) /*!< Gain equal to 1 */
+#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2 */
+#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4 */
+#define SDADC_GAIN_8 ((uint32_t)0x00300000) /*!< Gain equal to 8 */
+#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16 */
+#define SDADC_GAIN_32 ((uint32_t)0x00500000) /*!< Gain equal to 32 */
+#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1/2 */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_CommonMode SDADC Common Mode
+ * @{
+ */
+#define SDADC_COMMON_MODE_VSSA ((uint32_t)0x00000000) /*!< Select SDADC VSSA as common mode */
+#define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
+#define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup SDADC_Channel_Selection SDADC Channel Selection
+ * @{
+ */
+
+/* SDADC Channels ------------------------------------------------------------*/
+/* The SDADC channels are defined as follows:
+ - in 16-bit LSB the channel mask is set
+ - in 16-bit MSB the channel number is set
+ e.g. for channel 5 definition:
+ - the channel mask is 0x00000020 (bit 5 is set)
+ - the channel number 5 is 0x00050000
+ --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
+#define SDADC_CHANNEL_0 ((uint32_t)0x00000001)
+#define SDADC_CHANNEL_1 ((uint32_t)0x00010002)
+#define SDADC_CHANNEL_2 ((uint32_t)0x00020004)
+#define SDADC_CHANNEL_3 ((uint32_t)0x00030008)
+#define SDADC_CHANNEL_4 ((uint32_t)0x00040010)
+#define SDADC_CHANNEL_5 ((uint32_t)0x00050020)
+#define SDADC_CHANNEL_6 ((uint32_t)0x00060040)
+#define SDADC_CHANNEL_7 ((uint32_t)0x00070080)
+#define SDADC_CHANNEL_8 ((uint32_t)0x00080100)
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
+ * @{
+ */
+#define SDADC_CALIBRATION_SEQ_1 ((uint32_t)0x00000000) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
+#define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
+#define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
+ * @{
+ */
+#define SDADC_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */
+#define SDADC_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Trigger SDADC Trigger
+ * @{
+ */
+#define SDADC_SOFTWARE_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */
+#define SDADC_SYNCHRONOUS_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
+#define SDADC_EXTERNAL_TRIGGER ((uint32_t)0x00000002) /*!< External trigger */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
+ * @{
+ */
+#define SDADC_EXT_TRIG_TIM13_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM14_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM16_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM17_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM12_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM12_CC2 ((uint32_t)0x00000100) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM15_CC2 ((uint32_t)0x00000200) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM2_CC3 ((uint32_t)0x00000200) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM2_CC4 ((uint32_t)0x00000200) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM3_CC1 ((uint32_t)0x00000300) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM3_CC2 ((uint32_t)0x00000300) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM3_CC3 ((uint32_t)0x00000300) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM4_CC1 ((uint32_t)0x00000400) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM4_CC2 ((uint32_t)0x00000400) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM4_CC3 ((uint32_t)0x00000400) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM19_CC2 ((uint32_t)0x00000500) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM19_CC3 ((uint32_t)0x00000500) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM19_CC4 ((uint32_t)0x00000500) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_EXTI11 ((uint32_t)0x00000700) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+#define SDADC_EXT_TRIG_EXTI15 ((uint32_t)0x00000600) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
+ * @{
+ */
+#define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0 /*!< External rising edge */
+#define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1 /*!< External falling edge */
+#define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN /*!< External rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
+ * @{
+ */
+#define SDADC_INJECTED_DELAY_NONE ((uint32_t)0x00000000) /*!< No delay on injected conversion */
+#define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_MultimodeType SDADC Multimode Type
+ * @{
+ */
+#define SDADC_MULTIMODE_SDADC1_SDADC2 ((uint32_t)0x00000000) /*!< Get conversion values for SDADC1 and SDADC2 */
+#define SDADC_MULTIMODE_SDADC1_SDADC3 ((uint32_t)0x00000001) /*!< Get conversion values for SDADC1 and SDADC3 */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_ErrorCode SDADC Error Code
+ * @{
+ */
+#define SDADC_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define SDADC_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */
+#define SDADC_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */
+#define SDADC_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_interrupts_definition SDADC interrupts definition
+ * @{
+ */
+#define SDADC_IT_EOCAL SDADC_CR1_EOCALIE /*!< End of calibration interrupt enable */
+#define SDADC_IT_JEOC SDADC_CR1_JEOCIE /*!< Injected end of conversion interrupt enable */
+#define SDADC_IT_JOVR SDADC_CR1_JOVRIE /*!< Injected data overrun interrupt enable */
+#define SDADC_IT_REOC SDADC_CR1_REOCIE /*!< Regular end of conversion interrupt enable */
+#define SDADC_IT_ROVR SDADC_CR1_ROVRIE /*!< Regular data overrun interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_flags_definition SDADC flags definition
+ * @{
+ */
+#define SDADC_FLAG_EOCAL SDADC_ISR_EOCALF /*!< End of calibration flag */
+#define SDADC_FLAG_JEOC SDADC_ISR_JEOCF /*!< End of injected conversion flag */
+#define SDADC_FLAG_JOVR SDADC_ISR_JOVRF /*!< Injected conversion overrun flag */
+#define SDADC_FLAG_REOC SDADC_ISR_REOCF /*!< End of regular conversion flag */
+#define SDADC_FLAG_ROVR SDADC_ISR_ROVRF /*!< Regular conversion overrun flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SDADC_Exported_Macros SDADC Exported Macros
+ * @{
+ */
+
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/** @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
+ * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
+ * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
+ * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
+ * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
+ * @retval None
+ */
+#define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
+ * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
+ * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
+ * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
+ * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
+ * @retval None
+ */
+#define __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_IT_EOCAL: End of calibration interrupt enable
+ * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
+ * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
+ * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
+ * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_FLAG_EOCAL: End of calibration flag
+ * @arg SDADC_FLAG_JEOC: End of injected conversion flag
+ * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
+ * @arg SDADC_FLAG_REOC: End of regular conversion flag
+ * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
+ * @retval None
+ */
+#define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg SDADC_FLAG_EOCAL: End of calibration flag
+ * @arg SDADC_FLAG_JEOC: End of injected conversion flag
+ * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
+ * @arg SDADC_FLAG_REOC: End of regular conversion flag
+ * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
+ * @retval None
+ */
+#define __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
+
+/** @brief Reset SDADC handle state
+ * @param __HANDLE__: SDADC handle.
+ * @retval None
+ */
+#define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SDADC_Private_Macros SDADC Private Macros
+ * @{
+ */
+
+#define IS_SDADC_LOWPOWER_MODE(LOWPOWER) (((LOWPOWER) == SDADC_LOWPOWER_NONE) || \
+ ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
+ ((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
+
+#define IS_SDADC_FAST_CONV_MODE(FAST) (((FAST) == SDADC_FAST_CONV_DISABLE) || \
+ ((FAST) == SDADC_FAST_CONV_ENABLE))
+
+#define IS_SDADC_SLOW_CLOCK_MODE(MODE) (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
+ ((MODE) == SDADC_SLOW_CLOCK_ENABLE))
+
+#define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_EXT) || \
+ ((VREF) == SDADC_VREF_VREFINT1) || \
+ ((VREF) == SDADC_VREF_VREFINT2) || \
+ ((VREF) == SDADC_VREF_VDDA))
+
+#define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0) || \
+ ((CONF) == SDADC_CONF_INDEX_1) || \
+ ((CONF) == SDADC_CONF_INDEX_2))
+
+#define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF) || \
+ ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
+ ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
+
+#define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1) || \
+ ((GAIN) == SDADC_GAIN_2) || \
+ ((GAIN) == SDADC_GAIN_4) || \
+ ((GAIN) == SDADC_GAIN_8) || \
+ ((GAIN) == SDADC_GAIN_16) || \
+ ((GAIN) == SDADC_GAIN_32) || \
+ ((GAIN) == SDADC_GAIN_1_2))
+
+#define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA) || \
+ ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
+ ((MODE) == SDADC_COMMON_MODE_VDDA))
+
+#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFF)
+
+/* Just one channel of the 9 channels can be selected for regular conversion */
+#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \
+ ((CHANNEL) == SDADC_CHANNEL_1) || \
+ ((CHANNEL) == SDADC_CHANNEL_2) || \
+ ((CHANNEL) == SDADC_CHANNEL_3) || \
+ ((CHANNEL) == SDADC_CHANNEL_4) || \
+ ((CHANNEL) == SDADC_CHANNEL_5) || \
+ ((CHANNEL) == SDADC_CHANNEL_6) || \
+ ((CHANNEL) == SDADC_CHANNEL_7) || \
+ ((CHANNEL) == SDADC_CHANNEL_8))
+
+/* Any or all of the 9 channels can be selected for injected conversion */
+#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F01FF))
+
+
+#define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \
+ ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2) || \
+ ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
+
+#define IS_SDADC_CONTINUOUS_MODE(MODE) (((MODE) == SDADC_CONTINUOUS_CONV_OFF) || \
+ ((MODE) == SDADC_CONTINUOUS_CONV_ON))
+
+
+#define IS_SDADC_REGULAR_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
+ ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
+
+#define IS_SDADC_INJECTED_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
+ ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER) || \
+ ((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
+
+
+#define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
+ ((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
+
+#define IS_SDADC_EXT_TRIG_EDGE(TRIGGER) (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE) || \
+ ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE) || \
+ ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
+
+
+#define IS_SDADC_INJECTED_DELAY(DELAY) (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
+ ((DELAY) == SDADC_INJECTED_DELAY))
+
+#define IS_SDADC_MULTIMODE_TYPE(TYPE) (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
+ ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
+ * @{
+ */
+
+/** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
+void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t ConfIndex,
+ SDADC_ConfParamTypeDef* ConfParamStruct);
+HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ConfIndex);
+HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode);
+HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode);
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedExtTrigger,
+ uint32_t ExtTriggerEdge);
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedDelay);
+HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
+HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
+
+HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
+
+HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
+
+HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
+
+uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
+uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
+uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
+uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
+
+void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
+
+HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
+
+void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
+void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
+uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_SDADC_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard.h
@@ -0,0 +1,1015 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of SMARTCARD HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SMARTCARD_H
+#define __STM32F3xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARD
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+ * @{
+ */
+
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
+ The baud rate register is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits.
+ Only 1.5 stop bits are authorized in SmartCard mode. */
+
+ uint16_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref SMARTCARD_Parity
+ @note The parity is enabled by default (PCE is forced to 1).
+ Since the WordLength is forced to 8 bits + parity, M is
+ forced to 1 and the parity bit is the 9th bit. */
+
+ uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref SMARTCARD_Mode */
+
+ uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+ uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+ uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */
+
+ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */
+
+ uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
+ in case of parity error.
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
+ This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
+ it is used to implement the Character Wait Time (CWT) and
+ Block Wait Time (BWT). It is coded over 24 bits. */
+
+ uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+ This parameter can be any value from 0x0 to 0xFF */
+
+ uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
+ receive and transmit mode). When set to 0, retransmission is
+ disabled. Otherwise, its maximum value is 7 (before signalling
+ an error) */
+
+}SMARTCARD_InitTypeDef;
+
+/**
+ * @brief SMARTCARD advanced features initalization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
+ advanced features may be initialized at the same time. This parameter
+ can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref SMARTCARD_MSB_First */
+}SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
+
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code
+ This parameter can be a value of @ref SMARTCARD_Error */
+
+}SMARTCARD_HandleTypeDef;
+
+/**
+ * @brief SMARTCARD clock sources
+ */
+typedef enum
+{
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+}SMARTCARD_ClockSourceTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Error SMARTCARD Error
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020) /*!< Receiver TimeOut error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+ * @{
+ */
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits
+ * @{
+ */
+#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+ * @{
+ */
+#define SMARTCARD_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+ * @{
+ */
+#define SMARTCARD_MODE_RX ((uint16_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX ((uint16_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW ((uint16_t)0x0000)
+#define SMARTCARD_POLARITY_HIGH ((uint16_t)USART_CR2_CPOL)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+ * @{
+ */
+#define SMARTCARD_PHASE_1EDGE ((uint16_t)0x0000)
+#define SMARTCARD_PHASE_2EDGE ((uint16_t)USART_CR2_CPHA)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+ * @{
+ */
+#define SMARTCARD_LASTBIT_DISABLE ((uint16_t)0x0000)
+#define SMARTCARD_LASTBIT_ENABLE ((uint16_t)USART_CR2_LBCL)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+ * @{
+ */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint16_t)0x0000)
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint16_t)USART_CR3_ONEBIT)
+/**
+ * @}
+ */
+
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLE ((uint16_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE ((uint16_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+ * @{
+ */
+#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
+#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
+#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
+#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
+#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
+#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
+#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
+#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
+#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
+#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)
+#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
+#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
+#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
+#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+
+#define SMARTCARD_IT_PE ((uint16_t)0x0028)
+#define SMARTCARD_IT_TXE ((uint16_t)0x0727)
+#define SMARTCARD_IT_TC ((uint16_t)0x0626)
+#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)
+#define SMARTCARD_IT_IDLE ((uint16_t)0x0424)
+
+#define SMARTCARD_IT_ERR ((uint16_t)0x0060)
+#define SMARTCARD_IT_ORE ((uint16_t)0x0300)
+#define SMARTCARD_IT_NE ((uint16_t)0x0200)
+#define SMARTCARD_IT_FE ((uint16_t)0x0100)
+
+#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
+#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+ * @{
+ */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< Idle line detected clear flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
+ * @{
+ */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
+ * @{
+ */
+#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
+ * @{
+ */
+#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+ * @{
+ */
+#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+ * @{
+ */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMARTCARD handle state.
+ * @param __HANDLE__: SMARTCARD handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
+/** @brief Flush the Smartcard Data registers.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+
+/** @brief Clear the specified SMARTCARD pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag
+ * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag
+ * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag
+ * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag
+ * @arg SMARTCARD_CLEAR_IDLEF: Idle line detected clear flag
+ * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag
+ * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag
+ * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief Check whether the specified Smartcard flag is set or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
+ * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
+ * @arg SMARTCARD_FLAG_BUSY: Busy flag
+ * @arg SMARTCARD_FLAG_EOBF: End of block flag
+ * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
+ * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
+ * @arg SMARTCARD_FLAG_TC: Transmission complete flag
+ * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
+ * @arg SMARTCARD_FLAG_IDLE: Idle line detection flag
+ * @arg SMARTCARD_FLAG_ORE: Overrun error flag
+ * @arg SMARTCARD_FLAG_NE: Noise error flag
+ * @arg SMARTCARD_FLAG_FE: Framing error flag
+ * @arg SMARTCARD_FLAG_PE: Parity error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief Enable the specified SmartCard interrupt.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief Disable the specified SmartCard interrupt.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+
+/** @brief Check whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __IT__: specifies the SMARTCARD interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ORE: Overrun error interrupt
+ * @arg SMARTCARD_IT_NE: Noise error interrupt
+ * @arg SMARTCARD_IT_FE: Framing error interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __IT__: specifies the SMARTCARD interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ORE: Overrun error interrupt
+ * @arg SMARTCARD_IT_NE: Noise error interrupt
+ * @arg SMARTCARD_IT_FE: Framing error interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
+
+
+/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag
+ * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag
+ * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag
+ * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag
+ * @arg SMARTCARD_CLEAR_IDLEF: Idle line detection clear flag
+ * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag
+ * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag
+ * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific SMARTCARD request flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
+ * @param __REQ__: specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive data flush Request
+ * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the SMARTCARD one bit sample method.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the SMARTCARD one bit sample method.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable the USART associated to the SMARTCARD Handle
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
+ * @retval None
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+
+/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the
+ * maximum clock on F3 (i.e. 72 MHz) divided by the oversampling used
+ * on the SMARTCARD (i.e. 16).
+ * @param __BAUDRATE__: Baud rate set by the configuration function.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
+
+/** @brief Check the block length range.
+ * @note The maximum SMARTCARD block length is 0xFF.
+ * @param __LENGTH__: block length.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__: receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
+
+/** @brief Check the SMARTCARD autoretry counter value.
+ * @note The maximum number of retransmissions is 0x7.
+ * @param __COUNT__: number of retransmissions.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
+
+/**
+ * @brief Ensure that SMARTCARD frame length is valid.
+ * @param __LENGTH__: SMARTCARD frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/**
+ * @brief Ensure that SMARTCARD frame number of stop bits is valid.
+ * @param __STOPBITS__: SMARTCARD frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
+
+/**
+ * @brief Ensure that SMARTCARD frame parity is valid.
+ * @param __PARITY__: SMARTCARD frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+ ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/**
+ * @brief Ensure that SMARTCARD communication mode is valid.
+ * @param __MODE__: SMARTCARD communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
+
+/**
+ * @brief Ensure that SMARTCARD frame polarity is valid.
+ * @param __CPOL__: SMARTCARD frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that SMARTCARD frame phase is valid.
+ * @param __CPHA__: SMARTCARD frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/**
+ * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame sampling is valid.
+ * @param __ONEBIT__: SMARTCARD frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD NACK transmission setting is valid.
+ * @param __NACK__: SMARTCARD NACK transmission setting.
+ * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+ */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+ ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/**
+ * @brief Ensure that SMARTCARD receiver timeout setting is valid.
+ * @param __TIMEOUT__: SMARTCARD receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD advanced features initialization is valid.
+ * @param __INIT__: SMARTCARD advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+ * @param __TXINV__: SMARTCARD frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+ * @param __RXINV__: SMARTCARD frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame data inversion setting is valid.
+ * @param __DATAINV__: SMARTCARD frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+ * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame overrun setting is valid.
+ * @param __OVERRUN__: SMARTCARD frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+ * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that SMARTCARD frame MSB first setting is valid.
+ * @param __MSBFIRST__: SMARTCARD frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD request parameter is valid.
+ * @param __PARAM__: SMARTCARD request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @}
+ */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32f3xx_hal_smartcard_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smartcard_ex.h
@@ -0,0 +1,234 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of SMARTCARD HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SMARTCARD_EX_H
+#define __STM32F3xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMARTCARDEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Extended_Exported_Macros SMARTCARDEx Exported Macros
+ * @{
+ */
+
+/** @brief Reports the SMARTCARD clock source.
+ * @param __HANDLE__: specifies the SMARTCARD Handle
+ * @param __CLOCKSOURCE__ : output variable
+ * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#else
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#endif
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/* Peripheral State and Error functions ***************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_smbus.h
@@ -0,0 +1,664 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smbus.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of SMBUS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SMBUS_H
+#define __STM32F3xx_HAL_SMBUS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
+ * @{
+ */
+
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
+ * @brief SMBUS Configuration Structure definition
+ * @{
+ */
+typedef struct
+{
+ uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
+ This parameter can be a value of @ref SMBUS_Analog_Filter */
+
+ uint32_t OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
+ This parameter can be a value of @ref SMBUS_addressing_mode */
+
+ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
+ This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+
+ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
+ This parameter can be a 7-bit address. */
+
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref SMBUS_own_address2_masks. */
+
+ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
+ This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+
+ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
+ This parameter can be a value of @ref SMBUS_nostretch_mode */
+
+ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
+ This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+
+ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
+ This parameter can be a value of @ref SMBUS_peripheral_mode */
+
+ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
+ (Enable bits and different timeout values)
+ This parameter calculated by referring to SMBUS initialization
+ section in Reference manual */
+} SMBUS_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_state_definition HAL state definition
+ * @brief HAL State definition
+ * @{
+ */
+#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+ * @brief SMBUS Error Code definition
+ * @{
+ */
+#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
+ * @brief SMBUS handle Structure definition
+ * @{
+ */
+typedef struct
+{
+ I2C_TypeDef *Instance; /*!< SMBUS registers base address */
+
+ SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
+
+ uint16_t XferSize; /*!< SMBUS transfer size */
+
+ __IO uint16_t XferCount; /*!< SMBUS transfer counter */
+
+ __IO uint32_t XferOptions; /*!< SMBUS transfer options */
+
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
+
+ HAL_LockTypeDef Lock; /*!< SMBUS locking object */
+
+ __IO uint32_t State; /*!< SMBUS communication state */
+
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code */
+
+}SMBUS_HandleTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
+ * @{
+ */
+#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
+ * @{
+ */
+#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
+#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
+ * @{
+ */
+
+#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks
+ * @{
+ */
+
+#define SMBUS_OA2_NOMASK ((uint8_t)0x00)
+#define SMBUS_OA2_MASK01 ((uint8_t)0x01)
+#define SMBUS_OA2_MASK02 ((uint8_t)0x02)
+#define SMBUS_OA2_MASK03 ((uint8_t)0x03)
+#define SMBUS_OA2_MASK04 ((uint8_t)0x04)
+#define SMBUS_OA2_MASK05 ((uint8_t)0x05)
+#define SMBUS_OA2_MASK06 ((uint8_t)0x06)
+#define SMBUS_OA2_MASK07 ((uint8_t)0x07)
+/**
+ * @}
+ */
+
+
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+ * @{
+ */
+#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+ * @{
+ */
+#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
+ * @{
+ */
+#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
+ * @{
+ */
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+ * @{
+ */
+
+#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
+#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
+#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
+#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
+ * @{
+ */
+
+#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
+#define SMBUS_GENERATE_STOP I2C_CR2_STOP
+#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+ * @{
+ */
+
+#define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
+#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
+#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
+#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
+ * @brief SMBUS Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define SMBUS_IT_ERRI I2C_CR1_ERRIE
+#define SMBUS_IT_TCI I2C_CR1_TCIE
+#define SMBUS_IT_STOPI I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI I2C_CR1_RXIE
+#define SMBUS_IT_TXI I2C_CR1_TXIE
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXXXXXX : Flag mask
+ * @{
+ */
+
+#define SMBUS_FLAG_TXE I2C_ISR_TXE
+#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
+#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
+#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
+#define SMBUS_FLAG_AF I2C_ISR_NACKF
+#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
+#define SMBUS_FLAG_TC I2C_ISR_TC
+#define SMBUS_FLAG_TCR I2C_ISR_TCR
+#define SMBUS_FLAG_BERR I2C_ISR_BERR
+#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
+#define SMBUS_FLAG_OVR I2C_ISR_OVR
+#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
+#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
+#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
+#define SMBUS_FLAG_DIR I2C_ISR_DIR
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
+ * @{
+ */
+
+/** @brief Reset SMBUS handle state.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+
+/** @brief Enable the specified SMBUS interrupts.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified SMBUS interrupts.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
+ * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
+ * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
+ * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
+ * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
+ * @arg @ref SMBUS_IT_RXI RX interrupt enable
+ * @arg @ref SMBUS_IT_TXI TX interrupt enable
+ *
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SMBUS flag is set or not.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
+ * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
+ * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
+ * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
+ * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
+ * @arg @ref SMBUS_FLAG_BERR Bus error
+ * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref SMBUS_FLAG_ALERT SMBus alert
+ * @arg @ref SMBUS_FLAG_BUSY Bus busy
+ * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @param __FLAG__ specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
+ * @arg @ref SMBUS_FLAG_BERR Bus error
+ * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
+ * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref SMBUS_FLAG_ALERT SMBus alert
+ *
+ * @retval None
+ */
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Enable the specified SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Disable the specified SMBUS peripheral.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+ * @param __HANDLE__ specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+ * @{
+ */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
+ ((MASK) == SMBUS_OA2_MASK01) || \
+ ((MASK) == SMBUS_OA2_MASK02) || \
+ ((MASK) == SMBUS_OA2_MASK03) || \
+ ((MASK) == SMBUS_OA2_MASK04) || \
+ ((MASK) == SMBUS_OA2_MASK05) || \
+ ((MASK) == SMBUS_OA2_MASK06) || \
+ ((MASK) == SMBUS_OA2_MASK07))
+
+#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
+ ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
+#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f3xx_hal_smbus.c file */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+
+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_SMBUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h
@@ -0,0 +1,687 @@
+ /**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SPI_H
+#define __STM32F3xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_Mode */
+
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ This parameter can be a value of @ref SPI_Direction */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_Data_Size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
+ This parameter can be a value of @ref SPI_TI_mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ CRC Length is only used with Data8 and Data16, not other data size
+ This parameter can be a value of @ref SPI_CRC_length */
+
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ This parameter can be a value of @ref SPI_NSSP_Mode
+ This mode is activated by the NSSP bit in the SPIx_CR2 register and
+ it takes effect only if the SPI interface is configured as Motorola SPI
+ master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
+ CPOL setting is ignored).. */
+} SPI_InitTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
+}HAL_SPI_StateTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /* SPI registers base address */
+
+ SPI_InitTypeDef Init; /* SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SPI Tx Transfer size */
+
+ uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SPI Rx Transfer size */
+
+ uint16_t RxXferCount; /* SPI Rx Transfer Counter */
+
+ uint32_t CRCSize; /* SPI CRC size used for the transfer */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /* Locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
+
+ uint32_t ErrorCode; /* SPI Error code */
+
+}SPI_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_Error_Code SPI Error Code
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */
+#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknown error */
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_Mode SPI Mode
+ * @{
+ */
+#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+ * @{
+ */
+#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */
+#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */
+#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */
+#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */
+#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */
+#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */
+#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */
+#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */
+#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */
+#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */
+#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */
+#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */
+#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_9BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_7BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_6BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_5BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_4BIT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */
+#define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SPI Phase 1EDGE */
+#define SPI_PHASE_2EDGE SPI_CR1_CPHA /*!< SPI Phase 2EDGE */
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+ * @{
+ */
+#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+ ((NSSP) == SPI_NSS_PULSE_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_mode SPI TI mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+ * SPI_CRC_LENGTH_8BIT : CRC 8bit
+ * SPI_CRC_LENGTH_16BIT : CRC 16bit
+ */
+#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
+#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
+#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
+ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
+ * @{
+ * This parameter can be one of the following values:
+ * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+ * RXNE event is generated if the FIFO
+ * level is greater or equal to 1/2(16-bits).
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+ * level is greater or equal to 1/4(8 bits). */
+#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
+ * @brief SPI Interrupt definition
+ * Elements values convention: 0xXXXXXXXX
+ * - XXXXXXXX : Interrupt control mask
+ * @{
+ */
+#define SPI_IT_TXE SPI_CR2_TXEIE
+#define SPI_IT_RXNE SPI_CR2_RXNEIE
+#define SPI_IT_ERR SPI_CR2_ERRIE
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_Flag_definition SPI Flag definition
+ * @brief Flag definition
+ * Elements values convention: 0xXXXXYYYY
+ * - XXXX : Flag register Index
+ * - YYYY : Flag mask
+ * @{
+ */
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
+ * @{
+ */
+#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
+#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
+#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
+#define SPI_FTLVL_FULL ((uint32_t)0x1800)
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+ * @{
+ */
+#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
+#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
+#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
+#define SPI_FRLVL_FULL ((uint32_t)0x0600)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__: SPI handle.
+ * @retval None
+ */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief Enable or disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ *
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ *
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ *
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+
+/**
+ * @}
+ */
+
+/* Include SPI HAL Extended module */
+#include "stm32f3xx_hal_spi_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/** @addtogroup SPI_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SPI_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SPI_Exported_Functions_Group3
+ * @{
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h
@@ -0,0 +1,93 @@
+ /**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of SPI HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SPI_EX_H
+#define __STM32F3xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SPI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sram.h
@@ -0,0 +1,202 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sram.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of SRAM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_SRAM_H
+#define __STM32F3xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+ #include "stm32f3xx_ll_fmc.h"
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SRAM
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+ * @{
+ */
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
+
+}HAL_SRAM_StateTypeDef;
+
+/**
+ * @brief SRAM handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< SRAM locking object */
+
+ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
+
+ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
+
+}SRAM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+ * @{
+ */
+
+/** @brief Reset SRAM handle state
+ * @param __HANDLE__: SRAM handle
+ * @retval None
+ */
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+ * @{
+ */
+
+/* SRAM Control functions ****************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+
+/* SRAM Peripheral State functions ********************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_SRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h
@@ -0,0 +1,1580 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_TIM_H
+#define __STM32F3xx_HAL_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+
+/**
+ * @brief TIM Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClockConfigTypeDef;
+
+/**
+ * @brief TIM Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIMEx_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter can be a value of @ref TIM_ClearInput_Prescaler */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+}TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct {
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIMEx_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+}TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+}HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+}HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+typedef struct
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref TIM_DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+}TIM_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
+#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
+#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
+#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
+ * @{
+ */
+#define TIM_IT_UPDATE (TIM_DIER_UIE)
+#define TIM_IT_CC1 (TIM_DIER_CC1IE)
+#define TIM_IT_CC2 (TIM_DIER_CC2IE)
+#define TIM_IT_CC3 (TIM_DIER_CC3IE)
+#define TIM_IT_CC4 (TIM_DIER_CC4IE)
+#define TIM_IT_COM (TIM_DIER_COMIE)
+#define TIM_IT_TRIGGER (TIM_DIER_TIE)
+#define TIM_IT_BREAK (TIM_DIER_BIE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+#define TIM_DMA_UPDATE (TIM_DIER_UDE)
+#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
+#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
+#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
+#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
+#define TIM_DMA_COM (TIM_DIER_COMDE)
+#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE (TIM_SR_UIF)
+#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
+#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
+#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
+#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
+#define TIM_FLAG_COM (TIM_SR_COMIF)
+#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
+#define TIM_FLAG_BREAK (TIM_SR_BIF)
+#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
+#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
+#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
+#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
+#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
+#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
+#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
+#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+/**
+ * @}
+ */
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
+ * @{
+ */
+#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
+#define TIM_TS_ETRF ((uint32_t)0x0070)
+#define TIM_TS_NONE ((uint32_t)0xFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+ /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
+ * @{
+ */
+#define TIM_CCx_ENABLE ((uint32_t)0x0001)
+#define TIM_CCx_DISABLE ((uint32_t)0x0000)
+#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
+#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private Constants -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+/** @brief Set TIM IC prescaler
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @param __ICPSC__: specifies the prescaler value.
+ * @retval None
+ */
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+/** @brief Reset TIM IC prescaler
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+
+/** @brief Set TIM IC polarity
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @param __POLARITY__: specifies TIM Channel Polarity
+ * @retval None
+ */
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
+
+/** @brief Reset TIM IC polarity
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/* Private Functions --------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset TIM handle state
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
+
+/**
+ * @brief Enables the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Enables the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/**
+ * @brief Disables the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/**
+ * @brief Checks whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the specified TIM interrupt flag.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+ * @brief Checks whether the specified TIM interrupt has occurred or not.
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the TIM interrupt source to check.
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TIM interrupt pending bits
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @retval None
+ */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter
+ * @param __HANDLE__: TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+ * @brief Sets the TIM active prescaler register value on update event.
+ * @param __HANDLE__: TIM handle.
+ * @param __PRESC__: specifies the active prescaler register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+ * @brief Sets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __COUNTER__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
+ ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __AUTORELOAD__: specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
+ ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Sets the TIM Clock Division value on runtime without calling
+ * another time any Init function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CKD__: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1
+ * @arg TIM_CLOCKDIVISION_DIV2
+ * @arg TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Clock Division value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @brief Gets the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval None
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
+ * @param __HANDLE__: TIM handle.
+ * @note When the USR bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * (+) Counter overflow/underflow
+ * (+) Setting the UG bit
+ * (+) Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+
+/**
+ * @brief Sets the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__: Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+
+/**
+ * @}
+ */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32f3xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Output Compare functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3
+ * @{
+ */
+/* Timer PWM functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Input Capture functions ***********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5
+ * @{
+ */
+/* Timer One Pulse functions ***************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6
+ * @{
+ */
+/* Timer Encoder functions *****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7
+ * @{
+ */
+/* Interrupt Handler functions **********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group8
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
+ uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group9
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group10
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h
@@ -0,0 +1,1118 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of TIM HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_TIM_EX_H
+#define __STM32F3xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
+ * output
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
+ * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t BreakFilter; /*!< Specifies the brek input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Break2State; /*!< TIM Break2 State
+ This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity
+ This parameter can be a value of @ref TIMEx_Break2_Polarity */
+ uint32_t Break2Filter; /*!< TIM break2 input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note Advanced timers provide TRGO2 internal line which is redirected
+ * to the ADC
+ */
+typedef struct {
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
+ This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode */
+}TIM_MasterConfigTypeDef;
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
+ * @{
+ */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup TIMEx_Channel TIMEx Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define TIM_CHANNEL_3 ((uint32_t)0x0008)
+#define TIM_CHANNEL_4 ((uint32_t)0x000C)
+#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
+#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET ((uint16_t)0x0004)
+#define TIM_SLAVEMODE_GATED ((uint16_t)0x0005)
+#define TIM_SLAVEMODE_TRIGGER ((uint16_t)0x0006)
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint16_t)0x0007)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Event_Source TIMEx Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 (0x00000000)
+#define TIM_DMABASE_CR2 (0x00000001)
+#define TIM_DMABASE_SMCR (0x00000002)
+#define TIM_DMABASE_DIER (0x00000003)
+#define TIM_DMABASE_SR (0x00000004)
+#define TIM_DMABASE_EGR (0x00000005)
+#define TIM_DMABASE_CCMR1 (0x00000006)
+#define TIM_DMABASE_CCMR2 (0x00000007)
+#define TIM_DMABASE_CCER (0x00000008)
+#define TIM_DMABASE_CNT (0x00000009)
+#define TIM_DMABASE_PSC (0x0000000A)
+#define TIM_DMABASE_ARR (0x0000000B)
+#define TIM_DMABASE_RCR (0x0000000C)
+#define TIM_DMABASE_CCR1 (0x0000000D)
+#define TIM_DMABASE_CCR2 (0x0000000E)
+#define TIM_DMABASE_CCR3 (0x0000000F)
+#define TIM_DMABASE_CCR4 (0x00000010)
+#define TIM_DMABASE_BDTR (0x00000011)
+#define TIM_DMABASE_DCR (0x00000012)
+#define TIM_DMABASE_OR (0x00000013)
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup TIMEx_Channel TIMEx Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define TIM_CHANNEL_3 ((uint32_t)0x0008)
+#define TIM_CHANNEL_4 ((uint32_t)0x000C)
+#define TIM_CHANNEL_5 ((uint32_t)0x0010)
+#define TIM_CHANNEL_6 ((uint32_t)0x0014)
+#define TIM_CHANNEL_ALL ((uint32_t)0x003C)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
+#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
+
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
+#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
+#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
+#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
+ * @{
+ */
+#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
+#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
+ * @{
+ */
+#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
+#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
+ * @{
+ */
+#define TIM_TRGO2_RESET ((uint32_t)0x00000000)
+#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
+#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
+#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
+#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
+#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
+#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
+#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIMEx Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 (0x00000000)
+#define TIM_DMABASE_CR2 (0x00000001)
+#define TIM_DMABASE_SMCR (0x00000002)
+#define TIM_DMABASE_DIER (0x00000003)
+#define TIM_DMABASE_SR (0x00000004)
+#define TIM_DMABASE_EGR (0x00000005)
+#define TIM_DMABASE_CCMR1 (0x00000006)
+#define TIM_DMABASE_CCMR2 (0x00000007)
+#define TIM_DMABASE_CCER (0x00000008)
+#define TIM_DMABASE_CNT (0x00000009)
+#define TIM_DMABASE_PSC (0x0000000A)
+#define TIM_DMABASE_ARR (0x0000000B)
+#define TIM_DMABASE_RCR (0x0000000C)
+#define TIM_DMABASE_CCR1 (0x0000000D)
+#define TIM_DMABASE_CCR2 (0x0000000E)
+#define TIM_DMABASE_CCR3 (0x0000000F)
+#define TIM_DMABASE_CCR4 (0x00000010)
+#define TIM_DMABASE_BDTR (0x00000011)
+#define TIM_DMABASE_DCR (0x00000012)
+#define TIM_DMABASE_CCMR3 (0x00000015)
+#define TIM_DMABASE_CCR5 (0x00000016)
+#define TIM_DMABASE_CCR6 (0x00000017)
+#define TIM_DMABASE_OR (0x00000018)
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup TIMEx_Remap TIMEx Remapping
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
+#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup TIMEx_Remap TIMEx Remapping 1
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
+#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
+ * @{
+ */
+#define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */
+#define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */
+/**
+ * @}
+ */
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup TIMEx_Remap TIMEx Remapping 1
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
+#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
+#define TIM_TIM20_ADC3_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM20_ADC3_AWD1 (0x00000001) /*!< TIM20_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM20_ADC3_AWD2 (0x00000002) /*!< TIM20_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM20_ADC3_AWD3 (0x00000003) /*!< TIM20_ETR is connected to ADC3 AWD3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
+ * @{
+ */
+#define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */
+#define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */
+#define TIM_TIM20_ADC4_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM20_ADC4_AWD1 (0x00000004) /*!< TIM20_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM20_ADC4_AWD2 (0x00000008) /*!< TIM20_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM20_ADC4_AWD3 (0x0000000C) /*!< TIM20_ETR is connected to ADC4 AWD3 */
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx */
+
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup TIMEx_Remap TIMEx remapping
+ * @{
+ */
+#define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
+#define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */
+#define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
+#define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
+#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */
+#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */
+#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */
+#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+ * @{
+ */
+#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_DCR) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2) || \
+ ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
+ ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
+ ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
+ ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+ ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
+ ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
+ ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
+
+#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
+
+#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
+ ((STATE) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
+ ((SOURCE) == TIM_TRGO2_ENABLE) || \
+ ((SOURCE) == TIM_TRGO2_UPDATE) || \
+ ((SOURCE) == TIM_TRGO2_OC1) || \
+ ((SOURCE) == TIM_TRGO2_OC1REF) || \
+ ((SOURCE) == TIM_TRGO2_OC2REF) || \
+ ((SOURCE) == TIM_TRGO2_OC3REF) || \
+ ((SOURCE) == TIM_TRGO2_OC3REF) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF) || \
+ ((SOURCE) == TIM_TRGO2_OC5REF) || \
+ ((SOURCE) == TIM_TRGO2_OC6REF) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
+ ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
+ ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+ ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
+ ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
+ ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_CCMR3) || \
+ ((BASE) == TIM_DMABASE_CCR5) || \
+ ((BASE) == TIM_DMABASE_CCR6) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP) == TIM_TIM16_GPIO) ||\
+ ((REMAP) == TIM_TIM16_RTC) ||\
+ ((REMAP) == TIM_TIM16_HSE) ||\
+ ((REMAP) == TIM_TIM16_MCO))
+
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+
+#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
+ ((REMAP1) == TIM_TIM16_GPIO) ||\
+ ((REMAP1) == TIM_TIM16_RTC) ||\
+ ((REMAP1) == TIM_TIM16_HSE) ||\
+ ((REMAP1) == TIM_TIM16_MCO))
+
+#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
+ ((REMAP2) == TIM_TIM16_NONE))
+
+#endif /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+
+#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
+ ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
+ ((REMAP1) == TIM_TIM16_GPIO) ||\
+ ((REMAP1) == TIM_TIM16_RTC) ||\
+ ((REMAP1) == TIM_TIM16_HSE) ||\
+ ((REMAP1) == TIM_TIM16_MCO) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
+ ((REMAP1) == TIM_TIM20_ADC3_AWD3))
+
+#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
+ ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
+ ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
+ ((REMAP2) == TIM_TIM16_NONE) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
+ ((REMAP2) == TIM_TIM20_ADC4_AWD3))
+
+#endif /* STM32F303xE || STM32F398xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
+ ((REMAP) == TIM_TIM2_ETH_PTP) ||\
+ ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
+ ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
+ ((REMAP) == TIM_TIM14_GPIO) ||\
+ ((REMAP) == TIM_TIM14_RTC) ||\
+ ((REMAP) == TIM_TIM14_HSE) ||\
+ ((REMAP) == TIM_TIM14_MCO))
+
+#endif /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
+ * @{
+ */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval None
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Sets the TIM Capture Compare Register value on runtime without
+ * calling another time ConfigChannel function.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value
+ * @retval None
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+ ((__HANDLE__)->Instance->CCR6))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6
+ * @{
+ */
+/* Extended Callback *********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7
+ * @{
+ */
+/* Extended Peripheral State functions **************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F3xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tsc.h
@@ -0,0 +1,726 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tsc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of TSC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_TSC_H
+#define __STM32F3xx_HAL_TSC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TSC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TSC_Exported_Types TSC Exported Types
+ * @{
+ */
+
+/**
+ * @brief TSC state structure definition
+ */
+typedef enum
+{
+ HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */
+ HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
+ HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */
+ HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */
+} HAL_TSC_StateTypeDef;
+
+/**
+ * @brief TSC group status structure definition
+ */
+typedef enum
+{
+ TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */
+ TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */
+} TSC_GroupStatusTypeDef;
+
+/**
+ * @brief TSC init structure definition
+ */
+typedef struct
+{
+ uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
+ This parameter can be a value of @ref TSC_CTPulseHL_Config */
+ uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
+ This parameter can be a value of @ref TSC_CTPulseLL_Config */
+ uint32_t SpreadSpectrum; /*!< Spread spectrum activation
+ This parameter can be a value of @ref TSC_CTPulseLL_Config */
+ uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
+ This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
+ uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
+ This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
+ uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
+ This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
+ uint32_t MaxCountValue; /*!< Max count value
+ This parameter can be a value of @ref TSC_MaxCount_Value */
+ uint32_t IODefaultMode; /*!< IO default mode
+ This parameter can be a value of @ref TSC_IO_Default_Mode */
+ uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
+ This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
+ uint32_t AcquisitionMode; /*!< Acquisition mode
+ This parameter can be a value of @ref TSC_Acquisition_Mode */
+ uint32_t MaxCountInterrupt; /*!< Max count interrupt activation
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_InitTypeDef;
+
+/**
+ * @brief TSC IOs configuration structure definition
+ */
+typedef struct
+{
+ uint32_t ChannelIOs; /*!< Channel IOs mask */
+ uint32_t ShieldIOs; /*!< Shield IOs mask */
+ uint32_t SamplingIOs; /*!< Sampling IOs mask */
+} TSC_IOConfigTypeDef;
+
+/**
+ * @brief TSC handle Structure definition
+ */
+typedef struct
+{
+ TSC_TypeDef *Instance; /*!< Register base address */
+ TSC_InitTypeDef Init; /*!< Initialization parameters */
+ __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
+ HAL_LockTypeDef Lock; /*!< Lock feature */
+} TSC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TSC_Exported_Constants TSC Exported Constants
+ * @{
+ */
+
+/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
+ * @{
+ */
+#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
+#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
+#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))
+#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))
+#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))
+#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))
+#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))
+#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))
+#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))
+#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
+#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
+#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
+#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
+#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
+#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
+#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
+ * @{
+ */
+#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
+#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
+#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))
+#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))
+#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))
+#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))
+#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))
+#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))
+#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))
+#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
+#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
+#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
+#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
+#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
+#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
+#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
+ * @{
+ */
+#define TSC_SS_PRESC_DIV1 ((uint32_t)0)
+#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
+ * @{
+ */
+#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
+#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
+#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
+#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
+#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
+#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
+#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
+#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_MaxCount_Value Max Count Value
+ * @{
+ */
+#define TSC_MCV_255 ((uint32_t)(0 << 5))
+#define TSC_MCV_511 ((uint32_t)(1 << 5))
+#define TSC_MCV_1023 ((uint32_t)(2 << 5))
+#define TSC_MCV_2047 ((uint32_t)(3 << 5))
+#define TSC_MCV_4095 ((uint32_t)(4 << 5))
+#define TSC_MCV_8191 ((uint32_t)(5 << 5))
+#define TSC_MCV_16383 ((uint32_t)(6 << 5))
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IO_Default_Mode IO Default Mode
+ * @{
+ */
+#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
+#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
+ * @{
+ */
+#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0)
+#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Acquisition_Mode Acquisition Mode
+ * @{
+ */
+#define TSC_ACQ_MODE_NORMAL ((uint32_t)0)
+#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IO_Mode IO Mode
+ * @{
+ */
+#define TSC_IOMODE_UNUSED ((uint32_t)0)
+#define TSC_IOMODE_CHANNEL ((uint32_t)1)
+#define TSC_IOMODE_SHIELD ((uint32_t)2)
+#define TSC_IOMODE_SAMPLING ((uint32_t)3)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_interrupts_definition Interrupts definition
+ * @{
+ */
+#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
+#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_flags_definition Flags definition
+ * @{
+ */
+#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
+#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Group_definition Group definition
+ * @{
+ */
+#define TSC_NB_OF_GROUPS (8)
+
+#define TSC_GROUP1 ((uint32_t)0x00000001)
+#define TSC_GROUP2 ((uint32_t)0x00000002)
+#define TSC_GROUP3 ((uint32_t)0x00000004)
+#define TSC_GROUP4 ((uint32_t)0x00000008)
+#define TSC_GROUP5 ((uint32_t)0x00000010)
+#define TSC_GROUP6 ((uint32_t)0x00000020)
+#define TSC_GROUP7 ((uint32_t)0x00000040)
+#define TSC_GROUP8 ((uint32_t)0x00000080)
+#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
+
+#define TSC_GROUP1_IDX ((uint32_t)0)
+#define TSC_GROUP2_IDX ((uint32_t)1)
+#define TSC_GROUP3_IDX ((uint32_t)2)
+#define TSC_GROUP4_IDX ((uint32_t)3)
+#define TSC_GROUP5_IDX ((uint32_t)4)
+#define TSC_GROUP6_IDX ((uint32_t)5)
+#define TSC_GROUP7_IDX ((uint32_t)6)
+#define TSC_GROUP8_IDX ((uint32_t)7)
+
+#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
+#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
+#define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
+#define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
+#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
+
+#define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
+#define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
+#define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
+#define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
+#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
+
+#define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
+#define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
+#define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
+#define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
+#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
+
+#define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
+#define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
+#define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
+#define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
+#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
+
+#define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
+#define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
+#define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
+#define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
+#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
+
+#define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
+#define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
+#define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
+#define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
+#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
+
+#define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
+#define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
+#define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
+#define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
+#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
+
+#define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
+#define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
+#define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
+#define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
+#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
+
+#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+ * @{
+ */
+
+/** @brief Reset TSC handle state.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+
+/**
+ * @brief Enable the TSC peripheral.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+
+/**
+ * @brief Disable the TSC peripheral.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
+
+/**
+ * @brief Start acquisition.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+
+/**
+ * @brief Stop acquisition.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
+
+/**
+ * @brief Set IO default mode to output push-pull low.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
+
+/**
+ * @brief Set IO default mode to input floating.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+
+/**
+ * @brief Set synchronization polarity to falling edge.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
+
+/**
+ * @brief Set synchronization polarity to rising edge and high level.
+ * @param __HANDLE__: TSC handle
+ * @retval None
+ */
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+
+/**
+ * @brief Enable TSC interrupt.
+ * @param __HANDLE__: TSC handle
+ * @param __INTERRUPT__: TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+ * @brief Disable TSC interrupt.
+ * @param __HANDLE__: TSC handle
+ * @param __INTERRUPT__: TSC interrupt
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
+
+/** @brief Check whether the specified TSC interrupt source is enabled or not.
+ * @param __HANDLE__: TSC Handle
+ * @param __INTERRUPT__: TSC interrupt
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified TSC flag is set or not.
+ * @param __HANDLE__: TSC handle
+ * @param __FLAG__: TSC flag
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TSC's pending flag.
+ * @param __HANDLE__: TSC handle
+ * @param __FLAG__: TSC flag
+ * @retval None
+ */
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+ * @brief Enable schmitt trigger hysteresis on a group of IOs.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable schmitt trigger hysteresis on a group of IOs.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Open analog switch on a group of IOs.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Close analog switch on a group of IOs.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Enable a group of IOs in channel mode.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of channel IOs.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable a group of IOs in sampling mode.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+
+/**
+ * @brief Disable a group of sampling IOs.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_IOY_MASK__: IOs mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+
+/**
+ * @brief Enable acquisition groups.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_MASK__: Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
+
+/**
+ * @brief Disable acquisition groups.
+ * @param __HANDLE__: TSC handle
+ * @param __GX_MASK__: Groups mask
+ * @retval None
+ */
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
+
+/** @brief Gets acquisition group status.
+ * @param __HANDLE__: TSC Handle
+ * @param __GX_INDEX__: Group index
+ * @retval SET or RESET
+ */
+#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
+ * @{
+ */
+
+#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
+ ((VAL) == TSC_CTPH_2CYCLES) || \
+ ((VAL) == TSC_CTPH_3CYCLES) || \
+ ((VAL) == TSC_CTPH_4CYCLES) || \
+ ((VAL) == TSC_CTPH_5CYCLES) || \
+ ((VAL) == TSC_CTPH_6CYCLES) || \
+ ((VAL) == TSC_CTPH_7CYCLES) || \
+ ((VAL) == TSC_CTPH_8CYCLES) || \
+ ((VAL) == TSC_CTPH_9CYCLES) || \
+ ((VAL) == TSC_CTPH_10CYCLES) || \
+ ((VAL) == TSC_CTPH_11CYCLES) || \
+ ((VAL) == TSC_CTPH_12CYCLES) || \
+ ((VAL) == TSC_CTPH_13CYCLES) || \
+ ((VAL) == TSC_CTPH_14CYCLES) || \
+ ((VAL) == TSC_CTPH_15CYCLES) || \
+ ((VAL) == TSC_CTPH_16CYCLES))
+
+#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
+ ((VAL) == TSC_CTPL_2CYCLES) || \
+ ((VAL) == TSC_CTPL_3CYCLES) || \
+ ((VAL) == TSC_CTPL_4CYCLES) || \
+ ((VAL) == TSC_CTPL_5CYCLES) || \
+ ((VAL) == TSC_CTPL_6CYCLES) || \
+ ((VAL) == TSC_CTPL_7CYCLES) || \
+ ((VAL) == TSC_CTPL_8CYCLES) || \
+ ((VAL) == TSC_CTPL_9CYCLES) || \
+ ((VAL) == TSC_CTPL_10CYCLES) || \
+ ((VAL) == TSC_CTPL_11CYCLES) || \
+ ((VAL) == TSC_CTPL_12CYCLES) || \
+ ((VAL) == TSC_CTPL_13CYCLES) || \
+ ((VAL) == TSC_CTPL_14CYCLES) || \
+ ((VAL) == TSC_CTPL_15CYCLES) || \
+ ((VAL) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
+
+#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
+
+#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
+ ((VAL) == TSC_PG_PRESC_DIV2) || \
+ ((VAL) == TSC_PG_PRESC_DIV4) || \
+ ((VAL) == TSC_PG_PRESC_DIV8) || \
+ ((VAL) == TSC_PG_PRESC_DIV16) || \
+ ((VAL) == TSC_PG_PRESC_DIV32) || \
+ ((VAL) == TSC_PG_PRESC_DIV64) || \
+ ((VAL) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
+ ((VAL) == TSC_MCV_511) || \
+ ((VAL) == TSC_MCV_1023) || \
+ ((VAL) == TSC_MCV_2047) || \
+ ((VAL) == TSC_MCV_4095) || \
+ ((VAL) == TSC_MCV_8191) || \
+ ((VAL) == TSC_MCV_16383))
+
+#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
+
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
+
+#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
+
+#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
+ ((VAL) == TSC_IOMODE_CHANNEL) || \
+ ((VAL) == TSC_IOMODE_SHIELD) || \
+ ((VAL) == TSC_IOMODE_SAMPLING))
+
+#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TSC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+ /* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* TSC IRQHandler and Callbacks used in Interrupt mode */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F3xx_TSC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart.h
@@ -0,0 +1,1412 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_UART_H
+#define __STM32F3xx_HAL_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode */
+
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling */
+
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+}UART_InitTypeDef;
+
+/**
+ * @brief UART Advanced Features initalization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
+ Advanced Features may be initialized at the same time .
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref UART_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref UART_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref UART_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref UART_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref UART_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
+
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable */
+
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
+ detection is carried out.
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref UART_MSB_First */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
+{
+ uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+ be filled up. */
+
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref UART_WakeUp_Address_Length */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max) */
+} UART_WakeUpTypeDef;
+
+/**
+ * @brief HAL UART State structures definition
+ */
+typedef enum
+{
+ HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_UART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_UART_StateTypeDef;
+
+/**
+ * @brief UART clock sources definition
+ */
+typedef enum
+{
+ UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
+ UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
+}UART_ClockSourceTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< UART Rx RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_UART_StateTypeDef State; /*!< UART communication state */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+}UART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+ * @{
+ */
+
+/** @defgroup UART_Error UART Error
+ * @{
+ */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_1 ((uint32_t)0x0000)
+#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define UART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /*!< No hardware control */
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE ((uint32_t)0x00000000) /*!< UART disabled */
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+ * @{
+ */
+#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+ * @{
+ */
+#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< UART receiver timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN UART Local Interconnection Network mode
+ * @{
+ */
+#define UART_LIN_DISABLE ((uint32_t)0x00000000) /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Tx UART DMA Tx
+ * @{
+ */
+#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Rx UART DMA Rx
+ * @{
+ */
+#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
+ * @{
+ */
+#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
+ * @{
+ */
+#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART Status Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define UART_FLAG_REACK ((uint32_t)0x00400000)
+#define UART_FLAG_TEACK ((uint32_t)0x00200000)
+#define UART_FLAG_WUF ((uint32_t)0x00100000)
+#define UART_FLAG_RWU ((uint32_t)0x00080000)
+#define UART_FLAG_SBKF ((uint32_t)0x00040000)
+#define UART_FLAG_CMF ((uint32_t)0x00020000)
+#define UART_FLAG_BUSY ((uint32_t)0x00010000)
+#define UART_FLAG_ABRF ((uint32_t)0x00008000)
+#define UART_FLAG_ABRE ((uint32_t)0x00004000)
+#define UART_FLAG_EOBF ((uint32_t)0x00001000)
+#define UART_FLAG_RTOF ((uint32_t)0x00000800)
+#define UART_FLAG_CTS ((uint32_t)0x00000400)
+#define UART_FLAG_CTSIF ((uint32_t)0x00000200)
+#define UART_FLAG_LBDF ((uint32_t)0x00000100)
+#define UART_FLAG_TXE ((uint32_t)0x00000080)
+#define UART_FLAG_TC ((uint32_t)0x00000040)
+#define UART_FLAG_RXNE ((uint32_t)0x00000020)
+#define UART_FLAG_IDLE ((uint32_t)0x00000010)
+#define UART_FLAG_ORE ((uint32_t)0x00000008)
+#define UART_FLAG_NE ((uint32_t)0x00000004)
+#define UART_FLAG_FE ((uint32_t)0x00000002)
+#define UART_FLAG_PE ((uint32_t)0x00000001)
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * @{
+ */
+#define UART_IT_PE ((uint16_t)0x0028)
+#define UART_IT_TXE ((uint16_t)0x0727)
+#define UART_IT_TC ((uint16_t)0x0626)
+#define UART_IT_RXNE ((uint16_t)0x0525)
+#define UART_IT_IDLE ((uint16_t)0x0424)
+#define UART_IT_LBD ((uint16_t)0x0846)
+#define UART_IT_CTS ((uint16_t)0x096A)
+#define UART_IT_CM ((uint16_t)0x112E)
+#define UART_IT_WUF ((uint16_t)0x1476)
+
+/** Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ */
+#define UART_IT_ERR ((uint16_t)0x0060)
+
+/** Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ */
+#define UART_IT_ORE ((uint16_t)0x0300)
+#define UART_IT_NE ((uint16_t)0x0200)
+#define UART_IT_FE ((uint16_t)0x0100)
+/**
+ * @}
+ */
+
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
+ * @{
+ */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
+#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+ * @{
+ */
+#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
+ * @{
+ */
+#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+ * @{
+ */
+#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
+ * @{
+ */
+#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
+ * @{
+ */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First
+ * @{
+ */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
+ * @{
+ */
+#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000)
+#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
+#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
+/**
+ * @}
+ */
+
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
+ * @{
+ */
+#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /*!< UART Driver Enable assertion time LSB position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
+ * @{
+ */
+#define UART_IT_MASK ((uint32_t)0x001F) /*!< UART interruptions flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
+ * @{
+ */
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /*!< UART polling-based communications time-out value */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle state.
+ * @param __HANDLE__: UART handle.
+ * @retval None
+ */
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+
+/** @brief Flush the UART Data registers.
+ * @param __HANDLE__: UART handle.
+ * @retval None
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+
+/** @brief Clear the specified UART pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg UART_CLEAR_PEF, Parity Error Clear Flag
+ * @arg UART_CLEAR_FEF, Framing Error Clear Flag
+ * @arg UART_CLEAR_NEF, Noise detected Clear Flag
+ * @arg UART_CLEAR_OREF, OverRun Error Clear Flag
+ * @arg UART_CLEAR_IDLEF, IDLE line detected Clear Flag
+ * @arg UART_CLEAR_TCF, Transmission Complete Clear Flag
+ * @arg UART_CLEAR_LBDF, LIN Break Detection Clear Flag (not available on all devices)
+ * @arg UART_CLEAR_CTSF, CTS Interrupt Clear Flag
+ * @arg UART_CLEAR_RTOF, Receiver Time Out Clear Flag
+ * @arg UART_CLEAR_EOBF, End Of Block Clear Flag (not available on all devices)
+ * @arg UART_CLEAR_CMF, Character Match Clear Flag
+ * @arg UART_CLEAR_WUF, Wake Up from stop mode Clear Flag (not available on all devices)
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief Check whether the specified UART flag is set or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral (datasheet: up to five USART/UARTs)
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg UART_FLAG_REACK: Receive enable acknowledge flag
+ * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
+ * @arg UART_FLAG_WUF: Wake up from stop mode flag
+ * @arg UART_FLAG_RWU: Receiver wake up flag
+ * @arg UART_FLAG_SBKF: Send Break flag
+ * @arg UART_FLAG_CMF: Character match flag
+ * @arg UART_FLAG_BUSY: Busy flag
+ * @arg UART_FLAG_ABRF: Auto Baud rate detection flag
+ * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
+ * @arg UART_FLAG_EOBF: End of block flag
+ * @arg UART_FLAG_RTOF: Receiver timeout flag
+ * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg UART_FLAG_LBD: LIN Break detection flag
+ * @arg UART_FLAG_TXE: Transmit data register empty flag
+ * @arg UART_FLAG_TC: Transmission Complete flag
+ * @arg UART_FLAG_RXNE: Receive data register not empty flag
+ * @arg UART_FLAG_IDLE: Idle Line detection flag
+ * @arg UART_FLAG_ORE: OverRun Error flag
+ * @arg UART_FLAG_NE: Noise Error flag
+ * @arg UART_FLAG_FE: Framing Error flag
+ * @arg UART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral. (datasheet: up to five USART/UARTs)
+ * @param __INTERRUPT__: specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral. (datasheet: up to five USART/UARTs)
+ * @param __INTERRUPT__: specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Check whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral. (datasheet: up to five USART/UARTs)
+ * @param __IT__: specifies the UART interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_ORE: OverRun Error interrupt
+ * @arg UART_IT_NE: Noise Error interrupt
+ * @arg UART_IT_FE: Framing Error interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief Check whether the specified UART interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral. (datasheet: up to five USART/UARTs)
+ * @param __IT__: specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg UART_IT_WUF: Wakeup from stop mode interrupt
+ * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg UART_IT_LBD: LIN Break detection interrupt
+ * @arg UART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg UART_IT_TC: Transmission complete interrupt
+ * @arg UART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg UART_IT_IDLE: Idle line detection interrupt
+ * @arg UART_IT_ORE: OverRun Error interrupt
+ * @arg UART_IT_NE: Noise Error interrupt
+ * @arg UART_IT_FE: Framing Error interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
+
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral. (datasheet: up to five USART/UARTs)
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg UART_CLEAR_PEF: Parity Error Clear Flag
+ * @arg UART_CLEAR_FEF: Framing Error Clear Flag
+ * @arg UART_CLEAR_NEF: Noise detected Clear Flag
+ * @arg UART_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
+ * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
+ * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
+ * @arg UART_CLEAR_EOBF: End Of Block Clear Flag
+ * @arg UART_CLEAR_CMF: Character Match Clear Flag
+ * @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific UART request flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral. (datasheet: up to five USART/UARTs)
+ * @param __REQ__: specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
+ * @arg UART_SENDBREAK_REQUEST: Send Break Request
+ * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
+ * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the UART one bit sample method.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the UART one bit sample method.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART.
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART
+ * @param __HANDLE__: specifies the UART Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Enable CTS flow control.
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0)
+
+/** @brief Disable CTS flow control.
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0)
+
+/** @brief Enable RTS flow control.
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0)
+
+/** @brief Disable RTS flow control.
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__: UART clock.
+ * @param __BAUD__: Baud rate set by the user.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) (((__PCLK__)*2)/((__BAUD__)))
+
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__: UART clock.
+ * @param __BAUD__: Baud rate set by the user.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__))/((__BAUD__)))
+
+/** @brief Check UART Baud rate
+ * @param __BAUDRATE__: Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+ */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
+
+/** @brief Check UART assertion time.
+ * @param __TIME__: 5-bit value assertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+
+/** @brief Check UART deassertion time.
+ * @param __TIME__: 5-bit value deassertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+
+/**
+ * @brief Ensure that UART frame number of stop bits is valid.
+ * @param __STOPBITS__: UART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) UART_STOPBITS_1_5
+ */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_2) || \
+ ((__STOPBITS__) == UART_STOPBITS_1_5))
+
+/**
+ * @brief Ensure that UART frame parity is valid.
+ * @param __PARITY__: UART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+ ((__PARITY__) == UART_PARITY_EVEN) || \
+ ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+ * @brief Ensure that UART hardware flow control is valid.
+ * @param __CONTROL__: UART hardware flow control.
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+ */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+ * @brief Ensure that UART communication mode is valid.
+ * @param __MODE__: UART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+ * @brief Ensure that UART state is valid.
+ * @param __STATE__: UART state.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+ ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+ * @brief Ensure that UART oversampling is valid.
+ * @param __SAMPLING__: UART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+ * @brief Ensure that UART frame sampling is valid.
+ * @param __ONEBIT__: UART frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that Address Length detection parameter is valid.
+ * @param __ADDRESS__: UART Adress length value.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+ */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__: UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+ * @brief Ensure that UART receiver timeout setting is valid.
+ * @param __TIMEOUT__: UART receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__: UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
+ ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__: UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+ * @brief Ensure that UART DMA TX state is valid.
+ * @param __DMATX__: UART DMA TX state.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+ ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA RX state is valid.
+ * @param __DMARX__: UART DMA RX state.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+ ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that UART half-duplex state is valid.
+ * @param __HDSEL__: UART half-duplex state.
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+ */
+#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up method is valid.
+ * @param __WAKEUP__: UART wake-up method .
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+ */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+ * @brief Ensure that UART advanced features initialization is valid.
+ * @param __INIT__: UART advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+ UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that UART frame TX inversion setting is valid.
+ * @param __TXINV__: UART frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX inversion setting is valid.
+ * @param __RXINV__: UART frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame data inversion setting is valid.
+ * @param __DATAINV__: UART frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+ * @param __SWAP__: UART frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that UART frame overrun setting is valid.
+ * @param __OVERRUN__: UART frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate state is valid.
+ * @param __AUTOBAUDRATE__: UART auto Baud rate state.
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+ * @param __DMA__: UART DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that UART frame MSB first setting is valid.
+ * @param __MSBFIRST__: UART frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__: UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART mute mode state is valid.
+ * @param __MUTE__: UART mute mode state.
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+ */
+#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__: UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+ * @brief Ensure that UART driver enable polarity is valid.
+ * @param __POLARITY__: UART driver enable polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__: UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+/**
+ * @}
+ */
+
+/* Include UART HAL Extension module */
+#include "stm32f3xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_uart_ex.h
@@ -0,0 +1,472 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of UART HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_UART_EX_H
+#define __STM32F3xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
+#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+#else
+#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+ * @{
+ */
+
+/** @brief Report the UART clock source.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @param __CLOCKSOURCE__: output variable.
+ * @retval UART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+
+/** @brief Compute the UART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003F ; \
+ } \
+ } \
+} while(0)
+#else
+#define UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+} while(0)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Ensure that UART frame length is valid.
+ * @param __LENGTH__: UART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+#else
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart.h
@@ -0,0 +1,704 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_usart.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of USART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_USART_H
+#define __STM32F3xx_HAL_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup USART_Exported_Types USART Exported Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
+ The baud rate is computed using the following formula:
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USARTEx_Word_Length. */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits. */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode. */
+
+ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity. */
+
+ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase. */
+
+ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit. */
+}USART_InitTypeDef;
+
+/**
+ * @brief HAL USART State structures definition
+ */
+typedef enum
+{
+ HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+}HAL_USART_StateTypeDef;
+
+/**
+ * @brief USART clock sources definitions
+ */
+typedef enum
+{
+ USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
+ USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
+ USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
+ USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
+ USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
+ USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
+}USART_ClockSourceTypeDef;
+
+
+/**
+ * @brief USART handle Structure definition
+ */
+typedef struct
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ USART_InitTypeDef Init; /*!< USART communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */
+
+ uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */
+
+ uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< USART Rx RDR register mask */
+
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code */
+
+}USART_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_Error USART Error
+ * @{
+ */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits USART Number of Stop Bits
+ * @{
+ */
+#define USART_STOPBITS_1 ((uint32_t)0x0000)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity USART Parity
+ * @{
+ */
+#define USART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode USART Mode
+ * @{
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock USART Clock
+ * @{
+ */
+#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< USART clock disable */
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity USART Clock Polarity
+ * @{
+ */
+#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< USART Clock signal is steady Low */
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase USART Clock Phase
+ * @{
+ */
+#define USART_PHASE_1EDGE ((uint32_t)0x00000000) /*!< USART frame phase on first clock transition */
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit USART Last Bit
+ * @{
+ */
+#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Request_Parameters USART Request Parameters
+ * @{
+ */
+#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define USART_FLAG_REACK ((uint32_t)0x00400000) /*!< USART receive enable acknowledge flag */
+#define USART_FLAG_TEACK ((uint32_t)0x00200000) /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY ((uint32_t)0x00010000) /*!< USART busy flag */
+#define USART_FLAG_CTS ((uint32_t)0x00000400) /*!< USART clear to send flag */
+#define USART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< USART clear to send interrupt flag */
+#define USART_FLAG_TXE ((uint32_t)0x00000080) /*!< USART transmit data register empty */
+#define USART_FLAG_TC ((uint32_t)0x00000040) /*!< USART transmission complete */
+#define USART_FLAG_RXNE ((uint32_t)0x00000020) /*!< USART read data register not empty */
+#define USART_FLAG_IDLE ((uint32_t)0x00000010) /*!< USART idle flag */
+#define USART_FLAG_ORE ((uint32_t)0x00000008) /*!< USART overrun error */
+#define USART_FLAG_NE ((uint32_t)0x00000004) /*!< USART noise error */
+#define USART_FLAG_FE ((uint32_t)0x00000002) /*!< USART frame error */
+#define USART_FLAG_PE ((uint32_t)0x00000001) /*!< USART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition USART Interrupts Definition
+ * Elements values convention: 0000ZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028) /*!< USART parity error interruption */
+#define USART_IT_TXE ((uint16_t)0x0727) /*!< USART transmit data register empty interruption */
+#define USART_IT_TC ((uint16_t)0x0626) /*!< USART transmission complete interruption */
+#define USART_IT_RXNE ((uint16_t)0x0525) /*!< USART read data register not empty interruption */
+#define USART_IT_IDLE ((uint16_t)0x0424) /*!< USART idle interruption */
+#define USART_IT_ERR ((uint16_t)0x0060) /*!< USART error interruption */
+#define USART_IT_ORE ((uint16_t)0x0300) /*!< USART overrun error interruption */
+#define USART_IT_NE ((uint16_t)0x0200) /*!< USART noise error interruption */
+#define USART_IT_FE ((uint16_t)0x0100) /*!< USART frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
+ * @{
+ */
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
+ * @{
+ */
+#define USART_IT_MASK ((uint16_t)0x001F) /*!< USART interruptions flags mask */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup USART_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @brief Reset USART handle state.
+ * @param __HANDLE__: USART handle.
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+
+/** @brief Flush the USART Data registers.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+
+/** @brief Check whether the specified USART flag is set or not.
+ * @param __HANDLE__: specifies the USART Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_REACK: Receive enable acknowledge flag
+ * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag
+ * @arg USART_FLAG_BUSY: Busy flag
+ * @arg USART_FLAG_CTS: CTS Change flag
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified USART pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg USART_CLEAR_PEF
+ * @arg USART_CLEAR_FEF
+ * @arg USART_CLEAR_NEF
+ * @arg USART_CLEAR_OREF
+ * @arg USART_CLEAR_IDLEF
+ * @arg USART_CLEAR_TCF
+ * @arg USART_CLEAR_CTSF
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief Clear the USART NE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief Clear the USART ORE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief Enable the specified USART interrupt.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __INTERRUPT__: specifies the USART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+/** @brief Disable the specified USART interrupt.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __INTERRUPT__: specifies the USART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+
+
+/** @brief Check whether the specified USART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __IT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief Check whether the specified USART interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __IT__: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
+ (((uint16_t)(__IT__)) & USART_IT_MASK)))
+
+
+/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt.
+ * This parameter can be one of the following values:
+ * @arg USART_CLEAR_PEF: Parity Error Clear Flag
+ * @arg USART_CLEAR_FEF: Framing Error Clear Flag
+ * @arg USART_CLEAR_NEF: Noise detected Clear Flag
+ * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
+ * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific USART request flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __REQ__: specifies the request flag to set.
+ * This parameter can be one of the following values:
+ * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ *
+ * @retval None
+ */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
+
+/** @brief Enable the USART one bit sample method.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the USART one bit sample method.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable USART.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable USART.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+
+/** @brief Check USART Baud rate.
+ * @param __BAUDRATE__: Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
+
+/**
+ * @brief Ensure that USART frame number of stop bits is valid.
+ * @param __STOPBITS__: USART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
+ ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+ * @brief Ensure that USART frame parity is valid.
+ * @param __PARITY__: USART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+ ((__PARITY__) == USART_PARITY_EVEN) || \
+ ((__PARITY__) == USART_PARITY_ODD))
+
+/**
+ * @brief Ensure that USART communication mode is valid.
+ * @param __MODE__: USART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+ * @brief Ensure that USART clock state is valid.
+ * @param __CLOCK__: USART clock state.
+ * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+ */
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+ ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+ * @brief Ensure that USART frame polarity is valid.
+ * @param __CPOL__: USART frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that USART frame phase is valid.
+ * @param __CPHA__: USART frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
+
+/**
+ * @brief Ensure that USART frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__: USART frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == USART_LASTBIT_ENABLE))
+
+/**
+ * @brief Ensure that USART request parameter is valid.
+ * @param __PARAM__: USART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @}
+ */
+
+/* Include USART HAL Extension module */
+#include "stm32f3xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ***********************************************/
+
+/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_usart_ex.h
@@ -0,0 +1,338 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_usart_ex.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of USART HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_USART_EX_H
+#define __STM32F3xx_HAL_USART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USARTEx USARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup USARTEx_Word_Length USARTEx Word Length
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#else
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
+ * @{
+ */
+
+/** @brief Reports the USART clock source.
+ * @param __HANDLE__: specifies the USART Handle
+ * @param __CLOCKSOURCE__ : output variable
+ * @retval the USART clocking source, written in __CLOCKSOURCE__.
+ */
+#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ } \
+ } \
+ } while(0)
+#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+/** @brief Compute the USART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define USART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003F ; \
+ } \
+ } \
+} while(0)
+#else
+#define USART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FF ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007F ; \
+ } \
+ } \
+} while(0)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+
+/**
+ * @brief Ensure that USART frame length is valid.
+ * @param __LENGTH__: USART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_9B))
+#else
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_9B))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_USART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_wwdg.h
@@ -0,0 +1,327 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_wwdg.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of WWDG HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_WWDG_H
+#define __STM32F3xx_HAL_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Types WWDG Exported Types
+ * @{
+ */
+
+/**
+ * @brief WWDG HAL State Structure definition
+ */
+typedef enum
+{
+ HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */
+ HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */
+ HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */
+ HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */
+ HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */
+}HAL_WWDG_StateTypeDef;
+
+/**
+ * @brief WWDG Init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number lower than Max_Data = 0x80 */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+}WWDG_InitTypeDef;
+
+/**
+ * @brief WWDG handle Structure definition
+ */
+typedef struct
+{
+ WWDG_TypeDef *Instance; /*!< Register base address */
+
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< WWDG locking object */
+
+ __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
+
+}WWDG_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
+ * @{
+ */
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Flag_definition WWDG Flag definition
+ * @brief WWDG Flag definition
+ * @{
+ */
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Prescaler WWDG Prescaler
+ * @{
+ */
+#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
+ * @{
+ */
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
+
+#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
+
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
+/**
+ * @}
+ */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+
+/** @brief Reset WWDG handle state.
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
+
+/**
+ * @brief Enable the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+
+/**
+ * @brief Disable the WWDG peripheral.
+ * @param __HANDLE__: WWDG handle
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enable, WWDG Peripheral cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
+
+/**
+ * @brief Enable the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to enable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+
+/**
+ * @brief Disable the WWDG early wakeup interrupt.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt to disable.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early wakeup interrupt
+ * @note WARNING: This is a dummy macro for HAL code alignment.
+ * Once enabled this interrupt cannot be disabled except by a system reset.
+ * @retval None
+ */
+#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
+
+/**
+ * @brief Check whether the selected WWDG interrupt has occurred or not.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the it to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+
+/** @brief Clear the WWDG interrupt pending bits.
+ * bits to clear the selected interrupt pending bits.
+ * @param __HANDLE__: WWDG handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ */
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified WWDG flag is set or not.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval The new state of WWDG_FLAG (SET or RESET).
+ */
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the WWDG's pending flags.
+ * @param __HANDLE__: WWDG handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
+ * @retval None
+ */
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief Check whether the specified WWDG interrupt source is enabled or not.
+ * @param __HANDLE__: WWDG Handle.
+ * @param __INTERRUPT__: specifies the WWDG interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg WWDG_IT_EWI: Early Wakeup Interrupt
+ * @retval state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup WWDG_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h
@@ -0,0 +1,1014 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_fmc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Header file of FMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_FMC_H
+#define __STM32F3xx_LL_FMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal_def.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FMC_LL FMC Low Layer
+ * @{
+ */
+
+/** @addtogroup FMC_LL_Private_Macros FMC Low Layer Private Macros
+ * @{
+ */
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FMC_NORSRAM_BANK4))
+
+
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+
+
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_1024))
+
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
+
+
+#define IS_FMC_NAND_BANK(_BANK_) (((_BANK_) == FMC_NAND_BANK2) || \
+ ((_BANK_) == FMC_NAND_BANK3))
+
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+ ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+
+/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
+ * @{
+ */
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
+ * @{
+ */
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
+ * @{
+ */
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Device_Instance
+ * @{
+ */
+#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
+
+/**
+ * @}
+ */
+
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FMC_WRAP_MODE(_MODE_) (((_MODE_) == FMC_WRAP_MODE_DISABLE) || \
+ ((_MODE_) == FMC_WRAP_MODE_ENABLE))
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+
+
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+/** @defgroup FMC_Address_Setup_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Hold_Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Setup_Time
+ * @{
+ */
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Bus_Turn_around_Duration
+ * @{
+ */
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_CLK_Division
+ * @{
+ */
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Latency
+ * @{
+ */
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
+ * @{
+ */
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Setup_Time
+ * @{
+ */
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @addtogroup FMC_LL_Exported_Typedef FMC Low Layer Exported Typedef
+ * @{
+ */
+#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
+#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
+#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
+
+#define FMC_NORSRAM_DEVICE FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+#define FMC_NAND_DEVICE FMC_Bank2_3
+#define FMC_PCCARD_DEVICE FMC_Bank4
+
+/**
+ * @brief FMC_NORSRAM Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
+ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the data bus or not.
+ This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory device.
+ This parameter can be a value of @ref FMC_Memory_Type */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
+
+ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FMC_Burst_Access_Mode */
+
+ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
+
+ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FMC_Wrap_Mode */
+
+ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Timing */
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+ This parameter can be a value of @ref FMC_Write_Operation */
+
+ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FMC_Wait_Signal */
+
+ uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FMC_Extended_Mode */
+
+ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FMC_AsynchronousWait */
+
+ uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FMC_Write_Burst */
+
+ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
+ through FMC_BCR2..4 registers.
+ This parameter can be a value of @ref FMC_Continous_Clock */
+
+}FMC_NORSRAM_InitTypeDef;
+
+/**
+ * @brief FMC_NORSRAM Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ @note This parameter is not used with synchronous NOR Flash memories. */
+
+ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ NOR Flash memories. */
+
+ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+ @note This parameter is only used for multiplexed NOR Flash memories. */
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+ HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ accesses. */
+
+ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The parameter value depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FMC_Access_Mode */
+}FMC_NORSRAM_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FMC_NAND_Data_Width */
+
+ uint32_t EccComputation; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FMC_ECC */
+
+ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FMC_ECC_Page_Size */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_NAND_InitTypeDef;
+
+/**
+ * @brief FMC_NAND_PCCARD Timing parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command de-assertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ data bus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FMC_NAND_PCC_TimingTypeDef;
+
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+ This parameter can be any value of @ref FMC_Wait_feature */
+
+ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
+
+ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+
+}FMC_PCCARD_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
+ * @{
+ */
+
+/** @defgroup FMC_NOR_SRAM_Exported_constants FMC NOR/SRAM Exported constants
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
+ * @{
+ */
+#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
+#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
+#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
+ * @{
+ */
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Memory_Type FMC Memory Type
+ * @{
+ */
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0)
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
+ * @{
+ */
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NORSRAM Flash Access
+ * @{
+ */
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
+ * @{
+ */
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN)
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
+ * @{
+ */
+#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRAP_MODE_ENABLE ((uint32_t)FMC_BCRx_WRAPMOD)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
+ * @{
+ */
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Operation FMC Write Operation
+ * @{
+ */
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+ * @{
+ */
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
+ * @{
+ */
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
+ * @{
+ */
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Write_Burst FMC Write Burst
+ * @{
+ */
+
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Continous_Clock FMC Continous Clock
+ * @{
+ */
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Access_Mode FMC Access Mode
+ * @{
+ */
+#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
+#define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1)
+#define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0|FMC_BTRx_ACCMOD_1))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Controller FMC NAND Exported constants
+ * @{
+ */
+
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
+ * @{
+ */
+#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_feature FMC Wait feature
+ * @{
+ */
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCRx_PWAITEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
+ * @{
+ */
+#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCRx_PTYP)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
+ * @{
+ */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCRx_PWID_0)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC FMC NAND ECC
+ * @{
+ */
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCRx_ECCEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_ECC_Page_Size FMC NAND ECC Page Size
+ * @{
+ */
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCRx_ECCPS_0)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCRx_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCRx_ECCPS_2)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_2)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt_definition FMC Interrupt definition
+ * @brief FMC Interrupt definition
+ * @{
+ */
+#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SRx_IREN)
+#define FMC_IT_LEVEL ((uint32_t)FMC_SRx_ILEN)
+#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SRx_IFEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Flag_definition FMC Flag definition
+ * @brief FMC Flag definition
+ * @{
+ */
+#define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SRx_IRS)
+#define FMC_FLAG_LEVEL ((uint32_t)FMC_SRx_ILS)
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SRx_IFS)
+#define FMC_FLAG_FEMPT ((uint32_t)FMC_SRx_FEMPT)
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
+ * @{
+ */
+
+/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the NORSRAM device access.
+ * @param __INSTANCE__: FMC_NORSRAM Instance
+ * @param __BANK__: FMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+ * @brief Disable the NORSRAM device access.
+ * @param __INSTANCE__: FMC_NORSRAM Instance
+ * @param __BANK__: FMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Macros FMC NAND Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
+ SET_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
+
+/**
+ * @brief Disable the NAND device access.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
+ CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Macros FMC PCCARD Macros
+ * @brief macros to handle PCCARD read/write operations
+ * @{
+ */
+
+/**
+ * @brief Enable the PCCARD device access.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
+
+/**
+ * @brief Disable the PCCARD device access.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Interrupt FMC Interrupt
+ * @brief macros to handle FMC interrupts
+ * @{
+ */
+
+/**
+ * @brief Enable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
+ SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
+
+/**
+ * @brief Disable the NAND device interrupt.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __INTERRUPT__: FMC_NAND interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
+ CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
+
+/**
+ * @brief Get flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+/**
+ * @brief Clear flag status of the NAND device.
+ * @param __INSTANCE__: FMC_NAND Instance
+ * @param __BANK__: FMC_NAND Bank
+ * @param __FLAG__: FMC_NAND flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
+ CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
+/**
+ * @brief Enable the PCCARD device interrupt.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
+
+/**
+ * @brief Disable the PCCARD device interrupt.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FMC_IT_LEVEL: Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @retval None
+ */
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
+
+/**
+ * @brief Get flag status of the PCCARD device.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __FLAG__: FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear flag status of the PCCARD device.
+ * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __FLAG__: FMC_PCCARD flag
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @retval None
+ */
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+ * @{
+ */
+
+/* FMC_LL_NORSRAM Controller functions *******************************************/
+/** @addgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_LL_NORSRAM_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+/* FMC_NORSRAM Control functions */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/* FMC_NAND Controller functions **********************************************/
+/** @addtogroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions
+ * @{
+ */
+/* FMC_NAND Control functions */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_PCCARD_Exported_Functions_Group1 FMC Low Layer Peripheral Control functions
+ * @{
+ */
+/* FMC_PCCARD Controller functions ********************************************/
+/* Initialization/de-initialization functions */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_FMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
@@ -0,0 +1,453 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs categories:
+ (+) HAL Initialization and de-initialization functions
+ (+) HAL Control functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HAL_Private Constants
+ * @{
+ */
+/**
+ * @brief STM32F3xx HAL Driver version number V1.2.0
+ */
+#define __STM32F3xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32F3xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F3xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24)\
+ |(__STM32F3xx_HAL_VERSION_SUB1 << 16)\
+ |(__STM32F3xx_HAL_VERSION_SUB2 << 8 )\
+ |(__STM32F3xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
+static __IO uint32_t uwTick;
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface, the NVIC allocation and initial clock
+ configuration. It initializes the source of time base also when timeout
+ is needed and the backup domain when enabled.
+ (+) de-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) Systick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __Weak
+ to make override possible in case of other implementations in user file.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function configures the Flash prefetch,
+ * Configures time base source, NVIC and Low level hardware
+ * @note This function is called at the beginning of program after reset and before
+ * the clock configuration
+ *
+ * @note The Systick configuration is based on HSI clock, as HSI is the clock
+ * used after a system Reset and the NVIC configuration is set to Priority group 4
+ *
+ * @note The time base configuration is based on MSI clock when exting from Reset.
+ * Once done, time base tick start incrementing.
+ * In the default implementation,Systick is used as source of time base.
+ * The tick variable is incremented each 1ms in its ISR.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the source
+ * of time base.
+ * @note This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
+
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
+
+ __HAL_RCC_AHB_FORCE_RESET();
+ __HAL_RCC_AHB_RELEASE_RESET();
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The the SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /*Configure the SysTick to have interrupt in 1ms time basis*/
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ /*Configure the SysTick IRQ priority */
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick++;
+}
+
+/**
+ * @brief Povides a tick value in millisecond.
+ * @note The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ return uwTick;
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(__IO uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ while((HAL_GetTick() - tickstart) < Delay)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * The function is declared as __Weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+
+}
+
+/**
+ * @brief This function returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32F3xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @retval None
+ */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c
@@ -0,0 +1,899 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * ++ Initialization and Configuration of ADC
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of regular
+ * group, using 3 possible modes: polling, interruption or DMA.
+ * + Control functions
+ * ++ Channels configuration on regular group
+ * ++ Channels configuration on injected group
+ * ++ Analog Watchdog configuration
+ * + State functions
+ * ++ ADC state machine management
+ * ++ Interrupts and flags management
+ * Other functions (extended functions) are available in file
+ * "stm32f3xx_hal_adc_ex.c".
+ *
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
+ STM32F30xxC devices).
+
+ (+) Interrupt generation at the end of regular conversion, end of injected
+ conversion, and in case of analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (channel wise)
+
+ (+) ADC conversion of regular group and injected group.
+
+ (+) External trigger (timer or EXTI) with configurable polarity
+ for both regular and injected groups.
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) Multimode dual mode (available on devices with 2 ADCs or more).
+
+ (+) Configurable DMA data storage in Multimode Dual mode (available on devices
+ with 2 DCs or more).
+
+ (+) Configurable delay between conversions in Dual interleaved mode (available
+ on devices with 2 DCs or more).
+
+ (+) ADC calibration
+
+ (+) ADC channels selectable single/differential input (available only on
+ STM32F30xxC devices)
+
+ (+) ADC Injected sequencer&channels configuration context queue (available
+ only on STM32F30xxC devices)
+
+ (+) ADC offset on injected and regular groups (offset on regular group
+ available only on STM32F30xxC devices)
+
+ (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ slower speed.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+ (++) For STM32F30x/STM32F33x devices:
+ Two possible clock sources: synchronous clock derived from AHB clock
+ or asynchronous clock derived from ADC dedicated PLL 72MHz.
+ - Synchronous clock is mandatory since used as ADC core clock.
+ Synchronous clock can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
+ Synchronous clock is configured using macro __ADCx_CLK_ENABLE().
+ - Asynchronous can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
+ Asynchronous clock is configured using function HAL_RCCEx_PeriphCLKConfig().
+ (+++) For example, in case of device with a single ADC:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC1_CLK_ENABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
+ (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)
+
+ (+++) For example, in case of device with 4 ADCs:
+
+ (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
+ (+++) {
+ (+++) __HAL_RCC_ADC12_CLK_ENABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock)
+ (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock)
+ (+++) }
+ (+++) else
+ (+++) {
+ (+++) __HAL_RCC_ADC34_CLK_ENABLE() (mandatory)
+ (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_DIV1; (optional, if ADC conversion from asynchronous clock)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure); (optional, if ADC conversion from asynchronous clock)
+ (+++) }
+
+ (++) For STM32F37x devices:
+ One clock setting is mandatory:
+ ADC clock (core and conversion clock) from APB2 clock.
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_DIV2
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, groups regular/injected, channels parameters ***
+ ==========================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the injected group parameters (conversion trigger,
+ sequencer, ..., of injected group)
+ and the channels for injected group parameters (channel number,
+ channel rank into sequencer, ..., into injected group)
+ using function HAL_ADCEx_InjectedConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ (#) Optionally, for devices with several ADC instances: configure the
+ multimode parameters
+ using function HAL_ADCEx_MultiModeConfigChannel().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (or for injected group: HAL_ADCEx_InjectedGetValue() )
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (or for injected group: HAL_ADCEx_InjectedGetValue() )
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ (++) For devices with several ADCs: ADC multimode conversion
+ with transfer by DMA:
+ (+++) Activate the ADC peripheral (slave)
+ using function HAL_ADC_Start()
+ (conversion start pending ADC master)
+ (+++) Activate the ADC peripheral (master) and start conversions
+ using function HAL_ADCEx_MultiModeStart_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral (master)
+ using function HAL_ADCEx_MultiModeStop_DMA()
+ (+++) Stop conversion and disable the ADC peripheral (slave)
+ using function HAL_ADC_Stop_IT()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+ (+@) HAL_ADCEx_InjectedConvCpltCallback()
+ (+@) HAL_ADCEx_InjectedQueueOverflowCallback() (for STM32F30x/STM32F33x devices)
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+
+ (++) For STM32F30x/STM32F33x devices:
+ Caution: For devices with several ADCs:
+ These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4
+ if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
+
+ (+++) For example, in case of device with a single ADC:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC1_FORCE_RESET() (optional)
+ (+++) __HAL_RCC_ADC1_RELEASE_RESET() (optional)
+ (+++) __HAL_RCC_ADC1_CLK_DISABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
+ (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_OFF (optional, if configured before)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
+
+ (+++) For example, in case of device with 4 ADCs:
+ (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
+ (+++) {
+ (+++) __HAL_RCC_ADC12_FORCE_RESET() (optional)
+ (+++) __HAL_RCC_ADC12_RELEASE_RESET() (optional)
+ (+++) __HAL_RCC_ADC12_CLK_DISABLE() (mandatory)
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before)
+ (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_OFF (optional, if configured before)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
+ (+++) }
+ (+++) else
+ (+++) {
+ (+++) __HAL_RCC_ADC32_FORCE_RESET() (optional)
+ (+++) __HAL_RCC_ADC32_RELEASE_RESET() (optional)
+ (+++) __HAL_RCC_ADC34_CLK_DISABLE() (mandatory)
+ (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_OFF (optional, if configured before)
+ (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
+ (+++) }
+
+ (++) For STM32F37x devices:
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_OFF
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * depending on both possible clock sources: PLL clock or AHB clock.
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note For devices with several ADCs: parameters related to common ADC
+ * registers (ADC clock mode) are set only if all ADCs sharing the
+ * same common group are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs sharing the same common group.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note For devices with several ADCs: Global reset of all ADCs sharing a
+ * common group is possible.
+ * As this function is intended to reset a single ADC, to not impact
+ * other ADCs, instructions for global reset of multiple ADCs have been
+ * let commented below.
+ * If needed, the example code can be copied and uncommented into
+ * function HAL_ADC_MspDeInit().
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Initializes the ADC MSP.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitializes the ADC MSP.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, converson is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Poll for conversion event.
+ * @param hadc: ADC handle
+ * @param EventType: the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
+ * @arg ADC_OVR_EVENT: ADC Overrun event
+ * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group) or EOS (end of
+ * sequence of regular group) depending on ADC initialization
+ * parameter "EOCSelection" (if available)
+ * - overrun (if available)
+ * Each of these interruptions has its dedicated callback function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interruption of
+ * end-of-conversion, disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun (if available)
+ * Each of these interruptions has its dedicated callback function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStart function.
+ * @param hadc: ADC handle
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note: Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStop function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+__weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading DR register automatically clears EOC (end of conversion of
+ * regular group) flag.
+ * Additionally, this functions clears EOS (end of sequence of
+ * regular group) flag, in case of the end of the sequence is reached.
+ * @param hadc: ADC handle
+ * @retval Converted value
+ */
+__weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Handles ADC interrupt request.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+}
+
+/**
+ * @brief Conversion complete callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog callback in non blocking mode.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non blocking mode
+ * (ADC conversion with interruption or transfer by DMA)
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc: ADC handle
+ * @param sConfig: Structure of ADC channel for regular group.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Configures the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @param hadc: ADC handle
+ * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_adc_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral state and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the ADC state
+ * @note ADC state machine is managed by bitfield, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
+ * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
+ * @param hadc: ADC handle
+ * @retval HAL state
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code
+ * @param hadc: ADC handle
+ * @retval ADC Error Code
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
@@ -0,0 +1,7448 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of injected
+ * group, using 2 possible modes: polling, interruption.
+ * ++ Multimode feature (available on devices with 2 ADCs or more)
+ * ++ Calibration (ADC automatic self-calibration)
+ * + Control functions
+ * ++ Channels configuration on injected group
+ * Other functions (generic functions) are available in file
+ * "stm32f3xx_hal_adc.c".
+ *
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32f3xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+ /* Fixed timeout values for ADC calibration, enable settling time, disable */
+ /* settling time. */
+ /* Values defined to be higher than worst cases: low clock frequency, */
+ /* maximum prescalers. */
+ /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */
+ /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */
+ /* resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
+ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 11)
+
+ /* Timeout to wait for current conversion on going to be completed. */
+ /* Timeout fixed to worst case, for 1 channel. */
+ /* - maximum sampling time (601.5 adc_clk) */
+ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
+ /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */
+ /* Unit: cycles of CPU clock. */
+ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 156928)
+
+ /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+ /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
+ /* Unit: us */
+ #define ADC_STAB_DELAY_US ((uint32_t) 10)
+
+ /* Delay for temperature sensor stabilization time. */
+ /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */
+ /* Unit: us */
+ #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+ /* Timeout values for ADC enable and disable settling time. */
+ /* Values defined to be higher than worst cases: low clocks freq, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
+
+ /* Delay for ADC calibration: */
+ /* Hardware prerequisite before starting a calibration: the ADC must have */
+ /* been in power-on state for at least two ADC clock cycles. */
+ /* Unit: ADC clock cycles */
+ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2)
+
+ /* Timeout value for ADC calibration */
+ /* Value defined to be higher than worst cases: low clocks freq, */
+ /* maximum prescaler. */
+ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
+ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* Unit: ms */
+ #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
+
+ /* Delay for ADC stabilization time. */
+ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+ /* Unit: us */
+ #define ADC_STAB_DELAY_US ((uint32_t) 1)
+
+ /* Delay for temperature sensor stabilization time. */
+ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
+ /* Unit: us */
+ #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+
+ /* Maximum number of CPU cycles corresponding to 1 ADC cycle */
+ /* Value fixed to worst case: clock prescalers slowing down ADC clock to */
+ /* minimum frequency */
+ /* - AHB prescaler: 16 */
+ /* - ADC prescaler: 8 */
+ /* Unit: cycles of CPU clock. */
+ #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ((uint32_t) 128)
+
+ /* ADC conversion cycles (unit: ADC clock cycles) */
+ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
+ /* resolution 12 bits) */
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
+static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
+#endif /* STM32F373xC || STM32F378xx */
+
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 ADCEx Initialization and de-initialization functions
+ * @brief ADC Extended Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * depending on possible clock sources: AHB clock or PLL clock.
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned by ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note For devices with several ADCs: parameters related to common ADC
+ * registers (ADC clock mode) are set only if all ADCs sharing the
+ * same common group are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs sharing the same common group.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+ uint32_t tmpCFGR = 0;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+
+ /* Configuration of ADC core parameters and ADC MSP related parameters */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
+ /* at RCC top level. */
+ /* Refer to header of this file for more details on clock enabling */
+ /* procedure. */
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ /* - ADC voltage regulator enable */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize HAL ADC API internal variables */
+ hadc->InjectionConfig.ChannelCount = 0;
+ hadc->InjectionConfig.ContextQueue = 0;
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+
+ /* Enable voltage regulator (if disabled at this step) */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
+ {
+ /* Note: The software must wait for the startup time of the ADC */
+ /* voltage regulator before launching a calibration or */
+ /* enabling the ADC. This temporization must be implemented by */
+ /* software and is equal to 10 us in the worst case */
+ /* process/temperature/power supply. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ /* Configuration of ADC parameters if previous preliminary actions */
+ /* are correctly completed. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ (tmp_hal_status == HAL_OK) )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Set the intermediate state before moving the ADC voltage */
+ /* regulator to state enable. */
+ CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
+ /* Set ADVREGEN bits to 0x01 */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
+
+ /* Delay for ADC stabilization time. */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ }
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
+ HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) )
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed and if there is no conversion on going on regular */
+ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
+ /* called to update a parameter on the fly). */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ (tmp_hal_status == HAL_OK) &&
+ (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Configuration of common ADC parameters */
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode clock configuration */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ((tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* Reset configuration of ADC common register CCR: */
+ /* - ADC clock mode: CKMODE */
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */
+ /* into HAL_ADCEx_MultiModeConfigChannel() ) */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() or */
+ /* HAL_ADCEx_InjectedConfigChannel() ) */
+
+ MODIFY_REG(tmpADC_Common->CCR ,
+ ADC_CCR_CKMODE ,
+ hadc->Init.ClockPrescaler );
+ }
+
+
+ /* Configuration of ADC: */
+ /* - resolution */
+ /* - data alignment */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - continuous conversion mode */
+ /* - overrun */
+ /* - discontinuous mode */
+ SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) |
+ ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ hadc->Init.Resolution );
+
+ /* Enable discontinuous mode only if continuous mode is disabled */
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ /* Set the number of channels to be converted in discontinuous mode */
+ SET_BIT(tmpCFGR, ADC_CFGR_DISCEN |
+ ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
+ hadc->Init.ExternalTrigConvEdge );
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - DMA continuous request */
+ /* - LowPowerAutoWait feature */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
+ ADC_CFGR_DMACFG );
+
+ SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+ }
+
+ /* Update ADC configuration register with previous settings */
+ MODIFY_REG(hadc->Instance->CFGR,
+ ADC_CFGR_DISCNUM |
+ ADC_CFGR_DISCEN |
+ ADC_CFGR_CONT |
+ ADC_CFGR_OVRMOD |
+ ADC_CFGR_EXTSEL |
+ ADC_CFGR_EXTEN |
+ ADC_CFGR_ALIGN |
+ ADC_CFGR_RES ,
+ tmpCFGR );
+
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion" */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Set number of ranks in regular group sequencer */
+ MODIFY_REG(hadc->Instance->SQR1 ,
+ ADC_SQR1_L ,
+ (hadc->Init.NbrOfConversion - (uint8_t)1) );
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ }
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Initializes the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (clock source APB2).
+ * See commented example code below that can be copied and uncommented
+ * into HAL_ADC_MspInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_cr1 = 0;
+ uint32_t tmp_cr2 = 0;
+ uint32_t tmp_sqr1 = 0;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+ if(hadc->Init.DiscontinuousConvMode != DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+
+ /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
+ /* at RCC top level. */
+ /* Refer to header of this file for more details on clock enabling */
+ /* procedure. */
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+ }
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ /* Note: In case of ADC already enabled, precaution to not launch an */
+ /* unwanted conversion while modifying register CR2 by writing 1 to */
+ /* bit ADON. */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ (tmp_hal_status == HAL_OK) )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Set ADC parameters */
+
+ /* Configuration of ADC: */
+ /* - data alignment */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity (always set to 1, because needed for all */
+ /* triggers: external trigger of SW start) */
+ /* - continuous conversion mode */
+ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
+ /* HAL_ADC_Start_xxx functions because if set in this function, */
+ /* a conversion on injected group would start a conversion also on */
+ /* regular group after ADC enabling. */
+ tmp_cr2 |= (hadc->Init.DataAlign |
+ hadc->Init.ExternalTrigConv |
+ ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
+
+ /* Configuration of ADC: */
+ /* - scan mode */
+ /* - discontinuous mode disable/enable */
+ /* - discontinuous mode number of conversions */
+ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
+
+ /* Enable discontinuous mode only if continuous mode is disabled */
+ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
+ /* discontinuous is set anyway, but will have no effect on ADC HW. */
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ /* Set the number of channels to be converted in discontinuous mode */
+ tmp_cr1 |= (ADC_CR1_DISCEN |
+ ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Update ADC configuration register CR1 with previous settings */
+ MODIFY_REG(hadc->Instance->CR1,
+ ADC_CR1_SCAN |
+ ADC_CR1_DISCEN |
+ ADC_CR1_DISCNUM ,
+ tmp_cr1 );
+
+ /* Update ADC configuration register CR2 with previous settings */
+ MODIFY_REG(hadc->Instance->CR2,
+ ADC_CR2_ALIGN |
+ ADC_CR2_EXTSEL |
+ ADC_CR2_EXTTRIG |
+ ADC_CR2_CONT ,
+ tmp_cr2 );
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is present by hardware on this device and, if */
+ /* disabled, discards automatically nb of conversions. Anyway, nb of */
+ /* conversions is forced to 0x00 for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion" */
+ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
+ {
+ tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
+ }
+
+ MODIFY_REG(hadc->Instance->SQR1,
+ ADC_SQR1_L ,
+ tmp_sqr1 );
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core IP clocking. */
+ /* Check through register CR2 (excluding bits set in other functions: */
+ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */
+ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */
+ /* measurement path bit (TSVREFE). */
+ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
+ ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
+ ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
+ ADC_CR2_TSVREFE ))
+ == tmp_cr2)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note For devices with several ADCs: Global reset of all ADCs sharing a
+ * common group is possible.
+ * As this function is intended to reset a single ADC, to not impact
+ * other ADCs, instructions for global reset of multiple ADCs have been
+ * let commented below.
+ * If needed, the example code can be copied and uncommented into
+ * function HAL_ADC_MspDeInit().
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Flush register JSQR: queue sequencer reset when injected queue */
+ /* sequencer is enabled and ADC disabled. */
+ /* Enable injected queue sequencer after injected conversion stop */
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_JQOVF | ADC_IT_OVR |
+ ADC_IT_JEOS | ADC_IT_JEOC |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY ) );
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_JQOVF | ADC_FLAG_OVR |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */
+ /* in access mode "read-set": no direct reset applicable. */
+ /* Reset Calibration mode to default setting (single ended): */
+ /* Disable voltage regulator: */
+ /* Note: Voltage regulator disable is conditioned to ADC state disabled: */
+ /* already done above. */
+ /* Note: Voltage regulator disable is intended for power saving. */
+ /* Sequence to disable voltage regulator: */
+ /* 1. Set the intermediate state before moving the ADC voltage regulator */
+ /* to disable state. */
+ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
+ /* 2. Set ADVREGEN bits to 0x10 */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
+ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |
+ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
+ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
+ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
+
+ /* Reset register TR1 */
+ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
+
+ /* Reset register TR2 */
+ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+
+ /* Reset register TR3 */
+ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+ ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+
+
+
+
+
+ /* ========== Reset common ADC registers ========== */
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+ /* Software is allowed to change common parameters only when all ADCs of */
+ /* the common group are disabled. */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* Reset configuration of ADC common register CCR:
+ - clock mode: CKMODE
+ - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into
+ HAL_ADCEx_MultiModeConfigChannel() )
+ - internal measurement paths: Vbat, temperature sensor, Vref (set into
+ HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+ */
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE |
+ ADC_CCR_VBATEN |
+ ADC_CCR_TSEN |
+ ADC_CCR_VREFEN |
+ ADC_CCR_MDMA |
+ ADC_CCR_DMACFG |
+ ADC_CCR_DELAY |
+ ADC_CCR_MULTI );
+
+ /* Other ADC common registers (CSR, CDR) are in access mode read only,
+ no direct reset applicable */
+ }
+
+
+ /* ========== Hard reset and clock disable of ADC peripheral ========== */
+ /* Into HAL_ADC_MspDeInit(), ADC clock can be hard reset and disabled */
+ /* at RCC top level. */
+ /* Refer to header of this file for more details on clock disabling */
+ /* procedure. */
+
+
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Deinitialize the ADC peripheral registers to its default reset values.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check ADC handle */
+ if(hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register SR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
+ ADC_FLAG_JSTRT | ADC_FLAG_STRT));
+
+ /* Reset register CR1 */
+ CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
+ ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
+ ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
+ ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ));
+
+ /* Reset register CR2 */
+ CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
+ ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
+ ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
+ ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
+ ADC_CR2_ADON ));
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP15 |
+ ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
+ ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 ));
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
+ ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
+ ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
+ ADC_SMPR2_SMP0 ));
+
+ /* Reset register JOFR1 */
+ CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
+ /* Reset register JOFR2 */
+ CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
+ /* Reset register JOFR3 */
+ CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
+ /* Reset register JOFR4 */
+ CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
+
+ /* Reset register HTR */
+ CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
+ /* Reset register LTR */
+ CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
+ ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
+ ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L |
+ ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
+ ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
+ ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
+ ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
+
+ /* Reset register JSQR */
+ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
+
+ /* Reset register JSQR */
+ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset VBAT measurement path, in case of enabled before by selecting */
+ /* channel ADC_CHANNEL_VBAT. */
+ SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT);
+
+
+ /* ========== Hard reset ADC peripheral ========== */
+ /* Performs a global reset of the entire ADC peripheral: ADC state is */
+ /* forced to a similar state after device power-on. */
+ /* If needed, copy-paste and uncomment the following reset code into */
+ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
+ /* */
+ /* __HAL_RCC_ADC1_FORCE_RESET() */
+ /* __HAL_RCC_ADC1_RELEASE_RESET() */
+
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
+ * @brief ADC Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+
+ (+) Start conversion of injected group.
+ (+) Stop conversion of injected group.
+ (+) Poll for conversion complete on injected group.
+ (+) Get result of injected channel conversion.
+ (+) Start conversion of injected group and enable interruptions.
+ (+) Stop conversion of injected group and disable interruptions.
+
+ (+) Start multimode and enable DMA transfer.
+ (+) Stop multimode and disable ADC DMA transfer.
+ (+) Get result of multimode conversion.
+
+ (+) Perform the ADC self-calibration for single or differential ending.
+ (+) Get calibration factors for single or differential ending.
+ (+) Set calibration factors for single or differential ending.
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (for devices with several ADCs):
+ * if ADC is slave, ADC is enabled only (conversion is not started).
+ * if ADC is master, ADC is enabled and multimode conversion is started.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) and multimode state */
+ /* for all cases of multimode: independent mode, multimode ADC master */
+ /* or multimode ADC slave (for devices with several ADCs): */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ /* Set ADC state (ADC independent or master) */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ else
+ {
+ /* Set ADC state (ADC slave) */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular*/
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group.
+ * Interruptions enabled in this function: None.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) */
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Note: Alternate trigger for single conversion could be to force an */
+ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC conversion of both groups regular and injected,
+ * disable ADC peripheral.
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use,
+ * it should be preliminarily stopped using function
+ * @ref HAL_ADCEx_InjectedStop().
+ * To stop ADC conversion only on ADC group regular
+ * while letting ADC group injected conversions running,
+ * use function @ref HAL_ADCEx_RegularStop().
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @note Depending on init parameter "EOCSelection", flags EOS or EOC is
+ * checked and cleared depending on autodelay status (bit AUTDLY).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_EOC;
+ ADC_Common_TypeDef *tmpADC_Common;
+ uint32_t tmp_cfgr = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+/* If end of conversion selected to end of sequence */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_EOC = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of each conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Check DMA configuration, depending on MultiMode set or not */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
+ {
+ if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
+
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if(ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion or End of Sequence flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Clear end of conversion flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
+ {
+ /* Clear regular group conversion flag */
+ /* (EOC or EOS depending on HAL ADC initialization parameter) */
+ __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode.
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion.
+ * @note On STM32F37x devices, limitation in case of sequencer enabled
+ * (several ranks selected): polling cannot be done on each
+ * conversion inside the sequence. In this case, polling is replaced by
+ * wait for maximum conversion time.
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Variables for polling in case of scan mode enabled */
+ uint32_t Conversion_Timeout_CPU_cycles_max = 0;
+ uint32_t Conversion_Timeout_CPU_cycles = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Polling for end of conversion: differentiation if single/sequence */
+ /* conversion. */
+ /* - If single conversion for regular group (Scan mode disabled or enabled */
+ /* with NbrOfConversion =1), flag EOC is used to determine the */
+ /* conversion completion. */
+ /* - If sequence conversion for regular group (scan mode enabled and */
+ /* NbrOfConversion >=2), flag EOC is set only at the end of the */
+ /* sequence. */
+ /* To poll for each conversion, the maximum conversion time is computed */
+ /* from ADC conversion time (selected sampling time + conversion time of */
+ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
+ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
+ /* As flag EOC is not set after each conversion, no timeout status can */
+ /* be set. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
+ HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) )
+ {
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Replace polling by wait for maximum conversion time */
+ /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
+ /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
+ /* channels. */
+ Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE() ;
+ Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
+
+ /* Poll with maximum conversion time */
+ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+ }
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F37x devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Poll for conversion event.
+ * @param hadc: ADC handle
+ * @param EventType: the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+ * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
+ * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+ * @arg ADC_OVR_EVENT: ADC Overrun event
+ * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get start tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+
+ switch(EventType)
+ {
+ /* Analog watchdog (level out of window) event */
+ /* Note: In case of several analog watchdog enabled, if needed to know */
+ /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
+ /* For example: */
+ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */
+ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */
+ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */
+ /* Check analog watchdog 1 flag */
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ break;
+
+ /* Check analog watchdog 2 flag */
+ case ADC_AWD2_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ break;
+
+ /* Check analog watchdog 3 flag */
+ case ADC_AWD3_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ break;
+
+ /* Injected context queue overflow event */
+ case ADC_JQOVF_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear ADC Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+ break;
+
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ }
+
+ /* Clear ADC Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ break;
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Poll for conversion event.
+ * @param hadc: ADC handle
+ * @param EventType: the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Analog watchdog (level out of window) event */
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group) or EOS (end of
+ * sequence of regular group) depending on ADC initialization
+ * parameter "EOCSelection"
+ * - overrun, depending on ADC initialization parameter "Overrun"
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) and multimode state */
+ /* for all cases of multimode: independent mode, multimode ADC master */
+ /* or multimode ADC slave (for devices with several ADCs): */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ /* Set ADC state (ADC independent or master) */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ else
+ {
+ /* Set ADC state (ADC slave) */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular*/
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ /* Enable ADC overrun interrupt */
+ switch(hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS));
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS));
+ break;
+ }
+
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun interrupt is not activated (overrun event is not considered */
+ /* as an error). */
+ /* (cf ref manual "Managing conversions without using the DMA and */
+ /* without overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group with interruption.
+ * Interruptions enabled in this function:
+ * - EOC (end of conversion of regular group)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) */
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable end of conversion interrupt for regular group */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC conversion of both groups regular and injected,
+ * disable ADC peripheral.
+ * Interruptions disabled in this function:
+ * - EOC (end of conversion of regular group) and EOS (end of
+ * sequence of regular group)
+ * - overrun
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use,
+ * it should be preliminarily stopped using function
+ * @ref HAL_ADCEx_InjectedStop().
+ * To stop ADC conversion only on ADC group regular
+ * while letting ADC group injected conversions running,
+ * use function @ref HAL_ADCEx_RegularStop_IT().
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStart function.
+ * @param hadc: ADC handle
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification if multimode is disabled (for devices with several ADC) */
+ /* If multimode is enabled, dedicated function multimode conversion */
+ /* start DMA must be used. */
+ if(ADC_COMMON_CCR_MULTI(hadc) == RESET)
+ {
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) and multimode state */
+ /* for all cases of multimode: independent mode, multimode ADC master */
+ /* or multimode ADC slave (for devices with several ADCs): */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ /* Set ADC state (ADC independent or master) */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ else
+ {
+ /* Set ADC state (ADC slave) */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+
+ /* If conversions on group regular are also triggering group injected,*/
+ /* update ADC state. */
+ if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular*/
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode */
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately.*/
+ /* If external trigger has been selected, conversion will start at */
+ /* next trigger event. */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * Each of these interruptions has its dedicated callback function.
+ * @note For devices with several ADCs: This function is for single-ADC mode
+ * only. For multimode, use the dedicated MultimodeStart function.
+ * @param hadc: ADC handle
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set group injected state (from auto-injection) */
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC DMA mode */
+ hadc->Instance->CR2 |= ADC_CR2_DMA;
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Note: Alternate trigger for single conversion could be to force an */
+ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
+ if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
+ {
+ /* Start ADC conversion on regular group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on regular group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC conversion of both groups regular and injected,
+ * disable ADC DMA transfer, disable ADC peripheral.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use,
+ * it should be preliminarily stopped using function
+ * @ref HAL_ADCEx_InjectedStop().
+ * To stop ADC conversion only on ADC group regular
+ * while letting ADC group injected conversions running,
+ * use function @ref HAL_ADCEx_RegularStop_DMA().
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStop function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note ADC peripheral disable is forcing interruption of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note For devices with several ADCs: This function is for single-ADC mode
+ * only. For multimode, use the dedicated MultimodeStop function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC DMA mode */
+ hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc: ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: ADC flag EOC is not cleared here by software because */
+ /* automatically cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc: ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Handles ADC interrupt request.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
+ ADC_Common_TypeDef *tmpADC_Common;
+ uint32_t tmp_cfgr = 0x0;
+ uint32_t tmp_cfgr_jqm = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Conversion flag for regular group ========== */
+ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
+ (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Disable interruption if no further conversion upcoming by regular */
+ /* external trigger or by continuous mode, */
+ /* and if scan sequence if completed. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: into callback, to determine if conversion has been triggered */
+ /* from EOC or EOS, possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved */
+ /* data. */
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
+ }
+
+
+ /* ========== Check End of Conversion flag for injected group ========== */
+ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) ||
+ (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS)) )
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Disable interruption if no further conversion upcoming by injected */
+ /* external trigger or by automatic injected conversion with regular */
+ /* group having no further conversion upcoming (same conditions as */
+ /* regular group interruption disabling above), */
+ /* and if injected scan sequence is completed. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
+ {
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: into callback, to determine if conversion has been triggered */
+ /* from JEOC or JEOS, possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+
+ /* ========== Check analog watchdog 1 flag ========== */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window 1 callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ }
+
+ /* ========== Check analog watchdog 2 flag ========== */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Level out of window 2 callback */
+ HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ }
+
+ /* ========== Check analog watchdog 3 flag ========== */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Level out of window 3 callback */
+ HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ }
+
+ /* ========== Check Overrun flag ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and */
+ /* without overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ overrun_error = 1;
+ }
+ else
+ {
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Check DMA configuration, depending on MultiMode set or not */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
+ {
+ if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
+ {
+ overrun_error = 1;
+ }
+ }
+ else
+ {
+ /* MultiMode is enabled, Common Control Register MDMA bits must be checked */
+ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
+ {
+ overrun_error = 1;
+ }
+ }
+ }
+
+ if (overrun_error == 1)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+ }
+
+ /* Clear the Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+
+ }
+
+
+ /* ========== Check Injected context queue overflow flag ========== */
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear the Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ /* Error callback */
+ HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+ }
+
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Handles ADC interrupt request
+ * @param hadc: ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+
+ /* ========== Check End of Conversion flag for regular group ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F37x devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Disable ADC end of single conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+ }
+ }
+
+ /* ========== Check End of Conversion flag for injected group ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, scan sequence on going or by automatic injected */
+ /* conversion from group regular (same conditions as group regular */
+ /* interruption disabling above). */
+ /* Note: On STM32F37x devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
+ {
+ /* Disable ADC end of single conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
+ }
+ }
+
+ /* ========== Check Analog watchdog flags ========== */
+ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
+ {
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+
+ /* Clear the ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ }
+ }
+
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @param hadc: ADC handle
+ * @param SingleDiff: Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
+ * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+
+ /* Select calibration mode single ended or differential ended */
+ hadc->Instance->CR &= (~ADC_CR_ADCALDIF);
+ if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ hadc->Instance->CR |= ADC_CR_ADCALDIF;
+ }
+
+ /* Start ADC calibration */
+ hadc->Instance->CR |= ADC_CR_ADCAL;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * During calibration process, ADC is enabled. ADC is let enabled at
+ * the completion of this function.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Calibration prerequisite: */
+ /* - ADC must be disabled for at least two ADC clock cycles in disable */
+ /* mode before ADC enable */
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Wait two ADC clock cycles */
+ while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2)
+ {
+ wait_loop_index++;
+ }
+
+ /* 2. Enable the ADC peripheral */
+ ADC_Enable(hadc);
+
+
+ /* 3. Resets ADC calibration registers */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration reset completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+
+ /* 4. Start ADC calibration */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for calibration completion */
+ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Get the calibration factor from automatic conversion result
+ * @param hadc: ADC handle
+ * @param SingleDiff: Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
+ * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
+ * @retval Converted value
+ */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Return the selected ADC calibration value */
+ if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
+ }
+ else
+ {
+ return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
+ }
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
+ * @param hadc: ADC handle
+ * @param SingleDiff: Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
+ * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
+ * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum)
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification of hardware constraints before modifying the calibration */
+ /* factors register: ADC must be enabled, no conversion on going. */
+ if ( (ADC_IS_ENABLE(hadc) != RESET) &&
+ (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
+ {
+ /* Set the selected ADC calibration value */
+ if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ MODIFY_REG(hadc->Instance->CALFACT ,
+ ADC_CALFACT_CALFACT_D ,
+ ADC_CALFACT_DIFF_SET(CalibrationFactor) );
+ }
+ else
+ {
+ MODIFY_REG(hadc->Instance->CALFACT,
+ ADC_CALFACT_CALFACT_S ,
+ CalibrationFactor );
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group.
+ * Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Case of independent mode or multimode(for devices with several ADCs):*/
+ /* Set multimode state. */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Enable conversion of injected group, if automatic injected */
+ /* conversion is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
+ ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group.
+ * Interruptions enabled in this function: None.
+ * @param hadc: ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable conversion of injected group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If automatic injected conversion is enabled, conversion will start */
+ /* after next regular group conversion. */
+ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Start ADC conversion on injected group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on injected group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC group injected conversion (potential conversion on going
+ * on ADC group regular is not impacted), disable ADC peripheral
+ * if no conversion is on going on group regular.
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ /* - For ADC injected group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group regular) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group regular) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
+ {
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group injected is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group regular) is intended to continue. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group injected group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group regular is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_EOC;
+ uint32_t tmp_cfgr = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_EOC = ADC_FLAG_JEOS;
+ }
+ /* If end of conversion selected to end of each conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ ((READ_BIT (tmp_cfgr, (ADC_CFGR_JAUTO) == RESET)) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Clear end of conversion flag of injected group if low power feature */
+ /* "Auto Wait" is disabled, to not interfere with this feature until data */
+ /* register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
+ {
+ /* Clear injected group conversion flag */
+ /* (JEOC or JEOS depending on HAL ADC initialization parameter) */
+ __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC);
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc: ADC handle
+ * @param Timeout: Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Variables for polling in case of scan mode enabled */
+ uint32_t Conversion_Timeout_CPU_cycles_max =0;
+ uint32_t Conversion_Timeout_CPU_cycles =0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Polling for end of conversion: differentiation if single/sequence */
+ /* conversion. */
+ /* For injected group, flag JEOC is set only at the end of the sequence, */
+ /* not for each conversion within the sequence. */
+ /* - If single conversion for injected group (scan mode disabled or */
+ /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */
+ /* conversion completion. */
+ /* - If sequence conversion for injected group (scan mode enabled and */
+ /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
+ /* sequence. */
+ /* To poll for each conversion, the maximum conversion time is computed */
+ /* from ADC conversion time (selected sampling time + conversion time of */
+ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
+ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
+ /* As flag JEOC is not set after each conversion, no timeout status can */
+ /* be set. */
+ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
+ {
+ /* Wait until End of Conversion flag is raised */
+ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Replace polling by wait for maximum conversion time */
+ /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
+ /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
+ /* channels. */
+ Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE();
+ Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
+
+ /* Poll with maximum conversion time */
+ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+ }
+
+
+ /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Return ADC state */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group with interruption.
+ * Interruptions enabled in this function:
+ * - JEOC (end of conversion of injected group) or JEOS (end of
+ * sequence of injected group) depending on ADC initialization
+ * parameter "EOCSelection"
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC slave first, then ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Case of independent mode or multimode(for devices with several ADCs):*/
+ /* Set multimode state. */
+ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Enable ADC Injected context queue overflow interrupt if this feature */
+ /* is enabled. */
+ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+ }
+
+ /* Enable ADC end of conversion interrupt */
+ switch(hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+ break;
+ }
+
+ /* Enable conversion of injected group, if automatic injected */
+ /* conversion is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (for devices with several ADCs): */
+ /* - if ADC is slave, ADC is enabled only (conversion is not started). */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
+ ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) )
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART);
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enables ADC, starts conversion of injected group with interruption.
+ * Interruptions enabled in this function:
+ * - JEOC (end of conversion of injected group)
+ * Each of these interruptions has its dedicated callback function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable end of conversion interrupt for injected channels */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Enable conversion of injected group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* If automatic injected conversion is enabled, conversion will start */
+ /* after next regular group conversion. */
+ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Start ADC conversion on injected group with SW start */
+ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+ }
+ else
+ {
+ /* Start ADC conversion on injected group with external trigger */
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
+ }
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC group injected conversion (potential conversion on going
+ * on ADC group regular is not impacted), disable ADC peripheral
+ * if no conversion is on going on group regular.
+ * Interruptions disabled in this function:
+ * - JEOC (end of conversion of injected group) and JEOS (end of
+ * sequence of injected group)
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function must be called for ADC master first, then ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ /* - For ADC injected group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group regular) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group regular) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
+ {
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group injected is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group regular) is intended to continue. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_IT_JQOVF));
+
+ if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) )
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group injected group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group regular is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief With ADC configured in multimode, for ADC master:
+ * Enables ADC, starts conversion of regular group and transfers result
+ * through DMA.
+ * Multimode must have been previously configured using
+ * HAL_ADCEx_MultiModeConfigChannel() function.
+ * Interruptions enabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * Each of these interruptions has its dedicated callback function.
+ * @note ADC slave must be preliminarily enabled using single-mode
+ * HAL_ADC_Start() function.
+ * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_HandleTypeDef tmphadcSlave;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ /* (check on ADC master only) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+
+ /* Enable the ADC peripherals: master and slave (in case if not already */
+ /* enabled previously) */
+ tmp_hal_status = ADC_Enable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Enable(&tmphadcSlave);
+ }
+
+ /* Start conversion all ADCs of multimode are effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state (ADC master) */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP | HAL_ADC_STATE_MULTIMODE_SLAVE,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
+
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief With ADC configured in multimode, for ADC master:
+ * Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted),
+ * disable ADC DMA transfer, disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @note Multimode is kept enabled after this function. To disable multimode
+ * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel of ADC slave.
+ * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential multimode conversion on going, on regular and */
+ /* injected groups. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait until ADSTP=0 for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
+ ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ /* Note: In case of ADC slave using its own DMA channel (multimode */
+ /* parameter "DMAAccessMode" set to disabled): */
+ /* DMA channel of ADC slave should stopped after this function with */
+ /* function HAL_ADC_Stop_DMA. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if ADC are effectively disabled */
+ if ((ADC_Disable(hadc) != HAL_ERROR) &&
+ (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
+ {
+ tmp_hal_status = HAL_OK;
+
+ /* Change ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* In case of error, attempt to disable ADC instances anyway */
+ ADC_Disable(hadc);
+ ADC_Disable(&tmphadcSlave);
+
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Returns the last ADC Master&Slave regular conversions results data
+ * in the selected multi mode.
+ * @note Reading register CDR does not clear flag ADC flag EOC
+ * (ADC group regular end of unitary conversion),
+ * as it is the case for independent mode data register.
+ * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval The converted data value.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
+{
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Return the multi mode conversion value */
+ return tmpADC_Common->CDR;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc: ADC handle
+ * @param InjectedRank: the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Note: ADC flag JEOC is not cleared here by software because */
+ /* automatically cleared by hardware when reading register JDRx. */
+
+ /* Get ADC converted value */
+ switch(InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc: ADC handle
+ * @param InjectedRank: the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Get ADC converted value */
+ switch(InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted), disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted), disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - EOC (end of conversion of regular group) and EOS (end of
+ * sequence of regular group)
+ * - overrun
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted),
+ * disable ADC DMA transfer, disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(),
+ * use function @ref HAL_ADC_Stop().
+ * @note Case of multimode enabled (for devices with several ADCs): This
+ * function is for single-ADC mode only. For multimode, use the
+ * dedicated MultimodeStop function.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief With ADC configured in multimode, for ADC master:
+ * Stop ADC group regular conversion (potential conversion on going
+ * on ADC group injected is not impacted),
+ * disable ADC DMA transfer, disable ADC peripheral
+ * if no conversion is on going on group injected.
+ * Interruptions disabled in this function:
+ * - DMA transfer complete
+ * - DMA half transfer
+ * - overrun
+ * @note To stop ADC conversion of both groups regular and injected and to
+ * to disable ADC peripheral, instead of using 2 functions
+ * @ref HAL_ADCEx_RegularMultiModeStop_DMA() and
+ * @ref HAL_ADCEx_InjectedStop(), use function
+ * @ref HAL_ADCEx_MultiModeStop_DMA.
+ * @note In case of auto-injection mode, this function also stop conversion
+ * on ADC group injected.
+ * @note Multimode is kept enabled after this function. To disable multimode
+ * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel of ADC slave.
+ * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential ADC conversion on going and disable ADC peripheral */
+ /* conditioned to: */
+ /* - For ADC regular group conversion stop: */
+ /* On this STM32 family, conversion on the other group */
+ /* (group injected) can continue (groups regular and injected */
+ /* conversion stop commands are independent) */
+ /* - For ADC disable: */
+ /* No conversion on the other group (group injected) must be intended to */
+ /* continue (groups regular and injected are both impacted by */
+ /* ADC disable) */
+
+ /* 1. Stop potential conversion on going, on regular group only */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversion on ADC group regular is */
+ /* effectively stopped and if no conversion on the other group */
+ /* (ADC group injected) is intended to continue. */
+ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) &&
+ ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) )
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
+ tickstart = HAL_GetTick();
+
+ while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
+ ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ /* Note: In case of ADC slave using its own DMA channel (multimode */
+ /* parameter "DMAAccessMode" set to disabled): */
+ /* DMA channel of ADC slave should stopped after this function with */
+ /* function HAL_ADC_Stop_DMA. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to retain a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if ADC are effectively disabled */
+ if ((ADC_Disable(hadc) != HAL_ERROR) &&
+ (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
+ {
+ tmp_hal_status = HAL_OK;
+
+ /* Change ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* In case of error, attempt to disable ADC instances anyway */
+ ADC_Disable(hadc);
+ ADC_Disable(&tmphadcSlave);
+
+ /* Update ADC state machine (ADC master) to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ }
+
+ }
+ /* Conversion on ADC group regular group is stopped, but ADC is not */
+ /* disabled since conversion on ADC group injected is still on going. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Injected conversion complete callback in non blocking mode
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
+ */
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Injected context queue overflow flag callback.
+ * @note This callback is called if injected context queue is enabled
+ (parameter "QueueInjectedContext" in injected channel configuration)
+ and if a new injected context is set when queue is full (maximum 2
+ contexts).
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
+ in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 2 callback in non blocking mode.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 3 callback in non blocking mode.
+ * @param hadc: ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
+{
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
+ */
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
+ * @brief ADC Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure channels on injected group
+ (+) Configure multimode
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc: ADC handle
+ * @param sConfig: Structure ADC channel for regular group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+ uint32_t tmpOffsetShifted;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
+ assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+
+
+ /* Verification of channel number: Channels 1 to 14 are available in */
+ /* differential mode. Channels 15, 16, 17, 18 can be used only in */
+ /* single-ended mode. */
+ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ }
+ else
+ {
+ assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel rank */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Regular sequence configuration */
+ /* For Rank 1 to 4 */
+ if (sConfig->Rank < 5)
+ {
+ MODIFY_REG(hadc->Instance->SQR1,
+ ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
+ ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 5 to 9 */
+ else if (sConfig->Rank < 10)
+ {
+ MODIFY_REG(hadc->Instance->SQR2,
+ ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
+ ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 10 to 14 */
+ else if (sConfig->Rank < 15)
+ {
+ MODIFY_REG(hadc->Instance->SQR3 ,
+ ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) ,
+ ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 15 to 16 */
+ else
+ {
+ MODIFY_REG(hadc->Instance->SQR4 ,
+ ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank) ,
+ ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+ /* Channel sampling time configuration */
+ /* For channels 10 to 18 */
+ if (sConfig->Channel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
+ }
+ else /* For channels 1 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
+ }
+
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset in function of the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */
+ /* to 0. */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
+
+ /* Configure the selected offset register: */
+ /* - Enable offset */
+ /* - Set channel number */
+ /* - Set offset value */
+ switch (sConfig->OffsetNumber)
+ {
+ case ADC_OFFSET_1:
+ /* Configure offset register 1 */
+ MODIFY_REG(hadc->Instance->OFR1 ,
+ ADC_OFR1_OFFSET1_CH |
+ ADC_OFR1_OFFSET1 ,
+ ADC_OFR1_OFFSET1_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_2:
+ /* Configure offset register 2 */
+ MODIFY_REG(hadc->Instance->OFR2 ,
+ ADC_OFR2_OFFSET2_CH |
+ ADC_OFR2_OFFSET2 ,
+ ADC_OFR2_OFFSET2_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_3:
+ /* Configure offset register 3 */
+ MODIFY_REG(hadc->Instance->OFR3 ,
+ ADC_OFR3_OFFSET3_CH |
+ ADC_OFR3_OFFSET3 ,
+ ADC_OFR3_OFFSET3_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_4:
+ /* Configure offset register 4 */
+ MODIFY_REG(hadc->Instance->OFR4 ,
+ ADC_OFR4_OFFSET4_CH |
+ ADC_OFR4_OFFSET4 ,
+ ADC_OFR4_OFFSET4_EN |
+ ADC_OFR_CHANNEL(sConfig->Channel) |
+ tmpOffsetShifted );
+ break;
+
+ /* Case ADC_OFFSET_NONE */
+ default :
+ /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
+ /* enabled. If this is the case, offset OFRx is disabled. */
+ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR1*/
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
+ }
+ if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR2*/
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
+ }
+ if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR3*/
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
+ }
+ if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ /* Disable offset OFR4*/
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
+ }
+ break;
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Configuration of differential mode */
+ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Disable differential mode (default mode: single-ended) */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
+ }
+ else
+ {
+ /* Enable differential mode */
+ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
+
+ /* Channel sampling time configuration (channel ADC_INx +1 */
+ /* corresponding to differential negative input). */
+ /* For channels 10 to 18 */
+ if (sConfig->Channel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1) );
+ }
+ else /* For channels 1 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1) );
+ }
+ }
+
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ /* Configuration of common ADC parameters */
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
+ ( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
+ ( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
+ )
+ {
+ /* Configuration of common ADC parameters (continuation) */
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* If Channel_16 is selected, enable Temp. sensor measurement path */
+ /* Note: Temp. sensor internal channels available on ADC1 only */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+ }
+ /* If Channel_17 is selected, enable VBAT measurement path */
+ /* Note: VBAT internal channels available on ADC1 only */
+ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
+ }
+ /* If Channel_18 is selected, enable VREFINT measurement path */
+ /* Note: VrefInt internal channels available on all ADCs, but only */
+ /* one ADC is allowed to be connected to VrefInt at the same */
+ /* time. */
+ else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
+ }
+ }
+ /* If the requested internal measurement path has already been */
+ /* enabled and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ }
+
+ }
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the the selected channel to be linked to the regular
+ * group.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into regular group, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_ChannelConfTypeDef".
+ * @param hadc: ADC handle
+ * @param sConfig: Structure of ADC channel for regular group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* Regular sequence configuration */
+ /* For Rank 1 to 6 */
+ if (sConfig->Rank < 7)
+ {
+ MODIFY_REG(hadc->Instance->SQR3 ,
+ ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
+ ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 7 to 12 */
+ else if (sConfig->Rank < 13)
+ {
+ MODIFY_REG(hadc->Instance->SQR2 ,
+ ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
+ ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ MODIFY_REG(hadc->Instance->SQR1 ,
+ ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) ,
+ ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
+ }
+
+
+ /* Channel sampling time configuration */
+ /* For channels 10 to 18 */
+ if (sConfig->Channel > ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
+ }
+ else /* For channels 0 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
+ }
+
+ /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
+ /* and VREFINT measurement path. */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
+ (sConfig->Channel == ADC_CHANNEL_VREFINT) )
+ {
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
+ else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+ {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the ADC injected group and the selected channel to be
+ * linked to the injected group.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InjectionConfTypeDef".
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
+ * be used.
+ * @note Caution: For Injected Context Queue use: a context must be fully
+ * defined before start of injected conversion: all channels configured
+ * consecutively for the same ADC instance. Therefore, Number of calls of
+ * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter
+ * InjectedNbrOfConversion for each context.
+ * - Example 1: If 1 context intended to be used (or not use of this feature:
+ * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks
+ * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be
+ * called once for each channel (3 times) before launching a conversion.
+ * This function must not be called to configure the 4th injected channel:
+ * it would start a new context into context queue.
+ * - Example 2: If 2 contexts intended to be used and usage of the 3 first
+ * injected ranks (InjectedNbrOfConversion=3),
+ * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+ * for each context (3 channels x 2 contexts = 6 calls). Conversion can
+ * start once the 1st context is set. The 2nd context can be set on the fly.
+ * @param hadc: ADC handle
+ * @param sConfigInjected: Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+ uint32_t tmpOffsetShifted;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Injected context queue feature: temporary JSQR variables defined in */
+ /* static to be passed over calls of this function */
+ uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
+ assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Verification of channel number: Channels 1 to 14 are available in */
+ /* differential mode. Channels 15, 16, 17, 18 can be used only in */
+ /* single-ended mode. */
+ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+ else
+ {
+ assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of Injected group sequencer. */
+ /* Hardware constraint: Must fully define injected context register JSQR */
+ /* before make it entering into injected sequencer queue. */
+ /* */
+ /* - if scan mode is disabled: */
+ /* * Injected channels sequence length is set to 0x00: 1 channel */
+ /* converted (channel on injected rank 1) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* * Injected context register JSQR setting is simple: register is fully */
+ /* defined on one call of this function (for injected rank 1) and can */
+ /* be entered into queue directly. */
+ /* - if scan mode is enabled: */
+ /* * Injected channels sequence length is set to parameter */
+ /* "InjectedNbrOfConversion". */
+ /* * Injected context register JSQR setting more complex: register is */
+ /* fully defined over successive calls of this function, for each */
+ /* injected channel rank. It is entered into queue only when all */
+ /* injected ranks have been set. */
+ /* Note: Scan mode is not present by hardware on this device, but used */
+ /* by software for alignment over all STM32 devices. */
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
+ (sConfigInjected->InjectedNbrOfConversion == 1) )
+ {
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer: fixed to 1st rank */
+ /* (scan mode disabled, only rank 1 used) */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */
+
+ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
+ ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
+ sConfigInjected->ExternalTrigInjecConvEdge );
+ }
+ else
+ {
+ SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
+ }
+
+ /* Update ADC register JSQR */
+ MODIFY_REG(hadc->Instance->JSQR ,
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JL ,
+ tmp_JSQR_ContextQueueBeingBuilt );
+
+ /* For debug and informative reasons, hadc handle saves JSQR setting */
+ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
+ }
+ /* If another injected rank than rank1 was intended to be set, and could */
+ /* not due to ScanConvMode disabled, error is reported. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ }
+ else
+ {
+ /* Case of scan mode enabled, several channels to set into injected group */
+ /* sequencer. */
+ /* Procedure to define injected context register JSQR over successive */
+ /* calls of this function, for each injected channel rank: */
+
+ /* 1. Start new context and set parameters related to all injected */
+ /* channels: injected sequence length and trigger */
+ if (hadc->InjectionConfig.ChannelCount == 0)
+ {
+ /* Initialize number of channels that will be configured on the context */
+ /* being built */
+ hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
+ /* Initialize value that will be set into register JSQR */
+ hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
+
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
+ ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
+ sConfigInjected->ExternalTrigInjecConvEdge );
+ }
+ else
+ {
+ SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
+ }
+
+ }
+
+ /* 2. Continue setting of context under definition with parameter */
+ /* related to each channel: channel rank sequence */
+
+ /* Set the JSQx bits for the selected rank */
+ MODIFY_REG(hadc->InjectionConfig.ContextQueue ,
+ ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank) ,
+ ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) );
+
+ /* Decrease channel count after setting into temporary JSQR variable */
+ hadc->InjectionConfig.ChannelCount --;
+
+ /* 3. End of context setting: If last channel set, then write context */
+ /* into register JSQR and make it enter into queue */
+ if (hadc->InjectionConfig.ChannelCount == 0)
+ {
+ /* Update ADC register JSQR */
+ MODIFY_REG(hadc->Instance->JSQR ,
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JL ,
+ hadc->InjectionConfig.ContextQueue );
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on injected group: */
+ /* - Injected context queue: Queue disable (active context is kept) or */
+ /* enable (context decremented, up to 2 contexts queued) */
+ /* - Injected discontinuous mode: can be enabled only if auto-injected */
+ /* mode is disabled. */
+ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
+ {
+ /* If auto-injected mode is disabled: no constraint */
+ if (sConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN ,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
+ ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
+ }
+ /* If auto-injected mode is enabled: Injected discontinuous setting is */
+ /* discarded. */
+ else
+ {
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN ,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );
+
+ /* If injected discontinuous mode was intended to be set and could not */
+ /* due to auto-injected enabled, error is reported. */
+ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Automatic injected conversion: can be enabled if injected group */
+ /* external triggers are disabled. */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+ /* If injected group external triggers are disabled (set to injected */
+ /* software start): no constraint */
+ if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ {
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_JAUTO ,
+ ADC_CFGR_INJECT_AUTO_CONVERSION(sConfigInjected->AutoInjectedConv) );
+ }
+ /* If Automatic injected conversion was intended to be set and could not */
+ /* due to injected group external triggers enabled, error is reported. */
+ else
+ {
+ /* Disable Automatic injected conversion */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+
+ if (sConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* Channel sampling time configuration */
+ /* For channels 10 to 18 */
+ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2 ,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) ,
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+ else /* For channels 1 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1 ,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) ,
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset in function of the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */
+ /* to 0. */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+
+ /* Configure the selected offset register: */
+ /* - Enable offset */
+ /* - Set channel number */
+ /* - Set offset value */
+ switch (sConfigInjected->InjectedOffsetNumber)
+ {
+ case ADC_OFFSET_1:
+ /* Configure offset register 1 */
+ MODIFY_REG(hadc->Instance->OFR1 ,
+ ADC_OFR1_OFFSET1_CH |
+ ADC_OFR1_OFFSET1 ,
+ ADC_OFR1_OFFSET1_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_2:
+ /* Configure offset register 2 */
+ MODIFY_REG(hadc->Instance->OFR2 ,
+ ADC_OFR2_OFFSET2_CH |
+ ADC_OFR2_OFFSET2 ,
+ ADC_OFR2_OFFSET2_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_3:
+ /* Configure offset register 3 */
+ MODIFY_REG(hadc->Instance->OFR3 ,
+ ADC_OFR3_OFFSET3_CH |
+ ADC_OFR3_OFFSET3 ,
+ ADC_OFR3_OFFSET3_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ case ADC_OFFSET_4:
+ /* Configure offset register 4 */
+ MODIFY_REG(hadc->Instance->OFR4 ,
+ ADC_OFR4_OFFSET4_CH |
+ ADC_OFR4_OFFSET4 ,
+ ADC_OFR4_OFFSET4_EN |
+ ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
+ tmpOffsetShifted );
+ break;
+
+ /* Case ADC_OFFSET_NONE */
+ default :
+ /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
+ /* enabled. If this is the case, offset OFRx is disabled. */
+ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR1*/
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
+ }
+ if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR2*/
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
+ }
+ if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR3*/
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
+ }
+ if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
+ {
+ /* Disable offset OFR4*/
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
+ }
+ break;
+ }
+
+ }
+
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Configuration of differential mode */
+ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Disable differential mode (default mode: single-ended) */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+ else
+ {
+ /* Enable differential mode */
+ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
+
+ /* Channel sampling time configuration (channel ADC_INx +1 */
+ /* corresponding to differential negative input). */
+ /* For channels 10 to 18 */
+ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR2,
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1),
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) );
+ }
+ else /* For channels 1 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR1,
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1),
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) );
+ }
+ }
+
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_deInit(). */
+
+ /* Configuration of common ADC parameters */
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
+ ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
+ ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
+ (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
+ )
+ {
+ /* Configuration of common ADC parameters (continuation) */
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ ( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
+ {
+ /* If Channel_16 is selected, enable Temp. sensor measurement path */
+ /* Note: Temp. sensor internal channels available on ADC1 only */
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+ }
+ /* If Channel_17 is selected, enable VBAT measurement path */
+ /* Note: VBAT internal channels available on ADC1 only */
+ else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
+ }
+ /* If Channel_18 is selected, enable VREFINT measurement path */
+ /* Note: VrefInt internal channels available on all ADCs, but only */
+ /* one ADC is allowed to be connected to VrefInt at the same */
+ /* time. */
+ else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+ {
+ SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
+ }
+ }
+ /* If the requested internal measurement path has already been enabled */
+ /* and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the ADC injected group and the selected channel to be
+ * linked to the injected group.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * this function must be called when ADC is not under conversion.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor.
+ * The recommended sampling time is at least:
+ * - For devices STM32F37x: 17.1us for temperature sensor
+ * - For the other STM32F3 devices: 2.2us for each of channels
+ * Vbat/VrefInt/TempSensor.
+ * These internal paths can be be disabled using function
+ * HAL_ADC_DeInit().
+ * @param hadc: ADC handle
+ * @param sConfigInjected: Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of injected group sequencer: */
+ /* - if scan mode is disabled, injected channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* Note: Scan mode is present by hardware on this device and, if */
+ /* disabled, discards automatically nb of conversions. Anyway, nb of */
+ /* conversions is forced to 0x00 for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, injected channels sequence length is set to */
+ /* parameter "InjectedNbrOfConversion". */
+ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+ {
+ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Clear the old SQx bits for all injected ranks */
+ MODIFY_REG(hadc->Instance->JSQR ,
+ ADC_JSQR_JL |
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 ,
+ ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
+ ADC_INJECTED_RANK_1,
+ 0x01) );
+ }
+ /* If another injected rank than rank1 was intended to be set, and could */
+ /* not due to ScanConvMode disabled, error is reported. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Since injected channels rank conv. order depends on total number of */
+ /* injected conversions, selected rank must be below or equal to total */
+ /* number of injected conversions to be updated. */
+ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
+ {
+ /* Clear the old SQx bits for the selected rank */
+ /* Set the SQx bits for the selected rank */
+ MODIFY_REG(hadc->Instance->JSQR ,
+
+ ADC_JSQR_JL |
+ ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) ,
+
+ ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
+ ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) );
+ }
+ else
+ {
+ /* Clear the old SQx bits for the selected rank */
+ MODIFY_REG(hadc->Instance->JSQR ,
+
+ ADC_JSQR_JL |
+ ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
+ sConfigInjected->InjectedRank,
+ sConfigInjected->InjectedNbrOfConversion) ,
+
+ 0x00000000 );
+ }
+ }
+
+ /* Configuration of injected group */
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - external trigger to start conversion */
+ /* Parameters update not conditioned to ADC state: */
+ /* - Automatic injected conversion */
+ /* - Injected discontinuous mode */
+ /* Note: In case of ADC already enabled, caution to not launch an unwanted */
+ /* conversion while modifying register CR2 by writing 1 to bit ADON. */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ MODIFY_REG(hadc->Instance->CR2 ,
+ ADC_CR2_JEXTSEL |
+ ADC_CR2_ADON ,
+ sConfigInjected->ExternalTrigInjecConv );
+ }
+
+ /* Configuration of injected group */
+ /* - Automatic injected conversion */
+ /* - Injected discontinuous mode */
+
+ /* Automatic injected conversion can be enabled if injected group */
+ /* external triggers are disabled. */
+ if (sConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ {
+ SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ /* Injected discontinuous can be enabled only if auto-injected mode is */
+ /* disabled. */
+ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
+ {
+ if (sConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+
+ /* InjectedChannel sampling time configuration */
+ /* For channels 10 to 18 */
+ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
+ {
+ MODIFY_REG(hadc->Instance->SMPR1,
+ ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel),
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+ else /* For channels 1 to 9 */
+ {
+ MODIFY_REG(hadc->Instance->SMPR2,
+ ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel),
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
+ }
+
+
+ /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
+ switch(sConfigInjected->InjectedRank)
+ {
+ case 1:
+ /* Set injected channel 1 offset */
+ MODIFY_REG(hadc->Instance->JOFR1,
+ ADC_JOFR1_JOFFSET1,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 2:
+ /* Set injected channel 2 offset */
+ MODIFY_REG(hadc->Instance->JOFR2,
+ ADC_JOFR2_JOFFSET2,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 3:
+ /* Set injected channel 3 offset */
+ MODIFY_REG(hadc->Instance->JOFR3,
+ ADC_JOFR3_JOFFSET3,
+ sConfigInjected->InjectedOffset);
+ break;
+ case 4:
+ default:
+ MODIFY_REG(hadc->Instance->JOFR4,
+ ADC_JOFR4_JOFFSET4,
+ sConfigInjected->InjectedOffset);
+ break;
+ }
+
+ /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
+ /* and VREFINT measurement path. */
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
+ (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
+ {
+ if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
+ {
+ SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
+
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
+ {
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ }
+ /* if ADC1 Channel_18 is selected, enable VBAT measurement path */
+ else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+ {
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @param hadc: ADC handle
+ * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ uint32_t tmpAWDHighThresholdShifted;
+ uint32_t tmpAWDLowThresholdShifted;
+
+ uint32_t tmpADCFlagAWD2orAWD3;
+ uint32_t tmpADCITAWD2orAWD3;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+ /* Verify if threshold is within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+
+ if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Analog watchdog channels */
+ /* - Analog watchdog thresholds */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
+ {
+
+ /* Analog watchdogs configuration */
+ if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+ {
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: regular and/or injected */
+ /* groups, one or overall group of channels. */
+ /* - Set the Analog watchdog channel (is not used if watchdog */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
+ MODIFY_REG(hadc->Instance->CFGR ,
+ ADC_CFGR_AWD1SGL |
+ ADC_CFGR_JAWD1EN |
+ ADC_CFGR_AWD1EN |
+ ADC_CFGR_AWD1CH ,
+ AnalogWDGConfig->WatchdogMode |
+ ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) );
+
+ /* Shift the offset in function of the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
+ /* are set to 0 */
+ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ /* Set the high and low thresholds */
+ MODIFY_REG(hadc->Instance->TR1 ,
+ ADC_TR1_HT1 |
+ ADC_TR1_LT1 ,
+ ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
+
+ /* Clear the ADC Analog watchdog flag (in case of left enabled by */
+ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
+ /* or HAL_ADC_PollForEvent(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
+ }
+
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+ else
+ {
+ /* Shift the threshold in function of the selected ADC resolution */
+ /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
+ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Set the Analog watchdog channel or group of channels. This also */
+ /* enables the watchdog. */
+ /* Note: Conditionnal register reset, because several channels can be */
+ /* set by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
+ {
+ /* Set the high and low thresholds */
+ MODIFY_REG(hadc->Instance->TR2 ,
+ ADC_TR2_HT2 |
+ ADC_TR2_LT2 ,
+ ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
+
+ SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+ }
+
+ /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
+ /* settings. */
+ tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
+ tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
+ }
+ /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ else
+ {
+ /* Set the Analog watchdog channel or group of channels. This also */
+ /* enables the watchdog. */
+ /* Note: Conditionnal register reset, because several channels can be */
+ /* set by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
+ {
+ /* Set the high and low thresholds */
+ MODIFY_REG(hadc->Instance->TR3 ,
+ ADC_TR3_HT3 |
+ ADC_TR3_LT3 ,
+ ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
+
+ SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel));
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+ }
+
+ /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
+ /* settings. */
+ tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
+ tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
+ }
+
+ /* Clear the ADC Analog watchdog flag (in case of left enabled by */
+ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
+ /* or HAL_ADC_PollForEvent(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
+ }
+ else
+ {
+ __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
+ }
+ }
+
+ }
+ /* If a conversion is on going on regular or injected groups, no update */
+ /* could be done on neither of the AWD configuration structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the analog watchdog.
+ * @note Analog watchdog thresholds can be modified while ADC conversion
+ * is on going.
+ * In this case, some constraints must be taken into account:
+ * the programmed threshold values are effective from the next
+ * ADC EOC (end of unitary conversion).
+ * Considering that registers write delay may happen due to
+ * bus activity, this might cause an uncertainty on the
+ * effective timing of the new programmed threshold values.
+ * @param hadc: ADC handle
+ * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+ assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
+
+ if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Analog watchdog configuration */
+
+ /* Configure ADC Analog watchdog interrupt */
+ if(AnalogWDGConfig->ITMode == ENABLE)
+ {
+ /* Enable the ADC Analog watchdog interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
+ }
+ else
+ {
+ /* Disable the ADC Analog watchdog interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
+ }
+
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: regular and/or injected groups, */
+ /* one or all channels. */
+ /* - Set the Analog watchdog channel (is not used if watchdog */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
+ MODIFY_REG(hadc->Instance->CR1 ,
+ ADC_CR1_AWDSGL |
+ ADC_CR1_JAWDEN |
+ ADC_CR1_AWDEN |
+ ADC_CR1_AWDCH ,
+ AnalogWDGConfig->WatchdogMode |
+ AnalogWDGConfig->Channel );
+
+ /* Set the high threshold */
+ WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
+
+ /* Set the low threshold */
+ WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/**
+ * @brief Enable ADC multimode and configure multimode parameters
+ * @note Possibility to update parameters on the fly:
+ * This function initializes multimode parameters, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
+ * the ADCs (both ADCs of the common group).
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_MultiModeTypeDef".
+ * @note To change back configuration from multimode to single mode, ADC must
+ * be reset (using function HAL_ADC_Init() ).
+ * @param hadc: ADC handle
+ * @param multimode : Structure of ADC multimode configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_MODE(multimode->Mode));
+ assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
+ assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* Set handle of the other ADC sharing the same common register */
+ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Multimode DMA configuration */
+ /* - Multimode DMA mode */
+ if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
+ {
+ /* Pointer to the common control register to which is belonging hadc */
+ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
+ /* control registers) */
+ tmpADC_Common = ADC_COMMON_REGISTER(hadc);
+
+ /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
+ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
+ /* - DMA access mode */
+ MODIFY_REG(tmpADC_Common->CCR ,
+ ADC_CCR_MDMA |
+ ADC_CCR_DMACFG ,
+ multimode->DMAAccessMode |
+ ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ /* Note: If ADC is not in the appropriate state to modify these */
+ /* parameters, their setting is bypassed without error reporting */
+ /* (as it can be the expected behaviour in case of intended action */
+ /* to update parameter above (which fulfills the ADC state */
+ /* condition: no conversion on going on group regular) */
+ /* on the fly). */
+ if ((ADC_IS_ENABLE(hadc) == RESET) &&
+ (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
+ {
+ /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
+ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
+ /* - set the selected multimode */
+ /* - DMA access mode */
+ /* - Set delay between two sampling phases */
+ /* Note: Delay range depends on selected resolution: */
+ /* from 1 to 12 clock cycles for 12 bits */
+ /* from 1 to 10 clock cycles for 10 bits, */
+ /* from 1 to 8 clock cycles for 8 bits */
+ /* from 1 to 6 clock cycles for 6 bits */
+ /* If a higher delay is selected, it will be clamped to maximum delay */
+ /* range */
+ MODIFY_REG(tmpADC_Common->CCR ,
+ ADC_CCR_MULTI |
+ ADC_CCR_DELAY ,
+ multimode->Mode |
+ multimode->TwoSamplingDelay );
+ }
+ }
+ /* If one of the ADC sharing the same common group is enabled, no update */
+ /* could be done on neither of the multimode structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F328xx || STM32F334x8 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Private_Functions ADCEx Private Functions
+ * @{
+ */
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F1 devices, in case of sequencer enabled */
+ /* (several ranks selected), end of conversion flag is raised */
+ /* at the end of the sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Half conversion callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+
+ /* Verification if ADC is not already disabled: */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if (ADC_IS_ENABLE(hadc) != RESET )
+ {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
+ {
+ /* Disable the ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
+ {
+ if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Stop ADC conversion.
+ * @param hadc: ADC handle
+ * @param ConversionGroup: ADC group regular and/or injected.
+ * This parameter can be one of the following values:
+ * @arg ADC_REGULAR_GROUP: ADC regular conversion type.
+ * @arg ADC_INJECTED_GROUP: ADC injected conversion type.
+ * @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
+{
+ uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
+ uint32_t tickstart = 0;
+ uint32_t Conversion_Timeout_CPU_cycles = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+ /* Verification if ADC is not already stopped (on regular and injected */
+ /* groups) to bypass this function if not needed. */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
+ {
+ /* Particular case of continuous auto-injection mode combined with */
+ /* auto-delay mode. */
+ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
+ /* injected group stop ADC_CR_JADSTP). */
+ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
+ /* (see reference manual). */
+ if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) &&
+ (hadc->Init.ContinuousConvMode==ENABLE) &&
+ (hadc->Init.LowPowerAutoWait==ENABLE) )
+ {
+ /* Use stop of regular group */
+ ConversionGroup = ADC_REGULAR_GROUP;
+
+ /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
+ {
+ if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+
+ /* Clear JEOS */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+ }
+
+ /* Stop potential conversion on going on regular group */
+ if (ConversionGroup != ADC_INJECTED_GROUP)
+ {
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
+ {
+ /* Stop conversions on regular group */
+ hadc->Instance->CR |= ADC_CR_ADSTP;
+ }
+ }
+
+ /* Stop potential conversion on going on injected group */
+ if (ConversionGroup != ADC_REGULAR_GROUP)
+ {
+ /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
+ {
+ /* Stop conversions on injected group */
+ hadc->Instance->CR |= ADC_CR_JADSTP;
+ }
+ }
+
+ /* Selection of start and stop bits in function of regular or injected group */
+ switch(ConversionGroup)
+ {
+ case ADC_REGULAR_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+ break;
+ case ADC_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+ break;
+ /* Case ADC_REGULAR_GROUP */
+ default:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+ break;
+ }
+
+ /* Wait for conversion effectively stopped */
+ tickstart = HAL_GetTick();
+
+ while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (ADC_IS_ENABLE(hadc) == RESET)
+ {
+ /* Enable the Peripheral */
+ __HAL_ADC_ENABLE(hadc);
+
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait for ADC effectively enabled */
+ while(ADC_IS_ENABLE(hadc) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop ADC conversion and disable the selected ADC
+ * @param hadc: ADC handle
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
+{
+ uint32_t tickstart = 0;
+
+ /* Verification if ADC is not already disabled: */
+ if (ADC_IS_ENABLE(hadc) != RESET)
+ {
+ /* Disable the ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait for ADC effectively disabled */
+ while(ADC_IS_ENABLE(hadc) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
@@ -0,0 +1,1413 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_can.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (++) Connect and configure the involved CAN pins to AF9 using the
+ following function HAL_GPIO_Init();
+
+ (#) Initialise and configure the CAN using HAL_CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
+ uint32_t tickstart = 0;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
+ ((uint32_t)hcan->Init.SJW) | \
+ ((uint32_t)hcan->Init.BS1) | \
+ ((uint32_t)hcan->Init.BS2) | \
+ ((uint32_t)hcan->Init.Prescaler - 1);
+
+ /* Request leave initialisation */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ status = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(status == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+
+ filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+
+ /* Initialisation mode for the filter */
+ hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
+
+ /* Filter Deactivation */
+ hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos;
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ hcan->Instance->FS1R |= filternbrbitpos;
+ /* 32-bit identifier or First 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ hcan->Instance->FM1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos;
+ }
+
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ hcan->Instance->FA1R |= filternbrbitpos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+
+ /* Select one empty transmit mailbox */
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = 0;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = 1;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ transmitmailbox = 2;
+ }
+
+ if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ {
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[0]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[4]));
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = 0;
+ }
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = 1;
+ }
+ else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ transmitmailbox = 2;
+ }
+
+ if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ {
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[0]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[4]));
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Enable Error warning Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Enable Error passive Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Enable Bus-off Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Enable Last error code Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Enable Error Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+
+ /* Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: FIFO number.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Get the Id */
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ {
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: FIFO number.
+ * @retval HAL status
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable Error warning Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Enable Error passive Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Enable Bus-off Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Enable Last error code Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Enable Error Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+ }
+
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ }
+
+ /* Check End of reception flag for FIFO0 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ /* Check End of reception flag for FIFO1 */
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Check Error Warning Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-Off Flag */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ /* No need for clear of Bus-Off Flag as read-only */
+ }
+
+ /* Check Last error code Flag */
+ if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ {
+ switch(hcan->Instance->ESR & CAN_ESR_LEC)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Clear ERRI Flag */
+ hcan->Instance->MSR |= CAN_MSR_ERRI;
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Private_Functions CAN Private Functions
+ * @brief CAN Frame message Rx/Tx functions
+ *
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable Error warning Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Disable Error passive Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Disable Bus-off Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Disable Last error code Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Get the Id */
+ hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ {
+ hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Disable Error warning Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
+
+ /* Disable Error passive Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
+
+ /* Disable Bus-off Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
+
+ /* Disable Last error code Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
+
+ /* Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+ }
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ {
+ /* Disable CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F302x8 || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c
@@ -0,0 +1,1129 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cec.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief CEC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
+ * Consumer Electronics Control Peripheral (CEC).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The CEC HAL driver can be used as follows:
+
+ (#) Declare a CEC_HandleTypeDef handle structure.
+ (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+ (++) Enable the CEC interface clock.
+ (++) CEC pins configuration:
+ (+++) Enable the clock for the CEC GPIOs.
+ (+++) Configure these CEC pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ and HAL_CEC_Receive_IT() APIs):
+ (+++) Configure the CEC interrupt priority.
+ (+++) Enable the NVIC CEC IRQ handle.
+
+ (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
+ in case of Bit Rising Error, Error-Bit generation conditions, device logical
+ address and Listen mode in the hcec Init structure.
+
+ (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
+
+ -@@- The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup CEC CEC
+ * @brief HAL CEC module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
+ | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
+ | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+ * @{
+ */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the CEC
+ (+) The following parameters need to be configured:
+ (++) SignalFreeTime
+ (++) Tolerance
+ (++) BRERxStop (RX stopped or not upon Bit Rising Error)
+ (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
+ (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
+ (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
+ (++) SignalFreeTimeOption (SFT Timer start definition)
+ (++) OwnAddress (CEC device address)
+ (++) ListenMode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle.
+ * @param hcec: CEC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tmpreg = 0x0;
+
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+ assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+ assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
+ assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
+ assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
+ assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+ assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
+ assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
+ assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
+
+
+ if(hcec->State == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_CEC_MspInit(hcec);
+ }
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ tmpreg = hcec->Init.SignalFreeTime;
+ tmpreg |= hcec->Init.Tolerance;
+ tmpreg |= hcec->Init.BRERxStop;
+ tmpreg |= hcec->Init.BREErrorBitGen;
+ tmpreg |= hcec->Init.LBPEErrorBitGen;
+ tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
+ tmpreg |= hcec->Init.SignalFreeTimeOption;
+ tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
+ tmpreg |= hcec->Init.ListenMode;
+
+ /* Write to CEC Control Register */
+ MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->State = HAL_CEC_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief DeInitialize the CEC peripheral.
+ * @param hcec: CEC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+ /* Check the CEC handle allocation */
+ if(hcec == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+ hcec->State = HAL_CEC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CEC_MspDeInit(hcec);
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->State = HAL_CEC_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief CEC MSP Init.
+ * @param hcec: CEC handle.
+ * @retval None
+ */
+ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CEC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief CEC MSP DeInit.
+ * @param hcec: CEC handle.
+ * @retval None
+ */
+ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CEC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation function #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+ (+) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+
+ (+) There are two mode of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non Blocking mode: The communication is performed using Interrupts.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated CEC IRQ when using Interrupt mode.
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ error is detected
+
+ (+) Blocking mode API's are :
+ (++) HAL_CEC_Transmit()
+ (++) HAL_CEC_Receive()
+
+ (+) Non-Blocking mode API's with Interrupt are :
+ (++) HAL_CEC_Transmit_IT()
+ (++) HAL_CEC_Receive_IT()
+ (++) HAL_CEC_IRQHandler()
+
+ (+) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_CEC_TxCpltCallback()
+ (++) HAL_CEC_RxCpltCallback()
+ (++) HAL_CEC_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send data in blocking mode.
+ * @param hcec: CEC handle.
+ * @param DestinationAddress: destination logical address.
+ * @param pData: pointer to input byte data buffer.
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+ uint8_t temp = 0;
+ uint32_t tempisr = 0;
+ uint32_t tickstart = 0;
+
+ if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if((pData == NULL) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+
+ hcec->TxXferCount = Size;
+
+ /* case no data to be sent, sender is only pinging the system */
+ if (Size == 0)
+ {
+ /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ while (hcec->TxXferCount > 0)
+ {
+ hcec->TxXferCount--;
+
+ tickstart = HAL_GetTick();
+ while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* check whether error occured while waiting for TXBR to be set:
+ * has Tx underrun occurred ?
+ * has Tx error occurred ?
+ * has Tx Missing Acknowledge error occurred ?
+ * has Arbitration Loss error occurred ? */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ }
+ /* TXBR to clear BEFORE writing TXDR register */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ if (hcec->TxXferCount == 0)
+ {
+ /* if last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ hcec->Instance->TXDR = *pData++;
+
+ /* error check after TX byte write up */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* end while (while (hcec->TxXferCount > 0)) */
+
+
+ /* if no error up to this point, check that transmission is
+ * complete, that is wait until TXEOM is reset */
+ tickstart = HAL_GetTick();
+
+ while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Final error check once all bytes have been transmitted */
+ tempisr = hcec->Instance->ISR;
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = tempisr;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
+ * @param hcec: CEC handle
+ * @param pData: pointer to received data buffer.
+ * @param Timeout: Timeout duration.
+ * @note The received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0;
+
+ if (hcec->State == HAL_CEC_STATE_READY)
+ {
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ if (pData == NULL)
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ hcec->RxXferSize = 0;
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+
+ /* Rx loop until CEC_FLAG_RXEND is set */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
+ {
+ tickstart = HAL_GetTick();
+ /* Wait for next byte to be received */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_TIMEOUT;
+ }
+ }
+ /* any error so far ?
+ * has Rx Missing Acknowledge occurred ?
+ * has Rx Long Bit Period error occurred ?
+ * has Rx Short Bit Period error occurred ?
+ * has Rx Bit Rising error occurred ?
+ * has Rx Overrun error occurred ? */
+ temp = (uint32_t) (hcec->Instance->ISR);
+ if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
+ {
+ /* copy ISR for error handling purposes */
+ hcec->ErrorCode = temp;
+ /* clear all error flags by default */
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
+ hcec->State = HAL_CEC_STATE_ERROR;
+ __HAL_UNLOCK(hcec);
+ return HAL_ERROR;
+ }
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) */
+
+
+ /* read received data */
+ *pData++ = hcec->Instance->RXDR;
+ temp = (uint32_t) (hcec->Instance->ISR);
+ /* end of message ? */
+ if ((temp & CEC_FLAG_RXEND) != 0)
+ {
+ assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+
+ /* clear Rx-Byte Received flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
+ /* increment payload byte counter */
+ hcec->RxXferSize++;
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) */
+
+ /* if the instructions below are executed, it means RXEND was set when RXBR was
+ * set for the first time:
+ * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))"
+ * loop has not been executed and this means a single byte has been sent */
+ *pData++ = hcec->Instance->RXDR;
+ /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
+ hcec->RxXferSize = 0;
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ __HAL_UNLOCK(hcec);
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Send data in interrupt mode.
+ * @param hcec: CEC handle.
+ * @param DestinationAddress: destination logical address.
+ * @param pData: pointer to input byte data buffer.
+ * @param Size: amount of data to be sent in bytes (without counting the header).
+ * 0 means only the header is sent (ping operation).
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+{
+ uint8_t temp = 0;
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
+ && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
+ {
+ if((pData == NULL) && (Size > 0))
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->pTxBuffPtr = pData;
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following two CEC Transmission interrupts as
+ * well as the following CEC Transmission Errors interrupts:
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ /* initialize the number of bytes to send,
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* in case of no payload (Size = 0), sender is only pinging the system;
+ * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ if (Size == 0)
+ {
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+
+ /* send header block */
+ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
+ hcec->Instance->TXDR = temp;
+ /* Set TX Start of Message (TXSOM) bit */
+ __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+ return HAL_OK;
+ }
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+ __HAL_LOCK(hcec);
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+ hcec->State = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle.
+ * @param pData: pointer to received data buffer.
+ * @note The received data size is not known beforehand, the latter is known
+ * when the reception is complete and is stored in hcec->RxXferSize.
+ * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
+ * If only a header is received, hcec->RxXferSize = 0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
+{
+ if(hcec->State == HAL_CEC_STATE_READY)
+ {
+ if(pData == NULL)
+ {
+ hcec->State = HAL_CEC_STATE_ERROR;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+ hcec->RxXferSize = 0;
+ hcec->pRxBuffPtr = pData;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ /* the IP is moving to a ready to receive state */
+ hcec->State = HAL_CEC_STATE_STANDBY_RX;
+
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Enable the following CEC Reception Error Interrupts:
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the following two CEC Reception interrupts:
+ * Rx Byte Received IT
+ * End of Reception IT */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
+
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+
+/**
+ * @brief Get size of the received frame.
+ * @param hcec: CEC handle.
+ * @retval Frame size
+ */
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+{
+ return hcec->RxXferSize;
+}
+
+
+/**
+ * @brief This function handles CEC interrupt requests.
+ * @param hcec: CEC handle.
+ * @retval None
+ */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+ /* save interrupts register for further error or interrupts handling purposes */
+ hcec->ErrorCode = hcec->Instance->ISR;
+ /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC transmit error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX underrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC TX arbitration error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX overrun error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX bit rising error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX short bit period error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX long bit period error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
+ hcec->State = HAL_CEC_STATE_ERROR;
+ }
+
+ if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)
+ {
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
+ /* CEC RX byte received interrupt ---------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+ /* CEC RX end received interrupt ---------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
+ {
+ /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Receive_IT(hcec);
+ }
+
+
+ /* CEC TX byte request interrupt ------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
+ {
+ /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+
+ /* CEC TX end interrupt ------------------------------------------------*/
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
+ {
+ /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
+ CEC_Transmit_IT(hcec);
+ }
+
+}
+
+
+/**
+ * @brief Tx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback
+ * @param hcec: CEC handle
+ * @retval None
+ */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CEC_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief CEC error callback.
+ * @param hcec: CEC handle.
+ * @retval None
+ */
+ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+ /* NOTE : This function should not be modified; when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief CEC control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CEC.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+ (+) HAL_CEC_GetError() API report the CEC handle error code.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CEC state.
+ * @param hcec: CEC handle.
+ * @retval HAL state
+ */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+{
+ return hcec->State;
+}
+
+/**
+* @brief Return the CEC error code.
+* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC.
+* @retval CEC Error Code
+*/
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+{
+ return hcec->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+ /**
+ * @brief Send data in interrupt mode.
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
+{
+ /* if the IP is already busy or if there is a previous transmission
+ already pending due to arbitration loss */
+ if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
+ || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ {
+
+ /* set state to BUSY TX, in case it wasn't set already (case
+ * of transmission new attempt after arbitration loss) */
+ if (hcec->State != HAL_CEC_STATE_BUSY_TX)
+ {
+ hcec->State = HAL_CEC_STATE_BUSY_TX;
+ }
+
+ /* if all data have been sent */
+ if(hcec->TxXferCount == 0)
+ {
+ /* Disable Peripheral to write CEC_IER register */
+ __HAL_CEC_DISABLE(hcec);
+
+ /* Disable the CEC Transmission Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
+ /* Disable the CEC Transmission Error Interrupts */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
+
+ /* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */
+ if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IT_RXBR|CEC_IT_RXEND) ) != RESET)
+ {
+ hcec->State = HAL_CEC_STATE_STANDBY_RX;
+ }
+ else
+ {
+ hcec->State = HAL_CEC_STATE_READY;
+ }
+
+ HAL_CEC_TxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (hcec->TxXferCount == 1)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Receive data in interrupt mode.
+ * @param hcec: CEC handle.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_CEC_Receive_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
+{
+ uint32_t tempisr;
+
+ /* Three different conditions are tested to carry out the RX IT processing:
+ * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
+ * the reception of the first byte is starting
+ * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
+ * and a new byte is being received
+ * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
+ * but has been interrupted by a new message reception or discarded due to
+ * arbitration loss: the reception of the first or higher priority message
+ * (the arbitration winner) is starting */
+ if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_RX)
+ || (hcec->State == HAL_CEC_STATE_BUSY_TX))
+ {
+ /* reception is starting */
+ hcec->State = HAL_CEC_STATE_BUSY_RX;
+ tempisr = (uint32_t) (hcec->Instance->ISR);
+ if ((tempisr & CEC_FLAG_RXBR) != 0)
+ {
+ /* read received byte */
+ *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
+ /* if last byte has been received */
+ if ((tempisr & CEC_FLAG_RXEND) != 0)
+ {
+ /* clear IT */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND);
+ /* RX interrupts are not disabled at this point.
+ * Indeed, to disable the IT, the IP must be disabled first
+ * which resets the TXSOM flag. In case of arbitration loss,
+ * this leads to a transmission abort.
+ * Therefore, RX interruptions disabling if so required,
+ * is done in HAL_CEC_RxCpltCallback */
+
+ /* IP state is moved to READY.
+ * If the IP must remain in standby mode to listen
+ * any new message, it is up to HAL_CEC_RxCpltCallback
+ * to move it again to HAL_CEC_STATE_STANDBY_RX */
+ hcec->State = HAL_CEC_STATE_READY;
+
+ HAL_CEC_RxCpltCallback(hcec);
+
+ return HAL_OK;
+ }
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
+
+ hcec->RxXferSize++;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+
+#endif /* HAL_CEC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c
@@ -0,0 +1,817 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_comp.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief COMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the COMP peripheral:
+ * + Initialization and de-initialization functions
+ * + Start/Stop operation functions in polling mode.
+ * + Start/Stop operation functions in interrupt mode.
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+================================================================================
+ ##### COMP Peripheral features #####
+================================================================================
+
+ [..]
+ The STM32F3xx device family integrates up to 7 analog comparators COMP1, COMP2...COMP7:
+ (#) The non inverting input and inverting input can be set to GPIO pins
+ as shown in table1. COMP Inputs below for STM32F303xB/STM32F303xC as example.
+ For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
+ Reference Manual.
+
+ (#) The COMP output is available using HAL_COMP_GetOutputLevel()
+ and can be set on GPIO pins. Refer to table 2. COMP Outputs below for STM32F303xB/STM32F303xC as example.
+ For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
+ Reference Manual.
+
+ (#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
+ Refer to table 3. COMP Outputs redirection to embedded timers below for STM32F303xB/STM32F303xC as example.
+ For other STM32F3xx devices please refer to the COMP peripheral section in corresponding
+ Reference Manual.
+
+ (#) Each couple of comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
+ mode and respectively COMP1, COMP3 and COMP5 non inverting input is used as common non-inverting input.
+
+ (#) The seven comparators have interrupt capability with wake-up
+ from Sleep and Stop modes (through the EXTI controller):
+ (++) COMP1 is internally connected to EXTI Line 21
+ (++) COMP2 is internally connected to EXTI Line 22
+ (++) COMP3 is internally connected to EXTI Line 29
+ (++) COMP4 is internally connected to EXTI Line 30
+ (++) COMP5 is internally connected to EXTI Line 31
+ (++) COMP6 is internally connected to EXTI Line 32
+ (++) COMP7 is internally connected to EXTI Line 33.
+
+ From the corresponding IRQ handler, the right interrupt source can be retrieved with the
+ adequate macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
+
+[..] Table 1. COMP Inputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
+ +------------------------------------------------------------------------------------------+
+ | | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-----------------|----------------|---------------|---------------------------------------|
+ | | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK |
+ | | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK |
+ | | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
+ | | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
+ |-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
+ | Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
+ | Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
+ +------------------------------------------------------------------------------------------+
+
+ [..] Table 2. COMP Outputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
+ +-------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |-------|-------|-------|-------|-------|-------|-------|
+ | PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
+ | PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
+ | PA6 | PA12 | --- | --- | --- | --- | --- |
+ | PA11 | PB9 | --- | --- | --- | --- | --- |
+ | PB8 | --- | --- | --- | --- | --- | --- |
+ +-------------------------------------------------------+
+
+ [..] Table 3. COMP Outputs redirection to embedded timers for the STM32F303xB/STM32F303xC devices
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | | | | | | | |
+ | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
+ | | | | | | | |
+ | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
+ | | | | | | | |
+ | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
+ | | | | | | | |
+ | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
+ | | | | | | | |
+ | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
+ | | | | | | | |
+ | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
+ | | | | | | | |
+ | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
+ | | | | | | | |
+ | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+ [..] Table 4. COMP Outputs redirection to embedded timers for the STM32F303xE devices
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1) | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1) |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | | | | | | | |
+ | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1) | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1) |
+ | | | | | | | |
+ | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
+ | | | | | | | |
+ | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
+ | | | | | | | |
+ | TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
+ | | | | | | | |
+ | TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
+ | | | | | | | |
+ | TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
+ | | | | | | | |
+ | TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
+ | | | | | | | |
+ | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
+ | | | | | | | |
+ | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1)| TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1)|
+ | | | | | | | |
+ | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
+ | | | | | | | |
+ | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
+ | + | + | + | + | + | + | + |
+ | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
+ | | | | | | | |
+ +----------------------------------------------------------------------------------------------------------------------+
+ (1):This connection consists of connecting both GPIO and COMP output to TIM1/8/20 BRK input through an OR gate, instead
+ of connecting the GPIO to the TIM1/8/20 BRK input and the COMP output to the TIM1/8/20 BRK_ACTH input. The aim is to
+ add a digital filter (3 bits) on the COMP output.
+
+ [..] Table 5. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC/STM32F303xE devices
+ +----------------------------------------------------------------------------------------------------------------------+
+ | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
+ |----------------|----------------|----------------|----------------|----------------|----------------|----------------|
+ | TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | -------- | TIM8 OC5 | TIM1 OC5 |
+ | | | | | | | |
+ | TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM3 OC3 | TIM2 OC4 | TIM8 OC5 |
+ | | | | | | | |
+ | TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 OC5 | TIM15 OC2 | TIM15 OC2 |
+ | | | | | | | |
+ +----------------------------------------------------------------------------------------------------------------------+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ This driver provides functions to configure and program the Comparators of all STM32F3xx devices.
+
+ To use the comparator, perform the following steps:
+
+ (#) Fill in the HAL_COMP_MspInit() to
+ (++) Configure the comparator input in analog mode using HAL_GPIO_Init()
+ (++) Configure the comparator output in alternate function mode using HAL_GPIO_Init() to map the comparator
+ output to the GPIO pin
+ (++) If required enable the COMP interrupt (EXTI line Interrupt): by configuring and enabling EXTI line in Interrupt mode and
+ selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
+ interrupt vector using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() functions.
+
+ (#) Configure the comparator using HAL_COMP_Init() function:
+ (++) Select the inverting input (input minus)
+ (++) Select the non-inverting input (input plus)
+ (++) Select the output polarity
+ (++) Select the output redirection
+ (++) Select the hysteresis level
+ (++) Select the power mode
+ (++) Select the event/interrupt mode
+
+ -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
+ to enable the comparator(s).
+
+ (#) On-the-fly reconfiguration of comparator(s) may be done by calling again HAL_COMP_Init(
+ function with new input parameter values; HAL_COMP_MspInit() function shall be adapted
+ to support multi configurations.
+
+ (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() functions.
+
+ (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
+ to manage comparator outputs (events and output level).
+
+ (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
+ function.
+
+ (#) De-initialize the comparator using HAL_COMP_DeInit() function.
+
+ (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
+ Only a MCU reset can reset that protection.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup COMP COMP
+ * @brief COMP HAL module driver
+ * @{
+ */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+ * @{
+ */
+#define COMP_LOCK_DISABLE ((uint32_t)0x00000000)
+#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and de-initialization functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions to initialize and de-initialize comparators.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the COMP peripheral according to the specified
+ * parameters in the COMP_InitTypeDef and initialize the associated handle.
+ * @note If the selected comparator is locked, initialization cannot be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+ assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
+ assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
+ assert_param(IS_COMP_NONINVERTINGINPUT_INSTANCE(hcomp->Instance, hcomp->Init.NonInvertingInput));
+ assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
+ assert_param(IS_COMP_OUTPUT_INSTANCE(hcomp->Instance, hcomp->Init.Output));
+ assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
+ assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
+ assert_param(IS_COMP_MODE(hcomp->Init.Mode));
+ assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
+ assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
+ assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+
+ if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
+ {
+ assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
+ assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
+ }
+
+ /* Init SYSCFG and the low level hardware to access comparators */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ /* Init the low level hardware : SYSCFG to access comparators */
+ HAL_COMP_MspInit(hcomp);
+
+ if(hcomp->State == HAL_COMP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcomp->Lock = HAL_UNLOCKED;
+ }
+
+ /* Set COMP parameters */
+ /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
+ /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
+ /* Set COMPxBLANKING bits according to hcomp->Init.BlankingSrce value */
+ /* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
+ /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
+ /* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */
+ /* Set COMPxMODE bits according to hcomp->Init.Mode value */
+ COMP_INIT(hcomp);
+
+ /* Initialize the COMP state*/
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+
+ return status;
+}
+
+/**
+ * @brief DeInitialize the COMP peripheral.
+ * @note If the selected comparator is locked, deinitialization cannot be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set COMP_CSR register to reset value */
+ COMP_DEINIT(hcomp);
+
+ /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
+ HAL_COMP_MspDeInit(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcomp);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the COMP MSP.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the COMP MSP.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group2 Start Stop operation functions
+ * @brief Start-Stop operation functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Start Stop operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start a comparator without interrupt generation.
+ (+) Stop a comparator without interrupt generation.
+ (+) Start a comparator with interrupt generation.
+ (+) Stop a comparator with interrupt generation.
+ (+) Handle interrupts from a comparator with associated callback function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the comparator.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t extiline = 0;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if(hcomp->State == HAL_COMP_STATE_READY)
+ {
+ /* Get the EXTI Line output configuration */
+ extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Configure the event generation */
+ if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_EVENT_RISING|COMP_TRIGGERMODE_EVENT_FALLING)) != RESET)
+ {
+ /* Configure the event trigger rising edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_RISING) != RESET)
+ {
+ COMP_EXTI_RISING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_RISING_DISABLE(extiline);
+ }
+
+ /* Configure the trigger falling edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_EVENT_FALLING) != RESET)
+ {
+ COMP_EXTI_FALLING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_FALLING_DISABLE(extiline);
+ }
+
+ /* Enable EXTI event generation */
+ COMP_EXTI_ENABLE_EVENT(extiline);
+
+ /* Clear COMP EXTI pending bit */
+ COMP_EXTI_CLEAR_FLAG(extiline);
+ }
+
+ /* Enable the selected comparator */
+ __HAL_COMP_ENABLE(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop the comparator.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if(hcomp->State == HAL_COMP_STATE_BUSY)
+ {
+ /* Disable the EXTI Line event mode if any */
+ COMP_EXTI_DISABLE_EVENT(COMP_GET_EXTI_LINE(hcomp->Instance));
+
+ /* Disable the selected comparator */
+ __HAL_COMP_DISABLE(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Start the comparator in Interrupt mode.
+ * @param hcomp COMP handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t extiline = 0;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ if(hcomp->State == HAL_COMP_STATE_READY)
+ {
+ /* Configure the EXTI event generation */
+ if((hcomp->Init.TriggerMode & (COMP_TRIGGERMODE_IT_RISING|COMP_TRIGGERMODE_IT_FALLING)) != RESET)
+ {
+ /* Get the EXTI Line output configuration */
+ extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Configure the trigger rising edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
+ {
+ COMP_EXTI_RISING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_RISING_DISABLE(extiline);
+ }
+ /* Configure the trigger falling edge */
+ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
+ {
+ COMP_EXTI_FALLING_ENABLE(extiline);
+ }
+ else
+ {
+ COMP_EXTI_FALLING_DISABLE(extiline);
+ }
+
+ /* Clear COMP EXTI pending bit if any */
+ COMP_EXTI_CLEAR_FLAG(extiline);
+
+ /* Enable EXTI interrupt mode */
+ COMP_EXTI_ENABLE_IT(extiline);
+
+ /* Enable the selected comparator */
+ __HAL_COMP_ENABLE(hcomp);
+
+ hcomp->State = HAL_COMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Stop the comparator in Interrupt mode.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable the EXTI Line interrupt mode */
+ COMP_EXTI_DISABLE_IT(COMP_GET_EXTI_LINE(hcomp->Instance));
+
+ status = HAL_COMP_Stop(hcomp);
+
+ return status;
+}
+
+/**
+ * @brief Comparator IRQ Handler.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
+{
+ uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+ /* Check COMP EXTI flag */
+ if(COMP_EXTI_GET_FLAG(extiline) != RESET)
+ {
+ /* Clear COMP EXTI pending bit */
+ COMP_EXTI_CLEAR_FLAG(extiline);
+
+ /* COMP trigger user callback */
+ HAL_COMP_TriggerCallback(hcomp);
+ }
+}
+
+/**
+ * @brief Comparator callback.
+ * @param hcomp COMP handle
+ * @retval None
+ */
+__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_COMP_TriggerCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the comparators.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Lock the selected comparator configuration.
+ * @note A system reset is required to unlock the comparator configuration.
+ * @param hcomp COMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the COMP handle allocation and lock status */
+ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Set lock flag on state */
+ switch(hcomp->State)
+ {
+ case HAL_COMP_STATE_BUSY:
+ hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
+ break;
+ case HAL_COMP_STATE_READY:
+ hcomp->State = HAL_COMP_STATE_READY_LOCKED;
+ break;
+ default:
+ /* unexpected state */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Set the lock bit corresponding to selected comparator */
+ __HAL_COMP_LOCK(hcomp);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return the output level (high or low) of the selected comparator.
+ * The output level depends on the selected polarity.
+ * If the polarity is not inverted:
+ * - Comparator output is low when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is high when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * If the polarity is inverted:
+ * - Comparator output is high when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - Comparator output is low when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * @param hcomp COMP handle
+ * @retval Returns the selected comparator output level:
+ * @arg @ref COMP_OUTPUTLEVEL_LOW
+ * @arg @ref COMP_OUTPUTLEVEL_HIGH
+ *
+ */
+uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+{
+ uint32_t level=0;
+
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT);
+
+ if(level != 0)
+ {
+ return(COMP_OUTPUTLEVEL_HIGH);
+ }
+ return(COMP_OUTPUTLEVEL_LOW);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the COMP handle state.
+ * @param hcomp COMP handle
+ * @retval HAL state
+ */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+{
+ /* Check the COMP handle allocation */
+ if(hcomp == NULL)
+ {
+ return HAL_COMP_STATE_RESET;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ /* Return COMP handle state */
+ return hcomp->State;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
@@ -0,0 +1,494 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_cortex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ * @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M4 exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+ function according to the following table.
+
+ @brief CORTEX_NVIC_Priority_Table
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
+ ==========================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ==========================================================================================================================
+ NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ --------------------------------------------------------------------------------------------------------------------------
+ NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ==========================================================================================================================
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest pre-emption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure Systick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base
+
+ (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32f3xx_hal_cortex.h file.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Sets the priority grouping field (pre-emption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup: The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Initializes and configures the Region and the memory to be protected.
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != RESET)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00;
+ MPU->RASR = 0x00;
+ }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+ if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+ {
+ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+ }
+}
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c
@@ -0,0 +1,532 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief CRC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+ (+) Initialize CRC calculator
+ (++)specify generating polynomial (IP default or non-default one)
+ (++)specify initialization value (IP default or non-default one)
+ (++)specify input data format
+ (++)specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
+ initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
+ (default or non-default) to initiate CRC calculation
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRC CRC
+ * @brief CRC HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the CRC according to the specified parameters
+ in the CRC_InitTypeDef and create the associated handle
+ (+) DeInitialize the CRC peripheral
+ (+) Initialize the CRC MSP (MCU Specific Package)
+ (+) DeInitialize the CRC MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the CRC according to the specified
+ * parameters in the CRC_InitTypeDef and initialize the associated handle.
+ * @param hcrc: CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ if(hcrc->State == HAL_CRC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_CRC_MspInit(hcrc);
+ }
+
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* check whether or not non-default generating polynomial has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+ {
+ /* initialize IP with default generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+ }
+ else
+ {
+ /* initialize CRC IP with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* check whether or not non-default CRC initial value has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+ if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+ {
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+ }
+ else
+ {
+ WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+ }
+
+
+ /* set input data inversion mode */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
+ /* set output data inversion mode */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
+ /* makes sure the input data format (bytes, halfwords or words stream)
+ * is properly specified by user */
+ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the CRC peripheral.
+ * @param hcrc: CRC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* Check the CRC handle allocation */
+ if(hcrc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+ /* Check the CRC peripheral state */
+ if(hcrc->State == HAL_CRC_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC calculation unit */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ /* DeInit the low level hardware */
+ HAL_CRC_MspDeInit(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CRC MSP.
+ * @param hcrc: CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the CRC MSP.
+ * @param hcrc: CRC handle
+ * @retval None
+ */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CRC_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ using the combination of the previous CRC value and the new one
+
+ [..] or
+
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ independently of the previous CRC value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with the previously computed CRC as initialization value.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength: input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0; /* CRC input data buffer index */
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter Data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+
+/**
+ * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ * starting with hcrc->Instance->INIT as initialization value.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * provided by hcrc->InputDataFormat.
+ * @param BufferLength: input data buffer length (number of bytes if pBuffer
+ * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+ * number of words if pBuffer type is * uint32_t).
+ * @note By default, the API expects a uint32_t pointer as input buffer parameter.
+ * Input buffer pointers with other types simply need to be cast in uint32_t
+ * and the API will internally adjust its input data processing based on the
+ * handle field hcrc->InputDataFormat.
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0; /* CRC input data buffer index */
+ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+
+ /* Process locked */
+ __HAL_LOCK(hcrc);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+ * written in hcrc->Instance->DR) */
+ __HAL_CRC_DR_RESET(hcrc);
+
+ switch (hcrc->InputDataFormat)
+ {
+ case CRC_INPUTDATA_FORMAT_WORDS:
+ /* Enter 32-bit input data to the CRC calculator */
+ for(index = 0; index < BufferLength; index++)
+ {
+ hcrc->Instance->DR = pBuffer[index];
+ }
+ temp = hcrc->Instance->DR;
+ break;
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ /* Specific 8-bit input data handling */
+ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ break;
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ /* Specific 16-bit input data handling */
+ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcrc);
+
+ /* Return the CRC computed value */
+ return temp;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the CRC handle state.
+ * @param hcrc: CRC handle
+ * @retval HAL state
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+ /* Return CRC handle state */
+ return hcrc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Functions CRC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Enter 8-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the IP */
+ for(i = 0; i < (BufferLength/4); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength%4) != 0)
+ {
+ if (BufferLength%4 == 1)
+ {
+ *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
+ }
+ if (BufferLength%4 == 2)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+ }
+ if (BufferLength%4 == 3)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+ *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
+ }
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+
+
+/**
+ * @brief Enter 16-bit input data to the CRC calculator.
+ * Specific data handling to optimize processing time.
+ * @param hcrc: CRC handle
+ * @param pBuffer: pointer to the input data buffer
+ * @param BufferLength: input data buffer length
+ * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+ */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t i = 0; /* input data buffer index */
+
+ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the IP */
+ for(i = 0; i < (BufferLength/2); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1];
+ }
+ if ((BufferLength%2) != 0)
+ {
+ *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
+ }
+
+ /* Return the CRC computed value */
+ return hcrc->Instance->DR;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_crc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended CRC HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the CRC peripheral.
+ *
+ @verbatim
+================================================================================
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+ (+) Configure Input or Output data inversion
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CRCEx CRCEx
+ * @brief CRC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 CRC Extended Initialization and de-initialization functions
+ * @brief CRC Extended Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the generating polynomial
+ (+) Configure the input data inversion
+ (+) Configure the output data inversion
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Initialize the CRC polynomial if different from default one.
+ * @param hcrc: CRC handle
+ * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long).
+ * This parameter is written in normal representation, e.g.
+ * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength: CRC polynomial length.
+ * This parameter can be one of the following values:
+ * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
+ * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
+ * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
+ * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+ uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+ /* Check the parameters */
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while (((Pol & (1U << msb)) == 0) && (msb-- > 0)){}
+
+ switch (PolyLength)
+ {
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ break;
+ }
+
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
+
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Input data mode.
+ * @param hcrc: CRC handle
+ * @param InputReverseMode: Input Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
+ * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
+ * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set input data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Reverse Output data mode.
+ * @param hcrc: CRC handle
+ * @param OutputReverseMode: Output Data inversion mode.
+ * This parameter can be one of the following values:
+ * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
+ * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+ /* Check the parameters */
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+ /* set output data inversion mode */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c
@@ -0,0 +1,731 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief DAC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Digital to Analog Converter (DAC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### DAC Peripheral features #####
+ ==============================================================================
+ [..]
+ *** DAC Channels ***
+ ====================
+ [..]
+ The device integrates up to 3 12-bit Digital Analog Converters that can
+ be used independently or simultaneously (dual mode):
+ (#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
+ (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
+ (for STM32F3 devices having 2 channels on DAC1)
+ (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
+ (for STM32F3 devices having 2 DAC)
+
+ *** DAC Triggers ***
+ ====================
+ [..]
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
+ and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
+ [..]
+ Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+ The used pin (GPIOx_PIN_9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
+
+ (#) Software using DAC_TRIGGER_SOFTWARE
+
+ *** DAC Buffer mode feature ***
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+ Or
+ An output switch
+ (in STM32F303x4, STM32F303x6, STM32F303x8
+ c, STM32F334x6, STM32F334x8
+ & STM32F334xx).
+ To enable, the output switch
+ sConfig.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE;
+ [..]
+ (@) Refer to the device datasheet for more details about output
+ impedance value with and without output buffer.
+
+ *** GPIO configurations guidelines ***
+ =====================
+ [..]
+ When a DAC channel is used (ex channel1 on PA4) and the other is not
+ (ex channel2 on PA5 is configured in Analog and disabled).
+ Channel1 may disturb channel2 as coupling effect.
+ Note that there is no coupling on channel2 as soon as channel2 is turned on.
+ Coupling on adjacent channel could be avoided as follows:
+ when unused PA5 is configured as INPUT PULL-UP or DOWN.
+ PA5 is configured in ANALOG just before it is turned on.
+
+
+ *** DAC wave generation feature ***
+ ===================================
+ [..]
+ Both DAC channels of DAC1 can be used to generate
+ note that wave generation is not available in DAC2.
+ (#) Noise wave
+ (#) Triangle wave
+
+ Wave generation is NOT available in DAC2.
+
+ *** DAC data format ***
+ =======================
+ [..]
+ The DAC data format can be:
+ (#) 8-bit right alignment using DAC_ALIGN_8B_R
+ (#) 12-bit left alignment using DAC_ALIGN_12B_L
+ (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+ *** DAC data value to voltage correspondance ***
+ ================================================
+ [..]
+ The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ [..]
+ DAC_OUTx = VREF+ * DOR / 4095
+ (+) with DOR is the Data Output Register
+ [..]
+ VEF+ is the input voltage reference (refer to the device datasheet)
+ [..]
+ e.g. To set DAC_OUT1 to 0.7V, use
+ (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ *** DMA requests ***
+ =====================
+ [..]
+ A DMA1 or DMA2 request can be generated when an external trigger
+ (but not a software trigger) occurs if DMA1 or DMA2 requests are
+ enabled using HAL_DAC_Start_DMA().
+ [..]
+ DMA1 requests are mapped as following:
+ (#) DAC1 channel1: mapped either on
+ (++) DMA1 channel3
+ (++) or DMA2 channel3 (for STM32F3 devices having 2 DMA)
+ which must be already configured
+ (#) DAC1 channel2:
+ (for STM32F3 devices having 2 channels on DAC1)
+ mapped either on
+ (++) DMA1 channel4
+ (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
+ which must be already configured
+
+ (#) DAC2 channel1: mapped either on
+ (for STM32F3 devices having 2 DAC)
+ (++) DMA1 channel4
+ (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
+ which must be already configured
+
+
+ (@) For Dual mode and specific signal (Triangle and noise) generation please
+ refer to Extended Features Driver description
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) DAC APB clock must be enabled to get write access to DAC
+ registers using HAL_DAC_Init()
+ (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+ (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start()
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
+ (+) Stop the DAC peripheral using HAL_DAC_Stop()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+ of data to be transferred at each end of conversion
+ (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+ (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
+ (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+ *** DAC HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DAC HAL driver.
+
+ (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+ (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+ (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
+ [..]
+ (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DAC DAC
+ * @brief DAC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct and initialize the associated handle.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ if(hdac->State == HAL_DAC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_DAC_MspInit(hdac);
+ }
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Initialize the DAC state*/
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitialize the DAC peripheral registers to their default reset values.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+ /* Check DAC handle */
+ if(hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_DAC_MspDeInit(hdac);
+
+ /* Set DAC error code to none */
+ hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the DAC MSP.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+ (+) Get result of dual mode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+
+{
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables DAC and stop conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Disable the selected DAC channel DMA request */
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+
+ /* Disable the Peripheral */
+ __HAL_DAC_DISABLE(hdac, Channel);
+
+ /* Disable the DMA channel */
+ /* Channel1 is used */
+ if (Channel == DAC_CHANNEL_1)
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+ }
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+ /* For all products including channel 2 */
+ /* DAC channel 2 is available on top of DAC channel 1 */
+ else /* Channel2 is used for */
+ {
+ /* Disable the DMA channel */
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+ }
+#endif
+
+ /* Check if DMA Channel effectively disabled */
+ if (status != HAL_OK)
+ {
+ /* Update DAC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval The selected DAC channel data output value.
+ */
+__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel)
+{
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+__weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+{
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_OK;
+}
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Configure Triangle wave generation.
+ (+) Configure Noise wave generation.
+ (+) Set the specified data holding register value for DAC channel.
+ (+) Set the specified data holding register value for Dual DAC channels.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+
+__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ /* Return function status */
+ return HAL_OK;
+}
+
+__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t alignment, uint32_t data)
+{
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+__weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t alignment, uint32_t data1, uint32_t data2)
+{
+ /* Note : This function is defined into this file for library reference */
+ /* Function content is located into file stm32f3xx_hal_dac_ex.c */
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief DAC Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### DAC Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DAC state.
+ (+) Check the DAC Errors.
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the DAC handle state
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval HAL state
+ */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+{
+ /* Return DAC handle state */
+ return hdac->State;
+}
+
+/**
+ * @brief Return the DAC error code
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval DAC Error Code
+ */
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+{
+ return hdac->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallback1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief DMA underrun DAC callback for Channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
@@ -0,0 +1,1157 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dac_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief DACEx HAL module driver.
+ * This file provides firmware functions to manage the extended
+ * functionalities of the DAC peripheral.
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+ Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+ HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
+ (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+/** @defgroup DACEx DACEx
+ * @brief DAC HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx Private Functions
+ * @{
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1 */
+static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Set the specified data holding register value for DAC channel.
+ (+) Set the specified data holding register value for dual DAC channel
+ (when DAC channel 2 is present in DAC 1)
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set the specified data holding register value for DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data: Data to be loaded in the selected data holding register.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t) (hdac->Instance);
+
+/* DAC 1 has 1 or 2 channels - no DAC2 */
+/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+ }
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+ else /* channel = DAC_CHANNEL_2 */
+ {
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+ }
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is present in DAC 1 */
+/**
+ * @brief Set the specified data holding register value for dual DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Alignment: Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(Alignment));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (Alignment == DAC_ALIGN_8B_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t) (hdac->Instance);
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group2 DACEx Input and Output operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Get result of conversion.
+ (+) Handle DAC IRQ's.
+ (+) Generate triangular-wave
+ (+) Generate noise-wave
+ (+) Callback functions for DAC1 Channel2 (when supported)
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Check if software trigger enabled */
+ if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+ }
+ }
+ else
+ {
+ /* Check if software trigger enabled */
+ if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+ }
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC 1 has 1 channels 1 */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Check if software trigger enabled */
+ if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
+ {
+ /* Enable the selected DAC software conversion */
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+ }
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC 1 has 2 channels 1 & 2 */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Case of use of channel 1 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+ /* Enable the selected DAC channel2 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Case of use of channel 2 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R2 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Enable the DMA Channel */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+ }
+ else
+ {
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC 1 has 1 channel (channel 1) */
+/**
+ * @brief Enables DAC and starts conversion of channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @param pData: The destination peripheral Buffer address.
+ * @param Length: The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment: Specifies the data alignment for DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+ assert_param(IS_DAC_ALIGN(Alignment));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+ /* Enable the selected DAC channel1 DMA request */
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Case of use of channel 1 */
+ switch(Alignment)
+ {
+ case DAC_ALIGN_12B_R:
+ /* Get DHR12R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+ break;
+ case DAC_ALIGN_12B_L:
+ /* Get DHR12L1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+ break;
+ case DAC_ALIGN_8B_R:
+ /* Get DHR8R1 address */
+ tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+ break;
+ default:
+ break;
+ }
+
+ /* Enable the DMA Channel */
+ /* Enable the DAC DMA underrun interrupt */
+ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Enable the Peripheral */
+ __HAL_DAC_ENABLE(hdac, Channel);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC 1 has 2 channels 1 & 2 */
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Returns the DAC channel data output register value */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ return hdac->Instance->DOR1;
+ }
+ else /* channel = DAC_CHANNEL_2 */
+ {
+ return hdac->Instance->DOR2;
+ }
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC 1 has 1 channel (channel 1) */
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
+
+ /* Returns the DAC channel data output register value */
+ return hdac->Instance->DOR1;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Return the last data output value of the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval The selected DAC channel data output value.
+ */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+ uint32_t tmp = 0;
+
+ tmp |= hdac->Instance->DOR1;
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is present in DAC 1 */
+ tmp |= hdac->Instance->DOR2 << 16;
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+ /* Returns the DAC channel data output register value */
+ return tmp;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1 */
+/**
+ * @brief Handles DAC interrupt request
+ * This function uses the interruption of DMA
+ * underrun.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
+{
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
+ /* Check underrun flag of DAC channel 1 */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+ }
+
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+ {
+ /* Check underrun flag of DAC channel 1 */
+ if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to channel2 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+ /* Error callback */
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+ }
+ }
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/* DAC channel 2 is NOT available. Only DAC channel 1 is available */
+/**
+ * @brief Handles DAC interrupt request
+ * This function uses the interruption of DMA
+ * underrun.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
+{
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
+ /* Check underrun flag of DAC channel 1 */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
+
+ /* Set DAC error code to chanel1 DMA underrun error */
+ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+
+ /* Disable the selected DAC channel1 DMA request */
+ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
+ }
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
+#if defined(STM32F328xx)
+ assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
+#endif
+#if defined(STM32F334x8)
+ if (Channel == DAC_CHANNEL_1) /* DAC1 channel 1 or DAC2 channel 1*/
+ {
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ }
+ else /* DAC1 channel 2 */
+ {
+ assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
+ }
+#endif
+#if defined(STM32F303x8)
+ /* DAC1 channel 1 */
+ if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
+ {
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+ }
+ else /* DAC1 channel 2 & DAC2 channel 1 */
+ {
+ assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
+ }
+#endif
+ assert_param(IS_DAC_CHANNEL(Channel));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Get the DAC CR value */
+ tmpreg1 = hdac->Instance->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+#if defined(STM32F328xx)
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
+#else
+ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+#endif
+
+ /* Configure for the selected DAC channel: buffer output or switch output, trigger */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value OR */
+ /* Set OUTEN bit according to DAC_OutputSwitch value */
+#if defined(STM32F328xx)
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
+#elif defined(STM32F334x8)
+ if (Channel == DAC_CHANNEL_1) /* DAC1 channel 1 or DAC2 channel 1*/
+ {
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+ }
+ else /* DAC1 channel 2 */
+ {
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
+ }
+#elif defined(STM32F303x8)
+ /* DAC1 channel 1 */
+ if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
+ {
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+ }
+ else /* DAC1 channel 2 & DAC2 channel 1 */
+ {
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
+ }
+#else
+ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
+#endif
+
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << Channel;
+ /* Write to DAC CR */
+ hdac->Instance->CR = tmpreg1;
+
+ /* Disable wave generation */
+ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @param Amplitude: Select max triangle amplitude.
+ * This parameter can be one of the following values:
+ * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+ * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+ * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+ * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+ * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+ * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+ * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+ * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+ * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+ * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+ * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+ * @note Wave generation is not available in DAC2.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
+ * This parameter can be one of the following values:
+ * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+ * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(Channel));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_BUSY;
+
+ /* Enable the selected wave generation for the selected DAC channel */
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdac);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1 */
+/**
+ * @brief Conversion complete callback in non blocking mode for Channel2
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel2.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel2.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+ */
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DAC_ErrorCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/* DAC channel 2 is available on top of DAC channel 1 */
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DACEx_ErrorCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c
@@ -0,0 +1,709 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_dma.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief DMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Channel
+ (except for internal SRAM / FLASH memories: no initialization is
+ necessary) please refer to Reference manual for connection between peripherals
+ and DMA requests .
+
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ using HAL_DMA_Init() function.
+
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+ (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+ (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Channel source
+ and destination addresses, incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmp = 0;
+
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ if(hdma->State == HAL_DMA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
+ }
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Get the CR register value */
+ tmp = hdma->Instance->CCR;
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
+ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
+ DMA_CCR_DIR));
+
+ /* Prepare the DMA Channel configuration */
+ tmp |= hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* Write to DMA Channel CR register */
+ hdma->Instance->CCR = tmp;
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the DMA peripheral
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA handle allocation */
+ if(hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+ /* Check the DMA peripheral state */
+ if(hdma->State == HAL_DMA_STATE_BUSY)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the selected DMA Channelx */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Reset DMA Channel control register */
+ hdma->Instance->CCR = 0;
+
+ /* Reset DMA Channel Number of Data to Transfer register */
+ hdma->Instance->CNDTR = 0;
+
+ /* Reset DMA Channel peripheral address register */
+ hdma->Instance->CPAR = 0;
+
+ /* Reset DMA Channel memory address register */
+ hdma->Instance->CMAR = 0;
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Initialise the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief I/O operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DMA Transfer.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+
+ /* Enable the Half transfer complete interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+
+ /* Enable the transfer Error interrupt */
+ __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ *
+ * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
+ * effectively disabled is added. If a Channel is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Channel will be effectively disabled only after the transfer of
+ * this single data is finished.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tickstart = 0x00;
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check if the DMA Channel is effectively disabled */
+ while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CompleteLevel: Specifies the DMA level complete.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+ uint32_t temp;
+ uint32_t tickstart = 0x00;
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Transfer Complete flag */
+ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ {
+ if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
+ {
+ /* Clear the transfer error flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers are complete) */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ }
+ else
+ {
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
+ all transfers of half buffer are complete) */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles DMA interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ /* Transfer Error Interrupt management ***************************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+ {
+ /* Disable the transfer error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+
+ /* Clear the transfer error flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_READY_HALF;
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ {
+ if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ {
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable the transfer complete interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+ }
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* Update error code */
+ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions DMA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Configure DMA Channel data length */
+ hdma->Instance->CNDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CPAR = DstAddress;
+
+ /* Configure DMA Channel source address */
+ hdma->Instance->CMAR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Channel source address */
+ hdma->Instance->CPAR = SrcAddress;
+
+ /* Configure DMA Channel destination address */
+ hdma->Instance->CMAR = DstAddress;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
@@ -0,0 +1,702 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief FLASH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the internal FLASH memory:
+ * + Program operations functions
+ * + Memory Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FLASH peripheral features #####
+ ==============================================================================
+ [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+ to the Flash memory. It implements the erase and program Flash memory operations
+ and the read and write protection mechanisms.
+
+ [..] The Flash memory interface accelerates code execution with a system of instruction
+ prefetch.
+
+ [..] The FLASH main features are:
+ (+) Flash memory read operations
+ (+) Flash memory program/erase operations
+ (+) Read / write protections
+ (+) Prefetch on I-Code
+ (+) Option Bytes programming
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions and macros to configure and program the FLASH
+ memory of all STM32F3xx devices.
+
+ (#) FLASH Memory I/O Programming functions: this group includes all needed
+ functions to erase and program the main memory:
+ (++) Lock and Unlock the FLASH interface
+ (++) Erase function: Erase page, erase all pages
+ (++) Program functions: half word, word and doubleword
+
+ (#) FLASH Option Bytes Programming functions: this group includes all needed
+ functions to manage the Option Bytes:
+ (++) Lock and Unlock the Option Bytes
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user Option Bytes
+ (++) Launch the Option Bytes loader
+ (++) Erase Option Bytes
+ (++) Program the data Option Bytes
+ (++) Get the Write protection.
+ (++) Get the user option bytes.
+
+ (#) Interrupts and flags management functions : this group
+ includes all needed functions to:
+ (++) Handle FLASH interrupts
+ (++) Wait for last FLASH operation according to its status
+ (++) Get error flag status
+
+ [..] In addition to these function, this driver includes a set of macros allowing
+ to handle the following operations:
+
+ (+) Set/Get the latency
+ (+) Enable/Disable the prefetch buffer
+ (+) Enable/Disable the half cycle access
+ (+) Enable/Disable the FLASH interrupts
+ (+) Monitor the FLASH flags status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH FLASH
+ * @brief FLASH HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macro ---------------------------- ---------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void FLASH_SetErrorCode(void);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
+ *
+@verbatim
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Program halfword, word or double word at a specified address
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @note FLASH should be previously erased before new programmation (only exception to this
+ * is when 0x0000 is programmed)
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint8_t index = 0;
+ uint8_t nbiterations = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ /* Program halfword (16-bit) at a specified address. */
+ nbiterations = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ /* Program word (32-bit = 2*16-bit) at a specified address. */
+ nbiterations = 2;
+ }
+ else
+ {
+ /* Program double word (64-bit = 4*16-bit) at a specified address. */
+ nbiterations = 4;
+ }
+
+ for (index = 0; index < nbiterations; index++)
+ {
+ FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+ /* In case of error, stop programation procedure */
+ if (status != HAL_OK)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Program halfword, word or double word at a specified address with interrupt enabled.
+ * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
+ *
+ * @note If an erase and a program operations are requested simultaneously,
+ * the erase operation is performed before the program one.
+ *
+ * @param TypeProgram: Indicate the way to program at a specified address.
+ * This parameter can be a value of @ref FLASH_Type_Program
+ * @param Address: Specifies the address to be programmed.
+ * @param Data: Specifies the data to be programmed
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+
+ pFlash.Address = Address;
+ pFlash.Data = Data;
+
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
+ /*Program halfword (16-bit) at a specified address.*/
+ pFlash.DataRemaining = 1;
+ }
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
+ /*Program word (32-bit : 2*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 2;
+ }
+ else
+ {
+ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
+ /*Program double word (64-bit : 4*16-bit) at a specified address.*/
+ pFlash.DataRemaining = 4;
+ }
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(Address, (uint16_t)Data);
+
+ return status;
+}
+
+/**
+ * @brief This function handles FLASH interrupt request.
+ * @retval None
+ */
+void HAL_FLASH_IRQHandler(void)
+{
+ uint32_t addresstmp = 0;
+
+ /* Check FLASH operation error flags */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*return the faulty address*/
+ addresstmp = pFlash.Address;
+ /* Reset address */
+ pFlash.Address = 0xFFFFFFFF;
+
+ /*Save the Error code*/
+ FLASH_SetErrorCode();
+
+ /* FLASH error interrupt user callback */
+ HAL_FLASH_OperationErrorCallback(addresstmp);
+
+ /* Stop the procedure ongoing*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+
+ /* Check FLASH End of Operation flag */
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+ /* Process can continue only if no error detected */
+ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ addresstmp = pFlash.Address;
+ /*Indicate user which sector has been erased*/
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+
+ /*Increment sector number*/
+ addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
+ pFlash.Address = addresstmp;
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase, user callback can be called.*/
+ /*Reset Sector and stop Erase pages procedure*/
+ pFlash.Address = addresstmp = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(addresstmp);
+ }
+ }
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
+ /* Operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+
+ /* MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
+
+ /* Stop Mass Erase procedure*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ else
+ {
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
+ /* Operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
+ }
+ else
+ {
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ }
+ }
+ }
+
+
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+ {
+ /* Operation is completed, disable the PG, PER and MER Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
+
+ /* Disable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ }
+}
+
+
+/**
+ * @brief FLASH end of operation interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which has been erased
+ * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH operation error interrupt callback
+ * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * - Mass Erase: No return value expected
+ * - Pages Erase: Address of the page which returned an error
+ * - Program: Address which was selected for data program
+ * @retval none
+ */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlock the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+ if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
+ {
+ /* Authorize the FLASH Registers access */
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Unlock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+ if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
+ {
+ /* Authorizes the Option Byte register programming */
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Lock the FLASH Option Control Registers access.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+ /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @note This function will reset automatically the MCU.
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+ /* Set the OBL_Launch bit to launch the option byte loading */
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
+ /* Wait for last operation to be completed */
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the FLASH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Get the specific FLASH error flag.
+ * @retval FLASH_ErrorCode: The returned value can be:
+ * @ref FLASH_Error_Codes
+ */
+uint32_t HAL_FLASH_GetError(void)
+{
+ return pFlash.ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Program a half-word (16-bit) at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval None
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+ /* Write data in the address */
+ *(__IO uint16_t*)Address = Data;
+}
+
+/**
+ * @brief Wait for a FLASH operation to complete.
+ * @param Timeout: maximum flash operation timeout
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+ Even if the FLASH operation fails, the BUSY flag will be reset and an error
+ flag will be set */
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
+ __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ /*Save the error code*/
+ FLASH_SetErrorCode();
+ return HAL_ERROR;
+ }
+
+ /* If there is no error flag set */
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Set the specific FLASH error flag.
+ * @retval None
+ */
+static void FLASH_SetErrorCode(void)
+{
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+ }
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+ }
+
+ /* Clear FLASH error pending bits */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
@@ -0,0 +1,1009 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_flash_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended FLASH HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the FLASH peripheral:
+ * + Extended Initialization/de-initialization functions
+ * + Extended I/O operation functions
+ * + Extended Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Flash peripheral extended features #####
+ ==============================================================================
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure and program the FLASH memory
+ of all STM32F3xxx devices. It includes
+
+ (++) Set/Reset the write protection
+ (++) Program the user Option Bytes
+ (++) Get the Read protection Level
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @addtogroup FLASH
+ * @{
+ */
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH HAL Extension module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
+ * @{
+ */
+#define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
+#define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
+#define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+/* Erase operations */
+static void FLASH_MassErase(void);
+
+/* Option bytes control */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
+static uint32_t FLASH_OB_GetWRP(void);
+static uint32_t FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetUser(void);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+ * @{
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
+ * @brief FLASH Memory Erasing functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FLASH Erasing Programming functions #####
+ ==============================================================================
+
+ [..] The FLASH Memory Erasing functions, includes the following functions:
+ (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
+ (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
+ is called with parameter 0xFFFFFFFF
+
+ [..] Any operation of erase should follow these steps:
+ (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
+ program memory access.
+ (#) Call the desired function to erase page.
+ (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
+ (recommended to protect the FLASH memory against possible unwanted operation).
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
+ * must be called before.
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @param[out] PageError pointer to variable that
+ * contains the configuration information on faulty page in case of error
+ * (0xFFFFFFFF means that all the pages have been correctly erased)
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+ uint32_t address = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /* Mass Erase requested for Bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ }
+ }
+ else
+ {
+ /* Page Erase is requested */
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ /* Page Erase requested on address located on bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Erase page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
+ address += FLASH_PAGE_SIZE)
+ {
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
+ * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
+ * must be called before.
+ * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+ * contains the configuration information for the erasing.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* If procedure already ongoing, reject the next one */
+ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+ /* Enable End of FLASH Operation and Error source interrupts */
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+ {
+ /*Mass erase to be done*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+ FLASH_MassErase();
+ }
+ else
+ {
+ /* Erase by page to be done*/
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
+
+ pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+ pFlash.DataRemaining = pEraseInit->NbPages;
+ pFlash.Address = pEraseInit->PageAddress;
+
+ /*Erase 1st page and wait for IT*/
+ FLASH_PageErase(pEraseInit->PageAddress);
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
+ * @brief Option Bytes Programming functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Option Bytes Programming functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ option bytes operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
+{
+ uint8_t rdptmp = OB_RDP_LEVEL_0;
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Get the actual read protection Option Byte value */
+ rdptmp = FLASH_OB_GetRDP();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Restore the last read protection Option Byte value */
+ status = FLASH_OB_RDP_LevelConfig(rdptmp);
+ }
+ }
+
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Program option bytes
+ * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ *
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval HAL_StatusTypeDef HAL Status
+ */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Process Locked */
+ __HAL_LOCK(&pFlash);
+
+ /* Check the parameters */
+ assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+ /* Write protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+ {
+ assert_param(IS_WRPSTATE(pOBInit->WRPState));
+ if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+ {
+ /* Enable of Write protection on the selected page */
+ status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
+ }
+ else
+ {
+ /* Disable of Write protection on the selected page */
+ status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
+ }
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* Read protection configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+ {
+ status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* USER configuration */
+ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+ {
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* DATA configuration*/
+ if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
+ {
+ status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
+ if (status != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+ return status;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&pFlash);
+
+ return status;
+}
+
+/**
+ * @brief Get the Option byte configuration
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
+ * contains the configuration information for the programming.
+ *
+ * @retval None
+ */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+ pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
+
+ /*Get WRP*/
+ pOBInit->WRPPage = FLASH_OB_GetWRP();
+
+ /*Get RDP Level*/
+ pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+ /*Get USER*/
+ pOBInit->USERConfig = FLASH_OB_GetUser();
+}
+
+/**
+ * @brief Get the Option byte user data
+ * @param DATAAdress Address of the option byte DATA
+ * This parameter can be one of the following values:
+ * @arg @ref OB_DATA_ADDRESS_DATA0
+ * @arg @ref OB_DATA_ADDRESS_DATA1
+ * @retval Value programmed in USER data
+ */
+uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
+{
+ uint32_t value = 0;
+
+ if (DATAAdress == OB_DATA_ADDRESS_DATA0)
+ {
+ /* Get value programmed in OB USER Data0 */
+ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
+ }
+ else
+ {
+ /* Get value programmed in OB USER Data1 */
+ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
+ }
+
+ return value;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Full erase of FLASH memory Bank
+ *
+ * @retval None
+ */
+static void FLASH_MassErase(void)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Only bank1 will be erased*/
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @brief Enable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage specifies the page(s) to be write protected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(OB_WRP1_WRP1)
+ uint16_t WRP1_Data = 0xFFFF;
+#endif /* OB_WRP1_WRP1 */
+#if defined(OB_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFF;
+#endif /* OB_WRP2_WRP2 */
+#if defined(OB_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFF;
+#endif /* OB_WRP3_WRP3 */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ /* Get current write protected pages and the new pages to be protected ******/
+ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
+
+#if defined(OB_WRP_PAGES0TO15MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES16TO31MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES32TO47MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES48TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO255MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+#endif /* OB_WRP_PAGES48TO63MASK */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
+ {
+ /* Enable write protection */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(OB_WRP0_WRP0)
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 &= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP0_WRP0 */
+
+#if defined(OB_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 &= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP1_WRP1 */
+
+#if defined(OB_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 &= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP2_WRP2 */
+
+#if defined(OB_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 &= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash page i if
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WriteProtectPage specifies the page(s) to be write unprotected.
+ * The value of this parameter depend on device used within the same series
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint16_t WRP0_Data = 0xFFFF;
+#if defined(OB_WRP1_WRP1)
+ uint16_t WRP1_Data = 0xFFFF;
+#endif /* OB_WRP1_WRP1 */
+#if defined(OB_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFF;
+#endif /* OB_WRP2_WRP2 */
+#if defined(OB_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFF;
+#endif /* OB_WRP3_WRP3 */
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(WriteProtectPage));
+
+ /* Get current write protected pages and the new pages to be unprotected ******/
+ WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
+
+#if defined(OB_WRP_PAGES0TO15MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES16TO31MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES32TO47MASK)
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES48TO127MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+#elif defined(OB_WRP_PAGES48TO255MASK)
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+#endif /* OB_WRP_PAGES48TO63MASK */
+
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
+ {
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(OB_WRP0_WRP0)
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 |= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP0_WRP0 */
+
+#if defined(OB_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 |= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP1_WRP1 */
+
+#if defined(OB_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 |= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP2_WRP2 */
+
+#if defined(OB_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 |= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Set the read protection level.
+ * @param ReadProtectLevel specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
+ * @arg @ref OB_RDP_LEVEL_2 Full chip protection
+ * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+
+ if(status == HAL_OK)
+ {
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ WRITE_REG(OB->RDP, ReadProtectLevel);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Program the FLASH User Option Byte.
+ * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
+ * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
+ assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
+ assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
+ assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
+ assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
+ assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
+#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
+ assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET)));
+#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
+ OB->USER = (UserConfig | 0x08);
+#else
+ OB->USER = (UserConfig | 0x88);
+#endif
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
+ * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
+ * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * (system reset will occur)
+ * Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
+ * @param Address specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data specifies the data to be programmed.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
+{
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Enables the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(READ_REG(FLASH->WRPR));
+}
+
+/**
+ * @brief Returns the FLASH Read Protection level.
+ * @retval FLASH ReadOut Protection Status:
+ * This parameter can be one of the following values:
+ * @arg @ref OB_RDP_LEVEL_0 No protection
+ * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
+ * @arg @ref OB_RDP_LEVEL_2 Full chip protection
+ */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+ uint32_t readstatus = OB_RDP_LEVEL_0;
+ uint32_t tmp_reg = 0;
+
+ /* Read RDP level bits */
+#if defined(FLASH_OBR_RDPRT)
+ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
+#endif
+#if defined(FLASH_OBR_LEVEL1_PROT)
+ tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT));
+#endif /* FLASH_OBR_LEVEL1_PROT */
+
+#if defined(FLASH_OBR_RDPRT)
+ if (tmp_reg == FLASH_OBR_RDPRT_1)
+#endif
+#if defined(FLASH_OBR_LEVEL1_PROT)
+ if (tmp_reg == FLASH_OBR_LEVEL1_PROT)
+#endif /* FLASH_OBR_LEVEL1_PROT */
+ {
+ readstatus = OB_RDP_LEVEL_1;
+ }
+#if defined(FLASH_OBR_RDPRT)
+ else if (tmp_reg == FLASH_OBR_RDPRT_2)
+#elif defined(FLASH_OBR_LEVEL2_PROT)
+ else if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
+#endif
+ {
+ readstatus = OB_RDP_LEVEL_2;
+ }
+ else
+ {
+ readstatus = OB_RDP_LEVEL_0;
+ }
+
+ return readstatus;
+}
+
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
+ * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
+ */
+static uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Erase the specified FLASH memory page
+ * @param PageAddress FLASH page to erase
+ * The value of this parameter depend on device used within the same series
+ *
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t PageAddress)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR, FLASH_CR_PER);
+ WRITE_REG(FLASH->AR, PageAddress);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
@@ -0,0 +1,546 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_gpio.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+ configured by software in several modes:
+ (++) Input mode
+ (++) Analog mode
+ (++) Output mode
+ (++) Alternate function mode
+ (++) External interrupt/event lines
+
+ (+) During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+ multiplexer that allows only one peripheral alternate function (AF) connected
+ to an IO pin at a time. In this way, there can be no conflict between peripherals
+ sharing the same IO pin.
+
+ (+) All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ (+) The external interrupt/event controller consists of up to 23 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup GPIO_Private_Defines GPIO Private Defines
+ * @{
+ */
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+
+#define GPIO_NUMBER ((uint32_t)16)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t temp = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ while ((GPIO_Init->Pin) >> position)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Init->Pin) & (1 << position);
+
+ if(iocurrent)
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3];
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ GPIOx->AFR[position >> 3] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ GPIOx->MODER = temp;
+
+ /* In case of Output or Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ temp |= (GPIO_Init->Speed << (position * 2));
+ GPIOx->OSPEEDR = temp;
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ GPIOx->OTYPER = temp;
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ temp |= ((GPIO_Init->Pull) << (position * 2));
+ GPIOx->PUPDR = temp;
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ temp = SYSCFG->EXTICR[position >> 2];
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
+ SYSCFG->EXTICR[position >> 2] = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->IMR = temp;
+
+ temp = EXTI->EMR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->EMR = temp;
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->RTSR = temp;
+
+ temp = EXTI->FTSR;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->FTSR = temp;
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @brief De-initialize the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position = 0x00;
+ uint32_t iocurrent = 0x00;
+ uint32_t tmp = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Configure the port pins */
+ while (GPIO_Pin >> position)
+ {
+ /* Get current io position */
+ iocurrent = (GPIO_Pin) & (1 << position);
+
+ if (iocurrent)
+ {
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floting Mode */
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+
+
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ /* Clear the External Interrupt or Event for the current IO */
+
+ tmp = SYSCFG->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+ {
+ tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+ }
+ }
+
+ position++;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the specified input port pin.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Set or clear the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ *
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param PinState: specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if(PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = (uint32_t)GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Toggle the specified GPIO pin.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin: specifies the pin to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+* @brief Lock GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32L4 family
+ * @param GPIO_Pin: specifies the port bits to be locked.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callback.
+ * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c
@@ -0,0 +1,7932 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_hrtim.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Resolution Timer (HRTIM) peripheral:
+ * + HRTIM Initialization
+ * + DLL Calibration Start
+ * + Timer Time Base Unit Configuration
+ * + Simple Time Base Start/Stop
+ * + Simple Time Base Start/Stop Interrupt
+ * + Simple Time Base Start/Stop DMA Request
+ * + Simple Output Compare/PWM Channel Configuration
+ * + Simple Output Compare/PWM Channel Start/Stop Interrupt
+ * + Simple Output Compare/PWM Channel Start/Stop DMA Request
+ * + Simple Input Capture Channel Configuration
+ * + Simple Input Capture Channel Start/Stop Interrupt
+ * + Simple Input Capture Channel Start/Stop DMA Request
+ * + Simple One Pulse Channel Configuration
+ * + Simple One Pulse Channel Start/Stop Interrupt
+ * + HRTIM External Synchronization Configuration
+ * + HRTIM Burst Mode Controller Configuration
+ * + HRTIM Burst Mode Controller Enabling
+ * + HRTIM External Events Conditioning Configuration
+ * + HRTIM Faults Conditioning Configuration
+ * + HRTIM Faults Enabling
+ * + HRTIM ADC trigger Configuration
+ * + Waveform Timer Configuration
+ * + Waveform Event Filtering Configuration
+ * + Waveform Dead Time Insertion Configuration
+ * + Waveform Chopper Mode Configuration
+ * + Waveform Compare Unit Configuration
+ * + Waveform Capture Unit Configuration
+ * + Waveform Output Configuration
+ * + Waveform Counter Start/Stop
+ * + Waveform Counter Start/Stop Interrupt
+ * + Waveform Counter Start/Stop DMA Request
+ * + Waveform Output Enabling
+ * + Waveform Output Level Set/Get
+ * + Waveform Output State Get
+ * + Waveform Burst DMA Operation Configuration
+ * + Waveform Burst DMA Operation Start
+ * + Waveform Timer Counter Software Reset
+ * + Waveform Capture Software Trigger
+ * + Waveform Burst Mode Controller Software Trigger
+ * + Waveform Timer Pre-loadable Registers Update Enabling
+ * + Waveform Timer Pre-loadable Registers Software Update
+ * + Waveform Timer Delayed Protection Status Get
+ * + Waveform Timer Burst Status Get
+ * + Waveform Timer Push-Pull Status Get
+ * + Peripheral State Get
+ @verbatim
+==============================================================================
+ ##### Simple mode v.s. waveform mode #####
+==============================================================================
+ [..] The HRTIM HAL API is split into 2 categories:
+ (#)Simple functions: these functions allow for using a HRTIM timer as a
+ general purpose timer with high resolution capabilities.
+ HRTIM simple modes are managed through the set of functions named
+ HAL_HRTIM_Simple. These functions are similar in name and usage
+ to the one defined for the TIM peripheral. When a HRTIM timer operates in
+ simple mode, only a very limited set of HRTIM features are used.
+ Following simple modes are proposed:
+ (++)Output compare mode,
+ (++)PWM output mode,
+ (++)Input capture mode,
+ (++)One pulse mode.
+ (#)Waveform functions: These functions allow taking advantage of the HRTIM
+ flexibility to produce numerous types of control signal. When a HRTIM timer
+ operates in waveform mode, all the HRTIM features are accessible without
+ any restriction. HRTIM waveform modes are managed through the set of
+ functions named HAL_HRTIM_Waveform
+ ##### How to use this driver #####
+==============================================================================
+ [..]
+ (#)Initialize the HRTIM low level resources by implementing the
+ HAL_HRTIM_MspInit() function:
+ (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
+ (##)Connect HRTIM pins to MCU I/Os
+ (+++) Enable the clock for the HRTIM GPIOs using the following
+ function: __HAL_RCC_GPIOx_CLK_ENABLE()
+ (+++) Configure these GPIO pins in Alternate Function mode using
+ HAL_GPIO_Init()
+ (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
+ (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++)Initialize the DMA handle
+ (+++)Associate the initialized DMA handle to the appropriate DMA
+ handle of the HRTIM handle using __HAL_LINKDMA()
+ (+++)Initialize the DMA channel using HAL_DMA_Init()
+ (+++)Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
+ and HAL_NVIC_EnableIRQ()
+ (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
+ (+++)Configure the priority and enable the NVIC for the concerned
+ HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+ (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
+ structure (field of the HRTIM handle) specifies which global interrupt of
+ whole HRTIM must be enabled (Burst mode period, System fault, Faults).
+ It also contains the HRTIM external synchronization configuration. HRTIM
+ can act as a master (generating a synchronization signal) or as a slave
+ (waiting for a trigger to be synchronized).
+
+ (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
+ calibration is executed periodically and compensate for potential voltage
+ and temperature drifts. DLL calibration period is specified by the
+ CalibrationRate argument.
+
+ (#)HRTIM timers cannot be used until the high resolution unit is ready. This
+ can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
+ HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
+ is still going on when timeout given as argument expires. DLL calibration
+ can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
+ In that case an interrupt is generated when the DLL calibration is completed.
+ Note that as DLL calibration is executed on a periodic basis an interrupt
+ will be generated at the end of every DLL calibration operation
+ (worst case: one interrupt every 14 micro seconds !).
+
+ (#) Configure HRTIM resources shared by all HRTIM timers
+ (##)Burst Mode Controller:
+ (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
+ controller: operating mode (continuous or one-shot mode), clock
+ (source, prescaler) , trigger(s), period, idle duration.
+ (##)External Events Conditionning:
+ (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
+ external event channel: source, polarity, edge-sensitivity.
+ External event can be used as triggers (timer reset, input
+ capture, burst mode, ADC triggers, delayed protection)
+ They can also be used to set or reset timer outputs. Up to
+ 10 event channels are available.
+ (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
+ event sampling clock (used for digital filtering).
+ (##)Fault Conditionning:
+ (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
+ fault channel: source, polarity, edge-sensitivity. Fault
+ channels are used to disable the outputs in case of an
+ abnormal operation. Up to 5 fault channels are available.
+ (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
+ sampling clock (used for digital filtering).
+ (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
+ circuitry. By default all fault inputs are disabled.
+ (##)ADC trigger:
+ (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
+ the update of the ADC trigger register and the ADC trigger.
+ 4 independent triggers are available to start both the regular
+ and the injected sequencers of the 2 ADCs
+
+ (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
+ function must be called whatever the HRTIM timer operating mode is
+ (simple v.s. waveform). It configures mainly:
+ (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
+ (##)The HRTIM timer clock prescaler
+ (##)The HRTIM timer period
+ (##)The HRTIM timer repetition counter
+
+ *** If the HRTIM timer operates in simple mode ***
+ ===================================================
+ [..]
+ (#) Start or Stop simple timers
+ (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
+ HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
+ HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
+ (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
+ HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
+ HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
+ HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
+ (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
+ HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
+ HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
+ HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
+ (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
+ HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
+ HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
+ HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
+ (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
+ HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
+ HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
+
+ *** If the HRTIM timer operates in waveform mode ***
+ ====================================================
+ [..]
+ (#) Completes waveform timer configuration
+ (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
+ operating in wave form mode mainly consists in:
+ (+++)Enabling the HRTIM timer interrupts and DMA requests.
+ (+++)Enabling the half mode for the HRTIM timer.
+ (+++)Defining how the HRTIM timer reacts to external synchronization input.
+ (+++)Enabling the push-pull mode for the HRTIM timer.
+ (+++)Enabling the fault channels for the HRTIM timer.
+ (+++)Enabling the dead-time insertion for the HRTIM timer.
+ (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
+ on which the delayed protection are applied).
+ (+++)Specifying the HRTIM timer update and reset triggers.
+ (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
+ (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
+ event blanking and windowing circuitry of a HRTIM timer:
+ (+++)Blanking: to mask external events during a defined time period a defined time period
+ (+++)Windowing, to enable external events only during a defined time period
+ (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
+ unit for a HRTIM timer. Allows to generate a couple of
+ complementary signals from a single reference waveform,
+ with programmable delays between active state.
+ (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
+ the high-frequency carrier signal added on top of the timing
+ unit output. Chopper mode can be enabled or disabled for each
+ timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
+ (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
+ controller. Allows having multiple HRTIM registers updated
+ with a single DMA request. The burst DMA operation is started
+ by calling HAL_HRTIM_BurstDMATransfer().
+ (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
+ of a HRTIM timer. This operation consists in setting the
+ compare value and possibly specifying the auto delayed mode
+ for compare units 2 and 4 (allows to have compare events
+ generated relatively to capture events). Note that when auto
+ delayed mode is needed, the capture unit associated to the
+ compare unit must be configured separately.
+ (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
+ of a HRTIM timer. This operation consists in specifying the
+ source(s) triggering the capture (timer register update event,
+ external event, timer output set/reset event, other HRTIM
+ timer related events).
+ (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
+ output mainly consists in:
+ (+++)Setting the output polarity (active high or active low),
+ (+++)Defining the set/reset crossbar for the output,
+ (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
+
+ (#) Set waveform timer output(s) level
+ (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
+ active or inactive level. For example, when deadtime insertion
+ is enabled it is necessary to force the output level by software
+ to have the outputs in a complementary state as soon as the RUN mode is entered.
+
+ (#) Enable or Disable waveform timer output(s)
+ (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
+
+ (#) Start or Stop waveform HRTIM timer(s).
+ (++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
+ (++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
+ (++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
+ (#) Burst mode controller enabling:
+ (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
+ burst mode controller.
+
+ (#) Some HRTIM operations can be triggered by software:
+ (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
+ trigs the burst operation.
+ (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
+ capture of the HRTIM timer counter.
+ (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
+ update of the pre-loadable registers of the HRTIM timer
+ (++)HAL_HRTIM_SoftwareReset():calling this function resets the
+ HRTIM timer counter.
+
+ (#) Some functions can be used any time to retrieve HRTIM timer related
+ information
+ (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
+ capture register of the designated capture unit.
+ (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
+ (ACTIVE/INACTIVE) of the designated timer output.
+ (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
+ (IDLE/RUN/FAULT) of the designated timer output.
+ (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
+ (ACTIVE/INACTIVE) of the designated output when the delayed
+ protection was triggered.
+ (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
+ (ACTIVE/INACTIVE) of the burst mode controller.
+ (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
+ is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
+ the push-pull status indicates on which output the signal is currently
+ active (e.g signal applied on output 1 and output 2 forced
+ inactive or vice versa).
+ (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
+ is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
+ the idle push-pull status indicates during which period the
+ delayed protection request occurred (e.g. protection occurred
+ when the output 1 was active and output 2 forced inactive or
+ vice versa).
+
+ (#) Some functions can be used any time to retrieve actual HRTIM status
+ (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+
+#if defined(STM32F334x8)
+
+/** @defgroup HRTIM HRTIM
+ * @brief HRTIM HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HRTIM_Private_Defines HRTIM Private Define
+ * @{
+ */
+#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
+ HRTIM_FLTR_FLT2EN |\
+ HRTIM_FLTR_FLT3EN |\
+ HRTIM_FLTR_FLT4EN | \
+ HRTIM_FLTR_FLT5EN)
+
+#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_A |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_B |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_C |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_D |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_E)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HRTIM_Private_Variables HRTIM Private Variables
+ * @{
+ */
+static uint32_t TimerIdxToTimerId[] =
+{
+ HRTIM_TIMERID_TIMER_A,
+ HRTIM_TIMERID_TIMER_B,
+ HRTIM_TIMERID_TIMER_C,
+ HRTIM_TIMERID_TIMER_D,
+ HRTIM_TIMERID_TIMER_E,
+ HRTIM_TIMERID_MASTER,
+};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HRTIM_Private_Functions HRTIM Private Functions
+ * @{
+ */
+static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+
+static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+
+static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimerCfgTypeDef * pTimerCfg);
+
+static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg);
+
+static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * pCompareCfg);
+
+static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event);
+
+static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef * pEventCfg);
+
+static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event);
+
+static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+
+static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx);
+
+static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx);
+
+static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
+
+static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
+
+static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx);
+
+static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
+ * @{
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+@verbatim
+ ===============================================================================
+ ##### Initialization and Time Base Configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize a HRTIM instance
+ (+) De-initialize a HRTIM instance
+ (+) Initialize the HRTIM MSP
+ (+) De-initialize the HRTIM MSP
+ (+) Start the high-resolution unit (start DLL calibration)
+ (+) Check that the high resolution unit is ready (DLL calibration done)
+ (+) Configure the time base unit of a HRTIM timer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes a HRTIM instance
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
+{
+ uint8_t timer_idx;
+ uint32_t hrtim_mcr;
+
+ /* Check the HRTIM handle allocation */
+ if(hhrtim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
+ assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
+
+ /* Set the HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Initialize the DMA handles */
+ hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
+ hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
+
+ /* HRTIM output synchronization configuration (if required) */
+ if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
+ assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
+
+ /* The synchronization output initialization procedure must be done prior
+ to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
+ */
+ if (hhrtim->Instance == HRTIM1)
+ {
+ /* Enable the HRTIM peripheral clock */
+ __HAL_RCC_HRTIM1_CLK_ENABLE();
+ }
+
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+ /* Set the event to be sent on the synchronization output */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
+ hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
+
+ /* Set the polarity of the synchronization output */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
+ hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_HRTIM_MspInit(hhrtim);
+
+ /* HRTIM input synchronization configuration (if required) */
+ if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
+
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+ /* Set the synchronization input source */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
+ hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ }
+
+ /* Initialize the HRTIM state*/
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Initialize the lock status of the HRTIM HAL API */
+ __HAL_UNLOCK(hhrtim);
+
+ /* Tnitialize timer related parameters */
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx <= HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
+ hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
+ hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
+ hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
+ hhrtim->TimerParam[timer_idx].DMASrcAddress = 0;
+ hhrtim->TimerParam[timer_idx].DMASize = 0;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initializes a HRTIM instance
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Check the HRTIM handle allocation */
+ if(hhrtim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
+
+ /* Set the HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_HRTIM_MspDeInit(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief MSP initialization for a HRTIM instance
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief MSP de-initialization for a for a HRTIM instance
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the DLL calibration
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param CalibrationRate: DLL calibration period
+ * This parameter can be one of the following values:
+ * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
+ * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
+ * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
+ * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
+ * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
+ * @retval HAL status
+ * @note This function locks the HRTIM instance. HRTIM instance is unlocked
+ * within the HAL_HRTIM_PollForDLLCalibration function, just before
+ * exiting the function.
+ */
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t CalibrationRate)
+{
+ uint32_t hrtim_dllcr;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure DLL Calibration */
+ hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
+
+ if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
+ {
+ /* One shot DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
+ hrtim_dllcr |= HRTIM_DLLCR_CAL;
+ }
+ else
+ {
+ /* Periodic DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
+ hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
+ }
+
+ /* Update HRTIM register */
+ hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the DLL calibration.
+ * DLL ready interrupt is enabled
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param CalibrationRate: DLL calibration period
+ * This parameter can be one of the following values:
+ * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
+ * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
+ * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
+ * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
+ * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
+ * @retval HAL status
+ * @note This function locks the HRTIM instance. HRTIM instance is unlocked
+ * within the IRQ processing function when processing the DLL ready
+ * interrupt.
+ * @note If this function is called for periodic calibration, the DLLRDY
+ * interrupt is generated every time the calibration completes which
+ * will significantly increases the overall interrupt rate.
+ */
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t CalibrationRate)
+{
+ uint32_t hrtim_dllcr;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable DLL Ready interrupt flag */
+ __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
+
+ /* Configure DLL Calibration */
+ hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
+
+ if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
+ {
+ /* One shot DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
+ hrtim_dllcr |= HRTIM_DLLCR_CAL;
+ }
+ else
+ {
+ /* Periodic DLL calibration */
+ hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
+ hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
+ }
+
+ /* Update HRTIM register */
+ hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polls the DLL calibration ready flag and returns when the flag is
+ * set (DLL calibration completed) or upon timeout expiration
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timeout: Timeout duration in millisecond
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timeout)
+{
+ uint32_t tickstart=0;
+
+ tickstart = HAL_GetTick();
+
+ /* Check End of conversion flag */
+ while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == RESET)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set HRTIM State */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the time base unit of a timer
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pTimeBaseCfg: pointer to the time base configuration structure
+ * @note This function must be called prior starting the timer
+ * @note The time-base unit initialization parameters specify:
+ * The timer counter operating mode (continuous, one shot),
+ * The timer clock prescaler,
+ * The timer period ,
+ * The timer repetition counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
+ assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Set the HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure master timer time base unit */
+ HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
+ }
+ else
+ {
+ /* Configure timing unit time base unit */
+ HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
+ }
+
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
+ * @brief Simple time base mode functions.
+@verbatim
+ ===============================================================================
+ ##### Simple time base mode functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start simple time base
+ (+) Stop simple time base
+ (+) Start simple time base and enable interrupt
+ (+) Stop simple time base and disable interrupt
+ (+) Start simple time base and enable DMA transfer
+ (+) Stop simple time base and disable DMA transfer
+ -@- When a HRTIM timer operates in simple time base mode, the timer
+ counter counts from 0 to the period value.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the counter of a timer operating in simple time base mode.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of a timer operating in simple time base mode.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of a timer operating in simple time base mode
+ * (Timer repetition interrupt is enabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the repetition interrupt */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+ }
+ else
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of a timer operating in simple time base mode
+ * (Timer repetition interrupt is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the repetition interrupt */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+ }
+ else
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of a timer operating in simple time base mode
+ * (Timer repetition DMA request is enabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param SrcAddr: DMA transfer source address
+ * @param DestAddr: DMA transfer destination address
+ * @param Length: The length of data items (data size) to be transferred
+ * from source to destination
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ {
+ if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Set the DMA transfer completed callback */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
+ }
+ else
+ {
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+ }
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ /* Enable the timer repetition DMA request */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
+ }
+ else
+ {
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of a timer operating in simple time base mode
+ * (Timer repetition DMA request is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index.
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Disable the DMA */
+ HAL_DMA_Abort(hhrtim->hdmaMaster);
+
+ /* Disable the timer repetition DMA request */
+ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
+ }
+ else
+ {
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Disable the timer repetition DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
+ * @brief Simple output compare functions
+@verbatim
+ ===============================================================================
+ ##### Simple output compare functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure simple output channel
+ (+) Start simple output compare
+ (+) Stop simple output compare
+ (+) Start simple output compare and enable interrupt
+ (+) Stop simple output compare and disable interrupt
+ (+) Start simple output compare and enable DMA transfer
+ (+) Stop simple output compare and disable DMA transfer
+ -@- When a HRTIM timer operates in simple output compare mode
+ the output level is set to a programmable value when a match
+ is found between the compare register and the counter.
+ Compare unit 1 is automatically associated to output 1
+ Compare unit 2 is automatically associated to output 2
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output in simple output compare mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pSimpleOCChannelCfg: pointer to the simple output compare output configuration structure
+ * @note When the timer operates in simple output compare mode:
+ * Output 1 is implicitly controlled by the compare unit 1
+ * Output 2 is implicitly controlled by the compare unit 2
+ * Output Set/Reset crossbar is set according to the selected output compare mode:
+ * Toggle: SETxyR = RSTxyR = CMPy
+ * Active: SETxyR = CMPy, RSTxyR = 0
+ * Inactive: SETxy =0, RSTxy = CMPy
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
+{
+ uint32_t CompareUnit = 0xFFFFFFFF;
+ HRTIM_CompareCfgTypeDef CompareCfg = {0};
+ HRTIM_OutputCfgTypeDef OutputCfg = {0};
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+ assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer compare unit */
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ }
+
+ CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(hhrtim,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
+ OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
+ OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ switch (pSimpleOCChannelCfg->Mode)
+ {
+ case HRTIM_BASICOCMODE_TOGGLE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = OutputCfg.SetSource;
+ }
+ break;
+ case HRTIM_BASICOCMODE_ACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+ }
+ break;
+ case HRTIM_BASICOCMODE_INACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
+ }
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+ }
+ break;
+ }
+
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ OCChannel,
+ &OutputCfg);
+
+ /* Set HRTIM state */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * (Interrupt is enabled (see note note below)).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @note Interrupt enabling depends on the chosen output compare mode
+ * Output toggle: compare match interrupt is enabled
+ * Output set active: output set interrupt is enabled
+ * Output set inactive: output reset interrupt is enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t interrupt;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Get the interrupt to enable (depends on the output compare mode) */
+ interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+ /* Enable the timer interrupt (depends on the output compare mode) */
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * (Interrupt is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t interrupt;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+ /* Get the interrupt to disable (depends on the output compare mode) */
+ interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Disable the timer interrupt */
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * (DMA request is enabled (see note below)).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param SrcAddr: DMA transfer source address
+ * @param DestAddr: DMA transfer destination address
+ * @param Length: The length of data items (data size) to be transferred
+ * from source to destination
+ * @note DMA request enabling depends on the chosen output compare mode
+ * Output toggle: compare match DMA request is enabled
+ * Output set active: output set DMA request is enabled
+ * Output set inactive: output reset DMA request is enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+ uint32_t dma_request;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ {
+ if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+ /* Get the DMA request to enable */
+ dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * (DMA request is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ DMA_HandleTypeDef * hdma;
+ uint32_t dma_request;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Get the DMA request to disable */
+ dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+ /* Disable the timer DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
+ * @brief Simple PWM output functions
+@verbatim
+ ===============================================================================
+ ##### Simple PWM output functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure simple PWM output channel
+ (+) Start simple PWM output
+ (+) Stop simple PWM output
+ (+) Start simple PWM output and enable interrupt
+ (+) Stop simple PWM output and disable interrupt
+ (+) Start simple PWM output and enable DMA transfer
+ (+) Stop simple PWM output and disable DMA transfer
+ -@- When a HRTIM timer operates in simple PWM output mode
+ the output level is set to a programmable value when a match is
+ found between the compare register and the counter and reset when
+ the timer period is reached. Duty cycle is determined by the
+ comparison value.
+ Compare unit 1 is automatically associated to output 1
+ Compare unit 2 is automatically associated to output 2
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output in simple PWM mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pSimplePWMChannelCfg: pointer to the simple PWM output configuration structure
+ * @note When the timer operates in simple PWM output mode:
+ * Output 1 is implicitly controlled by the compare unit 1
+ * Output 2 is implicitly controlled by the compare unit 2
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * @note When Simple PWM mode is used the registers preload mechanism is
+ * enabled (otherwise the behavior is not guaranteed).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
+{
+ uint32_t CompareUnit = 0xFFFFFFFF;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+ uint32_t hrtim_timcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim); hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer compare unit */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ }
+
+ CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(hhrtim,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
+ OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
+ OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ PWMChannel,
+ &OutputCfg);
+
+ /* Enable the registers preload mechanism */
+ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+ hrtim_timcr |= HRTIM_TIMCR_PREEN;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * (The compare interrupt is enabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+ /* Enable the timer interrupt (depends on the PWM output) */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * (The compare interrupt is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+ /* Disable the timer interrupt (depends on the PWM output) */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * (The compare DMA request is enabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param SrcAddr: DMA transfer source address
+ * @param DestAddr: DMA transfer destination address
+ * @param Length: The length of data items (data size) to be transferred
+ * from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ {
+ if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ /* Enable the timer DMA request */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
+ }
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * (The compare DMA request is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Disable the timer DMA request */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
+ }
+ break;
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
+ * @brief Simple input capture functions
+@verbatim
+ ===============================================================================
+ ##### Simple input capture functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure simple input capture channel
+ (+) Start simple input capture
+ (+) Stop simple input capture
+ (+) Start simple input capture and enable interrupt
+ (+) Stop simple input capture and disable interrupt
+ (+) Start simple input capture and enable DMA transfer
+ (+) Stop simple input capture and disable DMA transfer
+ -@- When a HRTIM timer operates in simple input capture mode
+ the Capture Register (HRTIM_CPT1/2xR) is used to latch the
+ value of the timer counter counter after a transition detected
+ on a given external event input.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures a simple capture
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel: Capture unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pSimpleCaptureChannelCfg: pointer to the simple capture configuration structure
+ * @note When the timer operates in simple capture mode the capture is trigerred
+ * by the designated external event and GPIO input is implicitly used as event source.
+ * The cature can be triggered by a rising edge, a falling edge or both
+ * edges on event channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
+{
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+ assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
+ pSimpleCaptureChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
+ pSimpleCaptureChannelCfg->EventFilter));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
+ EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_EventConfig(hhrtim,
+ pSimpleCaptureChannelCfg->Event,
+ &EventCfg);
+
+ /* Memorize capture trigger (will be configured when the capture is started */
+ HRTIM_CaptureUnitConfig(hhrtim,
+ TimerIdx,
+ CaptureChannel,
+ pSimpleCaptureChannelCfg->Event);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables a simple capture on the designed capture unit
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ * @note The external event triggering the capture is available for all timing
+ * units. It can be used directly and is active as soon as the timing
+ * unit counter is enabled.
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+ }
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables a simple capture on the designed capture unit
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables a simple capture on the designed capture unit
+ * (Capture interrupt is enabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+
+ /* Enable the capture unit 1 interrupt */
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+
+ /* Enable the capture unit 2 interrupt */
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+ }
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables a simple capture on the designed capture unit
+ * (Capture interrupt is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 1 interrupt */
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 2 interrupt */
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+ }
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables a simple capture on the designed capture unit
+ * (Capture DMA request is enabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param SrcAddr: DMA transfer source address
+ * @param DestAddr: DMA transfer destination address
+ * @param Length: The length of data items (data size) to be transferred
+ * from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ uint32_t SrcAddr,
+ uint32_t DestAddr,
+ uint32_t Length)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
+
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ /* Set the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ /* Set the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
+ }
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables a simple capture on the designed capture unit
+ * (Capture DMA request is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ /* Reset the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 1 DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ /* Reset the capture unit trigger */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+ /* Disable the capture unit 2 DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
+ }
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
+ * @brief Simple one pulse functions
+@verbatim
+ ===============================================================================
+ ##### Simple one pulse functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure one pulse channel
+ (+) Start one pulse generation
+ (+) Stop one pulse generation
+ (+) Start one pulse generation and enable interrupt
+ (+) Stop one pulse generation and disable interrupt
+ -@- When a HRTIM timer operates in simple one pulse mode
+ the timer counter is started in response to transition detected
+ on a given external event input to generate a pulse with a
+ programmable length after a programmable delay.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output simple one pulse mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pSimpleOnePulseChannelCfg: pointer to the simple one pulse output configuration structure
+ * @note When the timer operates in simple one pulse mode:
+ * the timer counter is implicitly started by the reset event,
+ * the reset of the timer counter is triggered by the designated external event
+ * GPIO input is implicitly used as event source,
+ * Output 1 is implicitly controlled by the compare unit 1,
+ * Output 2 is implicitly controlled by the compare unit 2.
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * @retval HAL status
+ * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
+ * outputs, the reset event related configuration data provided in the
+ * second call will override the reset event related configuration data
+ * provided in the first call.
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
+{
+ uint32_t CompareUnit = 0xFFFFFFFF;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
+ assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
+ pSimpleOnePulseChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
+ pSimpleOnePulseChannelCfg->EventFilter));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer compare unit */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ }
+
+ CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(hhrtim,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
+ OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
+ OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ OnePulseChannel,
+ &OutputCfg);
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
+ EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_EventConfig(hhrtim,
+ pSimpleOnePulseChannelCfg->Event,
+ &EventCfg);
+
+ /* Configure the timer reset register */
+ HRTIM_TIM_ResetConfig(hhrtim,
+ TimerIdx,
+ pSimpleOnePulseChannelCfg->Event);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the simple one pulse signal generation on the designed output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the simple one pulse signal generation on the designed output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the simple one pulse signal generation on the designed output
+ * (The compare interrupt is enabled (pulse start)).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the timer output */
+ hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
+
+ /* Enable the timer interrupt (depends on the OnePulse output) */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the simple one pulse signal generation on the designed output
+ * (The compare interrupt is disabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable the timer output */
+ hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
+
+ /* Disable the timer interrupt (depends on the OnePulse output) */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+ }
+ break;
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
+ * @brief HRTIM configuration functions
+@verbatim
+ ===============================================================================
+ ##### HRTIM configuration functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the HRTIM
+ resources shared by all the HRTIM timers operating in waveform mode:
+ (+) Configure the burst mode controller
+ (+) Configure an external event conditionning
+ (+) Configure the external events sampling clock
+ (+) Configure a fault conditionning
+ (+) Enable or disable fault inputs
+ (+) Configure the faults sampling clock
+ (+) Configure an ADC trigger
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the burst mode feature of the HRTIM
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param pBurstModeCfg: pointer to the burst mode configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the burst mode
+ * controller
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
+{
+ uint32_t hrtim_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
+ assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
+ assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
+ assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
+ assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+ /* Set the burst mode operating mode */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
+ hrtim_bmcr |= pBurstModeCfg->Mode;
+
+ /* Set the burst mode clock source */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
+ hrtim_bmcr |= pBurstModeCfg->ClockSource;
+
+ /* Set the burst mode prescaler */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
+ hrtim_bmcr |= pBurstModeCfg->Prescaler;
+
+ /* Enable/disable burst mode registers preload */
+ hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
+ hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
+
+ /* Set the burst mode trigger */
+ hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
+
+ /* Set the burst mode compare value */
+ hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
+
+ /* Set the burst mode period */
+ hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the conditioning of an external event
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Event: external event to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pEventCfg: pointer to the event conditioning configuration structure
+ * @note This function must be called before starting the timer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
+ assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
+ assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the event channel */
+ HRTIM_EventConfig(hhrtim, Event, pEventCfg);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the external event conditioning block prescaler
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Prescaler: Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
+ * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
+ * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
+ * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
+ * @note This function must be called before starting the timer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Prescaler)
+{
+ uint32_t hrtim_eecr3;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the external event prescaler */
+ hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
+ hrtim_eecr3 |= Prescaler;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the conditioning of fault input
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Fault: fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param pFaultCfg: pointer to the fault conditioning configuration structure
+ * @note This function must be called before starting the timer and before
+ * enabling faults inputs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Fault,
+ HRTIM_FaultCfgTypeDef* pFaultCfg)
+{
+ uint32_t hrtim_fltinr1;
+ uint32_t hrtim_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Fault));
+ assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
+ assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
+ assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
+ assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure fault channel */
+ hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
+ hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
+
+ switch (Fault)
+ {
+ case HRTIM_FAULT_1:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
+ hrtim_fltinr1 |= pFaultCfg->Polarity;
+ hrtim_fltinr1 |= pFaultCfg->Source;
+ hrtim_fltinr1 |= pFaultCfg->Filter;
+ hrtim_fltinr1 |= pFaultCfg->Lock;
+ }
+ break;
+ case HRTIM_FAULT_2:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 8);
+ hrtim_fltinr1 |= (pFaultCfg->Source << 8);
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 8);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 8);
+ }
+ break;
+ case HRTIM_FAULT_3:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 16);
+ hrtim_fltinr1 |= (pFaultCfg->Source << 16);
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 16);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 16);
+ }
+ break;
+ case HRTIM_FAULT_4:
+ {
+ hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 24);
+ hrtim_fltinr1 |= (pFaultCfg->Source << 24);
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 24);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 24);
+ }
+ break;
+ case HRTIM_FAULT_5:
+ {
+ hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
+ hrtim_fltinr2 |= pFaultCfg->Polarity;
+ hrtim_fltinr2 |= pFaultCfg->Source;
+ hrtim_fltinr2 |= pFaultCfg->Filter;
+ hrtim_fltinr2 |= pFaultCfg->Lock;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
+ hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the fault conditioning block prescaler
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Prescaler: Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
+ * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
+ * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
+ * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
+ * @retval HAL status
+ * @note This function must be called before starting the timer and before
+ * enabling faults inputs
+ */
+HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Prescaler)
+{
+ uint32_t hrtim_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the external event prescaler */
+ hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
+ hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
+ hrtim_fltinr2 |= Prescaler;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the HRTIMx Fault mode.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Faults: fault input(s) to enable or disable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param Enable: Fault(s) enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
+ * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
+ * @retval None
+ */
+void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Faults,
+ uint32_t Enable)
+{
+ uint32_t hrtim_fltinr1;
+ uint32_t hrtim_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Faults));
+ assert_param(IS_HRTIM_FAULTMODECTL(Enable));
+
+ /* Configure fault channel */
+ hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
+ hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
+
+ if ((Faults & HRTIM_FAULT_1) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
+ hrtim_fltinr1 |= Enable;
+ }
+ if ((Faults & HRTIM_FAULT_2) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
+ hrtim_fltinr1 |= (Enable << 8);
+ }
+ if ((Faults & HRTIM_FAULT_3) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
+ hrtim_fltinr1 |= (Enable << 16);
+ }
+ if ((Faults & HRTIM_FAULT_4) != RESET)
+ {
+ hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
+ hrtim_fltinr1 |= (Enable << 24);
+ }
+ if ((Faults & HRTIM_FAULT_5) != RESET)
+ {
+ hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
+ hrtim_fltinr2 |= Enable;
+ }
+
+ /* Update the HRTIMx registers */
+ hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
+ hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
+}
+
+/**
+ * @brief Configures both the ADC trigger register update source and the ADC
+ * trigger source.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param ADCTrigger: ADC trigger to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
+ * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
+ * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
+ * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
+ * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
+{
+ uint32_t hrtim_cr1;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
+ assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the ADC trigger update source */
+ hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
+
+ switch (ADCTrigger)
+ {
+ case HRTIM_ADCTRIGGER_1:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
+ hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
+
+ /* Set the ADC trigger 1 source */
+ hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_2:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3) & HRTIM_CR1_ADC2USRC);
+
+ /* Set the ADC trigger 2 source */
+ hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_3:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6) & HRTIM_CR1_ADC3USRC);
+
+ /* Set the ADC trigger 3 source */
+ hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_4:
+ {
+ hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9) & HRTIM_CR1_ADC4USRC);
+
+ /* Set the ADC trigger 4 source */
+ hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ }
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
+ * @brief HRTIM timer configuration and control functions
+@verbatim
+ ===============================================================================
+ ##### HRTIM timer configuration and control functions #####
+ ===============================================================================
+ [..] This section provides functions used to configure and control a
+ HRTIM timer operating in waveform mode:
+ (+) Configure HRTIM timer general behavior
+ (+) Configure HRTIM timer event filtering
+ (+) Configure HRTIM timer deadtime insertion
+ (+) Configure HRTIM timer chopper mode
+ (+) Configure HRTIM timer burst DMA
+ (+) Configure HRTIM timer compare unit
+ (+) Configure HRTIM timer capture unit
+ (+) Configure HRTIM timer output
+ (+) Set HRTIM timer output level
+ (+) Enable HRTIM timer output
+ (+) Disable HRTIM timer output
+ (+) Start HRTIM timer
+ (+) Stop HRTIM timer
+ (+) Start HRTIM timer and enable interrupt
+ (+) Stop HRTIM timer and disable interrupt
+ (+) Start HRTIM timer and enable DMA transfer
+ (+) Stop HRTIM timer and disable DMA transfer
+ (+) Enable or disable the burst mode controller
+ (+) Start the burst mode controller (by software)
+ (+) Trigger a Capture (by software)
+ (+) Update the HRTIM timer preloadable registers (by software)
+ (+) Reset the HRTIM timer counter (by software)
+ (+) Start a burst DMA transfer
+ (+) Enable timer register update
+ (+) Disable timer register update
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the general behavior of a timer operating in waveform mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pTimerCfg: pointer to the timer configuration structure
+ * @note When the timer operates in waveform mode, all the features supported by
+ * the HRTIM are available without any limitation.
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Relevant for all HRTIM timers, including the master */
+ assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
+ assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
+ assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
+ assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro));
+ assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
+ assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
+ assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
+ assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
+ assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
+
+ /* Configure master timer */
+ HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
+ }
+ else
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
+ assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
+ assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
+ assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
+ assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
+ assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
+ assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
+ pTimerCfg->DeadTimeInsertion));
+ assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
+ pTimerCfg->DelayedProtectionMode));
+ assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
+ assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
+ assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
+ }
+
+ /* Update timer parameters */
+ hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
+ hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
+ hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
+ hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
+ hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
+
+ /* Force a software update */
+ HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Event: external event for which timer event filtering must be configured
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
+ * @note This function must be called before starting the timer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
+{
+ uint32_t hrtim_eefr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_EVENT(Event));
+ assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
+ assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure timer event filtering capabilities */
+ switch (Event)
+ {
+ case HRTIM_EVENT_NONE:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0;
+ }
+ break;
+ case HRTIM_EVENT_1:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
+ hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
+ hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
+ hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
+ hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
+ }
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the deadtime insertion feature for a timer
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pDeadTimeCfg: pointer to the deadtime insertion configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
+{
+ uint32_t hrtim_dtr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
+
+ /* Clear timer deadtime configuration */
+ hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
+ HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
+ HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
+
+ /* Set timer deadtime configuration */
+ hrtim_dtr |= pDeadTimeCfg->Prescaler;
+ hrtim_dtr |= pDeadTimeCfg->RisingValue;
+ hrtim_dtr |= pDeadTimeCfg->RisingSign;
+ hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
+ hrtim_dtr |= pDeadTimeCfg->RisingLock;
+ hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16);
+ hrtim_dtr |= pDeadTimeCfg->FallingSign;
+ hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
+ hrtim_dtr |= pDeadTimeCfg->FallingLock;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the chopper mode feature for a timer
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param pChopperModeCfg: pointer to the chopper mode configuration structure
+ * @retval HAL status
+ * @note This function must be called before configuring the timer output(s)
+ */
+HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
+{
+ uint32_t hrtim_chpr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
+ assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
+ assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
+
+ /* Clear timer chopper mode configuration */
+ hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
+
+ /* Set timer choppe mode configuration */
+ hrtim_chpr |= pChopperModeCfg->CarrierFreq;
+ hrtim_chpr |= (pChopperModeCfg->DutyCycle);
+ hrtim_chpr |= (pChopperModeCfg->StartPulse);
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the burst DMA controller for a timer
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param RegistersToUpdate: registers to be written by DMA
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
+ * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
+ * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
+ * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
+ * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
+ * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
+ * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
+ * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
+ * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
+ * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
+ * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
+ * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
+ * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
+ * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
+ * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
+ * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
+ * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
+ * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
+ * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
+ * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
+ * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Set the burst DMA timer update register */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
+ }
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the compare unit of a timer operating in waveform mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CompareUnit: Compare unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param pCompareCfg: pointer to the compare unit configuration structure
+ * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
+ * application has to configure separately the capture unit. Capture unit
+ * to configure in that case depends on the compare unit auto delayed mode
+ * is applied to (see below):
+ * Auto delayed on output compare 2: capture unit 1 must be configured
+ * Auto delayed on output compare 4: capture unit 2 must be configured
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the compare unit */
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
+ }
+ break;
+ }
+ }
+ else
+ {
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ /* DELCMP2 bitfield must be reset when reprogrammed from one value */
+ /* to the other to reinitialize properly the auto-delayed mechanism */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+ /* Set the compare value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ /* DELCMP4 bitfield must be reset when reprogrammed from one value */
+ /* to the other to reinitialize properly the auto-delayed mechanism */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2);
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ }
+ }
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the capture unit of a timer operating in waveform mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureUnit: Capture unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pCaptureCfg: pointer to the compare unit configuration structure
+ * @retval HAL status
+ * @note This function must be called before starting the timer
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the output of a timer operating in waveform mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pOutputCfg: pointer to the timer output configuration structure
+ * @retval HAL status
+ * @note This function must be called before configuring the timer and after
+ * configuring the deadtime insertion feature (if required).
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
+ assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
+ assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
+ assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
+ assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Configure the timer output */
+ HRTIM_OutputConfig(hhrtim,
+ TimerIdx,
+ Output,
+ pOutputCfg);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Forces the timer output to its active or inactive state
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param OutputLevel: indicates whether the output is forced to its active or inactive level
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
+ * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
+ * @retval HAL status
+ * @note The 'software set/reset trigger' bit in the output set/reset registers
+ * is automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force timer output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
+ }
+ }
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output enabling.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param OutputsToStart: Timer output(s) to enable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t OutputsToStart)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the HRTIM outputs */
+ hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output disabling.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param OutputsToStop: Timer output(s) to disable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t OutputsToStop)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable the HRTIM outputs */
+ hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_TIMER_A
+ * @arg HRTIM_TIMERID_TIMER_B
+ * @arg HRTIM_TIMERID_TIMER_C
+ * @arg HRTIM_TIMERID_TIMER_D
+ * @arg HRTIM_TIMERID_TIMER_E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR |= (Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval HAL status
+ * @note The counter of a timer is stopped only if all timer outputs are disabled
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
+ * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
+ * to the timers to start are enabled within this function.
+ * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
+ * function.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ uint8_t timer_idx;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable HRTIM interrupts (if required) */
+ __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
+
+ /* Enable master timer related interrupts (if required) */
+ if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
+ {
+ __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
+ }
+
+ /* Enable timing unit related interrupts (if required) */
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
+ {
+ __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].InterruptRequests);
+ }
+ }
+
+ /* Enable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR |= (Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval HAL status
+ * @note The counter of a timer is stopped only if all timer outputs are disabled
+ * @note All enabled timer related interrupts are disabled.
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* ++ WA */
+ __IO uint32_t delai = (uint32_t)(0x17F);
+ /* -- WA */
+
+ uint8_t timer_idx;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Disable HRTIM interrupts (if required) */
+ __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
+
+ /* Disable master timer related interrupts (if required) */
+ if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
+ {
+ /* Interrupts enable flag must be cleared one by one */
+ __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
+ }
+
+ /* Disable timing unit related interrupts (if required) */
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
+ {
+ __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
+ }
+ }
+
+ /* ++ WA */
+ do { delai--; } while (delai != 0);
+ /* -- WA */
+
+ /* Disable timer(s) counter */
+ hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval HAL status
+ * @note This function enables the dma request(s) mentionned in the timer
+ * configuration data structure for every timers to start.
+ * @note The source memory address, the destination memory address and the
+ * size of each DMA transfer are specified at timer configuration time
+ * (see HAL_HRTIM_WaveformTimerConfig)
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ uint8_t timer_idx;
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
+ (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
+ {
+ /* Set the DMA error callback */
+ hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hhrtim->hdmaMaster,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
+ }
+
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
+ (hhrtim->TimerParam[timer_idx].DMARequests != 0))
+ {
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma,
+ hhrtim->TimerParam[timer_idx].DMASrcAddress,
+ hhrtim->TimerParam[timer_idx].DMADstAddress,
+ hhrtim->TimerParam[timer_idx].DMASize);
+
+ /* Enable the timer DMA request */
+ __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].DMARequests);
+ }
+ }
+
+ /* Enable the timer counter */
+ __HAL_HRTIM_ENABLE(hhrtim, Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval HAL status
+ * @note The counter of a timer is stopped only if all timer outputs are disabled
+ * @note All enabled timer related DMA requests are disabled.
+ */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ uint8_t timer_idx;
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERID(Timers));
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
+ (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
+ {
+ /* Disable the DMA */
+ HAL_DMA_Abort(hhrtim->hdmaMaster);
+
+ /* Disable the DMA request(s) */
+ __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
+ hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
+ }
+
+ for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+ timer_idx < HRTIM_TIMERINDEX_MASTER ;
+ timer_idx++)
+ {
+ if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
+ (hhrtim->TimerParam[timer_idx].DMARequests != 0))
+ {
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
+
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
+
+ /* Disable the DMA request(s) */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].DMARequests);
+ }
+ }
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables or disables the HRTIM burst mode controller.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Enable: Burst mode controller enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
+ * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
+ * @retval HAL status
+ * @note This function must be called after starting the timer(s)
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Enable)
+{
+ uint32_t hrtim_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODECTL(Enable));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable/Disable the burst mode controller */
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+ hrtim_bmcr &= ~(HRTIM_BMCR_BME);
+ hrtim_bmcr |= Enable;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers the burst mode operation.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
+{
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Software trigger of the burst mode controller */
+ hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers a software capture on the designed capture unit
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureUnit: Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval HAL status
+ * @note The 'software capture' bit in the capure configuration register is
+ * automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force a software capture on concerned capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
+ }
+ break;
+ }
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers the update of the registers of one or several timers
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: timers concerned with the software register update
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval HAL status
+ * @note The 'software update' bits in the HRTIM conrol register 2 register are
+ * automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force timer(s) registers update */
+ hhrtim->Instance->sCommonRegs.CR2 |= Timers;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Triggers the reset of one or several timers
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: timers concerned with the software counter reset
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERRESET_MASTER
+ * @arg HRTIM_TIMERRESET_TIMER_A
+ * @arg HRTIM_TIMERRESET_TIMER_B
+ * @arg HRTIM_TIMERRESET_TIMER_C
+ * @arg HRTIM_TIMERRESET_TIMER_D
+ * @arg HRTIM_TIMERRESET_TIMER_E
+ * @retval HAL status
+ * @note The 'software reset' bits in the HRTIM conrol register 2 are
+ * automatically reset by hardware
+ */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Timers)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERRESET(Timers));
+
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Force timer(s) registers reset */
+ hhrtim->Instance->sCommonRegs.CR2 = Timers;
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts a burst DMA operation to update HRTIM control registers content
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param BurstBufferAddress: address of the buffer the HRTIM control registers
+ * content will be updated from.
+ * @param BurstBufferLength: size (in WORDS) of the burst buffer.
+ * @retval HAL status
+ * @note The TimerIdx parameter determines the dma channel to be used by the
+ * DMA burst controller (see below)
+ * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
+ * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
+ */
+HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t TimerIdx,
+ uint32_t BurstBufferAddress,
+ uint32_t BurstBufferLength)
+{
+ DMA_HandleTypeDef * hdma;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ {
+ if((BurstBufferAddress == 0 ) || (BurstBufferLength == 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+ }
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ /* Get the timer DMA handler */
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ /* Set the DMA transfer completed callback */
+ hdma->XferCpltCallback = HRTIM_BurstDMACplt;
+
+ /* Set the DMA error callback */
+ hdma->XferErrorCallback = HRTIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hdma,
+ BurstBufferAddress,
+ (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
+ BurstBufferLength);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the transfer from preload to active registers for one
+ * or several timing units (including master timer).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer(s) concerned by the register preload enabling command
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable timer(s) registers update */
+ hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+ }
+
+/**
+ * @brief Disables the transfer from preload to active registers for one
+ * or several timing units (including master timer).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Timers: Timer(s) concerned by the register preload disabling command
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
+ uint32_t Timers)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+ /* Process Locked */
+ __HAL_LOCK(hhrtim);
+
+ hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+ /* Enable timer(s) registers update */
+ hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_OK;
+ }
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
+ * @brief Peripheral State functions
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..] This section provides functions used to get HRTIM or HRTIM timer
+ specific information:
+ (+) Get HRTIM HAL state
+ (+) Get captured value
+ (+) Get HRTIM timer output level
+ (+) Get HRTIM timer output state
+ (+) Get delayed protection status
+ (+) Get burst status
+ (+) Get current push-pull status
+ (+) Get idle push-pull status
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the HRTIM HAL state
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval HAL state
+ */
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
+{
+ /* Return ADC state */
+ return hhrtim->State;
+}
+
+/**
+ * @brief Returns actual value of the capture register of the designated capture unit
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param CaptureUnit: Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval Captured value
+ */
+uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ uint32_t captured_value = 0;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ /* Read captured value */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
+ }
+ break;
+ }
+
+ return captured_value;
+}
+
+/**
+ * @brief Returns actual level (active or inactive) of the designated output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output level
+ * @note Returned output level is taken before the output stage (chopper,
+ * polarity).
+ */
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ }
+
+ return output_level;
+}
+
+/**
+ * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output state
+ */
+uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_bit = 0;
+ uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Set output state according to output control status and output disable status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ {
+ output_bit = HRTIM_OENR_TA1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ {
+ output_bit = HRTIM_OENR_TA2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB1:
+ {
+ output_bit = HRTIM_OENR_TB1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB2:
+ {
+ output_bit = HRTIM_OENR_TB2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC1:
+ {
+ output_bit = HRTIM_OENR_TC1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC2:
+ {
+ output_bit = HRTIM_OENR_TC2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD1:
+ {
+ output_bit = HRTIM_OENR_TD1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD2:
+ {
+ output_bit = HRTIM_OENR_TD2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE1:
+ {
+ output_bit = HRTIM_OENR_TE1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE2:
+ {
+ output_bit = HRTIM_OENR_TE2OEN;
+ }
+ break;
+ }
+
+ if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
+ {
+ /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
+ output_state = HRTIM_OUTPUTSTATE_RUN;
+ }
+ else
+ {
+ if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
+ {
+ /* Output is disabled: output in FAULT state */
+ output_state = HRTIM_OUTPUTSTATE_FAULT;
+ }
+ else
+ {
+ /* Output is disabled: output in IDLE state */
+ output_state = HRTIM_OUTPUTSTATE_IDLE;
+ }
+ }
+
+ return(output_state);
+}
+
+/**
+ * @brief Returns the level (active or inactive) of the designated output
+ * when the delayed protection was triggered.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
+ * @retval Delayed protection status
+ */
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the delayed protection status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
+ {
+ /* Output 1 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 1 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
+ {
+ /* Output 2 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 2 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ }
+
+ return delayed_protection_status;
+}
+
+/**
+ * @brief Returns the actual status (active or inactive) of the burst mode controller
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval Burst mode controller status
+ */
+uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
+{
+ uint32_t burst_mode_status;
+
+ /* Read burst mode status */
+ burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
+
+ return burst_mode_status;
+}
+
+/**
+ * @brief Indicates on which output the signal is currently active (when the
+ * push pull mode is enabled).
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval Burst mode controller status
+ */
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ uint32_t current_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
+
+ return current_pushpull_status;
+}
+
+
+/**
+ * @brief Indicates on which output the signal was applied, in push-pull mode,
+ balanced fault mode or delayed idle mode, when the protection was triggered.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval Idle Push Pull Status
+ */
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ uint32_t idle_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
+
+ return idle_pushpull_status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
+ * @brief Functions called when HRTIM generates an interrupt
+ * 7 interrupts can be generated by the master timer:
+ * - Master timer registers update
+ * - Synchronization event received
+ * - Master timer repetition event
+ * - Master Compare 1 to 4 event
+ * 14 interrupts can be generated by each timing unit:
+ * - Delayed protection triggered
+ * - Counter reset or roll-over event
+ * - Output 1 and output 2 reset (transition active to inactive)
+ * - Output 1 and output 2 set (transition inactive to active)
+ * - Capture 1 and 2 events
+ * - Timing unit registers update
+ * - Repetition event
+ * - Compare 1 to 4 event
+ * 8 global interrupts are generated for the whole HRTIM:
+ * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
+ * - DLL calibration done
+ * - Burst mode period completed
+@verbatim
+ ===============================================================================
+ ##### HRTIM interrupts handling #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the HRTIM
+ interrupts:
+ (+) HRTIM interrupt handler
+ (+) Callback function called when Fault1 interrupt occurs
+ (+) Callback function called when Fault2 interrupt occurs
+ (+) Callback function called when Fault3 interrupt occurs
+ (+) Callback function called when Fault4 interrupt occurs
+ (+) Callback function called when Fault5 interrupt occurs
+ (+) Callback function called when system Fault interrupt occurs
+ (+) Callback function called when DLL ready interrupt occurs
+ (+) Callback function called when burst mode period interrupt occurs
+ (+) Callback function called when synchronization input interrupt occurs
+ (+) Callback function called when a timer register update interrupt occurs
+ (+) Callback function called when a timer repetition interrupt occurs
+ (+) Callback function called when a compare 1 match interrupt occurs
+ (+) Callback function called when a compare 2 match interrupt occurs
+ (+) Callback function called when a compare 3 match interrupt occurs
+ (+) Callback function called when a compare 4 match interrupt occurs
+ (+) Callback function called when a capture 1 interrupt occurs
+ (+) Callback function called when a capture 2 interrupt occurs
+ (+) Callback function called when a delayed protection interrupt occurs
+ (+) Callback function called when a timer counter reset interrupt occurs
+ (+) Callback function called when a timer output 1 set interrupt occurs
+ (+) Callback function called when a timer output 1 reset interrupt occurs
+ (+) Callback function called when a timer output 2 set interrupt occurs
+ (+) Callback function called when a timer output 2 reset interrupt occurs
+ (+) Callback function called when a timer output 2 reset interrupt occurs
+ (+) Callback function called upon completion of a burst DMA transfer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function handles HRTIM interrupt request.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be any value of @ref HRTIM_Timer_Index
+ * @retval None
+ */
+void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* HRTIM interrupts handling */
+ if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
+ {
+ HRTIM_HRTIM_ISR(hhrtim);
+ }
+ else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Master related interrupts handling */
+ HRTIM_Master_ISR(hhrtim);
+ }
+ else
+ {
+ /* Timing unit related interrupts handling */
+ HRTIM_Timer_ISR(hhrtim, TimerIdx);
+ }
+
+}
+
+/**
+ * @brief Callback function invoked when a fault 1 interrupt occured
+ * @param hhrtim: pointer to HAL HRTIM handle * @retval None
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault1Callback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 2 interrupt occured
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault2Callback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 3 interrupt occured
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault3Callback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 4 interrupt occured
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault4Callback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a fault 5 interrupt occured
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Fault5Callback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a system fault interrupt occured
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the DLL calibration is completed
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_DLLCalbrationCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the end of the burst mode period is reached
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_BurstModeCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a synchronization input event is received
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when timer registers are updated
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when timer repetition period has elapsed
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 1 register
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 2 register
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ */
+__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 3 register
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer counter matches the value
+ * programmed in the compare 4 register.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x capture 1 event occurs
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x capture 2 event occurs
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the delayed idle or balanced idle mode is
+ * entered.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x counter reset/roll-over
+ * event occurs.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 1 is set
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 1 is reset
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 2 is set
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when the timer x output 2 is reset
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a DMA burst transfer is completed
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_MASTER for master timer
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+ */
+__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @brief Callback function invoked when a DMA error occurs
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+__weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HRTIM_ErrorCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the master timer time base
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param pTimeBaseCfg: pointer to the time base configuration structure
+ * @retval None
+ */
+static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+{
+ uint32_t hrtim_mcr;
+
+ /* Configure master timer */
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+ /* Set the prescaler ratio */
+ hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
+ hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
+
+ /* Set the operating mode */
+ hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
+ hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
+ hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
+}
+
+/**
+ * @brief Configures timing unit (timer A to timer E) time base
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param pTimeBaseCfg: pointer to the time base configuration structure
+ * @retval None
+ */
+static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx ,
+ HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+{
+ uint32_t hrtim_timcr;
+
+ /* Configure master timing unit */
+ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+
+ /* Set the prescaler ratio */
+ hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
+ hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
+
+ /* Set the operating mode */
+ hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
+ hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
+}
+
+/**
+ * @brief Configures the master timer in waveform mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param pTimerCfg: pointer to the timer configuration data structure
+ * @retval None
+ */
+static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ uint32_t hrtim_mcr;
+ uint32_t hrtim_bmcr;
+
+ /* Configure master timer */
+ hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+ /* Enable/Disable the half mode */
+ hrtim_mcr &= ~(HRTIM_MCR_HALF);
+ hrtim_mcr |= pTimerCfg->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
+ hrtim_mcr |= pTimerCfg->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
+ hrtim_mcr |= pTimerCfg->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
+ hrtim_mcr |= pTimerCfg->DACSynchro;
+
+ /* Enable/Disable preload meachanism for timer registers */
+ hrtim_mcr &= ~(HRTIM_MCR_PREEN);
+ hrtim_mcr |= pTimerCfg->PreloadEnable;
+
+ /* Master timer registers update handling */
+ hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
+ hrtim_mcr |= (pTimerCfg->UpdateGating << 2);
+
+ /* Enable/Disable registers update on repetition */
+ hrtim_mcr &= ~(HRTIM_MCR_MREPU);
+ hrtim_mcr |= pTimerCfg->RepetitionUpdate;
+
+ /* Set the timer burst mode */
+ hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
+ hrtim_bmcr |= pTimerCfg->BurstMode;
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+}
+
+/**
+ * @brief Configures timing unit (timer A to timer E) in waveform mode
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param pTimerCfg: pointer to the timer configuration data structure
+ * @retval None
+ */
+static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ uint32_t hrtim_timcr;
+ uint32_t hrtim_timfltr;
+ uint32_t hrtim_timoutr;
+ uint32_t hrtim_timrstr;
+ uint32_t hrtim_bmcr;
+
+ /* UPDGAT bitfield must be reset before programming a new value */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
+
+ /* Configure timing unit (Timer A to Timer E) */
+ hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+ hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
+ hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
+ hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
+ hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+ /* Enable/Disable the half mode */
+ hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
+ hrtim_timcr |= pTimerCfg->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
+ hrtim_timcr |= pTimerCfg->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
+ hrtim_timcr |= pTimerCfg->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
+ hrtim_timcr |= pTimerCfg->DACSynchro;
+
+ /* Enable/Disable preload meachanism for timer registers */
+ hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
+ hrtim_timcr |= pTimerCfg->PreloadEnable;
+
+ /* Timing unit registers update handling */
+ hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
+ hrtim_timcr |= pTimerCfg->UpdateGating;
+
+ /* Enable/Disable registers update on repetition */
+ hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
+ if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
+ {
+ hrtim_timcr |= HRTIM_TIMCR_TREPU;
+ }
+
+ /* Set the push-pull mode */
+ hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
+ hrtim_timcr |= pTimerCfg->PushPull;
+
+ /* Enable/Disable registers update on timer counter reset */
+ hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
+ hrtim_timcr |= pTimerCfg->ResetUpdate;
+
+ /* Set the timer update trigger */
+ hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
+ hrtim_timcr |= pTimerCfg->UpdateTrigger;
+
+
+ /* Enable/Disable the fault channel at timer level */
+ hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
+ hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
+
+ /* Lock/Unlock fault sources at timer level */
+ hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
+ hrtim_timfltr |= pTimerCfg->FaultLock;
+
+ /* The deadtime cannot be used simultaneously with the push-pull mode */
+ if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
+ {
+ /* Enable/Disable dead time insertion at timer level */
+ hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
+ hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
+ }
+
+ /* Enable/Disable delayed protection at timer level
+ Delayed Idle is available whatever the timer operating mode (regular, push-pull)
+ Balanced Idle is only available in push-pull mode
+ */
+ if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
+ && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
+ || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
+ {
+ hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
+ hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
+ }
+
+ /* Set the timer counter reset trigger */
+ hrtim_timrstr = pTimerCfg->ResetTrigger;
+
+ /* Set the timer burst mode */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 1);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 2);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 3);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 4);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 5);
+ }
+ break;
+ }
+
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
+ hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+}
+
+/**
+ * @brief Configures a compare unit
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param CompareUnit: Compare unit identifier
+ * @param pCompareCfg: pointer to the compare unit configuration data structure
+ * @retval None
+ */
+static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * pCompareCfg)
+{
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure the compare unit of the master timer */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
+ }
+ break;
+ }
+ }
+ else
+ {
+ /* Configure the compare unit of the timing unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+ }
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Configures a capture unit
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param CaptureUnit: Capture unit identifier
+ * @param Event: Event reference
+ * @retval None
+ */
+static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event)
+{
+ uint32_t CaptureTrigger = 0xFFFFFFFF;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
+ }
+ break;
+ }
+
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
+ }
+ break;
+ }
+}
+
+/**
+ * @brief Configures the output of a timing unit
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param Output: timing unit output identifier
+ * @param pOutputCfg: pointer to the output configuration data structure
+ * @retval None
+ */
+static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ uint32_t hrtim_outr;
+ uint32_t hrtim_dtr;
+
+ uint32_t shift = 0xFFFFFFFF;
+
+ hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
+ hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
+
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Set the output set/reset crossbar */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
+
+ shift = 0;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Set the output set/reset crossbar */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
+
+ shift = 16;
+ }
+ break;
+ }
+
+ /* Clear output config */
+ hrtim_outr &= ~((HRTIM_OUTR_POL1 |
+ HRTIM_OUTR_IDLM1 |
+ HRTIM_OUTR_IDLES1|
+ HRTIM_OUTR_FAULT1|
+ HRTIM_OUTR_CHP1 |
+ HRTIM_OUTR_DIDL1) << shift);
+
+ /* Set the polarity */
+ hrtim_outr |= (pOutputCfg->Polarity << shift);
+
+ /* Set the IDLE mode */
+ hrtim_outr |= (pOutputCfg->IdleMode << shift);
+
+ /* Set the IDLE state */
+ hrtim_outr |= (pOutputCfg->IdleLevel << shift);
+
+ /* Set the FAULT state */
+ hrtim_outr |= (pOutputCfg->FaultLevel << shift);
+
+ /* Set the chopper mode */
+ hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
+
+ /* Set the burst mode entry mode : deadtime insertion when entering the idle
+ state during a burst mode operation is allowed only under the following
+ conditions:
+ - the outputs is active during the burst mode (IDLES=1)
+ - positive deadtimes (SDTR/SDTF set to 0)
+ */
+ if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
+ ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
+ ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
+ {
+ hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
+ }
+
+ /* Update HRTIM register */
+ hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
+}
+
+/**
+ * @brief Configures an external event channel
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param Event: Event channel identifier
+ * @param pEventCfg: pointer to the event channel configuration data structure
+ * @retval None
+ */
+static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef *pEventCfg)
+{
+ uint32_t hrtim_eecr1;
+ uint32_t hrtim_eecr2;
+ uint32_t hrtim_eecr3;
+
+ /* Configure external event channel */
+ hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
+ hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
+ hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
+ hrtim_eecr1 |= pEventCfg->Source;
+ hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
+ hrtim_eecr1 |= pEventCfg->Sensitivity;
+ /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE1FAST bit) */
+ hrtim_eecr1 |= pEventCfg->FastMode;
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 6);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR1_EE2POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
+ /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE2FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 6);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 12);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR1_EE3POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
+ /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE3FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 12);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 18);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR1_EE4POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
+ /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE4FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 18);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 24);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR1_EE5POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
+ /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE5FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 24);
+ hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
+ hrtim_eecr2 |= pEventCfg->Source;
+ hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
+ hrtim_eecr2 |= pEventCfg->Sensitivity;
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
+ hrtim_eecr3 |= pEventCfg->Filter;
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 6);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR2_EE7POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 6);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 12);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR2_EE8POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 12);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 18);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR2_EE9POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 18);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 24);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR2_EE10POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 24);
+ /* Update the HRTIM registers */
+ hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+ hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the timer counter reset
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param Event: Event channel identifier
+ * @retval None
+ */
+static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Event)
+{
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
+ }
+ break;
+ }
+}
+
+/**
+ * @brief Returns the interrupt to enable or disable according to the
+ * OC mode.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Interrupt to enable or disable
+ */
+static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t hrtim_set;
+ uint32_t hrtim_reset;
+ uint32_t interrupt = 0;
+
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Retreives actual OC mode and set interrupt accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ interrupt = HRTIM_TIM_IT_CMP1;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ (hrtim_reset == 0))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ interrupt = HRTIM_TIM_IT_SET1;
+ }
+ else if ((hrtim_set == 0) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ interrupt = HRTIM_TIM_IT_RST1;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Retreives actual OC mode and set interrupt accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ interrupt = HRTIM_TIM_IT_CMP2;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ (hrtim_reset == 0))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ interrupt = HRTIM_TIM_IT_SET2;
+ }
+ else if ((hrtim_set == 0) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ interrupt = HRTIM_TIM_IT_RST2;
+ }
+ }
+ break;
+ }
+
+ return interrupt;
+}
+
+/**
+ * @brief Returns the DMA request to enable or disable according to the
+ * OC mode.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval DMA request to enable or disable
+ */
+static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ uint32_t hrtim_set;
+ uint32_t hrtim_reset;
+ uint32_t dma_request = 0;
+
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Retreives actual OC mode and set dma_request accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ dma_request = HRTIM_TIM_DMA_CMP1;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+ (hrtim_reset == 0))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ dma_request = HRTIM_TIM_DMA_SET1;
+ }
+ else if ((hrtim_set == 0) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ dma_request = HRTIM_TIM_DMA_RST1;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Retreives actual OC mode and set dma_request accordingly */
+ hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
+ hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
+
+ if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+ dma_request = HRTIM_TIM_DMA_CMP2;
+ }
+ else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+ (hrtim_reset == 0))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+ dma_request = HRTIM_TIM_DMA_SET2;
+ }
+ else if ((hrtim_set == 0) &&
+ ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
+ {
+ /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+ dma_request = HRTIM_TIM_DMA_RST2;
+ }
+ }
+ break;
+ }
+
+ return dma_request;
+}
+
+static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
+
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ hdma = hhrtim->hdmaMaster;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hdma = hhrtim->hdmaTimerA;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hdma = hhrtim->hdmaTimerB;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hdma = hhrtim->hdmaTimerC;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hdma = hhrtim->hdmaTimerD;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hdma = hhrtim->hdmaTimerE;
+ }
+ break;
+ }
+
+ return hdma;
+}
+
+static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
+{
+ uint32_t timed_idx = 0xFFFFFFFF;
+
+ if (hdma->Instance == DMA1_Channel2)
+ {
+ timed_idx = HRTIM_TIMERINDEX_MASTER;
+ }
+ else if (hdma->Instance == DMA1_Channel3)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_A;
+ }
+ else if (hdma->Instance == DMA1_Channel4)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_B;
+ }
+ else if (hdma->Instance == DMA1_Channel5)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_C;
+ }
+ else if (hdma->Instance == DMA1_Channel6)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_D;
+ }
+ else if (hdma->Instance == DMA1_Channel7)
+ {
+ timed_idx = HRTIM_TIMERINDEX_TIMER_E;
+ }
+
+ return timed_idx;
+}
+
+/**
+ * @brief Forces an immediate transfer from the preload to the active
+ * registers.
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * @retval None
+ */
+static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
+ }
+ break;
+ }
+}
+
+
+/**
+ * @brief HRTIM interrupts service routine
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @retval None
+ */
+static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* Fault 1 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
+
+ /* Invoke Fault 1 event callback */
+ HAL_HRTIM_Fault1Callback(hhrtim);
+ }
+ }
+
+ /* Fault 2 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
+
+ /* Invoke Fault 2 event callback */
+ HAL_HRTIM_Fault2Callback(hhrtim);
+ }
+ }
+
+ /* Fault 3 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
+
+ /* Invoke Fault 3 event callback */
+ HAL_HRTIM_Fault3Callback(hhrtim);
+ }
+ }
+
+ /* Fault 4 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
+
+ /* Invoke Fault 4 event callback */
+ HAL_HRTIM_Fault4Callback(hhrtim);
+ }
+ }
+
+ /* Fault 5 event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
+
+ /* Invoke Fault 5 event callback */
+ HAL_HRTIM_Fault5Callback(hhrtim);
+ }
+ }
+
+ /* System fault event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
+
+ /* Invoke System fault event callback */
+ HAL_HRTIM_SystemFaultCallback(hhrtim);
+ }
+ }
+}
+
+/**
+* @brief Master timer interrupts service routine
+* @param hhrtim: pointer to HAL HRTIM handle
+* @retval None
+*/
+static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
+{
+ /* DLL calibration ready event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
+
+ /* Set HRTIM State */
+ hhrtim->State = HAL_HRTIM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ /* Invoke System fault event callback */
+ HAL_HRTIM_DLLCalbrationReadyCallback(hhrtim);
+ }
+ }
+
+ /* Burst mode period event */
+ if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
+ {
+ if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
+ {
+ __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
+
+ /* Invoke Burst mode period event callback */
+ HAL_HRTIM_BurstModePeriodCallback(hhrtim);
+ }
+ }
+
+ /* Master timer compare 1 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
+
+ /* Invoke compare 1 event callback */
+ HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer compare 2 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
+
+ /* Invoke compare 2 event callback */
+ HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer compare 3 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
+
+ /* Invoke compare 3 event callback */
+ HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer compare 4 event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
+
+ /* Invoke compare 4 event callback */
+ HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Master timer repetition event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+
+ /* Invoke repetition event callback */
+ HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+
+ /* Synchronization input event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
+
+ /* Invoke synchronization event callback */
+ HAL_HRTIM_SynchronizationEventCallback(hhrtim);
+ }
+ }
+
+ /* Master timer registers update event */
+ if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
+ {
+ if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
+ {
+ __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
+
+ /* Invoke registers update event callback */
+ HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ }
+}
+
+/**
+ * @brief Timer interrupts service routine
+ * @param hhrtim: pointer to HAL HRTIM handle
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+ * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+ * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+ * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+ * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+ * @retval None
+*/
+static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
+ uint32_t TimerIdx)
+{
+ /* Timer compare 1 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+
+ /* Invoke compare 1 event callback */
+ HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer compare 2 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+
+ /* Invoke compare 2 event callback */
+ HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer compare 3 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
+
+ /* Invoke compare 3 event callback */
+ HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer compare 4 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
+
+ /* Invoke compare 4 event callback */
+ HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer repetition event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+
+ /* Invoke repetition event callback */
+ HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer registers update event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
+
+ /* Invoke registers update event callback */
+ HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer capture 1 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+
+ /* Invoke capture 1 event callback */
+ HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer capture 2 event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+
+ /* Invoke capture 2 event callback */
+ HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer ouput 1 set event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
+
+ /* Invoke ouput 1 set event callback */
+ HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer ouput 1 reset event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
+
+ /* Invoke ouput 1 reset event callback */
+ HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer ouput 2 set event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
+
+ /* Invoke ouput 2 set event callback */
+ HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer ouput 2 reset event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
+
+ /* Invoke ouput 2 reset event callback */
+ HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Timer reset event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
+
+ /* Invoke timer reset callback */
+ HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
+ }
+ }
+
+ /* Delayed protection event */
+ if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
+ {
+ if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
+ {
+ __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
+
+ /* Invoke delayed protection callback */
+ HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
+ }
+ }
+}
+
+/**
+ * @brief DMA callback invoked upon master timer related DMA request completion
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
+{
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
+ {
+ HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
+ {
+ HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
+ {
+ HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
+ {
+ HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
+ {
+ HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
+ {
+ HAL_HRTIM_SynchronizationEventCallback(hrtim);
+ }
+ else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
+ {
+ HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+ }
+}
+
+/**
+ * @brief DMA callback invoked upon timer A..E related DMA request completion
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
+{
+ uint8_t timer_idx;
+
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ timer_idx = GetTimerIdxFromDMAHandle(hdma);
+
+ if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
+ {
+ HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
+ {
+ HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
+ {
+ HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
+ {
+ HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
+ {
+ HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
+ {
+ HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
+ {
+ HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
+ {
+ HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
+ {
+ HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
+ {
+ HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
+ {
+ HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
+ {
+ HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
+ {
+ HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
+ {
+ HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
+ }
+}
+
+/**
+* @brief DMA error callback
+* @param hdma: pointer to DMA handle.
+* @retval None
+*/
+static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_HRTIM_ErrorCallback(hrtim);
+}
+
+/**
+ * @brief DMA callback invoked upon burst DMA transfer completion
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
+{
+ HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F334x8 */
+
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
@@ -0,0 +1,4194 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief I2C HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter Integrated Circuit (I2C) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The I2C HAL driver can be used as follows:
+
+ (#) Declare a I2C_HandleTypeDef handle structure, for example:
+ I2C_HandleTypeDef hi2c;
+
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (##) Enable the I2Cx interface clock
+ (##) I2C pins configuration
+ (+++) Enable the clock for the I2C GPIOs
+ (+++) Configure I2C pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the I2Cx interrupt priority
+ (+++) Enable the NVIC I2C IRQ Channel
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx interface clock using
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx channel
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+ Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+
+ *** Polling mode IO MEM operation ***
+ =====================================
+ [..]
+ (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+ *** Interrupt mode IO MEM operation ***
+ =======================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+ HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+ HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+ *** DMA mode IO MEM operation ***
+ =================================
+ [..]
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+
+
+ *** I2C HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in I2C HAL driver.
+
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ [..]
+ (@) You can refer to the I2C HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2C I2C
+ * @brief I2C HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+ * @{
+ */
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR ((uint32_t)10000) /*!< 10 s */
+#define I2C_TIMEOUT_BUSY ((uint32_t)25) /*!< 25 ms */
+#define I2C_TIMEOUT_DIR ((uint32_t)25) /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE ((uint32_t)25) /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF ((uint32_t)25) /*!< 25 ms */
+#define I2C_TIMEOUT_TC ((uint32_t)25) /*!< 25 ms */
+#define I2C_TIMEOUT_TCR ((uint32_t)25) /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS ((uint32_t)25) /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG ((uint32_t)25) /*!< 25 ms */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+
+static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c);
+
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the I2Cx peripheral:
+
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2C according to the specified parameters
+ * in the I2C_InitTypeDef and initialize the associated handle.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+ assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+ assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if(hi2c->State == HAL_I2C_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2C_MspInit(hi2c);
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+ if(hi2c->Init.OwnAddress1 != 0)
+ {
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Addressing Master mode */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Configure I2Cx: Dual mode and Own Address2 */
+ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+ /* Configure I2Cx: Generalcall and NoStretch mode */
+ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the I2C peripheral.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* Check the I2C handle allocation */
+ if(hi2c == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the I2C Peripheral Clock */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_I2C_MspDeInit(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->State = HAL_I2C_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the I2C MSP.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2C data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2C_Master_Transmit()
+ (++) HAL_I2C_Master_Receive()
+ (++) HAL_I2C_Slave_Transmit()
+ (++) HAL_I2C_Slave_Receive()
+ (++) HAL_I2C_Mem_Write()
+ (++) HAL_I2C_Mem_Read()
+ (++) HAL_I2C_IsDeviceReady()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2C_Master_Transmit_IT()
+ (++) HAL_I2C_Master_Receive_IT()
+ (++) HAL_I2C_Slave_Transmit_IT()
+ (++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Mem_Write_IT()
+ (++) HAL_I2C_Mem_Read_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2C_Master_Transmit_DMA()
+ (++) HAL_I2C_Master_Receive_DMA()
+ (++) HAL_I2C_Slave_Transmit_DMA()
+ (++) HAL_I2C_Slave_Receive_DMA()
+ (++) HAL_I2C_Mem_Write_DMA()
+ (++) HAL_I2C_Mem_Read_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_MasterTxCpltCallback()
+ (++) HAL_I2C_MasterRxCpltCallback()
+ (++) HAL_I2C_SlaveTxCpltCallback()
+ (++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*pData++);
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t sizetmp = 0;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to RXDR */
+ (*pData++) =hi2c->Instance->RXDR;
+ sizetmp--;
+ Size--;
+
+ if((sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* If 10bit addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Read data from TXDR */
+ hi2c->Instance->TXDR = (*pData++);
+ Size--;
+ }while(Size > 0);
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is reset Receiver mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ while(Size > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*pData++) = hi2c->Instance->RXDR;
+ }
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hi2c->Instance->RXDR;
+ Size--;
+ }
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Abort DMA */
+ HAL_DMA_Abort(hi2c->hdmatx);
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, I2C_FLAG_RXNE) != HAL_OK)
+ {
+ /* Abort DMA */
+ HAL_DMA_Abort(hi2c->hdmarx);
+
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = Size;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* If 10bits addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ {
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ }
+
+ /* Wait until DIR flag is set Transmitter mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferSize = Size;
+ hi2c->XferCount = Size;
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Wait until ADDR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* Wait until DIR flag is set Receiver mode */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write data to DR */
+ hi2c->Instance->TXDR = (*pData++);
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t Sizetmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ Sizetmp = Size;
+ }
+
+ do
+ {
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Read data from RXDR */
+ (*pData++) = hi2c->Instance->RXDR;
+
+ /* Decrement the Size counter */
+ Sizetmp--;
+ Size--;
+
+ if((Sizetmp == 0)&&(Size!=0))
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(Size > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ Sizetmp = Size;
+ }
+ }
+
+ }while(Size > 0);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ /* Size > 255, need to set RELOAD bit */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ if(Size > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = Size;
+ }
+
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set NBYTES to write and reload if size > 255 and generate RESTART */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Checks if target device is ready for communication.
+ * @note This function is used with Memory devices
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ __IO uint32_t I2C_Trials = 0;
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Device is ready */
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (I2C_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+ }while(I2C_Trials < Trials);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* I2C in mode Transmitter ---------------------------------------------------*/
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX)
+ {
+ I2C_SlaveTransmit_ISR(hi2c);
+ }
+ }
+
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX))
+ {
+ I2C_MasterTransmit_ISR(hi2c);
+ }
+ }
+
+ /* I2C in mode Receiver ----------------------------------------------------*/
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET))
+ {
+ /* Slave mode selected */
+ if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)
+ {
+ I2C_SlaveReceive_ISR(hi2c);
+ }
+ }
+ if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET))
+ {
+ /* Master mode selected */
+ if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
+ {
+ I2C_MasterReceive_ISR(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* I2C Bus error interrupt occurred ------------------------------------*/
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ }
+
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Tx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Memory Rx Transfer completed callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C error callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2C handle state.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL state
+ */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+ /* Return I2C handle state */
+ return hi2c->State;
+}
+
+/**
+* @brief Return the I2C error code.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Handle Interrupt Flags Master Transmit Mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
+ {
+ if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
+ {
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ if(hi2c->XferCount > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = hi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
+ {
+ if(hi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Flush TX register if not empty */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
+
+ /* Call the correct callback to inform upper layer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Master Receive Mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
+ {
+ if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
+ {
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ if(hi2c->XferCount > 255)
+ {
+ I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ hi2c->XferSize = hi2c->XferCount;
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
+ {
+ if(hi2c->XferCount == 0)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Wrong size Status regarding TCR flag event */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Disable ERR, TC, STOP, NACK, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Call the correct callback to inform upper layer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Transmit Mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
+{
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
+ {
+ /* Check that I2C transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if(hi2c->XferCount == 0)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+ /* Check first if STOPF is set */
+ /* to prevent a Write Data in TX buffer */
+ /* which is stuck in TXDR until next */
+ /* communication with Master */
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI );
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ if(hi2c->XferCount > 0)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Interrupt Flags Slave Receive Mode
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI );
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for write request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+return HAL_OK;
+}
+
+/**
+ * @brief Master sends target device address followed by internal memory address for read request.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+{
+ I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* If Memory address size is 8Bit */
+ if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send LSB of Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ }
+
+ /* Wait until TC flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA I2C master transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave transmit process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOP flag is set */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Normal Use case, a AF is generated by master */
+ /* to inform slave the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C master receive process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C slave receive process complete callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOPF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+}
+
+/**
+ * @brief DMA I2C Memory Write process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ uint16_t DevAddress;
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until TXIS flag is set */
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C Memory Read process complete callback
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint16_t DevAddress;
+
+ /* Check if last DMA request was done with RELOAD */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ hi2c->pBuffPtr += hi2c->XferSize;
+ hi2c->XferCount -= hi2c->XferSize;
+ if(hi2c->XferCount > 255)
+ {
+ hi2c->XferSize = 255;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ }
+
+ DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > 255 */
+ if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Wait until RXNE flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ }
+ }
+ else
+ {
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is reset */
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ else
+ {
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2C communication error callback.
+ * @param hdma DMA handle
+ * @retval None
+ */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ hi2c->XferCount = 0;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ HAL_I2C_ErrorCallback(hi2c);
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag Specifies the I2C flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ {
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check if a STOPF is detected */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles Acknowledge failed detection during an I2C Communication.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+{
+ uint32_t tickstart = 0x00;
+ tickstart = HAL_GetTick();
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ /* Wait until STOP Flag is reset */
+ /* AutoEnd should be initiate after AF */
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hi2c->State= HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Flush TX register if not empty */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hi2c I2C handle.
+ * @param DevAddress Specifies the slave address to be programmed.
+ * @param Size Specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+ * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+ * @param Request New state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_TRANSFER_MODE(Mode));
+ assert_param(IS_TRANSFER_REQUEST(Request));
+
+ /* Get the CR2 register value */
+ tmpreg = hi2c->Instance->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
+
+ /* update CR2 register */
+ hi2c->Instance->CR2 = tmpreg;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c
@@ -0,0 +1,330 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2c_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief I2C Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2C Extended peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### I2C peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the I2C interface for STM32F3xx
+ devices contains the following additional features
+
+ (+) Possibility to disable or enable Analog Noise Filter
+ (+) Use of a configured Digital Noise Filter
+ (+) Disable or enable wakeup from Stop mode
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+ (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+ (++) HAL_I2CEx_EnableWakeUp()
+ (++) HAL_I2CEx_DisableWakeUp()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_I2CEx_EnableFastModePlus()
+ (++) HAL_I2CEx_DisbleFastModePlus()
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2CEx I2CEx
+ * @brief I2C Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Noise Filters
+ (+) Configure Wake Up Feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure I2C Analog noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param AnalogFilter New state of the Analog filter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Reset I2Cx ANOFF bit */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hi2c->Instance->CR1 |= AnalogFilter;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure I2C Digital noise filter.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+ assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Get the old register value */
+ tmpreg = hi2c->Instance->CR1;
+
+ /* Reset I2Cx DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << 8;
+
+ /* Store the new register value */
+ hi2c->Instance->CR1 = tmpreg;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable I2C wakeup from stop mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disable I2C wakeup from stop mode.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2Cx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+ if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
+ || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Enable wakeup from stop mode */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_I2C_ENABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c
@@ -0,0 +1,1315 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief I2S HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Integrated Interchip Sound (I2S) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The I2S HAL driver can be used as follows:
+
+ (#) Declare a I2S_HandleTypeDef handle structure.
+ (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
+ (##) Enable the SPIx interface clock.
+ (##) I2S pins configuration:
+ (+++) Enable the clock for the I2S GPIOs.
+ (+++) Configure these I2S pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
+ and HAL_I2S_Receive_IT() APIs).
+ (+++) Configure the I2Sx interrupt priority.
+ (+++) Enable the NVIC I2S IRQ handle.
+ (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
+ and HAL_I2S_Receive_DMA() APIs:
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Channel.
+ (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Channel.
+
+ (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
+ using HAL_I2S_Init() function.
+
+ -@- The specific I2S interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
+ -@- Make sure that either:
+ (+@) I2S clock is configured based on SYSCLK or
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
+
+ (#) Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ *** I2S HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in I2S HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
+ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
+ (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
+
+ [..]
+ (@) You can refer to the I2S HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup I2S I2S
+ * @brief I2S HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+ (++) Full duplex mode
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx periperal.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f3xx_hal_i2s_ex.c to */
+ /* handle the possible I2S interfaces defined in STM32F3xx devices */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief DeInitializes the I2S peripheral
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_I2S_MspDeInit(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief I2S MSP Init
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S MSP DeInit
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_Transmit()
+ (++) HAL_I2S_Receive()
+
+ (#) No-Blocking mode functions with Interrupt are :
+ (++) HAL_I2S_Transmit_IT()
+ (++) HAL_I2S_Receive_IT()
+
+ (#) No-Blocking mode functions with DMA are :
+ (++) HAL_I2S_Transmit_DMA()
+ (++) HAL_I2S_Receive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_I2S_TxCpltCallback()
+ (++) HAL_I2S_RxCpltCallback()
+ (++) HAL_I2S_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout: Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ while(hi2s->TxXferCount > 0)
+ {
+ hi2s->Instance->DR = (*pData++);
+ hi2s->TxXferCount--;
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an underrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+ }
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout: Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Receive data */
+ while(hi2s->RxXferCount > 0)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ (*pData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pTxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pRxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Transmit data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Enable Tx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param pData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pRxBuffPtr = pData;
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Enable Rx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA Tx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA Rx request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA Tx request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA Rx request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ /* Disable the I2S Tx/Rx DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ /* Abort the I2S DMA tx channel */
+ if(hi2s->hdmatx != NULL)
+ {
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmatx);
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ /* Abort the I2S DMA rx channel */
+ if(hi2s->hdmarx != NULL)
+ {
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmarx);
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ __IO uint32_t i2ssr = hi2s->Instance->SR;
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* I2S in mode Receiver ----------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ }
+
+ /* I2S Overrun error interrupt occured -------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* I2S in mode Tramitter ---------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occured ------------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/**
+ * @brief Tx Transfer Half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer half completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2S error callbacks
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the I2S state
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL state
+ */
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->State;
+}
+
+/**
+ * @brief Return the I2S error code
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval I2S Error Code
+ */
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+{
+ return hi2s->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+ * @{
+ */
+/**
+ * @brief DMA I2S transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+ hi2s->TxXferCount = 0;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_TxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S transmit process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_TxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ {
+ /* Disable Rx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0;
+ hi2s->State = HAL_I2S_STATE_READY;
+ }
+ HAL_I2S_RxCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S receive process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2S_DMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0;
+ hi2s->RxXferCount = 0;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxCpltCallback(hi2s);
+ }
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+{
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_RxCpltCallback(hi2s);
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @param Flag: Flag checked
+ * @param State: Value of the flag expected
+ * @param Timeout: Duration of the timeout
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(State == RESET)
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c
@@ -0,0 +1,1605 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_i2s_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief I2S Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of I2S Extended peripheral:
+ * + Extended features Functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### I2S Extended features #####
+ ==============================================================================
+ [..]
+ (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
+ data simultaneously using two data lines. Each SPI peripheral has an extended block
+ called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
+ (#) The Extended block is not a full SPI IP, it is used only as I2S slave to
+ implement full duplex mode. The Extended block uses the same clock sources
+ as its master (refer to the following Figure).
+
+ +-----------------------+
+ I2Sx_SCK | |
+ ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
+ +--|-->| |
+ | | +-----------------------+
+ | |
+ I2S_WS | |
+ ------>| |
+ | | +-----------------------+
+ | +-->| |
+ | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
+ +----->| |
+ +-----------------------+
+
+ (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
+
+ -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
+ I2Sx can be I2S2 or I2S3.
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ Three mode of operations are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxCpltCallback
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2S_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+/** @defgroup I2SEx I2SEx
+ * @brief I2S Extended HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
+ * @{
+ */
+typedef enum
+{
+ I2S_USE_I2S = 0x00, /*!< I2Sx should be used */
+ I2S_USE_I2SEXT = 0x01 /*!< I2Sx_ext should be used */
+}I2S_UseTypeDef;
+/**
+ * @}
+ */
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
+ * @{
+ */
+static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma);
+static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma);
+static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
+static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
+static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup I2S I2S
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialiaze the I2Sx peripheral in simplex mode:
+
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Standard
+ (++) Data Format
+ (++) MCLK Output
+ (++) Audio frequency
+ (++) Polarity
+
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx periperal.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the I2S according to the specified parameters
+ * in the I2S_InitTypeDef and create the associated handle.
+ * @param hi2s: I2S handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0, i2sclk = 0;
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+ RCC_PeriphCLKInitTypeDef rccperiphclkinit;
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+ /* Check the I2S handle allocation */
+ if(hi2s == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+ assert_param(IS_I2S_MODE(hi2s->Init.Mode));
+ assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
+ assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+ assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
+ assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
+
+ hi2s->State = HAL_I2S_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ hi2s->Instance->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = hi2s->Instance->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) *******************/
+ if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get I2S source Clock frequency ****************************************/
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) || \
+ defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
+ rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S;
+
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f3xx_conf.h file */
+ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+ {
+ /* Set external clock as I2S clock source */
+ rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_EXT;
+ HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+ /* Set the I2S clock to the external clock value */
+ i2sclk = EXTERNAL_CLOCK_VALUE;
+ }
+ else
+ {
+ /* Set SYSCLK as I2S clock source */
+ rccperiphclkinit.I2sClockSelection = RCC_I2SCLKSOURCE_SYSCLK;
+ HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+ /* Get the I2S source clock value */
+ i2sclk = HAL_RCC_GetSysClockFreq();
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined (STM32F373xC) || defined (STM32F378xx)
+ if(hi2s->Instance == SPI1)
+ {
+ i2sclk = HAL_RCC_GetPCLK2Freq();
+ }
+ else if((hi2s->Instance == SPI2) || (hi2s->Instance == SPI3))
+ {
+ i2sclk = HAL_RCC_GetPCLK1Freq();
+ }
+#endif /* STM32F373xC || STM32F378xx */
+
+ /* Compute the Real divider depending on the MCLK output state, with a floating point */
+ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ }
+
+ /* Remove the flatting point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
+
+ /* Configure the I2S with the I2S_InitStruct values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
+ (uint16_t)hi2s->Init.CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ hi2s->Instance->I2SCFGR = tmpreg;
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) || \
+ defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
+ if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
+ {
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
+ I2SxEXT(hi2s->Instance)->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
+
+ /* Get the mode to be configured for the extended I2S */
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
+ {
+ tmp = I2S_MODE_SLAVE_RX;
+ }
+ else
+ {
+ if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
+ {
+ tmp = I2S_MODE_SLAVE_TX;
+ }
+ }
+
+ /* Configure the I2S Slave with the I2S Master parameter values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
+ (uint16_t)hi2s->Init.CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) || \
+ defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
+/** @addtogroup I2S_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/**
+ * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
+ * @param hi2s: I2S handle
+ * @retval HAL status
+ */
+void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ __IO uint32_t i2ssr = hi2s->Instance->SR ;
+ __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* I2S in mode Transmitter -------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2S);
+ }
+
+ /* I2Sext in mode Receiver -----------------------------------------------*/
+ if(((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
+ the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT);
+ }
+
+ /* I2Sext Overrun error interrupt occured --------------------------------*/
+ if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occured ----------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* I2Sext in mode Transmitter ----------------------------------------------*/
+ if(((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
+ I2S_FullDuplexTx_IT(hi2s, I2S_USE_I2SEXT);
+ }
+
+ /* I2S in mode Receiver --------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
+ the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
+ I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2S);
+ }
+
+ /* I2S Overrun error interrupt occured -------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+
+ /* I2Sext Underrun error interrupt occured -------------------------------*/
+ if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callbacks
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+__weak void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxRxCpltCallback could be implenetd in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
+ *
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Pauses the audio stream playing from the Media.
+ * @param hi2s : I2S handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) || \
+ defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s : I2S handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Enable the I2S DMA request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Enable the I2S DMA request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ }
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) || \
+ defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Pause the audio file playing by disabling the I2S DMA request */
+ hi2s->Instance->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+ I2SxEXT(hi2s->Instance)->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
+
+ /* If the I2Sext peripheral is still not enabled, enable it */
+ if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ {
+ /* Enable I2Sext peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ }
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resumes the audio stream playing from the Media.
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+{
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* Disable the I2S DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+
+ /* Disable the I2S DMA Channel */
+ HAL_DMA_Abort(hi2s->hdmatx);
+ }
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* Disable the I2S DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+
+ /* Disable the I2S DMA Channel */
+ HAL_DMA_Abort(hi2s->hdmarx);
+ }
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) || \
+ defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+ {
+ /* Disable the I2S DMA requests */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+
+ /* Disable the I2S DMA Channels */
+ HAL_DMA_Abort(hi2s->hdmatx);
+ HAL_DMA_Abort(hi2s->hdmarx);
+
+ /* Disable I2Sext peripheral */
+ __HAL_I2SEXT_DISABLE(hi2s);
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+ /* Disable I2S peripheral */
+ __HAL_I2S_DISABLE(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) || \
+ defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F358xx)
+/** @addtogroup I2SEx
+ * @brief I2S Extended HAL module driver
+ * @{
+ */
+
+/** @defgroup I2SEx_Exported_Functions I2S Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended Features Functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features Functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the I2S data
+ transfers.
+
+ (#) There is two mode of transfer:
+ (++) Blocking mode: The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA. These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+
+ (#) Blocking mode functions are :
+ (++) HAL_I2S_TransmitReceive()
+
+ (#) No-Blocking mode functions with Interrupt are:
+ (++) HAL_I2S_TransmitReceive_IT()
+ (++) HAL_I2SFullDuplex_IRQHandler()
+
+ (#) No-Blocking mode functions with DMA are:
+ (++) HAL_I2S_TransmitReceive_DMA()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (++) HAL_I2S_TxRxCpltCallback()
+ (++) HAL_I2S_TxRxErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in blocking mode.
+ * @param hi2s: I2S handle
+ * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout: Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the I2S State */
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Set the I2S State busy TX/RX */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ {
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+ }
+
+ /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
+ to avoid the clock de-synchronization between Master and Slave. */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2Sx peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ while(hi2s->RxXferCount > 0)
+ {
+ /* Wait until TXE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2s->TxXferCount > 0)
+ {
+ /* Check if an underrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ hi2s->Instance->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+ }
+
+ /* Wait until RXNE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* Prepare the First Data before enabling the I2S */
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral before the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
+
+ /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ while(hi2s->RxXferCount > 0)
+ {
+ /* Wait until TXE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ if (hi2s->TxXferCount > 0)
+ {
+ /* Check if an underrun occurs */
+ if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
+ hi2s->TxXferCount--;
+ }
+
+ /* Wait until RXNE flag is set */
+ if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
+ {
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_TIMEOUT;
+ }
+
+ /* Check if an overrun occurs */
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ HAL_I2S_ErrorCallback(hi2s);
+
+ return HAL_ERROR;
+ }
+
+ (*pRxData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+ }
+ }
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
+ * @param hi2s: I2S handle
+ * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
+{
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Enable I2Sx TXE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if(hi2s->TxXferCount != 0)
+ {
+ /* Transmit First data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0)
+ {
+ /* Disable I2Sext RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ }
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2Sx peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
+ else
+ {
+ /* Enable I2Sext TXE and ERR interrupts */
+ __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Enable I2Sext RXNE and ERR interrupts */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Prepare the First Data before enabling the I2S */
+ if(hi2s->TxXferCount != 0)
+ {
+ /* Transmit First data */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0)
+ {
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
+ * @param hi2s: I2S handle
+ * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData: a 16-bit pointer to the Receive data buffer.
+ * @param Size: number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ hi2s->pTxBuffPtr = pTxData;
+ hi2s->pRxBuffPtr = pRxData;
+
+ /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
+ is selected during the I2S configuration phase, the Size parameter means the number
+ of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
+ frame is selected the Size parameter means the number of 16-bit data length. */
+ if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
+ ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1);
+ hi2s->TxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1);
+ hi2s->RxXferCount = (Size << 1);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_TxRxDMACplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_TxRxDMAError;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_TxRxDMACplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_TxRxDMAError;
+
+ /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ /* Enable the Rx DMA Channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Enable Rx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
+
+ /* Enable the Tx DMA Channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+
+ /* Enable Tx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral after the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+ else
+ {
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Tx DMA Channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
+
+ /* Enable Tx DMA Request */
+ I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
+
+ /* Enable the Rx DMA Channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Enable Rx DMA Request */
+ hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
+ __HAL_I2SEXT_ENABLE(hi2s);
+
+ /* Enable I2S peripheral after the I2Sext*/
+ __HAL_I2S_ENABLE(hi2s);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
+ * @{
+ */
+
+/**
+ * @brief DMA I2S transmit receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if (hi2s->hdmarx == hdma)
+ {
+ /* Disable Rx DMA Request */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+ else
+ {
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ }
+
+ hi2s->RxXferCount = 0;
+
+ if (hi2s->TxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+
+ if (hi2s->hdmatx == hdma)
+ {
+ /* Disable Tx DMA Request */
+ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
+ {
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+ else
+ {
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ }
+
+ hi2s->TxXferCount = 0;
+
+ if (hi2s->RxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+}
+
+/**
+ * @brief DMA I2S communication error callback
+ * @param hdma : DMA handle
+ * @retval None
+ */
+static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Rx and Tx DMA Request */
+ hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+
+ hi2s->TxXferCount = 0;
+ hi2s->RxXferCount = 0;
+
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+ HAL_I2S_ErrorCallback(hi2s);
+}
+
+/**
+ * @brief Full-Duplex IT handler transmit function
+ * @param hi2s: I2S handle
+ * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
+ * @retval None
+ */
+static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+{
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ /* Transmit data */
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ else
+ {
+ /* Transmit data */
+ I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->TxXferCount--;
+
+ if(hi2s->TxXferCount == 0)
+ {
+ /* Disable I2Sext TXE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ if(hi2s->RxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Full-Duplex IT handler receive function
+ * @param hi2s: I2S handle
+ * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
+ * @retval None
+ */
+static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
+{
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ if(hi2s->TxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+ else
+ {
+ /* Receive data */
+ (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
+ hi2s->RxXferCount--;
+
+ if(hi2s->RxXferCount == 0)
+ {
+ /* Disable I2Sext RXNE and ERR interrupt */
+ __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ if(hi2s->TxXferCount == 0)
+ {
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+ }
+ }
+ }
+}
+
+/**
+ * @brief This function handles I2S Communication Timeout.
+ * @param hi2s: I2S handle
+ * @param Flag: Flag checked
+ * @param State: Value of the flag expected
+ * @param Timeout: Duration of the timeout
+ * @param i2sUsed: I2S instance reference
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2S_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
+ uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ if(i2sUsed == I2S_USE_I2S)
+ {
+ if(State == RESET)
+ {
+ /* Wait until flag is reset */
+ while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else /* State == SET */
+ {
+ /* Wait until flag is set */
+ while((__HAL_I2S_GET_FLAG(hi2s, Flag)) != SET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ else /* i2sUsed == I2S_USE_I2SEXT */
+ {
+ if(State == RESET)
+ {
+ /* Wait until flag is reset */
+ while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else /* State == SET */
+ {
+ /* Wait until flag is set */
+ while((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) != SET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Set the I2S State ready */
+ hi2s->State= HAL_I2S_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c
@@ -0,0 +1,1597 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_irda.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief IRDA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA (Infrared Data Association) Peripheral
+ * (IRDA)
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The IRDA HAL driver can be used as follows:
+
+ (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+ in setting the associated USART or UART in IRDA mode:
+ (++) Enable the USARTx/UARTx interface clock.
+ (++) USARTx/UARTx pins configuration:
+ (+++) Enable the clock for the USARTx/UARTx GPIOs.
+ (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx/UARTx interrupt priority.
+ (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+ (+++) The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ and HAL_IRDA_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
+ the normal or low power mode and the clock prescaler in the hirda handle Init structure.
+
+ (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_IRDA_MspInit() API.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
+
+ *** IRDA HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IRDA HAL driver.
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+ (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+ (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+ (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IRDA IRDA
+ * @brief IRDA HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
+ * @{
+ */
+#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
+#define IRDA_TXDMA_TIMEOUTVALUE 22000
+#define IRDA_TIMEOUT_VALUE 22000
+#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+ * @{
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ in asynchronous IRDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible IRDA frame formats are as listed in the following table:
+
+ (+++) Table 1. IRDA frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | IRDA frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | IRDA frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+
+ (++) Power mode
+ (++) Prescaler setting
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and initialize the associated handle.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ if(hirda->State == HAL_IRDA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_IRDA_MspInit(hirda);
+ }
+
+ hirda->State = HAL_IRDA_STATE_BUSY;
+
+ /* Disable the Peripheral to update the configuration registers */
+ __HAL_IRDA_DISABLE(hirda);
+
+ /* Set the IRDA Communication parameters */
+ if (IRDA_SetConfig(hirda) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
+ hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
+
+ /* set the UART/USART in IRDA mode */
+ hirda->Instance->CR3 |= USART_CR3_IREN;
+
+ /* Enable the Peripheral */
+ __HAL_IRDA_ENABLE(hirda);
+
+ /* TEACK and/or REACK to check before moving hirda->State to Ready */
+ return (IRDA_CheckIdleState(hirda));
+}
+
+/**
+ * @brief DeInitialize the IRDA peripheral.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+ hirda->State = HAL_IRDA_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_IRDA_MspDeInit(hirda);
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->State = HAL_IRDA_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the IRDA MSP.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the IRDA MSP.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the IRDA data transfers.
+
+ [..]
+ IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+ While receiving data, transmission should be avoided as the data to be transmitted
+ could be corrupted.
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: the communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: the communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_IRDA_Transmit()
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_IRDA_Transmit_IT()
+ (++) HAL_IRDA_Receive_IT()
+ (++) HAL_IRDA_IRQHandler()
+
+ (#) Non Blocking mode functions with DMA are :
+ (++) HAL_IRDA_Transmit_DMA()
+ (++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
+ (++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
+ (++) HAL_IRDA_RxCpltCallback()
+ (++) HAL_IRDA_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @param Timeout: Specify timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ while(hirda->TxXferCount > 0)
+ {
+ hirda->TxXferCount--;
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pData +=2;
+ }
+ else
+ {
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @param Timeout: Specify timeout value.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint16_t uhMask;
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+ uhMask = hirda->Mask;
+
+ /* Check data remaining to be received */
+ while(hirda->RxXferCount > 0)
+ {
+ hirda->RxXferCount--;
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData ;
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pData +=2;
+ }
+ else
+ {
+ *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Data Register not empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
+
+ /* Enable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Enable the IRDA transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ hirda->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @note When the IRDA parity is enabled (PCE = 1) the received data contains
+ * the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ hirda->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Disable the IRDA DMA Tx & Rx requests */
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the IRDA DMA Tx & Rx request */
+ SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+ HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
+ generated if the DMA transfer interruption occurs at the middle or at the end of the stream
+ and the corresponding call back is executed.
+ */
+
+ /* Disable the IRDA Tx/Rx DMA requests */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA tx channel */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ /* Abort the IRDA DMA rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+
+ hirda->State = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Handle IRDA interrupt request.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+ /* IRDA parity error interrupt occurred -------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* IRDA frame error interrupt occurred --------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* IRDA noise error interrupt occurred --------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ /* Set the IRDA state ready to be able to start again the process */
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ /* Call IRDA Error Call back function if need be --------------------------*/
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ /* Clear RXNE interrupt flag */
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+ }
+
+
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
+ {
+ IRDA_Transmit_IT(hirda);
+ }
+
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer complete callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA error callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief IRDA State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+ of the IRDA peripheral handle.
+ (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the IRDA handle state.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL state
+ */
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+{
+ /* Return IRDA handle state */
+ return hirda->State;
+}
+
+/**
+ * @brief Return the IRDA handle error code.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval IRDA Error Code
+ */
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+{
+ return hirda->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+
+/**
+ * @brief Configure the IRDA peripheral.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tmpreg = 0x00000000;
+ IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the communication parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the IRDA Word Length, Parity and transfer Mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ switch (clocksource)
+ {
+ case IRDA_CLOCKSOURCE_PCLK1:
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_PCLK2:
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_HSI:
+ hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_SYSCLK:
+ hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_LSE:
+ hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the IRDA Idle State.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+
+ /* Initialize the IRDA ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* TEACK bits in ISR is checked only when available.
+ Bit is defined and available only for UART instances supporting WakeUp from Stop Mode feature.
+ */
+ if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
+ {
+ /* Check if the Transmitter is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the IRDA state*/
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA Communication Timeout.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag: specifies the IRDA flag to check.
+ * @param Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= ~(USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_IRDA_TxCpltCallback(hirda);
+ }
+}
+
+/**
+ * @brief DMA IRDA transmit process half complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= ~(USART_CR3_DMAR);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0;
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT().
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+
+ if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+ if(hirda->TxXferCount == 0)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pTxBuffPtr;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ hirda->pTxBuffPtr += 2;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+ hirda->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT().
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = hirda->Mask;
+
+ if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pRxBuffPtr ;
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+ hirda->pRxBuffPtr +=2;
+ }
+ else
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ if(--hirda->RxXferCount == 0)
+ {
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c
@@ -0,0 +1,419 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_iwdg.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief IWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Independent Watchdog (IWDG) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### IWDG Generic features #####
+ ==============================================================================
+ [..]
+ (+) The IWDG can be started by either software or hardware (configurable
+ through option byte).
+
+ (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
+ thus stays active even if the main clock fails.
+ Once the IWDG is started, the LSI is forced ON and cannot be disabled
+ (LSI cannot be disabled too), and the counter starts counting down from
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)
+ a system reset is generated.
+
+ (+) The IWDG counter should be refreshed at regular intervals, otherwise the
+ watchdog generates an MCU reset when the counter reaches 0.
+
+ (+) The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ reset occurs.
+
+ [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM16 CH1 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ If Window option is disabled
+
+ (+) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable write access to IWDG_PR, IWDG_RLR.
+ (++) Configure the IWDG prescaler, counter reload value.
+ This reload value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
+ (+) Use IWDG using HAL_IWDG_Start() function to :
+ (++) Reload IWDG counter with value defined in the IWDG_RLR register.
+ (++) Start the IWDG, when the IWDG is used in software mode (no need
+ to enable the LSI, it will be enabled by hardware).
+ (+) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+ [..]
+ if Window option is enabled:
+
+ (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
+ (+) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ (++) Configure the IWDG prescaler, reload value and window value.
+ (+) Then the application program must refresh the IWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
+ HAL_IWDG_Refresh() function.
+
+ *** IWDG HAL driver macros list ***
+ ====================================
+ [..]
+ Below the list of most used macros in IWDG HAL driver.
+
+ (+) __HAL_IWDG_START: Enable the IWDG peripheral
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
+ (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IWDG IWDG
+ * @brief IWDG HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+ * @{
+ */
+
+#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
+/* Local define used to check the SR status register */
+#define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU)
+
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters
+ in the IWDG_InitTypeDef and create the associated handle
+ (+) Manage Window option
+ (+) Initialize the IWDG MSP
+ (+) DeInitialize the IWDG MSP
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IWDG according to the specified
+ * parameters in the IWDG_InitTypeDef and initialize the associated handle.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the IWDG handle allocation */
+ if(hiwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+ assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+ /* Check pending flag, if previous update not done, return error */
+ if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hiwdg->State == HAL_IWDG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hiwdg->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_IWDG_MspInit(hiwdg);
+ }
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
+ /* by writing 0x5555 in KR */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+ /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
+ MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
+ MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
+
+ /* check if window option is enabled */
+ if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
+ {
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
+ {
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Write to IWDG WINR the IWDG_Window value to compare with */
+ MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window);
+ }
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the IWDG MSP.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval None
+ */
+__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start the IWDG.
+ (+) Refresh the IWDG.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the IWDG.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart = 0;
+
+ /* Process locked */
+ __HAL_LOCK(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ /* Reload IWDG counter with value defined in the RLR register */
+ if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
+ {
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+ }
+
+ /* Start the IWDG peripheral */
+ __HAL_IWDG_START(hiwdg);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until PVU, RVU, WVU flag are RESET */
+ while(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0)
+ {
+
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Refresh the IWDG.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_BUSY;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until RVU flag is RESET */
+ while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ /* Set IWDG state */
+ hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hiwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the IWDG handle state.
+ * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified IWDG module.
+ * @retval HAL state
+ */
+HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
+{
+ /* Return IWDG handle state */
+ return hiwdg->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c
@@ -0,0 +1,119 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_msp_template.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief HAL MSP module.
+ * This file template is located in the HAL folder and should be copied
+ * to the user folder.
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_MSP HAL MSP module
+ * @brief HAL MSP module.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the Global MSP.
+ * @retval None
+ */
+void HAL_MspInit(void)
+{
+
+}
+
+/**
+ * @brief DeInitializes the Global MSP.
+ * @retval None
+ */
+void HAL_MspDeInit(void)
+{
+
+}
+
+/**
+ * @brief Initializes the PPP MSP.
+ * @retval None
+ */
+void HAL_PPP_MspInit(void)
+{
+
+}
+
+/**
+ * @brief DeInitializes the PPP MSP.
+ * @retval None
+ */
+void HAL_PPP_MspDeInit(void)
+{
+
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c
@@ -0,0 +1,1171 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nand.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief NAND HAL module driver.
+ * This file provides a generic firmware to drive NAND memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NAND flash memories. It uses the FMC layer functions to interface
+ with NAND devices. This driver is used as follows:
+
+ (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
+ with control and timing parameters for both common and attribute spaces.
+
+ (+) Read NAND flash memory maker and device IDs using the function
+ HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NAND flash memory by read/write operations using the functions
+ HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
+ to read/write page(s)/spare area(s). These functions use specific device
+ information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
+ structure. The read/write address information is contained by the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
+
+ (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
+ The erase block address information is contained in the Nand_Address_Typedef
+ structure passed as parameter.
+
+ (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
+
+ (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
+ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
+ feature or the function HAL_NAND_GetECC() to get the ECC correction code.
+
+ (+) You can monitor the NAND device HAL state by calling the function
+ HAL_NAND_GetState()
+
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NAND flash operations.
+ If a NAND flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup NAND NAND
+ * @brief NAND HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup NAND_Private_Functions NAND Private Functions
+ * @{
+ */
+static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NAND memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform NAND memory Initialization sequence
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ComSpace_Timing: pointer to Common space timing structure
+ * @param AttSpace_Timing: pointer to Attribute space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+{
+ /* Check the NAND handle state */
+ if(hnand == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnand->State == HAL_NAND_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnand->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspInit(hnand);
+ }
+
+ /* Initialize NAND control Interface */
+ FMC_NAND_Init(hnand->Instance, &(hnand->Init));
+
+ /* Initialize NAND common space timing Interface */
+ FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+
+ /* Initialize NAND attribute space timing Interface */
+ FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+
+ /* Enable the NAND device */
+ __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NAND memory De-Initialization sequence
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
+{
+ /* Initialize the low level hardware (MSP) */
+ HAL_NAND_MspDeInit(hnand);
+
+ /* Configure the NAND registers with their reset values */
+ FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+
+ /* Reset the NAND controller state */
+ hnand->State = HAL_NAND_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND MSP Init
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NAND MSP DeInit
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function handles NAND device interrupt request.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+*/
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
+{
+ /* Check NAND interrupt Rising edge flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Rising edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check NAND interrupt Level flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Level pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
+ }
+
+ /* Check NAND interrupt Falling edge flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt Falling edge pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check NAND interrupt FIFO empty flag */
+ if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
+ {
+ /* NAND interrupt callback*/
+ HAL_NAND_ITCallback(hnand);
+
+ /* Clear NAND interrupt FIFO empty pending bit */
+ __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
+ }
+}
+
+/**
+ * @brief NAND interrupt feature callback
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval None
+ */
+__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NAND_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NAND Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NAND
+ memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read the NAND memory electronic signature
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pNAND_ID: NAND ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
+{
+ __IO uint32_t data = 0;
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Read ID command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+
+ /* Read the electronic signature from NAND flash */
+ data = *(__IO uint32_t *)deviceaddress;
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory reset
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send NAND reset command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
+
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
+ * @param pBuffer: pointer to destination read buffer
+ * @param NumPageToRead: number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0;
+ uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numpagesread++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Write Page(s) to NAND memory block
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
+ * @param pBuffer: pointer to source buffer to write
+ * @param NumPageToWrite: number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+{
+ __IO uint32_t index = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numpageswritten++;
+
+ /* Decrement pages to write */
+ NumPageToWrite--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
+ * @param pBuffer: pointer to source buffer to write
+ * @param NumSpareAreaToRead: Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Get Data into Buffer */
+ for ( ;index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ num_spare_area_read++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
+ * @param pBuffer: pointer to source buffer to write
+ * @param NumSpareAreaTowrite: number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0;
+ uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
+ NAND_AddressTypeDef nandaddress;
+ uint32_t addressoffset = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Save the content of pAddress as it will be modified */
+ nandaddress.Block = pAddress->Block;
+ nandaddress.Page = pAddress->Page;
+ nandaddress.Zone = pAddress->Zone;
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* update the buffer size */
+ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
+
+ /* Get the address offset */
+ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ num_spare_area_written++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory Block erase
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t deviceaddress = 0;
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Send Erase block command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+
+ /* for 512 and 1 GB devices, 4th cycle is required */
+ if(hnand->Info.BlockNbr >= 1024)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_TIMEOUT;
+ }
+}
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NAND memory read status
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval NAND status
+ */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+ uint32_t data = 0;
+ uint32_t deviceaddress = 0;
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Send Read status operation command */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
+
+ /* Read status register data */
+ data = *(__IO uint8_t *)deviceaddress;
+
+ /* Return the status */
+ if((data & NAND_ERROR) == NAND_ERROR)
+ {
+ return NAND_ERROR;
+ }
+ else if((data & NAND_READY) == NAND_READY)
+ {
+ return NAND_READY;
+ }
+
+ return NAND_BUSY;
+}
+
+/**
+ * @brief Increment the NAND memory address
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress: pointer to NAND address structure
+ * @retval The new status of the increment address operation. It can be:
+ * - NAND_VALID_ADDRESS: When the new address is valid address
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address
+ */
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+ uint32_t status = NAND_VALID_ADDRESS;
+
+ /* Increment page address */
+ pAddress->Page++;
+
+ /* Check NAND address is valid */
+ if(pAddress->Page == hnand->Info.BlockSize)
+ {
+ pAddress->Page = 0;
+ pAddress->Block++;
+
+ if(pAddress->Block == hnand->Info.ZoneSize)
+ {
+ pAddress->Block = 0;
+ pAddress->Zone++;
+
+ if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+/**
+ * @}
+ */
+
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically NAND ECC feature.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Enable ECC feature */
+ FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+{
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Disable ECC feature */
+ FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NAND ECC feature.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param ECCval: pointer to ECC value
+ * @param Timeout: maximum timeout to wait
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Get NAND ECC value */
+ status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+
+ /* Update the NAND state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NAND State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NAND controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NAND state
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @retval HAL state
+ */
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+{
+ return hnand->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Increment the NAND memory address.
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param Address: address to be incremented.
+ * @retval The new status of the increment address operation. It can be:
+ * - NAND_VALID_ADDRESS: When the new address is valid address
+ * - NAND_INVALID_ADDRESS: When the new address is invalid address
+ */
+static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
+{
+ uint32_t status = NAND_VALID_ADDRESS;
+
+ Address->Page++;
+
+ if(Address->Page == hnand->Info.BlockSize)
+ {
+ Address->Page = 0;
+ Address->Block++;
+
+ if(Address->Block == hnand->Info.ZoneSize)
+ {
+ Address->Block = 0;
+ Address->Zone++;
+
+ if(Address->Zone == hnand->Info.BlockNbr)
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c
@@ -0,0 +1,1049 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_nor.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief NOR HAL module driver.
+ * This file provides a generic firmware to drive NOR memories mounted
+ * as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control NOR flash memories. It uses the FMC layer functions to interface
+ with NOR devices. This driver is used as follows:
+
+ (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
+ with control and timing parameters for both normal and extended mode.
+
+ (+) Read NOR flash memory manufacturer code and device IDs using the function
+ HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
+ structure declared by the function caller.
+
+ (+) Access NOR flash memory by read/write data unit operations using the functions
+ HAL_NOR_Read(), HAL_NOR_Program().
+
+ (+) Perform NOR flash erase block/chip operations using the functions
+ HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
+
+ (+) Read the NOR flash CFI (common flash interface) IDs using the function
+ HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
+ structure declared by the function caller.
+
+ (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
+ HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
+
+ (+) You can monitor the NOR device HAL state by calling the function
+ HAL_NOR_GetState()
+ [..]
+ (@) This driver is a set of generic APIs which handle standard NOR flash operations.
+ If a NOR flash device contains different operations and/or implementations,
+ it should be implemented separately.
+
+ *** NOR HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in NOR HAL driver.
+
+ (+) NOR_WRITE: NOR memory write data to specified address
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup NOR NOR
+ * @brief NOR HAL module driver
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+ * @{
+ */
+
+/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
+#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
+#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
+
+/* Constants to define data to program a command */
+#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
+#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
+#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
+#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
+#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
+#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
+#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
+#define NOR_CMD_DATA_CFI (uint16_t)0x0098
+
+#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
+#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
+#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+
+/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
+#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup NOR_Private_Variables NOR Private Variables
+ * @{
+ */
+
+static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the NOR memory Initialization sequence
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timing: pointer to NOR control timing structure
+ * @param ExtTiming: pointer to NOR extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the NOR handle parameter */
+ if(hnor == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hnor->State == HAL_NOR_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hnor->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_NOR_MspInit(hnor);
+ }
+
+ /* Initialize NOR control Interface */
+ FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+
+ /* Initialize NOR timing Interface */
+ FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+
+ /* Initialize NOR extended mode timing Interface */
+ FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
+
+ /* Initialize NOR Memory Data Width*/
+ if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_8B;
+ }
+ else
+ {
+ uwNORMemoryDataWidth = NOR_MEMORY_16B;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Perform NOR memory De-Initialization sequence
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_NOR_MspDeInit(hnor);
+
+ /* Configure the NOR registers with their reset values */
+ FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief NOR MSP Init
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP DeInit
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval None
+ */
+__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief NOR MSP Wait fro Ready/Busy signal
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Timeout: Maximum timeout value
+ * @retval None
+ */
+__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_NOR_MspWait could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### NOR Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the NOR memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read NOR flash IDs
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_ID: pointer to NOR ID structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read ID command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the NOR memory to Read mode.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read data from NOR memory
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress: pointer to Device address
+ * @param pData: pointer to read data
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Read the data */
+ *pData = *(__IO uint32_t *)(uint32_t)pAddress;
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Program data to NOR memory
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pAddress: Device address
+ * @param pData: pointer to the data to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send program data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+
+ /* Write the data */
+ NOR_WRITE(pAddress, *pData);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a block of data from the FMC NOR memory.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param uwAddress: NOR memory internal address to read from.
+ * @param pData: pointer to the buffer that receives the data read from the
+ * NOR memory.
+ * @param uwBufferSize: number of Half word to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read data command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
+
+ /* Read buffer */
+ while( uwBufferSize > 0)
+ {
+ *pData++ = *(__IO uint16_t *)uwAddress;
+ uwAddress += 2;
+ uwBufferSize--;
+ }
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a half-word buffer to the FMC NOR memory. This function
+ * must be used only with S29GL128P NOR memory.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param uwAddress: NOR memory internal address from which the data
+ * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
+ * 64 bytes boundary for example).
+ * @param pData: pointer to source data buffer.
+ * @param uwBufferSize: number of Half words to write.
+ * @note The maximum buffer size allowed is NOR memory dependent
+ * (can be 64 Bytes max for example).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+{
+ uint16_t * p_currentaddress = (uint16_t *)NULL;
+ uint16_t * p_endaddress = (uint16_t *)NULL;
+ uint32_t lastloadedaddress = 0, deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Initialize variables */
+ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
+ p_endaddress = p_currentaddress + (uwBufferSize-1);
+ lastloadedaddress = (uint32_t)(uwAddress);
+
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+
+ /* Write Buffer Load Command */
+ NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
+
+ /* Load Data into NOR Buffer */
+ while(p_currentaddress <= p_endaddress)
+ {
+ /* Store last loaded address & data value (for polling) */
+ lastloadedaddress = (uint32_t)p_currentaddress;
+
+ NOR_WRITE(p_currentaddress, *pData++);
+
+ p_currentaddress++;
+ }
+
+ NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the specified block of the NOR memory
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param BlockAddress: Block to erase address
+ * @param Address: Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send block erase command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Erase the entire NOR chip.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address: Device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send NOR chip erase command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+
+ /* Check the NOR memory status and update the controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read NOR flash CFI IDs
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param pNOR_CFI: pointer to NOR CFI IDs structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
+ uint32_t deviceaddress = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Check the NOR controller state */
+ if(hnor->State == HAL_NOR_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Send read CFI query command */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+ /* read the NOR CFI information */
+ pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+ pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+ pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+ pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+ /* Check the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the NOR interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically NOR write operation.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Enable write operation */
+ FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically NOR write operation.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+ /* Process Locked */
+ __HAL_LOCK(hnor);
+
+ /* Update the SRAM controller state */
+ hnor->State = HAL_NOR_STATE_BUSY;
+
+ /* Disable write operation */
+ FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnor);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### NOR State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the NOR controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the NOR controller state
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @retval NOR controller state
+ */
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+{
+ return hnor->State;
+}
+
+/**
+ * @brief Returns the NOR operation status.
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
+ * @param Address: Device address
+ * @param Timeout: NOR progamming Timeout
+ * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+ * or HAL_NOR_STATUS_TIMEOUT
+ */
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+{
+ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+ uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
+ uint32_t tickstart = 0;
+
+ /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
+ HAL_NOR_MspWait(hnor, Timeout);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmp_sr1 = *(__IO uint16_t *)Address;
+ tmp_sr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return NOR_Success */
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmp_sr1 = *(__IO uint16_t *)Address;
+ tmp_sr2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return NOR_Success */
+ if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
+ }
+ }
+
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c
@@ -0,0 +1,916 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_opamp.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief OPAMP HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
+ * peripheral:
+ * + OPAMP Configuration
+ * + OPAMP calibration
+ * Thanks to
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+================================================================================
+ ##### OPAMP Peripheral Features #####
+================================================================================
+
+ [..] The device integrates up to 4 operational amplifiers OPAMP1, OPAMP2,
+ OPAMP3 and OPAMP4:
+
+ (#) The OPAMP(s) provides several exclusive running modes.
+ (++) Standalone mode
+ (++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
+ (++) Follower mode
+
+ (#) The OPAMP(s) provide(s) calibration capabilities.
+ (++) Calibration aims at correcting some offset for running mode.
+ (++) The OPAMP uses either factory calibration settings OR user defined
+ calibration (trimming) settings (i.e. trimming mode).
+ (++) The user defined settings can be figured out using self calibration
+ handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
+ (++) HAL_OPAMP_SelfCalibrate:
+ (++) Runs automatically the calibration in 2 steps.
+ (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
+ (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
+ appropriate and enough in most cases).
+ (++) Enables the user trimming mode
+ (++) Updates the init structure with trimming values with fresh calibration
+ results.
+ The user may store the calibration results for larger
+ (ex monitoring the trimming as a function of temperature
+ for instance)
+ (++) for STM32F3 devices having 2 or 4 OPAMPs
+ HAL_OPAMPEx_SelfCalibrateAll
+ runs calibration of 2 or 4 OPAMPs in parallel.
+
+ (#) For any running mode, an additional Timer-controlled Mux (multiplexer)
+ mode can be set on top.
+ (++) Timer-controlled Mux mode allows Automatic switching between inverting
+ and non-inverting input.
+ (++) Hence on top of defaults (primary) inverting and non-inverting inputs,
+ the user shall select secondary inverting and non inverting inputs.
+ (++) TIM1 CC6 provides the alternate switching tempo between defaults
+ (primary) and secondary inputs.
+
+ (#) Running mode: Standalone mode
+ (++) Gain is set externally (gain depends on external loads).
+ (++) Follower mode also possible externally by connecting the inverting input to
+ the output.
+
+ (#) Running mode: Follower mode
+ (++) No Inverting Input is connected.
+
+ (#) Running mode: Programmable Gain Amplifier (PGA) mode
+ (Resistor feedback output)
+ (++) The OPAMP(s) output(s) can be internally connected to resistor feedback
+ output.
+ (++) OPAMP gain is either 2, 4, 8 or 16.
+
+ (#) The OPAMPs non inverting input (both default and secondary) can be
+ selected among the list shown by table below.
+
+ (#) The OPAMPs non inverting input (both default and secondary) can be
+ selected among the list shown by table below.
+
+ [..] Table 1. OPAMPs inverting/non-inverting inputs for the STM32F3 devices:
+
+ +--------------------------------------------------------------+
+ | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | No conn| X | X | X | X |
+ | Inverting Input | VM0 | PC5 | PC5 | PB10 | PB10 |
+ | (1) | VM1 | PA3 | PA5 | PB2 | PD8 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | VP0 | PA1 | PA7 | PB0 | PB13 |
+ | Non Inverting | VP1 | PA7 | PD14 | PB13 | PD11 |
+ | Input | VP2 | PA3 | PB0 | PA1 | PA4 |
+ | | VP3 | PA5 | PB14 | PA5 | PB11 |
+ +--------------------------------------------------------------+
+ (1): NA in follower mode.
+
+ [..] Table 2. OPAMPs outputs for the STM32F3 devices:
+
+ +--------------------------------------------------------------+
+ | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | Output | | PA2 | PA6 | PB1 | PB12 |
+ |-----------------|--------|--------|--------|--------|--------|
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ *** Calibration ***
+ ============================================
+ [..]
+ To run the opamp calibration self calibration:
+
+ (#) Start calibration using HAL_OPAMP_SelfCalibrate.
+ Store the calibration results.
+
+ *** Running mode ***
+ ============================================
+ [..]
+ To use the opamp, perform the following steps:
+
+ (#) Fill in the HAL_OPAMP_MspInit() to
+ (++) Configure the opamp input AND output in analog mode using
+ HAL_GPIO_Init() to map the opamp output to the GPIO pin.
+
+ (#) Configure the opamp using HAL_OPAMP_Init() function:
+ (++) Select the mode
+ (++) Select the inverting input
+ (++) Select the non-inverting input
+ (++) Select if the Timer controlled Mux mode is enabled/disabled
+ (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input
+ (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input
+ (++) If PGA mode is enabled, Select if inverting input is connected.
+ (++) Select either factory or user defined trimming mode.
+ (++) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
+ (typ. settings returned by HAL_OPAMP_SelfCalibrate function).
+
+ (#) Enable the opamp using HAL_OPAMP_Start() function.
+
+ (#) Disable the opamp using HAL_OPAMP_Stop() function.
+
+ (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function. From then The configuration
+ can be modified
+ (++) After HW reset
+ (++) OR thanks to HAL_OPAMP_MspDeInit called (user defined) from HAL_OPAMP_DeInit.
+
+ *** Running mode: change of configuration while OPAMP ON ***
+ ============================================
+ [..]
+ To Re-configure OPAMP when OPAMP is ON (change on the fly)
+ (#) If needed, Fill in the HAL_OPAMP_MspInit()
+ (++) This is the case for instance if you wish to use new OPAMP I/O
+
+ (#) Configure the opamp using HAL_OPAMP_Init() function:
+ (++) As in configure case, selects first the parameters you wish to modify.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup OPAMP OPAMP
+ * @brief OPAMP HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup OPAMP_Private_Define OPAMP Private Define
+ * @{
+ */
+/* CSR register reset value */
+#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the OPAMP according to the specified
+ * parameters in the OPAMP_InitTypeDef and create the associated handle.
+ * @note If the selected opamp is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
+
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation and lock status */
+ /* Init not allowed if calibration is ongoing */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set OPAMP parameters */
+ assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
+ assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
+ if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
+ {
+ assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
+ }
+
+ assert_param(IS_OPAMP_TIMERCONTROLLED_MUXMODE(hopamp->Init.TimerControlledMuxmode));
+
+ if ((hopamp->Init.TimerControlledMuxmode) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE)
+ {
+ assert_param(IS_OPAMP_SEC_NONINVERTINGINPUT(hopamp->Init.NonInvertingInputSecondary));
+ if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
+ {
+ assert_param(IS_OPAMP_SEC_INVERTINGINPUT(hopamp->Init.InvertingInputSecondary));
+ }
+ }
+
+ if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
+ {
+ assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
+ assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
+ }
+
+ assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
+ if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
+ {
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
+ assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
+ }
+
+ /* Init SYSCFG and the low level hardware to access opamp */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ if(hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hopamp->Lock = HAL_UNLOCKED;
+ }
+
+ /* Call MSP init function */
+ HAL_OPAMP_MspInit(hopamp);
+
+ /* Set OPAMP parameters */
+ /* Set bits according to hopamp->hopamp->Init.Mode value */
+ /* Set bits according to hopamp->hopamp->Init.InvertingInput value */
+ /* Set bits according to hopamp->hopamp->Init.NonInvertingInput value */
+ /* Set bits according to hopamp->hopamp->Init.TimerControlledMuxmode value */
+ /* Set bits according to hopamp->hopamp->Init.InvertingInputSecondary value */
+ /* Set bits according to hopamp->hopamp->Init.NonInvertingInputSecondary value */
+ /* Set bits according to hopamp->hopamp->Init.PgaConnect value */
+ /* Set bits according to hopamp->hopamp->Init.PgaGain value */
+ /* Set bits according to hopamp->hopamp->Init.UserTrimming value */
+ /* Set bits according to hopamp->hopamp->Init.TrimmingValueP value */
+ /* Set bits according to hopamp->hopamp->Init.TrimmingValueN value */
+
+
+ /* check if OPAMP_PGA_MODE & in Follower mode */
+ /* - InvertingInput */
+ /* - InvertingInputSecondary */
+ /* are Not Applicable */
+
+ if ((hopamp->Init.Mode == OPAMP_PGA_MODE) || (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE))
+ {
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
+ hopamp->Init.Mode | \
+ hopamp->Init.NonInvertingInput | \
+ hopamp->Init.TimerControlledMuxmode | \
+ hopamp->Init.NonInvertingInputSecondary | \
+ hopamp->Init.PgaConnect | \
+ hopamp->Init.PgaGain | \
+ hopamp->Init.UserTrimming | \
+ (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
+ (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
+
+ }
+ else /* OPAMP_STANDALONE_MODE */
+ {
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK, \
+ hopamp->Init.Mode | \
+ hopamp->Init.InvertingInput | \
+ hopamp->Init.NonInvertingInput | \
+ hopamp->Init.TimerControlledMuxmode | \
+ hopamp->Init.InvertingInputSecondary | \
+ hopamp->Init.NonInvertingInputSecondary | \
+ hopamp->Init.PgaConnect | \
+ hopamp->Init.PgaGain | \
+ hopamp->Init.UserTrimming | \
+ (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
+ (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
+ }
+
+ /* Update the OPAMP state*/
+ if (hopamp->State == HAL_OPAMP_STATE_RESET)
+ {
+ /* From RESET state to READY State */
+ hopamp->State = HAL_OPAMP_STATE_READY;
+ }
+ /* else: remain in READY or BUSY state (no update) */
+
+ return status;
+ }
+}
+
+
+/**
+ * @brief DeInitializes the OPAMP peripheral
+ * @note Deinitialization can't be performed if the OPAMP configuration is locked.
+ * To unlock the configuration, perform a system reset.
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* DeInit not allowed if calibration is ongoing */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set OPAMP_CSR register to reset value */
+ WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
+
+ /* DeInit the low level hardware: GPIO, CLOCK and NVIC */
+ /* When OPAMP is locked, unlocking can be achieved thanks to */
+ /* __HAL_RCC_SYSCFG_CLK_DISABLE() call within HAL_OPAMP_MspDeInit */
+ /* Note that __HAL_RCC_SYSCFG_CLK_DISABLE() also disables comparator */
+ HAL_OPAMP_MspDeInit(hopamp);
+
+ if (OPAMP_CSR_RESET_VALUE == hopamp->Instance->CSR)
+ {
+ /* Update the OPAMP state */
+ hopamp->State = HAL_OPAMP_STATE_RESET;
+ }
+ else /* RESET STATE */
+ {
+ /* DeInit not complete */
+ /* It can be the case if OPAMP was formerly locked */
+ status = HAL_ERROR;
+
+ /* The OPAMP state is NOT updated */
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hopamp);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the OPAMP MSP.
+ * @param hopamp: OPAMP handle
+ * @retval None
+ */
+__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OPAMP_MspInit could be implemented in the user file
+ */
+
+ /* Example */
+}
+
+/**
+ * @brief DeInitializes OPAMP MSP.
+ * @param hopamp: OPAMP handle
+ * @retval None
+ */
+__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_OPAMP_MspDeInit could be implemented in the user file
+ */
+
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the OPAMP data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the opamp
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ if(hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ /* Enable the selected opamp */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Update the OPAMP state*/
+ /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
+ hopamp->State = HAL_OPAMP_STATE_BUSY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+
+ }
+ return status;
+}
+
+/**
+ * @brief Stop the opamp
+ * @param hopamp: OPAMP handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ /* Check if OPAMP calibration ongoing */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ if(hopamp->State == HAL_OPAMP_STATE_BUSY)
+ {
+ /* Disable the selected opamp */
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Update the OPAMP state*/
+ /* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
+ hopamp->State = HAL_OPAMP_STATE_READY;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Run the self calibration of one OPAMP
+ * @param hopamp handle
+ * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
+ * @retval HAL status
+ * @note Calibration runs about 25 ms.
+ */
+
+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t trimmingvaluen = 0;
+ uint32_t trimmingvaluep = 0;
+ uint32_t delta;
+
+ /* Check the OPAMP handle allocation */
+ /* Check if OPAMP locked */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ if(hopamp->State == HAL_OPAMP_STATE_READY)
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Set Calibration mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Enable calibration */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ /* Select 90% VREF */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+
+ /* Enable the selected opamp */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen = 16;
+ delta = 8;
+
+ while (delta != 0)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen -= delta;
+ }
+
+ delta >>= 1;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep = 16;
+ delta = 8;
+
+ while (delta != 0)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep += delta;
+ }
+ else
+ {
+ trimmingvaluep -= delta;
+ }
+
+ delta >>= 1;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluep++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Disable the OPAMP */
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Set operating mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* Self calibration is successful */
+ /* Store calibration(user timming) results in init structure. */
+
+ /* Write calibration result N */
+ hopamp->Init.TrimmingValueN = trimmingvaluen;
+
+ /* Write calibration result P */
+ hopamp->Init.TrimmingValueP = trimmingvaluep;
+
+ /* Select user timming mode */
+ /* And updated with calibrated settings */
+ hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<State == HAL_OPAMP_STATE_RESET) \
+ || (hopamp->State == HAL_OPAMP_STATE_READY) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
+ || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+
+ {
+ status = HAL_ERROR;
+ }
+
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ /* Lock OPAMP */
+ SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_LOCK);
+
+ /* OPAMP state changed to locked */
+ hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
+ }
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the OPAMP state
+ * @param hopamp: OPAMP handle
+ * @retval HAL state
+ */
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
+{
+ /* Check the OPAMP handle allocation */
+ if(hopamp == NULL)
+ {
+ return HAL_OPAMP_STATE_RESET;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+ return hopamp->State;
+}
+
+/**
+ * @brief Return the OPAMP factory trimming value
+ * @param hopamp: OPAMP handle
+ * @param trimmingoffset: Trimming offset (P or N)
+ * @retval Trimming value (P or N): range: 0->31
+ * or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
+ */
+
+OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
+{
+ uint32_t oldusertrimming = 0;
+ OPAMP_TrimmingValueTypeDef oldtrimmingvaluep = 0, oldtrimmingvaluen = 0, trimmingvalue = 0;
+
+ /* Check the OPAMP handle allocation */
+ /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
+ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
+ || (hopamp->State == HAL_OPAMP_STATE_BUSY) \
+ || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
+ || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ return OPAMP_FACTORYTRIMMING_DUMMY;
+ }
+ else
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+ assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
+
+ /* Check the trimming mode */
+ if ((READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)) != RESET)
+ {
+ /* User trimming is used */
+ oldusertrimming = OPAMP_TRIMMING_USER;
+ /* Store the TrimmingValueP & TrimmingValueN */
+ oldtrimmingvaluep = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
+ oldtrimmingvaluen = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING;
+ }
+
+ /* Set factory timming mode */
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Get factory trimming */
+ if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
+ {
+ /* Return TrimOffsetP */
+ trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING);
+ }
+ else
+ {
+ /* Return TrimOffsetN */
+ trimmingvalue = ((hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING);
+ }
+
+ /* Restore user trimming configuration if it was formerly set */
+ /* Check if user trimming was used */
+ if (oldusertrimming == OPAMP_TRIMMING_USER)
+ {
+ /* Restore user trimming */
+ SET_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM);
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, oldtrimmingvaluep<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, oldtrimmingvaluen<© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup OPAMPEx OPAMPEx
+ * @brief OPAMP Extended HAL module driver.
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
+ * @{
+ */
+
+
+/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief Extended Self calibration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended IO operation functions #####
+ ===============================================================================
+ [..]
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC)
+/* 2 OPAMPS available */
+/* 2 OPAMPS can be calibrated in parallel */
+
+/**
+ * @brief Run the self calibration of 2 OPAMPs in parallel.
+ * @param hopamp1 handle
+ * @param hopamp2 handle
+ * @retval HAL status
+ * @note Updated offset trimming values (PMOS & NMOS), user trimming is enabled
+ * @note Calibration runs about 25 ms.
+ */
+
+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ uint32_t trimmingvaluen1 = 0;
+ uint32_t trimmingvaluep1 = 0;
+ uint32_t trimmingvaluen2 = 0;
+ uint32_t trimmingvaluep2 = 0;
+
+ uint32_t delta;
+
+ if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ status = HAL_ERROR;
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY))
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
+
+ /* Set Calibration mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Enable calibration */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ /* Select 90% VREF */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+
+ /* Enable the opamps */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen1 = 16;
+ trimmingvaluen2 = 16;
+ delta = 8;
+
+ while (delta != 0)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen1 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen1 -= delta;
+ }
+
+ if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen2 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen2 -= delta;
+ }
+
+ delta >>= 1;
+ }
+
+ // Still need to check if righ calibration is current value or un step below
+ // Indeed the first value that causes the OUTCAL bit to change from 1 to 0
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep1 = 16;
+ trimmingvaluep2 = 16;
+ delta = 8;
+
+ while (delta != 0)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep1 += delta;
+ }
+ else
+ {
+ trimmingvaluep1 -= delta;
+ }
+
+ if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep2 += delta;
+ }
+ else
+ {
+ trimmingvaluep2 -= delta;
+ }
+
+ delta >>= 1;
+ }
+
+ // Still need to check if righ calibration is current value or un step below
+ // Indeed the first value that causes the OUTCAL bit to change from 1 to 0
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluep1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR & OPAMP_CSR_OUTCAL)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluep2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Disable the OPAMPs */
+ CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Set operating mode back */
+ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* Self calibration is successful */
+ /* Store calibration(user timming) results in init structure. */
+ /* Select user timming mode */
+
+ /* Write calibration result N */
+ hopamp1->Init.TrimmingValueN = trimmingvaluen1;
+ hopamp2->Init.TrimmingValueN = trimmingvaluen2;
+
+ /* Write calibration result P */
+ hopamp1->Init.TrimmingValueP = trimmingvaluep1;
+ hopamp2->Init.TrimmingValueP = trimmingvaluep2;
+
+ /* Calibration */
+ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ /* Select user timming mode */
+ /* And updated with calibrated settings */
+ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED) || \
+ (hopamp4 == NULL) || (hopamp4->State == HAL_OPAMP_STATE_BUSYLOCKED))
+ {
+ status = HAL_ERROR;
+ }
+
+ if(status == HAL_OK)
+ {
+ /* Check if OPAMP in calibration mode and calibration not yet enable */
+ if((hopamp1->State == HAL_OPAMP_STATE_READY) && (hopamp2->State == HAL_OPAMP_STATE_READY) && \
+ (hopamp3->State == HAL_OPAMP_STATE_READY) && (hopamp4->State == HAL_OPAMP_STATE_READY))
+ {
+ /* Check the parameter */
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
+ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance));
+
+ /* Set Calibration mode */
+ /* Non-inverting input connected to calibration reference voltage. */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
+ SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* user trimming values are used for offset calibration */
+ SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_USERTRIM);
+ SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM);
+
+ /* Enable calibration */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
+ SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* 1st calibration - N */
+ /* Select 90% VREF */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
+
+ /* Enable the opamps */
+ SET_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluen1 = 16;
+ trimmingvaluen2 = 16;
+ trimmingvaluen3 = 16;
+ trimmingvaluen4 = 16;
+ delta = 8;
+
+ while (delta != 0)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen1 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen1 -= delta;
+ }
+
+ if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen2 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen2 -= delta;
+ }
+
+ if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen3 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen3 -= delta;
+ }
+
+ if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluen4 += delta;
+ }
+ else
+ {
+ /* OPAMP_CSR_OUTCAL is LOW try lower trimming */
+ trimmingvaluen4 -= delta;
+ }
+
+ delta >>= 1;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen3++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is actually one value more */
+ trimmingvaluen4++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
+
+ /* Init trimming counter */
+ /* Medium value */
+ trimmingvaluep1 = 16;
+ trimmingvaluep2 = 16;
+ trimmingvaluep3 = 16;
+ trimmingvaluep4 = 16;
+
+ delta = 8;
+
+ while (delta != 0)
+ {
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep1 += delta;
+ }
+ else
+ {
+ trimmingvaluep1 -= delta;
+ }
+
+ if ((hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep2 += delta;
+ }
+ else
+ {
+ trimmingvaluep2 -= delta;
+ }
+
+ if ((hopamp3->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep3 += delta;
+ }
+ else
+ {
+ trimmingvaluep3 -= delta;
+ }
+
+ if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
+ trimmingvaluep4 += delta;
+ }
+ else
+ {
+ trimmingvaluep4 -= delta;
+ }
+
+ delta >>= 1;
+ }
+
+ /* Still need to check if righ calibration is current value or un step below */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ /* Set candidate trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep1++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep2++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep3++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
+ {
+ /* Trimming value is actually one value more */
+ trimmingvaluep4++;
+ /* Set right trimming */
+ MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_CALON);
+ CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
+
+ /* Disable the OPAMPs */
+ CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+ CLEAR_BIT (hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Set normal operating mode back */
+ CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
+ CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
+
+ /* Self calibration is successful */
+ /* Store calibration(user timming) results in init structure. */
+ /* Select user timming mode */
+
+ /* Write calibration result N */
+ hopamp1->Init.TrimmingValueN = trimmingvaluen1;
+ hopamp2->Init.TrimmingValueN = trimmingvaluen2;
+ hopamp3->Init.TrimmingValueN = trimmingvaluen3;
+ hopamp4->Init.TrimmingValueN = trimmingvaluen4;
+
+ /* Write calibration result P */
+ hopamp1->Init.TrimmingValueP = trimmingvaluep1;
+ hopamp2->Init.TrimmingValueP = trimmingvaluep2;
+ hopamp3->Init.TrimmingValueP = trimmingvaluep3;
+ hopamp4->Init.TrimmingValueP = trimmingvaluep4;
+
+ /* Select user timming mode */
+ /* And updated with calibrated settings */
+ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
+ hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER;
+
+ MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3<Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4<© COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup PCCARD PCCARD
+ * @brief PCCARD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
+ * @{
+ */
+
+#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF
+#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
+
+#define PCCARD_STATUS_OK (uint8_t)0x58
+#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize
+ the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform the PCCARD memory Initialization sequence
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param ComSpaceTiming: Common space timing structure
+ * @param AttSpaceTiming: Attribute space timing structure
+ * @param IOSpaceTiming: IO space timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
+{
+ /* Check the PCCARD controller state */
+ if(hpccard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hpccard->State == HAL_PCCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpccard->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspInit(hpccard);
+ }
+
+ /* Initialize the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize PCCARD control Interface */
+ FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
+
+ /* Init PCCARD common space timing Interface */
+ FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
+
+ /* Init PCCARD attribute space timing Interface */
+ FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
+
+ /* Init PCCARD IO space timing Interface */
+ FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
+
+ /* Enable the PCCARD device */
+ __FMC_PCCARD_ENABLE(hpccard->Instance);
+
+ /* Update the PCCARD state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Perform the PCCARD memory De-initialization sequence
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_PCCARD_MspDeInit(hpccard);
+
+ /* Configure the PCCARD registers with their reset values */
+ FMC_PCCARD_DeInit(hpccard->Instance);
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief PCCARD MSP Init
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PCCARD MSP DeInit
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### PCCARD Input Output and memory functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the PCCARD memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Read Compact Flash's ID.
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param CompactFlash_ID: Compact flash ID structure.
+ * @param pStatus: pointer to compact flash status
+ * @retval HAL status
+ *
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize the CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Send the Identify Command */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
+
+ /* Read CF IDs and timeout treatment */
+ do
+ {
+ /* Read the CF status */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+ else
+ {
+ /* Read CF ID bytes */
+ for(index = 0; index < 16; index++)
+ {
+ CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
+ }
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read sector from PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to destination read buffer
+ * @param SectorAddress: Sector address to read
+ * @param pStatus: pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
+
+ do
+ {
+ /* wait till the Status = 0x80 */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status == 0x80) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ timeout = 0xFFFF;
+
+ do
+ {
+ /* wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Read bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Write sector to PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to source write buffer
+ * @param SectorAddress: Sector address to write
+ * @param pStatus: pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Write bytes */
+ for(; index < PCCARD_SECTOR_SIZE; index++)
+ {
+ *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
+ }
+
+ do
+ {
+ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Erase sector from PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param SectorAddress: Sector address to erase
+ * @param pStatus: pointer to CF status
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
+{
+ uint32_t timeout = 0x400;
+ uint8_t status = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Update the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ /* Initialize CF status */
+ *pStatus = PCCARD_READY;
+
+ /* Set the parameters to write a sector */
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
+ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
+
+ /* wait till the CF is ready */
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status != PCCARD_STATUS_WRITE_OK) && timeout)
+ {
+ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0)
+ {
+ *pStatus = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the PCCARD memory
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Process Locked */
+ __HAL_LOCK(hpccard);
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Provide an SW reset and Read and verify the:
+ - CF Configuration Option Register at address 0x98000200 --> 0x80
+ - Card Configuration and Status Register at address 0x98000202 --> 0x00
+ - Pin Replacement Register at address 0x98000204 --> 0x0C
+ - Socket and Copy Register at address 0x98000206 --> 0x00
+ */
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_BUSY;
+
+ *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
+
+ /* Check the PCCARD controller state */
+ hpccard->State = HAL_PCCARD_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hpccard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles PCCARD device interrupt request.
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL status
+*/
+void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
+{
+ /* Check PCCARD interrupt Rising edge flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Rising edge pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE);
+ }
+
+ /* Check PCCARD interrupt Level flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Level pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_LEVEL);
+ }
+
+ /* Check PCCARD interrupt Falling edge flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt Falling edge pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE);
+ }
+
+ /* Check PCCARD interrupt FIFO empty flag */
+ if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT))
+ {
+ /* PCCARD interrupt callback*/
+ HAL_PCCARD_ITCallback(hpccard);
+
+ /* Clear PCCARD interrupt FIFO empty pending bit */
+ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT);
+ }
+
+}
+
+/**
+ * @brief PCCARD interrupt feature callback
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval None
+ */
+__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCCARD_ITCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### PCCARD Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the PCCARD controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the PCCARD controller state
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL state
+ */
+HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
+{
+ return hpccard->State;
+}
+
+/**
+ * @brief Get the compact flash memory status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval New status of the CF operation. This parameter can be:
+ * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
+ * a Timeout error
+ * - CompactFlash_READY: when memory is ready for the next operation
+ *
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ while((status_cf == PCCARD_BUSY) && timeout)
+ {
+ status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+ timeout--;
+ }
+
+ if(timeout == 0)
+ {
+ status_cf = PCCARD_TIMEOUT_ERROR;
+ }
+
+ /* Return the operation status */
+ return (HAL_PCCARD_StatusTypeDef) status_cf;
+}
+
+/**
+ * @brief Reads the Compact Flash memory status using the Read status command
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval The status of the Compact Flash memory. This parameter can be:
+ * - CompactFlash_BUSY: when memory is busy
+ * - CompactFlash_READY: when memory is ready for the next operation
+ * - CompactFlash_ERROR: when the previous operation gererates error
+ */
+HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
+{
+ uint8_t data = 0, status_cf = PCCARD_BUSY;
+
+ /* Check the PCCARD controller state */
+ if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+ {
+ return HAL_PCCARD_STATUS_ONGOING;
+ }
+
+ /* Read status operation */
+ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+ if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
+ {
+ status_cf = PCCARD_TIMEOUT_ERROR;
+ }
+ else if((data & PCCARD_READY) == PCCARD_READY)
+ {
+ status_cf = PCCARD_READY;
+ }
+
+ return (HAL_PCCARD_StatusTypeDef) status_cf;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c
@@ -0,0 +1,1306 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The PCD HAL driver can be used as follows:
+
+ (#) Declare a PCD_HandleTypeDef handle structure, for example:
+ PCD_HandleTypeDef hpcd;
+
+ (#) Fill parameters of Init structure in HCD handle
+
+ (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+
+ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+ (##) Enable the PCD/USB Low Level interface clock using
+ (+++) __HAL_RCC_USB_CLK_ENABLE();
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure PCD pin-out
+ (##) Configure PCD NVIC interrupt
+
+ (#)Associate the Upper USB device stack to the HAL PCD Driver:
+ (##) hpcd.pData = pdev;
+
+ (#)Enable HCD transmission and reception:
+ (##) HAL_PCD_Start();
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCD PCD
+ * @brief PCD HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup PCD_Private_Define PCD Private Define
+ * @{
+ */
+#define BTABLE_ADDRESS (0x000)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the PCD according to the specified
+ * parameters in the PCD_InitTypeDef and create the associated handle.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t i = 0;
+
+ uint32_t wInterrupt_Mask = 0;
+
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+ if(hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Init endpoints structures */
+ for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1;
+ hpcd->IN_ep[i].num = i;
+ /* Control until ep is actvated */
+ hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0;
+ hpcd->IN_ep[i].xfer_buff = 0;
+ hpcd->IN_ep[i].xfer_len = 0;
+ }
+
+ for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+ {
+ hpcd->OUT_ep[i].is_in = 0;
+ hpcd->OUT_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0;
+ hpcd->OUT_ep[i].xfer_buff = 0;
+ hpcd->OUT_ep[i].xfer_len = 0;
+ }
+
+ /* Init Device */
+ /*CNTR_FRES = 1*/
+ hpcd->Instance->CNTR = USB_CNTR_FRES;
+
+ /*CNTR_FRES = 0*/
+ hpcd->Instance->CNTR = 0;
+
+ /*Clear pending interrupts*/
+ hpcd->Instance->ISTR = 0;
+
+ /*Set Btable Adress*/
+ hpcd->Instance->BTABLE = BTABLE_ADDRESS;
+
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+ | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+
+ /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+
+ hpcd->USB_Address = 0;
+ hpcd->State= HAL_PCD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the PCD peripheral
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* Check the PCD handle allocation */
+ if(hpcd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
+ /* Stop Device */
+ HAL_PCD_Stop(hpcd);
+
+ /* DeInit the low level hardware */
+ HAL_PCD_MspDeInit(hpcd);
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the PCD MSP.
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes PCD MSP.
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the USB device.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+ /* DP Pull-Down is external */
+ HAL_PCDEx_SetConnectionState (hpcd, 1);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the USB device.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* disable all interrupts and force USB reset */
+ hpcd->Instance->CNTR = USB_CNTR_FRES;
+
+ /* clear interrupt status register */
+ hpcd->Instance->ISTR = 0;
+
+ /* switch-off device */
+ hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Private_Functions PCD Private Functions
+ * @{
+ */
+/**
+ * @brief This function handles PCD Endpoint interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
+{
+ PCD_EPTypeDef *ep;
+ uint16_t count=0;
+ uint8_t EPindex;
+ __IO uint16_t wIstr;
+ __IO uint16_t wEPVal = 0;
+
+ /* stay in loop while pending interrupts */
+ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+ if (EPindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+
+ /* DIR bit = origin of the interrupt */
+ if ((wIstr & USB_ISTR_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ ep = &hpcd->IN_ep[0];
+
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff += ep->xfer_count;
+
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, 0);
+
+
+ if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
+ {
+ hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+ hpcd->USB_Address = 0;
+ }
+
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+ ep = &hpcd->OUT_ep[0];
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if ((wEPVal & USB_EP_SETUP) != 0)
+ {
+ /* Get SETUP Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
+ /* SETUP bit kept frozen while CTR_RX = 1*/
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+ /* Process SETUP Packet*/
+ HAL_PCD_SetupStageCallback(hpcd);
+ }
+
+ else if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ /* Get Control Data OUT Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ ep->xfer_buff+=ep->xfer_count;
+ }
+
+ /* Process Control Data OUT Packet*/
+ HAL_PCD_DataOutStageCallback(hpcd, 0);
+
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
+ }
+ }
+ else
+ {
+
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
+ if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ /* clear int flag */
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
+ ep = &hpcd->OUT_ep[EPindex];
+
+ /* OUT double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
+ }
+ /*multi-packet on the NON control OUT endpoint*/
+ ep->xfer_count+=count;
+ ep->xfer_buff+=count;
+
+ if ((ep->xfer_len == 0) || (count < ep->maxpacket))
+ {
+ /* RX COMPLETE */
+ HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+
+ } /* if((wEPVal & EP_CTR_RX) */
+
+ if ((wEPVal & USB_EP_CTR_TX) != 0)
+ {
+ ep = &hpcd->IN_ep[EPindex];
+
+ /* clear int flag */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
+
+ /* IN double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
+ }
+ /*multi-packet on the NON control IN endpoint*/
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff+=ep->xfer_count;
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0)
+ {
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @addtogroup PCD_Exported_Functions
+ * @{
+ */
+
+/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/**
+ * @brief This function handles PCD interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+ uint32_t wInterrupt_Mask = 0;
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
+ {
+ /* servicing of the endpoint correct transfer interrupt */
+ /* clear of the CTR flag into the sub */
+ PCD_EP_ISR_Handler(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+ HAL_PCD_ResetCallback(hpcd);
+ HAL_PCD_SetAddress(hpcd, 0);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+ }
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
+ {
+ hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE);
+
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+ | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+
+ /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+
+ HAL_PCD_ResumeCallback(hpcd);
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
+ {
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
+ /* Force low-power mode in the macrocell */
+ hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+ hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
+ {
+ HAL_PCD_SuspendCallback(hpcd);
+ }
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+ HAL_PCD_SOFCallback(hpcd);
+ }
+
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
+ {
+ /* clear ESOF flag in ISTR */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+ }
+}
+
+/**
+ * @brief Data out stage callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataOutStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Data IN stage callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DataInStageCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Setup stage callback
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SetupStageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Start Of Frame callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SOFCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USB Reset callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResetCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Suspend event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_SuspendCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Resume event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ResumeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO OUT callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Incomplete ISO IN callbacks
+ * @param hpcd: PCD handle
+ * @param epnum: endpoint number
+ * @retval None
+ */
+ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Connection event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_ConnectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Disconnection event callbacks
+ * @param hpcd: PCD handle
+ * @retval None
+ */
+ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCD_DisconnectCallback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the PCD data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Connect the USB device
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
+ HAL_PCDEx_SetConnectionState(hpcd, 1);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Disconnect the USB device
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+ __HAL_LOCK(hpcd);
+
+ /* Disable DP Pull-Down bit*/
+ HAL_PCDEx_SetConnectionState(hpcd, 0);
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the USB Device address
+ * @param hpcd: PCD handle
+ * @param address: new device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+ __HAL_LOCK(hpcd);
+
+ if(address == 0)
+ {
+ /* set device address and enable function */
+ hpcd->Instance->DADDR = USB_DADDR_EF;
+ }
+ else /* USB Address will be applied later */
+ {
+ hpcd->USB_Address = address;
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+/**
+ * @brief Open and configure an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param ep_mps: endpoint max packet size
+ * @param ep_type: endpoint type
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+ ep->maxpacket = ep_mps;
+ ep->type = ep_type;
+
+ __HAL_LOCK(hpcd);
+
+ /* initialize Endpoint */
+ switch (ep->type)
+ {
+ case PCD_EP_TYPE_CTRL:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
+ break;
+ case PCD_EP_TYPE_BULK:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
+ break;
+ case PCD_EP_TYPE_INTR:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
+ break;
+ case PCD_EP_TYPE_ISOC:
+ PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
+ break;
+ }
+
+ PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
+
+ if (ep->doublebuffer == 0)
+ {
+ if (ep->is_in)
+ {
+ /*Set the endpoint Transmit buffer address */
+ PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ /* Configure NAK status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /*Set the endpoint Receive buffer address */
+ PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
+ /*Set the endpoint Receive buffer counter*/
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure VALID status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ /*Set the endpoint as double buffered*/
+ PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
+ /*Set buffer address for double buffered mode*/
+ PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
+
+ if (ep->is_in==0)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(hpcd->Instance, ep->num);
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ }
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return ret;
+}
+
+
+/**
+ * @brief Deactivate an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if ((ep_addr & 0x80) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ }
+ ep->num = ep_addr & 0x7F;
+
+ ep->is_in = (0x80 & ep_addr) != 0;
+
+ __HAL_LOCK(hpcd);
+
+ if (ep->doublebuffer == 0)
+ {
+ if (ep->is_in)
+ {
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ if (ep->is_in==0)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(hpcd->Instance, ep->num);
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_RX_DTOG(hpcd->Instance, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ }
+ }
+
+ __HAL_UNLOCK(hpcd);
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param pBuf: pointer to the reception buffer
+ * @param len: amount of data to be received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0;
+ ep->is_in = 0;
+ ep->num = ep_addr & 0x7F;
+
+ __HAL_LOCK(hpcd);
+
+ /* Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len=ep->maxpacket;
+ ep->xfer_len-=len;
+ }
+ else
+ {
+ len=ep->xfer_len;
+ ep->xfer_len =0;
+ }
+
+ /* configure and validate Rx endpoint */
+ if (ep->doublebuffer == 0)
+ {
+ /*Set RX buffer count*/
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
+ }
+ else
+ {
+ /*Set the Double buffer counter*/
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+ }
+
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get Received Data Size
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval Data Size
+ */
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+}
+/**
+ * @brief Send an amount of data
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param pBuf: pointer to the transmission buffer
+ * @param len: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+ PCD_EPTypeDef *ep;
+ uint16_t pmabuffer = 0;
+
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+
+ /*setup and start the Xfer */
+ ep->xfer_buff = pBuf;
+ ep->xfer_len = len;
+ ep->xfer_count = 0;
+ ep->is_in = 1;
+ ep->num = ep_addr & 0x7F;
+
+ __HAL_LOCK(hpcd);
+
+ /*Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len=ep->maxpacket;
+ ep->xfer_len-=len;
+ }
+ else
+ {
+ len=ep->xfer_len;
+ ep->xfer_len =0;
+ }
+
+ /* configure and validate Tx endpoint */
+ if (ep->doublebuffer == 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
+ PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
+ }
+ else
+ {
+ /*Write the data to the USB endpoint*/
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
+ {
+ pmabuffer = ep->pmaaddr1;
+ }
+ else
+ {
+ pmabuffer = ep->pmaaddr0;
+ }
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
+ }
+
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set a STALL condition over an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ __HAL_LOCK(hpcd);
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 1;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+ if (ep->num == 0)
+ {
+ /* This macro sets STALL status for RX & TX*/
+ PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL);
+ }
+ else
+ {
+ if (ep->is_in)
+ {
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL);
+ }
+ else
+ {
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
+ }
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear a STALL condition over in an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ PCD_EPTypeDef *ep;
+
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ ep->is_stall = 0;
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+ __HAL_LOCK(hpcd);
+
+ if (ep->is_in)
+ {
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ }
+ __HAL_UNLOCK(hpcd);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Flush an endpoint
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ hpcd->Instance->CNTR |= USB_CNTR_RESUME;
+ return HAL_OK;
+}
+
+/**
+ * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
+ * @param hpcd: PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+ hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME);
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD state
+ * @param hpcd : PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+ return hpcd->State;
+}
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c
@@ -0,0 +1,303 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pcd_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended PCD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Configuration of the PMA for EP
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update PMA configuration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure PMA for EP
+ * @param hpcd: PCD handle
+ * @param ep_addr: endpoint address
+ * @param ep_kind: endpoint Kind
+ * @arg USB_SNG_BUF: Single Buffer used
+ * @arg USB_DBL_BUF: Double Buffer used
+ * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
+ * this parameter is 16-bit value providing the address
+ * in PMA allocated to endpoint.
+ * In case of double buffer endpoint this parameter
+ * is a 32-bit value providing the endpoint buffer 0 address
+ * in the LSB part of 32-bit value and endpoint buffer 1 address
+ * in the MSB part of 32-bit value.
+ * @retval : status
+ */
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress)
+
+{
+ PCD_EPTypeDef *ep;
+
+ /* initialize ep structure*/
+ if ((0x80 & ep_addr) == 0x80)
+ {
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ }
+ else
+ {
+ ep = &hpcd->OUT_ep[ep_addr];
+ }
+
+ /* Here we check if the endpoint is single or double Buffer*/
+ if (ep_kind == PCD_SNG_BUF)
+ {
+ /*Single Buffer*/
+ ep->doublebuffer = 0;
+ /*Configure the PMA*/
+ ep->pmaadress = (uint16_t)pmaadress;
+ }
+ else /*USB_DBL_BUF*/
+ {
+ /*Double Buffer Endpoint*/
+ ep->doublebuffer = 1;
+ /*Configure the PMA*/
+ ep->pmaaddr0 = pmaadress & 0xFFFF;
+ ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
+ }
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PCDEx_Private_Functions PCD Extended Private Functions
+ * @{
+ */
+#if defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || \
+ defined(STM32F373xC) || defined(STM32F378xx) || \
+ defined(STM32F302xC)
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+ uint32_t i, temp1, temp2;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t) * pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pdwVal++;
+ pbUsrBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;/* /2*/
+ uint32_t i;
+ uint32_t *pdwVal;
+ pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ }
+}
+#endif /* STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302x8)
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t i;
+ uint16_t temp1, temp2;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t) * pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pbUsrBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t i;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ }
+}
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || */
+ /* STM32F302x8 */
+
+/**
+ * @}
+ */
+
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup PCDEx_Exported_Functions_Group2 Extended Initialization and de-initialization functions
+ * @{
+ */
+/**
+ * @brief Software Device Connection
+ * @param hpcd: PCD handle
+ * @param state: Device state
+ * @retval None
+ */
+ __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCDEx_SetConnectionState could be implenetd in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
@@ -0,0 +1,483 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted
+ write accesses.
+ To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @retval None
+ */
+void HAL_PWR_DeInit(void)
+{
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+ * @brief Enables access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ * @note If the HSE divided by 32 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Disables access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ * @note If the HSE divided by 32 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ *** WakeUp pin configuration ***
+ ================================
+ [..]
+ (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
+ forced in input pull down configuration and is active on rising edges.
+ (+) There are up to three WakeUp pins:
+ (++)WakeUp Pin 1 on PA.00.
+ (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
+ (++)WakeUp Pin 3 on PE.06.
+
+ *** Main and Backup Regulators configuration ***
+ ================================================
+ [..]
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to
+ save battery life.
+
+ (+) The backup SRAM is not mass erased by a tamper event. It is read
+ protected to prevent confidential data, such as cryptographic private
+ key, from being accessed. The backup SRAM can be erased only through
+ the Flash interface when a protection level change from level 1 to
+ level 0 is requested.
+ -@- Refer to the description of Read protection (RDP) in the Flash
+ programming manual.
+
+ Refer to the datasheets for more details.
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ The devices feature 3 low-power modes:
+ (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+ (+) Stop mode: all clocks are stopped, regulator running, regulator
+ in low power mode
+ (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (+) Entry:
+ The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
+ functions with
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+ (+) Exit:
+ (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+ controller (NVIC) can wake up the device from Sleep mode.
+
+ *** Stop mode ***
+ =================
+ [..]
+ In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
+ and the HSE RC oscillators are disabled. Internal SRAM and register contents
+ are preserved.
+ The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.
+
+ (+) Entry:
+ The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
+ function with:
+ (++) Main regulator ON or
+ (++) Low Power regulator ON.
+ (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
+ (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
+ (+) Exit:
+ (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+ (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
+ when programmed in wakeup mode (the peripheral must be
+ programmed in wakeup mode and the corresponding interrupt vector
+ must be enabled in the NVIC).
+
+ *** Standby mode ***
+ ====================
+ [..]
+ The Standby mode allows to achieve the lowest power consumption. It is based
+ on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
+ The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
+ the HSE oscillator are also switched off. SRAM and register contents are lost
+ except for the RTC registers, RTC backup registers, backup SRAM and Standby
+ circuitry.
+ The voltage regulator is OFF.
+
+ (+) Entry:
+ (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+ (+) Exit:
+ (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+ tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+ *** Auto-wakeup (AWU) from low-power mode ***
+ =============================================
+ [..]
+ The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+ Wakeup event, a tamper event, a time-stamp event, or a comparator event,
+ without depending on an external interrupt (Auto-wakeup mode).
+
+ (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
+
+ (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+ configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+ (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+ is necessary to configure the RTC to detect the tamper or time stamp event using the
+ HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
+
+ (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+ configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
+
+ (+) Comparator auto-wakeup (AWU) from the Stop mode
+
+ (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
+ (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
+ to be sensitive to to the selected edges (falling, rising or falling
+ and rising) (Interrupt or Event modes) using the EXTI_Init() function.
+ (+++) Configure the comparator to generate the event.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ tmp = CSR_EWUP1_BB + (WakeUpPinx << 2);
+ *(__IO uint32_t *) (tmp) = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ tmp = CSR_EWUP1_BB + (WakeUpPinx << 2);
+ *(__IO uint32_t *) (tmp) = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Enters Sleep mode.
+ * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+ * @param Regulator: Specifies the regulator state in SLEEP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+ * @note This parameter has no effect in F3 family and is just maintained to
+ * offer full portability of other STM32 families softwares.
+ * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
+ * When WFI entry is used, tick interrupt have to be disabled if not desired as
+ * the interrupt wake up source.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
+ * the HSI RC oscillator is selected as system clock.
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ * @param Regulator: Specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
+ * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
+
+ /* Set LPDS bit according to Regulator value */
+ tmpreg |= Regulator;
+
+ /* Store the new value */
+ PWR->CR = tmpreg;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(STOPEntry == PWR_STOPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @note In Standby mode, all I/O pins are high impedance except for:
+ * - Reset pad (still available),
+ * - RTC alternate function pins if configured for tamper, time-stamp, RTC
+ * Alarm out, or RTC clock calibration out,
+ * - WKUP pins if enabled.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+ /* Select STANDBY mode */
+ PWR->CR |= PWR_CR_PDDS;
+
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters SLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+
+/**
+ * @brief Enables CORTEX M4 SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+ * @brief Disables CORTEX M4 SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
@@ -0,0 +1,290 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Extended Initialization and de-initialization functions
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWREx PWREx
+ * @brief PWREx HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWR Extended Private Constants
+ * @{
+ */
+#define PVD_MODE_IT ((uint32_t)0x00010000)
+#define PVD_MODE_EVT ((uint32_t)0x00020000)
+#define PVD_RISING_EDGE ((uint32_t)0x00000001)
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Extended control functions #####
+ ===============================================================================
+ *** PVD configuration (present on all other devices than STM32F3x8 devices) ***
+ =========================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
+ (+) The PVD is stopped in Standby mode.
+ -@- PVD is not available on STM32F3x8 Product Line
+
+
+ *** Voltage regulator ***
+ =========================
+ [..]
+ (+) The voltage regulator is always enabled after Reset. It works in three different
+ modes.
+ In Run mode, the regulator supplies full power to the 1.8V domain (core, memories
+ and digital peripherals).
+ In Stop mode, the regulator supplies low power to the 1.8V domain, preserving
+ contents of registers and SRAM.
+ In Stop mode, the regulator is powered off. The contents of the registers and SRAM
+ are lost except for the Standby circuitry and the Backup Domain.
+ Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the
+ microcontroller must be powered from a nominal VDD = 1.8V +/-8% voltage.
+
+
+ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
+ than the PVD threshold. This event is internally connected to the EXTI
+ line16 and can generate an interrupt if enabled. This is done through
+ __HAL_PWR_PVD_EXTI_ENABLE_IT() macro
+ (+) The PVD is stopped in Standby mode.
+
+
+ *** SDADC power configuration ***
+ ================================
+ [..]
+ (+) On STM32F373xC/STM32F378xx devices, there are up to
+ 3 SDADC instances that can be enabled/disabled.
+
+@endverbatim
+ * @{
+ */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * information for the PVD.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage threshold corresponding to each
+ * detection level.
+ * @retval None
+ */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+ /* Set PLS[7:5] bits according to PVDLevel value */
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+
+ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+ __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+ __HAL_PWR_PVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure interrupt mode */
+ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure event mode */
+ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+ }
+
+ /* Configure the edge */
+ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ {
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+}
+
+/**
+ * @brief Enables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Disables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief This function handles the PWR PVD interrupt request.
+ * @note This API should be called under the PVD_IRQHandler().
+ * @retval None
+ */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+ /* Check PWR exti flag */
+ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+
+ /* Clear PWR Exti pending bit */
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+ }
+}
+
+/**
+ * @brief PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWR_PVDCallback could be implemented in the user file
+ */
+}
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F303x8 || STM32F334x8 || */
+ /* STM32F301x8 || STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+/**
+ * @brief Enables the SDADC peripheral functionaliy
+ * @param Analogx: specifies the SDADC peripheral instance.
+ * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
+ * @retval None
+ */
+void HAL_PWREx_EnableSDADC(uint32_t Analogx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SDADC_ANALOG(Analogx));
+
+ /* Enable PWR clock interface for SDADC use */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ PWR->CR |= Analogx;
+}
+
+/**
+ * @brief Disables the SDADC peripheral functionaliy
+ * @param Analogx: specifies the SDADC peripheral instance.
+ * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
+ * @retval None
+ */
+void HAL_PWREx_DisableSDADC(uint32_t Analogx)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_SDADC_ANALOG(Analogx));
+
+ PWR->CR &= ~Analogx;
+}
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
@@ -0,0 +1,1242 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
+ and all peripherals are off except internal SRAM, Flash and JTAG.
+ (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+ all peripherals mapped on these busses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+ (+) All GPIOs are in input floating state, except the JTAG pins which
+ are assigned to be used for debug purpose.
+ [..] Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the System clock
+ (if the application needs higher frequency/performance)
+ (+) Configure the System clock frequency and Flash settings
+ (+) Configure the AHB and APB busses prescalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock source(s) for peripherals whose clocks are not
+ derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
+
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+* @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT GPIOA
+#define MCO1_PIN GPIO_PIN_8
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+ * @{
+ */
+const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 16};
+const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
+ 9,10, 11, 12, 13, 14, 15, 16};
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal/external oscillators
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+ and APB2).
+
+ [..] Internal/external clock and PLL configuration
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+ The HSI clock can be used also to clock the USART and I2C peripherals.
+
+ (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL (clocked by HSI or HSE), featuring different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 72 MHz)
+ (++) The second output is used to generate the clock for the USB FS (48 MHz)
+ (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
+ (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
+
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ clock source), the System clocks automatically switched to HSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
+ (Non-Maskable Interrupt) exception vector.
+
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
+ clock (divided by 2) output on pin (such as PA8 pin).
+
+ [..] System, AHB and APB buses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these buses. You can use
+ "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+ (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ (++) The FLASH program/erase clock which is always HSI 8MHz clock.
+ (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
+ (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
+ (++) The I2C clock which can be derived as well from HSI 8MHz clock.
+ (++) The ADC clock which is derived from PLL output.
+ (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
+ (HSE divided by a programmable prescaler). The System clock (SYSCLK)
+ frequency must be higher or equal to the RTC clock frequency.
+ (++) IWDG clock which is always the LSI clock.
+
+ (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ +-----------------------------------------------+
+ | Latency | SYSCLK clock frequency (MHz) |
+ |---------------|-------------------------------|
+ |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ |---------------|-------------------------------|
+ |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ |---------------|-------------------------------|
+ |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ +-----------------------------------------------+
+
+ (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
+ prefetch is disabled.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS and MCO1 OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval None
+ */
+void HAL_RCC_DeInit(void)
+{
+ /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
+ SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
+
+ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
+ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
+
+ /* Reset HSEON, CSSON, PLLON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
+
+ /* Reset HSEBYP bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+ /* Reset CFGR register */
+ CLEAR_REG(RCC->CFGR);
+
+ /* Reset CFGR2 register */
+ CLEAR_REG(RCC->CFGR2);
+
+ /* Reset CFGR3 register */
+ CLEAR_REG(RCC->CFGR3);
+
+ /* Disable all interrupts */
+ CLEAR_REG(RCC->CIR);
+}
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ /* Configure the HSE predivision factor --------------------------------*/
+ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
+#endif
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ /* Configure the main PLL clock source, predivider and multiplication factor. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PREDIV,
+ RCC_OscInitStruct->PLL.PLLMUL);
+#else
+ /* Configure the main PLL clock source and multiplication factor. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLMUL);
+#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ * @param FLatency FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) of the device. */
+
+ /* Increasing the CPU frequency */
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /* Decreasing the CPU frequency */
+ else
+ {
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration -------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ }
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+
+ @endverbatim
+ * @{
+ */
+
+#if defined(RCC_CFGR_MCOPRE)
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @note MCO pin should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param RCC_MCODiv specifies the MCO DIV.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
+ * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
+ * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
+ * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
+ * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock
+ * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock
+ * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
+ * @retval None
+ */
+#else
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @note MCO pin should be configured in alternate function mode.
+ * @param RCC_MCOx specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8).
+ * @param RCC_MCOSource specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
+ * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
+ * @param RCC_MCODiv specifies the MCO DIV.
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
+ * @retval None
+ */
+#endif
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ GPIO_InitTypeDef gpio = {0};
+
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+ /* MCO Clock Enable */
+ MCO1_CLK_ENABLE();
+
+ /* Configure the MCO1 pin in alternate function mode */
+ gpio.Pin = MCO1_PIN;
+ gpio.Mode = GPIO_MODE_AF_PP;
+ gpio.Speed = GPIO_SPEED_FREQ_HIGH;
+ gpio.Pull = GPIO_NOPULL;
+ gpio.Alternate = GPIO_AF0_MCO;
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
+
+ /* Configure the MCO clock source */
+ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
+}
+
+/**
+ * @brief Enables the Clock Security System.
+ * @note If a failure is detected on the HSE oscillator clock, this oscillator
+ * is automatically disabled and an interrupt is generated to inform the
+ * software about the failure (Clock Security System Interrupt, CSSI),
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * @retval None
+ */
+void HAL_RCC_EnableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Disables the Clock Security System.
+ * @retval None
+ */
+void HAL_RCC_DisableCSS(void)
+{
+ *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+ * @brief Returns the SYSCLK frequency
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+ * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**)
+ * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
+ * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
+ * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * @note The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @note This function can be used by the user application to compute the
+ * baudrate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time SYSCLK changes, this function must be called to update the
+ * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @retval SYSCLK frequency
+ */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
+ uint32_t sysclockfreq = 0;
+
+ tmpreg = RCC->CFGR;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmpreg & RCC_CFGR_SWS)
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE / prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (HSI_VALUE >> 1) * pllmul;
+ }
+#else
+ if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE / prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
+ pllclk = (HSI_VALUE / prediv) * pllmul;
+ }
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ sysclockfreq = pllclk;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
+}
+
+/**
+ * @brief Returns the HCLK frequency
+ * @note Each time HCLK changes, this function must be called to update the
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and updated within this function
+ * @retval HCLK frequency
+ */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+ return SystemCoreClock;
+}
+
+/**
+ * @brief Returns the PCLK1 frequency
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+}
+
+/**
+ * @brief Returns the PCLK2 frequency
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
+#endif
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+ /* Get the PLL configuration -----------------------------------------------*/
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
+#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+ * contains the current clock configuration.
+ * @param pFLatency Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(pFLatency != NULL);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
+ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+ * @brief This function handles the RCC CSS interrupt request.
+ * @note This API should be called under the NMI_Handler().
+ * @retval None
+ */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ /* Check RCC CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+ {
+ /* RCC Clock Security System interrupt user callback */
+ HAL_RCC_CSSCallback();
+
+ /* Clear RCC CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ }
+}
+
+/**
+ * @brief RCC Clock Security System interrupt callback
+ * @retval none
+ */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_CSSCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
@@ -0,0 +1,1668 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extension peripheral:
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC Extension HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
+ || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
+ || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
+ || defined(RCC_CFGR3_HRTIM1SW)
+/** @defgroup RCCEx_Private_Functions RCCEx Private Functions
+ * @{
+ */
+static uint32_t RCC_GetPLLCLKFreq(void);
+
+/**
+ * @}
+ */
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the specified
+ * parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains the configuration information for the Extended Peripherals clocks
+ * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
+ * the backup registers) and RCC_BDCR register are set to their reset values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ uint32_t tickstart = 0;
+ uint32_t temp_reg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- RTC configuration -------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+ {
+ /* check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of BDCR register */
+ RCC->BDCR = temp_reg;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))
+ {
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ }
+ }
+
+ /*------------------------------- USART1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+ /* Configure the USART1 clock source */
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ }
+
+ /*----------------------------- USART2 Configuration --------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
+
+ /* Configure the USART2 clock source */
+ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
+ }
+
+ /*------------------------------ USART3 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
+
+ /* Configure the USART3 clock source */
+ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
+ }
+
+ /*------------------------------ I2C1 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
+
+ /* Configure the I2C1 clock source */
+ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
+ }
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+ /*------------------------------ USB Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
+
+ /* Configure the USB clock source */
+ __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+
+ /*------------------------------ I2C2 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
+
+ /* Configure the I2C2 clock source */
+ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ I2C3 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
+
+ /* Configure the I2C3 clock source */
+ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
+ }
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+ /*------------------------------ UART4 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
+
+ /* Configure the UART4 clock source */
+ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
+ }
+
+ /*------------------------------ UART5 Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
+
+ /* Configure the UART5 clock source */
+ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+ /*------------------------------ I2S Configuration ------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
+
+ /* Configure the I2S clock source */
+ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ ADC1 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
+
+ /* Configure the ADC1 clock source */
+ __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
+ }
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+ /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
+
+ /* Configure the ADC12 clock source */
+ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
+
+ /* Configure the ADC34 clock source */
+ __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
+ }
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+ /*------------------------------ ADC1 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
+
+ /* Configure the ADC1 clock source */
+ __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
+ }
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ TIM1 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
+
+ /* Configure the TIM1 clock source */
+ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ /*------------------------------ TIM8 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
+
+ /* Configure the TIM8 clock source */
+ __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
+ }
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ /*------------------------------ TIM15 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
+
+ /* Configure the TIM15 clock source */
+ __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
+ }
+
+ /*------------------------------ TIM16 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
+
+ /* Configure the TIM16 clock source */
+ __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
+ }
+
+ /*------------------------------ TIM17 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
+
+ /* Configure the TIM17 clock source */
+ __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
+ }
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F334x8)
+
+ /*------------------------------ HRTIM1 clock Configuration ----------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
+
+ /* Configure the HRTIM1 clock source */
+ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+ }
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+ /*------------------------------ SDADC clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
+
+ /* Configure the SDADC clock prescaler */
+ __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
+ }
+
+ /*------------------------------ CEC clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+ /*------------------------------ TIM2 clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
+ }
+
+ /*------------------------------ TIM3 clock Configuration -------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
+ }
+
+ /*------------------------------ TIM15 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
+ }
+
+ /*------------------------------ TIM16 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
+ }
+
+ /*------------------------------ TIM17 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
+ }
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+ /*------------------------------ TIM20 clock Configuration ------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
+
+ /* Configure the CEC clock source */
+ __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
+ }
+#endif /* STM32F303xE || STM32F398xx */
+
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals clocks
+ * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ /* Set all possible values for the extended clock type parameter------------*/
+ /* Common part first */
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
+
+ /* Get the RTC configuration --------------------------------------------*/
+ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+ /* Get the USART1 clock configuration --------------------------------------------*/
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+ /* Get the USART2 clock configuration -----------------------------------------*/
+ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+ /* Get the USART3 clock configuration -----------------------------------------*/
+ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+ /* Get the I2C1 clock configuration -----------------------------------------*/
+ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
+
+#if defined(STM32F302xE) || defined(STM32F303xE)\
+ || defined(STM32F302xC) || defined(STM32F303xC)\
+ || defined(STM32F302x8) \
+ || defined(STM32F373xC)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
+ /* Get the USB clock configuration -----------------------------------------*/
+ PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
+ /* Get the I2C2 clock configuration -----------------------------------------*/
+ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
+ /* Get the I2C3 clock configuration -----------------------------------------*/
+ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
+
+ PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
+ /* Get the UART4 clock configuration -----------------------------------------*/
+ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
+ /* Get the UART5 clock configuration -----------------------------------------*/
+ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
+ /* Get the I2S clock configuration -----------------------------------------*/
+ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
+ || defined(STM32F373xC) || defined(STM32F378xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
+ /* Get the ADC1 clock configuration -----------------------------------------*/
+ PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
+ /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
+ PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
+ /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
+ PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
+ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
+ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
+ /* Get the TIM1 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)\
+ || defined(STM32F303xC) || defined(STM32F358xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
+ /* Get the TIM8 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
+
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+ PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
+ /* Get the TIM15 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
+ /* Get the TIM16 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
+ /* Get the TIM17 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F334x8)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
+ /* Get the HRTIM1 clock configuration -----------------------------------------*/
+ PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
+
+#endif /* STM32F334x8 */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
+ /* Get the SDADC clock configuration -----------------------------------------*/
+ PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
+ /* Get the CEC clock configuration -----------------------------------------*/
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
+ /* Get the TIM2 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
+ /* Get the TIM3 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
+ /* Get the TIM15 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
+ /* Get the TIM16 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
+
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
+ /* Get the TIM17 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined (STM32F303xE) || defined(STM32F398xx)
+ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
+ /* Get the TIM20 clock configuration -----------------------------------------*/
+ PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
+#endif /* STM32F303xE || STM32F398xx */
+}
+
+/**
+ * @brief Returns the peripheral clock frequency
+ * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable.
+ * @param PeriphClk Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ @if STM32F301x8
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ @endif
+ @if STM32F302x8
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ @endif
+ @if STM32F302xC
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ @endif
+ @if STM32F302xE
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
+ @endif
+ @if STM32F303x8
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ @endif
+ @if STM32F303xC
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ @endif
+ @if STM32F303xE
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
+ @endif
+ @if STM32F318xx
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ @endif
+ @if STM32F328xx
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ @endif
+ @if STM32F334x8
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock
+ @endif
+ @if STM32F358xx
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ @endif
+ @if STM32F373xC
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
+ @endif
+ @if STM32F378xx
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
+ @endif
+ @if STM32F398xx
+ * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock
+ @endif
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t frequency = 0;
+ uint32_t srcclk = 0;
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+ uint16_t adc_pll_prediv_table[12] = { 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR_SDADCPRE)
+ uint8_t sdadc_prescaler_table[16] = { 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44, 48};
+#endif /* RCC_CFGR_SDADCPRE */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_RTC:
+ {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
+ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ frequency = HSE_VALUE / 32;
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_USART1:
+ {
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ /* Check if USART1 clock selection is PCLK1 */
+#if defined(RCC_USART1CLKSOURCE_PCLK2)
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
+ {
+ frequency = HAL_RCC_GetPCLK2Freq();
+ }
+#else
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+#endif /* RCC_USART1CLKSOURCE_PCLK2 */
+ /* Check if HSI is ready and if USART1 clock selection is HSI */
+ else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART1 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART1 clock selection is LSE */
+ else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_USART2:
+ {
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ /* Check if USART2 clock selection is PCLK1 */
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART2 clock selection is HSI */
+ else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART2 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART2 clock selection is LSE */
+ else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART2*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_USART3:
+ {
+ /* Get the current USART3 source */
+ srcclk = __HAL_RCC_GET_USART3_SOURCE();
+
+ /* Check if USART3 clock selection is PCLK1 */
+ if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART3 clock selection is HSI */
+ else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART3 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART3 clock selection is LSE */
+ else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART3*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#if defined(RCC_CFGR3_UART4SW)
+ case RCC_PERIPHCLK_UART4:
+ {
+ /* Get the current UART4 source */
+ srcclk = __HAL_RCC_GET_UART4_SOURCE();
+
+ /* Check if UART4 clock selection is PCLK1 */
+ if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if UART4 clock selection is HSI */
+ else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if UART4 clock selection is SYSCLK */
+ else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if UART4 clock selection is LSE */
+ else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART4*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_UART4SW */
+#if defined(RCC_CFGR3_UART5SW)
+ case RCC_PERIPHCLK_UART5:
+ {
+ /* Get the current UART5 source */
+ srcclk = __HAL_RCC_GET_UART5_SOURCE();
+
+ /* Check if UART5 clock selection is PCLK1 */
+ if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if UART5 clock selection is HSI */
+ else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if UART5 clock selection is SYSCLK */
+ else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if UART5 clock selection is LSE */
+ else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for UART5*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_UART5SW */
+ case RCC_PERIPHCLK_I2C1:
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Check if HSI is ready and if I2C1 clock selection is HSI */
+ if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C1 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#if defined(RCC_CFGR3_I2C2SW)
+ case RCC_PERIPHCLK_I2C2:
+ {
+ /* Get the current I2C2 source */
+ srcclk = __HAL_RCC_GET_I2C2_SOURCE();
+
+ /* Check if HSI is ready and if I2C2 clock selection is HSI */
+ if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C2 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C2*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_I2C2SW */
+#if defined(RCC_CFGR3_I2C3SW)
+ case RCC_PERIPHCLK_I2C3:
+ {
+ /* Get the current I2C3 source */
+ srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+ /* Check if HSI is ready and if I2C3 clock selection is HSI */
+ if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C3 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C3*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_I2C3SW */
+#if defined(RCC_CFGR_I2SSRC)
+ case RCC_PERIPHCLK_I2S:
+ {
+ /* Get the current I2S source */
+ srcclk = __HAL_RCC_GET_I2S_SOURCE();
+
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */
+ if (srcclk == RCC_I2SCLKSOURCE_EXT)
+ {
+ /* External clock used. Frequency cannot be returned.*/
+ frequency = 0xDEADDEAD;
+ }
+ /* Check if I2S clock selection is SYSCLK */
+ else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2S*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_CFGR_USBPRE)
+ case RCC_PERIPHCLK_USB:
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Get the current USB source */
+ srcclk = __HAL_RCC_GET_USB_SOURCE();
+
+ /* Check if USB clock selection is not divided */
+ if (srcclk == RCC_USBCLKSOURCE_PLL)
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if USB clock selection is divided by 1.5 */
+ else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
+ {
+ frequency = (RCC_GetPLLCLKFreq() * 3) / 2;
+ }
+ }
+ /* Clock not enabled for USB*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR_USBPRE */
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE)
+ case RCC_PERIPHCLK_ADC1:
+ {
+ /* Get the current ADC1 source */
+ srcclk = __HAL_RCC_GET_ADC1_SOURCE();
+#if defined(RCC_CFGR2_ADC1PRES)
+ /* Check if ADC1 clock selection is AHB */
+ if (srcclk == RCC_ADC1PLLCLK_OFF)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* PLL clock has been selected */
+ else
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xF];
+ }
+ /* Clock not enabled for ADC1*/
+ else
+ {
+ frequency = 0;
+ }
+ }
+#else /* RCC_CFGR_ADCPRE */
+ /* ADC1 is set to PLCK2 frequency divided by 2/4/6/8 */
+ frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1) * 2);
+#endif /* RCC_CFGR2_ADC1PRES */
+ break;
+ }
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */
+#if defined(RCC_CFGR2_ADCPRE12)
+ case RCC_PERIPHCLK_ADC12:
+ {
+ /* Get the current ADC12 source */
+ srcclk = __HAL_RCC_GET_ADC12_SOURCE();
+ /* Check if ADC12 clock selection is AHB */
+ if (srcclk == RCC_ADC12PLLCLK_OFF)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* PLL clock has been selected */
+ else
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
+ }
+ /* Clock not enabled for ADC12*/
+ else
+ {
+ frequency = 0;
+ }
+ }
+ break;
+ }
+#endif /* RCC_CFGR2_ADCPRE12 */
+#if defined(RCC_CFGR2_ADCPRE34)
+ case RCC_PERIPHCLK_ADC34:
+ {
+ /* Get the current ADC34 source */
+ srcclk = __HAL_RCC_GET_ADC34_SOURCE();
+ /* Check if ADC34 clock selection is AHB */
+ if (srcclk == RCC_ADC34PLLCLK_OFF)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* PLL clock has been selected */
+ else
+ {
+ /* Check if PLL is ready */
+ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
+ {
+ /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
+ }
+ /* Clock not enabled for ADC34*/
+ else
+ {
+ frequency = 0;
+ }
+ }
+ break;
+ }
+#endif /* RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR3_TIM1SW)
+ case RCC_PERIPHCLK_TIM1:
+ {
+ /* Get the current TIM1 source */
+ srcclk = __HAL_RCC_GET_TIM1_SOURCE();
+
+ /* Check if PLL is ready and if TIM1 clock selection is PLL */
+ if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM1 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM1CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM1SW */
+#if defined(RCC_CFGR3_TIM2SW)
+ case RCC_PERIPHCLK_TIM2:
+ {
+ /* Get the current TIM2 source */
+ srcclk = __HAL_RCC_GET_TIM2_SOURCE();
+
+ /* Check if PLL is ready and if TIM2 clock selection is PLL */
+ if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM2 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM2CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM2*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM2SW */
+#if defined(RCC_CFGR3_TIM8SW)
+ case RCC_PERIPHCLK_TIM8:
+ {
+ /* Get the current TIM8 source */
+ srcclk = __HAL_RCC_GET_TIM8_SOURCE();
+
+ /* Check if PLL is ready and if TIM8 clock selection is PLL */
+ if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM8 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM8CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM8*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM8SW */
+#if defined(RCC_CFGR3_TIM15SW)
+ case RCC_PERIPHCLK_TIM15:
+ {
+ /* Get the current TIM15 source */
+ srcclk = __HAL_RCC_GET_TIM15_SOURCE();
+
+ /* Check if PLL is ready and if TIM15 clock selection is PLL */
+ if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM15 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM15CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM15*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM15SW */
+#if defined(RCC_CFGR3_TIM16SW)
+ case RCC_PERIPHCLK_TIM16:
+ {
+ /* Get the current TIM16 source */
+ srcclk = __HAL_RCC_GET_TIM16_SOURCE();
+
+ /* Check if PLL is ready and if TIM16 clock selection is PLL */
+ if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM16 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM16CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM16*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM16SW */
+#if defined(RCC_CFGR3_TIM17SW)
+ case RCC_PERIPHCLK_TIM17:
+ {
+ /* Get the current TIM17 source */
+ srcclk = __HAL_RCC_GET_TIM17_SOURCE();
+
+ /* Check if PLL is ready and if TIM17 clock selection is PLL */
+ if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM17 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM17CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM17*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM17SW */
+#if defined(RCC_CFGR3_TIM20SW)
+ case RCC_PERIPHCLK_TIM20:
+ {
+ /* Get the current TIM20 source */
+ srcclk = __HAL_RCC_GET_TIM20_SOURCE();
+
+ /* Check if PLL is ready and if TIM20 clock selection is PLL */
+ if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM20 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM20CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM20*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM20SW */
+#if defined(RCC_CFGR3_TIM34SW)
+ case RCC_PERIPHCLK_TIM34:
+ {
+ /* Get the current TIM34 source */
+ srcclk = __HAL_RCC_GET_TIM34_SOURCE();
+
+ /* Check if PLL is ready and if TIM34 clock selection is PLL */
+ if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if TIM34 clock selection is SYSCLK */
+ else if (srcclk == RCC_TIM34CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for TIM34*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_TIM34SW */
+#if defined(RCC_CFGR3_HRTIM1SW)
+ case RCC_PERIPHCLK_HRTIM1:
+ {
+ /* Get the current HRTIM1 source */
+ srcclk = __HAL_RCC_GET_HRTIM1_SOURCE();
+
+ /* Check if PLL is ready and if HRTIM1 clock selection is PLL */
+ if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ frequency = RCC_GetPLLCLKFreq();
+ }
+ /* Check if HRTIM1 clock selection is SYSCLK */
+ else if (srcclk == RCC_HRTIM1CLK_HCLK)
+ {
+ frequency = SystemCoreClock;
+ }
+ /* Clock not enabled for HRTIM1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_HRTIM1SW */
+#if defined(RCC_CFGR_SDADCPRE)
+ case RCC_PERIPHCLK_SDADC:
+ {
+ /* Get the current SDADC source */
+ srcclk = __HAL_RCC_GET_SDADC_SOURCE();
+ /* Frequency is the system frequency divided by SDADC prescaler (2/4/6/8/10/12/14/16/20/24/28/32/36/40/44/48) */
+ frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDADCPRE)) & 0xF];
+ break;
+ }
+#endif /* RCC_CFGR_SDADCPRE */
+#if defined(RCC_CFGR3_CECSW)
+ case RCC_PERIPHCLK_CEC:
+ {
+ /* Get the current CEC source */
+ srcclk = __HAL_RCC_GET_CEC_SOURCE();
+
+ /* Check if HSI is ready and if CEC clock selection is HSI */
+ if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if LSE is ready and if CEC clock selection is LSE */
+ else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for CEC*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_CECSW */
+ default:
+ {
+ break;
+ }
+ }
+ return(frequency);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \
+ || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \
+ || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \
+ || defined(RCC_CFGR3_HRTIM1SW)
+
+/** @addtogroup RCCEx_Private_Functions
+ * @{
+ */
+static uint32_t RCC_GetPLLCLKFreq(void)
+{
+ uint32_t pllmul = 0, pllsource = 0, prediv = 0, pllclk = 0;
+
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllmul = ( pllmul >> 18) + 2;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ if (pllsource != RCC_PLLSOURCE_HSI)
+ {
+ prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE/prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (HSI_VALUE >> 1) * pllmul;
+ }
+#else
+ prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE/prediv) * pllmul;
+ }
+ else
+ {
+ /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
+ pllclk = (HSI_VALUE/prediv) * pllmul;
+ }
+#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+
+ return pllclk;
+}
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c
@@ -0,0 +1,1569 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real-Time Clock (RTC) peripheral:
+ * + Initialization
+ * + Calendar (Time and Date) configuration
+ * + Alarms (Alarm A and Alarm B) configuration
+ * + WakeUp Timer configuration
+ * + TimeStamp configuration
+ * + Tampers configuration
+ * + Backup Data Registers configuration
+ * + RTC Tamper and TimeStamp Pins Selection
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### RTC Operating Condition #####
+ ===============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC
+ when VDD is turned off, VBAT pin can be connected to an optional
+ standby voltage supplied by a battery or by another source.
+
+ [..] To allow the RTC to operate even when the main digital supply (VDD)
+ is turned off, the VBAT pin powers the following blocks:
+ (#) The RTC
+ (#) The LSE oscillator
+ (#) PC13 to PC15 I/Os (when available)
+
+ [..] When the backup domain is supplied by VDD (analog switch connected
+ to VDD), the following functions are available:
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins
+ (#) PC13 can be used as a GPIO or as the RTC_OUT pin
+
+ [..] When the backup domain is supplied by VBAT (analog switch connected
+ to VBAT because VDD is not present), the following functions are available:
+ (#) PC14 and PC15 can be used as LSE pins only
+ (#) PC13 can be used as the RTC_OUT pin
+
+ ##### Backup Domain Reset #####
+ ===============================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR
+ register to their reset values.
+ A backup domain reset is generated when one of the following events
+ occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been
+ powered off.
+
+ ##### Backup Domain Access #####
+ ===================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted write
+ accesses.
+
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (#) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() function.
+ (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
+ (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+
+
+ ##### How to use RTC Driver #####
+ ===================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the
+ HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
+
+ *** RTC Wakeup configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
+ function. You can also configure the RTC Wakeup timer with interrupt mode
+ using the HAL_RTC_SetWakeUpTimer_IT() function.
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the
+ HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
+ function.
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, precharge or discharge and Pull-UP using the
+ HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
+ mode using HAL_RTC_SetTamper_IT() function.
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
+ function.
+
+
+ ##### RTC and low power modes #####
+ ===================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+ RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+ or the RTC wakeup events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wakeup from STOP and Standby modes is possible only when the RTC clock source
+ is LSE or LSI.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @brief RTC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup RTC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
+ RTC registers synchronization check and reference clock detection enable.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ It is split into 2 programmable prescalers to minimize power consumption.
+ (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
+ (++) When both prescalers are used, it is recommended to configure the
+ asynchronous prescaler to a high value to minimize power consumption.
+ (#) All RTC registers are Write protected. Writing to the RTC registers
+ is enabled by writing a key into the Write Protection register, RTC_WPR.
+ (#) To configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
+ complete, the calendar restarts counting after 4 RTCCLK cycles.
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wakeup from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ implements the above software sequence (RSF clear and RSF check).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the RTC according to the specified parameters
+ * in the RTC_InitTypeDef structure and initialize the associated handle.
+ * @param hrtc: RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
+{
+ /* Check the RTC peripheral state */
+ if(hrtc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+ assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
+ assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
+ assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
+ assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+ assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+ assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
+
+ if(hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
+ /* Initialize RTC MSP */
+ HAL_RTC_MspInit(hrtc);
+ }
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief DeInitialize the RTC peripheral.
+ * @param hrtc: RTC handle
+ * @note This function doesn't reset the RTC Backup Data registers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Reset TR, DR and CR registers */
+ hrtc->Instance->TR = (uint32_t)0x00000000;
+ hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
+ /* Reset All CR bits except CR[2:0] */
+ hrtc->Instance->CR &= RTC_CR_WUCKSEL;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till WUTWF flag is set and if Time out is reached exit */
+ while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset all RTC CR register bits */
+ hrtc->Instance->CR &= (uint32_t)0x00000000;
+ hrtc->Instance->WUTR = RTC_WUTR_WUT;
+ hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
+ hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
+ hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
+ hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
+ hrtc->Instance->CALR = (uint32_t)0x00000000;
+ hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
+ hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
+
+ /* Reset ISR register and exit initialization mode */
+ hrtc->Instance->ISR = (uint32_t)0x00000000;
+
+ /* Reset Tamper and alternate functions configuration register */
+ hrtc->Instance->TAFCR = (uint32_t)0x00000000;
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the RTC MSP.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the RTC MSP.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+ * @brief RTC Time and Date functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Time and Date functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Time and Date features
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set RTC current time.
+ * @param hrtc: RTC handle
+ * @param sTime: Pointer to Time structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
+ assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sTime->Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(sTime->Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sTime->Minutes));
+ assert_param(IS_RTC_SECONDS(sTime->Seconds));
+
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+ (((uint32_t)sTime->TimeFormat) << 16));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sTime->Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
+ else
+ {
+ sTime->TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
+ }
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
+ tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
+ ((uint32_t)(sTime->Minutes) << 8) | \
+ ((uint32_t)sTime->Seconds) | \
+ ((uint32_t)(sTime->TimeFormat) << 16));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_TR register */
+ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+ /* Clear the bits to be configured */
+ hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Get RTC current time.
+ * @param hrtc: RTC handle
+ * @param sTime: Pointer to Time structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
+ * value in second fraction ratio with time unit following generic formula:
+ * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
+ * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * in the higher-order calendar shadow registers.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get subseconds structure field from the corresponding register*/
+ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
+
+ /* Get the TR register */
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+ sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the time structure parameters to Binary format */
+ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
+ sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set RTC current date.
+ * @param hrtc: RTC handle
+ * @param sDate: Pointer to date structure
+ * @param Format: specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+ {
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
+ }
+
+ assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ assert_param(IS_RTC_YEAR(sDate->Year));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+ ((uint32_t)sDate->WeekDay << 13));
+ }
+ else
+ {
+ assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
+ datetmpreg = RTC_Bcd2ToByte(sDate->Month);
+ assert_param(IS_RTC_MONTH(datetmpreg));
+ datetmpreg = RTC_Bcd2ToByte(sDate->Date);
+ assert_param(IS_RTC_DATE(datetmpreg));
+
+ datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
+ (((uint32_t)sDate->Month) << 8) | \
+ ((uint32_t)sDate->Date) | \
+ (((uint32_t)sDate->WeekDay) << 13));
+ }
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the RTC_DR register */
+ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY ;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Get RTC current date.
+ * @param hrtc: RTC handle
+ * @param sDate: Pointer to Date structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN : Binary data format
+ * @arg RTC_FORMAT_BCD : BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
+{
+ uint32_t datetmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the DR register */
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the structure fields with the read parameters */
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the date structure parameters to Binary format */
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Set the specified RTC Alarm.
+ * @param hrtc: RTC handle
+ * @param sAlarm: Pointer to Alarm structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+
+ /* Configure the Alarm A or Alarm B Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if(sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Sub Second register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the specified RTC Alarm with Interrupt.
+ * @param hrtc: RTC handle
+ * @param sAlarm: Pointer to Alarm structure
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0;
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ }
+ else
+ {
+ tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ }
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ /* Configure the Alarm A or Alarm B Sub Second registers */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if(sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A interrupt */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Sub Second register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+ }
+ else
+ {
+ /* Disable the Alarm B interrupt */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* Clear flag alarm B */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Sub Second register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
+ }
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the specified RTC Alarm.
+ * @param hrtc: RTC handle
+ * @param Alarm: Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A : AlarmA
+ * @arg RTC_ALARM_B : AlarmB
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ if(Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* AlarmB */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC Alarm value and masks.
+ * @param hrtc: RTC handle
+ * @param sAlarm: Pointer to Date structure
+ * @param Alarm: Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
+ * @param Format: Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0, subsecondtmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ if(Alarm == RTC_ALARM_A)
+ {
+ /* AlarmA */
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
+ }
+ else
+ {
+ sAlarm->Alarm = RTC_ALARM_B;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
+ }
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
+ sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
+ sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
+
+ if(Format == RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Alarm interrupt request.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
+{
+ /* Get the AlarmA interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
+ {
+ /* Get the pending status of the AlarmA Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
+ {
+ /* AlarmA callback */
+ HAL_RTC_AlarmAEventCallback(hrtc);
+
+ /* Clear the AlarmA interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+ }
+ }
+
+ /* Get the AlarmB interrupt source enable status */
+ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
+ {
+ /* Get the pending status of the AlarmB Interrupt */
+ if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
+ {
+ /* AlarmB callback */
+ HAL_RTCEx_AlarmBEventCallback(hrtc);
+
+ /* Clear the AlarmB interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
+ }
+ }
+
+ /* Clear the EXTI's line Flag for RTC Alarm */
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle AlarmA Polling request.
+ * @param hrtc: RTC handle
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc: RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Clear RSF flag */
+ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get RTC state
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Return the RTC handle state.
+ * @param hrtc: RTC handle
+ * @retval HAL state
+ */
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+{
+ /* Return RTC handle state */
+ return hrtc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @@addtogroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Enter the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @param hrtc: RTC handle
+ * @retval An ErrorStatus enumeration value:
+ * - HAL_OK : RTC is in Init mode
+ * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
+ */
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Check if the Initialization mode is set */
+ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ /* Set the Initialization mode */
+ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Convert a 2 digit decimal to BCD format.
+ * @param Value: Byte to be converted
+ * @retval Converted byte
+ */
+uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+ uint32_t bcdhigh = 0;
+
+ while(Value >= 10)
+ {
+ bcdhigh++;
+ Value -= 10;
+ }
+
+ return ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+ * @brief Convert from 2 digit BCD to Binary.
+ * @param Value: BCD value to be converted
+ * @retval Converted word
+ */
+uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+ uint32_t tmp = 0;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ return (tmp + (Value & (uint8_t)0x0F));
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c
@@ -0,0 +1,1621 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_rtc_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended RTC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Real Time Clock (RTC) Extended peripheral:
+ * + RTC Time Stamp functions
+ * + RTC Tamper functions
+ * + RTC Wake-up functions
+ * + Extended Control functions
+ * + Extended RTC features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access.
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+
+ *** RTC Wakeup configuration ***
+ ================================
+ [..]
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+ function. You can also configure the RTC Wakeup timer with interrupt mode
+ using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ function.
+
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+ (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
+ HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
+ function.
+ (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13).
+
+ *** Tamper configuration ***
+ ============================
+ [..]
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, precharge or discharge and Pull-UP using the
+ HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
+ mode using HAL_RTCEx_SetTamper_IT() function.
+ (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13).
+
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+ (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
+ function.
+ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+ function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+
+
+/** @addtogroup RTCEx
+ * @brief RTC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup RTCEx_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @brief RTC TimeStamp and Tamper functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC TimeStamp and Tamper functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure TimeStamp feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set TimeStamp.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc: RTC handle
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg|= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set TimeStamp with Interrupt.
+ * @param hrtc: RTC handle
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * activated.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * falling edge of the related pin.
+ * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ tmpreg |= TimeStampEdge;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
+
+ /* Enable IT timestamp */
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
+
+ /* RTC timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate TimeStamp.
+ * @param hrtc: RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tmpreg = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
+
+ /* Get the RTC_CR register and clear the bits to be configured */
+ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+ /* Configure the Time Stamp TSEDGE and Enable bits */
+ hrtc->Instance->CR = (uint32_t)tmpreg;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the RTC TimeStamp value.
+ * @param hrtc: RTC handle
+ * @param sTimeStamp: Pointer to Time structure
+ * @param sTimeStampDate: Pointer to Date structure
+ * @param Format: specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+{
+ uint32_t tmptime = 0, tmpdate = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+
+ /* Get the TimeStamp time and date registers values */
+ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
+ tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
+
+ /* Fill the Time structure fields with the read parameters */
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+ sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
+ sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
+
+ /* Fill the Date structure fields with the read parameters */
+ sTimeStampDate->Year = 0;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+ /* Check the input parameters format */
+ if(Format == RTC_FORMAT_BIN)
+ {
+ /* Convert the TimeStamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
+ sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
+
+ /* Convert the DateTimeStamp structure parameters to Binary format */
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
+ }
+
+ /* Clear the TIMESTAMP Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Tamper
+ * @note By calling this API we disable the tamper interrupt for all tampers.
+ * @param hrtc: RTC handle
+ * @param sTamper: Pointer to Tamper Structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set Tamper with interrupt.
+ * @note By calling this API we force the tamper interrupt for all tampers.
+ * @param hrtc: RTC handle
+ * @param sTamper: Pointer to RTC Tamper.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Configure the tamper trigger */
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ {
+ sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1);
+ }
+
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ (uint32_t)RTC_TAFCR_TAMPPUDIS);
+
+ hrtc->Instance->TAFCR |= tmpreg;
+
+ /* Configure the Tamper Interrupt in the RTC_TAFCR */
+ hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
+
+ /* RTC Tamper Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate Tamper.
+ * @param hrtc: RTC handle
+ * @param Tamper: Selected tamper pin.
+ * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
+{
+ assert_param(IS_RTC_TAMPER(Tamper));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the selected Tamper pin */
+ hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle TimeStamp interrupt request.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the TimeStamp interrupt source enable status */
+ if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
+ {
+ /* Get the pending status of the TIMESTAMP Interrupt */
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
+ {
+ /* TIMESTAMP callback */
+ HAL_RTCEx_TimeStampEventCallback(hrtc);
+
+ /* Clear the TIMESTAMP interrupt pending bit */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+ }
+ }
+
+ /* Get the Tamper interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ {
+ /* Get the pending status of the Tamper1 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
+ {
+ /* Tamper1 callback */
+ HAL_RTCEx_Tamper1EventCallback(hrtc);
+
+ /* Clear the Tamper1 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+ }
+ }
+
+ /* Get the Tamper interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ {
+ /* Get the pending status of the Tamper2 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
+ {
+ /* Tamper2 callback */
+ HAL_RTCEx_Tamper2EventCallback(hrtc);
+
+ /* Clear the Tamper2 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+ }
+ }
+
+ /* Get the Tamper interrupts source enable status */
+ if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ {
+ /* Get the pending status of the Tamper3 Interrupt */
+ if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
+ {
+ /* Tamper3 callback */
+ HAL_RTCEx_Tamper3EventCallback(hrtc);
+
+ /* Clear the Tamper3 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+ }
+ }
+
+ /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief TimeStamp callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 1 callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 2 callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tamper 3 callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle TimeStamp polling request.
+ * @param hrtc: RTC handle
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+ {
+ if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+ {
+ /* Clear the TIMESTAMP OverRun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Change TIMESTAMP state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Tamper 1 Polling.
+ * @param hrtc: RTC handle
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Tamper 2 Polling.
+ * @param hrtc: RTC handle
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle Tamper 3 Polling.
+ * @param hrtc: RTC handle
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Get the status of the Interrupt */
+ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Tamper Flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @brief RTC Wake-up functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Wake-up functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Wake-up feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set wake up timer.
+ * @param hrtc: RTC handle
+ * @param WakeUpCounter: Wake up counter
+ * @param WakeUpClock: Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear the Wakeup Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* Configure the Wakeup Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Enable the Wakeup Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set wake up timer with interrupt.
+ * @param hrtc: RTC handle
+ * @param WakeUpCounter: Wake up counter
+ * @param WakeUpClock: Wake up clock
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the Wakeup Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+
+ /* Clear the Wakeup Timer clock source bits in CR register */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+ /* Configure the clock source */
+ hrtc->Instance->CR |= (uint32_t)WakeUpClock;
+
+ /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
+ /* Configure the Interrupt in the RTC_CR register */
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
+
+ /* Enable the Wakeup Timer */
+ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate wake up timer counter.
+ * @param hrtc: RTC handle
+ * @retval HAL status
+ */
+uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Disable the Wakeup Timer */
+ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+
+ tickstart = HAL_GetTick();
+ /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get wake up timer counter.
+ * @param hrtc: RTC handle
+ * @retval Counter value
+ */
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the counter value */
+ return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+ * @brief Handle Wake Up Timer interrupt request.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Get the pending status of the WAKEUPTIMER Interrupt */
+ if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
+ {
+ /* WAKEUPTIMER callback */
+ HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
+
+ /* Clear the WAKEUPTIMER interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+ }
+
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Wake Up Timer callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handle Wake Up Timer Polling.
+ * @param hrtc: RTC handle
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the WAKEUPTIMER Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Write a data in a specified RTC Backup data register
+ (+) Read a data in a specified RTC Backup data register
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
+ (+) Disable the RTC reference clock detection.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Write a data in a specified RTC Backup data register.
+ * @param hrtc: RTC handle
+ * @param BackupRegister: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
+ * specify the register.
+ * @param Data: Data to be written in the specified RTC Backup data register.
+ * @retval None
+ */
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @param hrtc: RTC handle
+ * @param BackupRegister: RTC Backup data Register number.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
+ * specify the register.
+ * @retval Read value
+ */
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_BKP(BackupRegister));
+
+ tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp += (BackupRegister * 4);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @brief Set the Smooth calibration parameters.
+ * @param hrtc: RTC handle
+ * @param SmoothCalibPeriod: Select the Smooth Calibration Period.
+ * This parameter can be can be one of the following values :
+ * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
+ * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
+ * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+ * This parameter can be one of the following values:
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
+ * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
+ * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+ * This parameter can be one any value from 0 to 0x000001FF.
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+ * SmoothCalibMinusPulsesValue mut be equal to 0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
+ assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* check if a calibration is pending*/
+ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ tickstart = HAL_GetTick();
+
+ /* check if a calibration is pending*/
+ while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure the Smooth calibration settings */
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Synchronization Shift Control Settings.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @param hrtc: RTC handle
+ * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
+ * This parameter can be one of the following values :
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+ * @arg RTC_SHIFTADD1S_RESET: No effect.
+ * @param ShiftSubFS: Select the number of Second Fractions to substitute.
+ * This parameter can be one any value from 0 to 0x7FFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
+ assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait until the shift is completed*/
+ while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+ {
+ if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the reference clock detection is disabled */
+ if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+ {
+ /* Configure the Shift settings */
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc: RTC handle
+ * @param CalibOutput: Select the Calibration output Selection .
+ * This parameter can be one of the following values:
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Clear flags before config */
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
+
+ /* Configure the RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)CalibOutput;
+
+ __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc: RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the RTC reference clock detection.
+ * @param hrtc: RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the RTC reference clock detection.
+ * @param hrtc: RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set Initialization mode */
+ if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state*/
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the Bypass Shadow feature.
+ * @param hrtc: RTC handle
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set the BYPSHAD bit */
+ hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Bypass Shadow feature.
+ * @param hrtc: RTC handle
+ * @note When the Bypass Shadow is enabled the calendar value are taken
+ * directly from the Calendar counter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
+{
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Reset the BYPSHAD bit */
+ hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RTCEx_Exported_Functions_Group4 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) RTC Alram B callback
+ (+) RTC Poll for Alarm B request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Alarm B callback.
+ * @param hrtc: RTC handle
+ * @retval None
+ */
+__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function handles AlarmB Polling request.
+ * @param hrtc: RTC handle
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm Flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c
@@ -0,0 +1,2663 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sdadc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Sigma-Delta Analog to Digital Converter
+ * (SDADC) peripherals:
+ * + Initialization and Configuration
+ * + Regular Channels Configuration
+ * + Injected channels Configuration
+ * + Power saving
+ * + Regular/Injected Channels DMA Configuration
+ * + Interrupts and flags management
+ @verbatim
+ ==============================================================================
+ ##### SDADC specific features #####
+ ==============================================================================
+ [..]
+ (#) 16-bit sigma delta architecture.
+ (#) Self calibration.
+ (#) Interrupt generation at the end of calibration, regular/injected conversion
+ and in case of overrun events.
+ (#) Single and continuous conversion modes.
+ (#) External trigger option with configurable polarity for injected conversion.
+ (#) Multi mode (synchronized another SDADC with SDADC1).
+ (#) DMA request generation during regular or injected channel conversion.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ *** Initialization ***
+ ======================
+ [..]
+ (#) As prerequisite, fill in the HAL_SDADC_MspInit() :
+ (++) Enable SDADCx clock interface with __SDADCx_CLK_ENABLE().
+ (++) Configure SDADCx clock divider with HAL_RCCEx_PeriphCLKConfig.
+ (++) Enable power on SDADC with HAL_PWREx_EnableSDADC().
+ (++) Enable the clocks for the SDADC GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (++) Configure these SDADC pins in analog mode using HAL_GPIO_Init().
+ (++) If interrupt mode is used, enable and configure SDADC global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (++) If DMA mode is used, configure DMA with HAL_DMA_Init and link it
+ with SDADC handle using __HAL_LINKDMA.
+ (#) Configure the SDADC low power mode, fast conversion mode, slow clock
+ mode and SDADC1 reference voltage using the HAL_ADC_Init() function.
+ Note: Common reference voltage. is common to all SDADC instances.
+ (#) Prepare channel configurations (input mode, common mode, gain and
+ offset) using HAL_SDADC_PrepareChannelConfig and associate channel
+ with one configuration using HAL_SDADC_AssociateChannelConfig.
+
+ *** Calibration ***
+ ============================================
+ [..]
+ (#) Start calibration using HAL_SDADC_StartCalibration or
+ HAL_SDADC_CalibrationStart_IT.
+ (#) In polling mode, use HAL_SDADC_PollForCalibEvent to detect the end of
+ calibration.
+ (#) In interrupt mode, HAL_SDADC_CalibrationCpltCallback will be called at
+ the end of calibration.
+
+ *** Regular channel conversion ***
+ ============================================
+ [..]
+ (#) Select trigger for regular conversion using
+ HAL_SDADC_SelectRegularTrigger.
+ (#) Select regular channel and enable/disable continuous mode using
+ HAL_SDADC_ConfigChannel.
+ (#) Start regular conversion using HAL_SDADC_Start, HAL_SDADC_Start_IT
+ or HAL_SDADC_Start_DMA.
+ (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
+ regular conversion.
+ (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
+ end of regular conversion.
+ (#) Get value of regular conversion using HAL_SDADC_GetValue.
+ (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+ HAL_SDADC_ConvCpltCallback will be called respectively at the half
+ transfer and at the transfer complete.
+ (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
+ or HAL_SDADC_Stop_DMA.
+
+ *** Injected channels conversion ***
+ ============================================
+ [..]
+ (#) Enable/disable delay on injected conversion using
+ HAL_SDADC_SelectInjectedDelay.
+ (#) If external trigger is used for injected conversion, configure this
+ trigger using HAL_SDADC_SelectInjectedExtTrigger.
+ (#) Select trigger for injected conversion using
+ HAL_SDADC_SelectInjectedTrigger.
+ (#) Select injected channels and enable/disable continuous mode using
+ HAL_SDADC_InjectedConfigChannel.
+ (#) Start injected conversion using HAL_SDADC_InjectedStart,
+ HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedStart_DMA.
+ (#) In polling mode, use HAL_SDADC_PollForInjectedConversion to detect the
+ end of injected conversion.
+ (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
+ at the end of injected conversion.
+ (#) Get value of injected conversion and corresponding channel using
+ HAL_SDADC_InjectedGetValue.
+ (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
+ HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
+ half transfer and at the transfer complete.
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop,
+ HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
+
+ *** Multi mode regular channels conversions ***
+ ======================================================
+ [..]
+ (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
+ HAL_SDADC_MultiModeConfigChannel.
+ (#) Select software trigger for SDADC1 and synchronized trigger for
+ SDADC2 (or SDADC3) using HAL_SDADC_SelectRegularTrigger.
+ (#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
+ HAL_SDADC_ConfigChannel.
+ (#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
+ (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
+ HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
+ (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
+ regular conversion for SDADC1.
+ (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
+ end of regular conversion for SDADC1.
+ (#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
+ (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+ HAL_SDADC_ConvCpltCallback will be called respectively at the half
+ transfer and at the transfer complete for SDADC1.
+ (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
+ or HAL_SDADC_MultiModeStop_DMA for SDADC1.
+ (#) Stop regular conversion using HAL_SDADC_Stop for SDADC2 (or SDADC3).
+
+ *** Multi mode injected channels conversions ***
+ ======================================================
+ [..]
+ (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
+ HAL_SDADC_InjectedMultiModeConfigChannel.
+ (#) Select software or external trigger for SDADC1 and synchronized
+ trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
+ (#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
+ HAL_SDADC_InjectedConfigChannel.
+ (#) Start injected conversion for SDADC2 (or SDADC3) with
+ HAL_SDADC_InjectedStart.
+ (#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
+ HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
+ (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
+ the end of injected conversion for SDADC1.
+ (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
+ at the end of injected conversion for SDADC1.
+ (#) Get value of injected conversions using
+ HAL_SDADC_InjectedMultiModeGetValue.
+ (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
+ HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
+ half transfer and at the transfer complete for SDADC1.
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop,
+ HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
+ for SDADC1.
+ (#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
+ (or SDADC3).
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_SDADC_MODULE_ENABLED
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup SDADC SDADC
+ * @brief SDADC HAL driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SDADC_Private_Define SDADC Private Define
+ * @{
+ */
+#define SDADC_TIMEOUT 200
+#define SDADC_CONFREG_OFFSET 0x00000020
+#define SDADC_JDATAR_CH_OFFSET 24
+#define SDADC_MSB_MASK 0xFFFF0000
+#define SDADC_LSB_MASK 0x0000FFFF
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SDADC_Private_Functions SDADC Private Functions
+ * @{
+ */
+
+static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc);
+static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc);
+static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels);
+static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc);
+static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc);
+static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc);
+static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc);
+static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
+static void SDADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SDADC_Exported_Functions SDADC Exported Functions
+ * @{
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize the SDADC.
+ (+) De-initialize the SDADC.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the SDADC according to the specified
+ * parameters in the SDADC_InitTypeDef structure.
+ * @note If multiple SDADC are used, please configure first SDADC1 to set
+ * the common reference voltage.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
+ assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
+ assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
+ assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
+
+ /* Check SDADC handle */
+ if(hsdadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Initialize SDADC variables with default values */
+ hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
+ hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
+ hsdadc->InjectedChannelsNbr = 1;
+ hsdadc->InjConvRemaining = 1;
+ hsdadc->RegularTrigger = SDADC_SOFTWARE_TRIGGER;
+ hsdadc->InjectedTrigger = SDADC_SOFTWARE_TRIGGER;
+ hsdadc->ExtTriggerEdge = SDADC_EXT_TRIG_RISING_EDGE;
+ hsdadc->RegularMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
+ hsdadc->InjectedMultimode = SDADC_MULTIMODE_SDADC1_SDADC2;
+ hsdadc->ErrorCode = SDADC_ERROR_NONE;
+
+ /* Call MSP init function */
+ HAL_SDADC_MspInit(hsdadc);
+
+ /* Set idle low power and slow clock modes */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI|SDADC_CR1_PDI|SDADC_CR1_SLOWCK);
+ hsdadc->Instance->CR1 |= (hsdadc->Init.IdleLowPowerMode | \
+ hsdadc->Init.SlowClockMode);
+
+ /* Set fast conversion mode */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_FAST);
+ hsdadc->Instance->CR2 |= hsdadc->Init.FastConversionMode;
+
+ /* Set reference voltage common to all SDADC instances */
+ /* Update this parameter only if needed to avoid unnecessary settling time */
+ if((SDADC1->CR1 & SDADC_CR1_REFV) != hsdadc->Init.ReferenceVoltage)
+ {
+ /* Voltage reference bits are common to all SADC instances but are */
+ /* present in SDADC1 register. */
+ SDADC1->CR1 &= ~(SDADC_CR1_REFV);
+ SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage;
+
+ /* Wait at least 2ms before setting ADON */
+ HAL_Delay(2);
+ }
+
+ /* Enable SDADC */
+ hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
+
+ /* Wait end of stabilization */
+ while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0);
+
+ /* Set SDADC to ready state */
+ hsdadc->State = HAL_SDADC_STATE_READY;
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief De-initializes the SDADC.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC handle */
+ if(hsdadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the SDADC */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
+
+ /* Reset all registers */
+ hsdadc->Instance->CR1 = 0x00000000;
+ hsdadc->Instance->CR2 = 0x00000000;
+ hsdadc->Instance->JCHGR = 0x00000001;
+ hsdadc->Instance->CONF0R = 0x00000000;
+ hsdadc->Instance->CONF1R = 0x00000000;
+ hsdadc->Instance->CONF2R = 0x00000000;
+ hsdadc->Instance->CONFCHR1 = 0x00000000;
+ hsdadc->Instance->CONFCHR2 = 0x00000000;
+
+ /* Call MSP deinit function */
+ HAL_SDADC_MspDeInit(hsdadc);
+
+ /* Set SDADC in reset state */
+ hsdadc->State = HAL_SDADC_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the SDADC MSP.
+ * @param hsdadc: SDADC handle
+ * @retval None
+ */
+__weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_MspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief De-initializes the SDADC MSP.
+ * @param hsdadc: SDADC handle
+ * @retval None
+ */
+__weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_MspDeInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group2 peripheral control functions
+ * @brief Peripheral control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Program one of the three different configurations for channels.
+ (+) Associate channel to one of configurations.
+ (+) Select regular and injected channels.
+ (+) Enable/disable continuous mode for regular and injected conversions.
+ (+) Select regular and injected triggers.
+ (+) Select and configure injected external trigger.
+ (+) Enable/disable delay addition for injected conversions.
+ (+) Configure multimode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows the user to set parameters for a configuration.
+ * Parameters are input mode, common mode, gain and offset.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc: SDADC handle.
+ * @param ConfIndex: Index of configuration to modify.
+ * This parameter can be a value of @ref SDADC_ConfIndex.
+ * @param ConfParamStruct: Parameters to apply for this configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t ConfIndex,
+ SDADC_ConfParamTypeDef* ConfParamStruct)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp = 0;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
+ assert_param(ConfParamStruct != NULL);
+ assert_param(IS_SDADC_INPUT_MODE(ConfParamStruct->InputMode));
+ assert_param(IS_SDADC_GAIN(ConfParamStruct->Gain));
+ assert_param(IS_SDADC_COMMON_MODE(ConfParamStruct->CommonMode));
+ assert_param(IS_SDADC_OFFSET_VALUE(ConfParamStruct->Offset));
+
+ /* Check SDADC state is ready */
+ if(hsdadc->State != HAL_SDADC_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Program configuration register with parameters */
+ tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \
+ SDADC_CONFREG_OFFSET + \
+ (uint32_t)(ConfIndex << 2));
+ *(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \
+ ConfParamStruct->Gain | \
+ ConfParamStruct->CommonMode | \
+ ConfParamStruct->Offset);
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows the user to associate a channel with one of the
+ * available configurations.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc: SDADC handle.
+ * @param Channel: Channel to associate with configuration.
+ * This parameter can be a value of @ref SDADC_Channel_Selection.
+ * @param ConfIndex: Index of configuration to associate with channel.
+ * This parameter can be a value of @ref SDADC_ConfIndex.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ConfIndex)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t channelnum = 0;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
+ assert_param(IS_SDADC_CONF_INDEX(ConfIndex));
+
+ /* Check SDADC state is ready */
+ if(hsdadc->State != HAL_SDADC_STATE_READY)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Program channel configuration register according parameters */
+ if(Channel != SDADC_CHANNEL_8)
+ {
+ /* Get channel number */
+ channelnum = (uint32_t)(Channel>>16);
+
+ /* Set the channel configuration */
+ hsdadc->Instance->CONFCHR1 &= (uint32_t) ~(SDADC_CONFCHR1_CONFCH0 << (channelnum << 2));
+ hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2));
+ }
+ else
+ {
+ hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
+ }
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select channel for regular conversion and
+ * to enable/disable continuous mode for regular conversion.
+ * @param hsdadc: SDADC handle.
+ * @param Channel: Channel for regular conversion.
+ * This parameter can be a value of @ref SDADC_Channel_Selection.
+ * @param ContinuousMode: Enable/disable continuous mode for regular conversion.
+ * This parameter can be a value of @ref SDADC_ContinuousMode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
+ assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
+ {
+ /* Set RCH[3:0] and RCONT bits in SDADC_CR2 */
+ hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH | SDADC_CR2_RCONT);
+ if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
+ }
+ else
+ {
+ hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
+ }
+ /* Store continuous mode information */
+ hsdadc->RegularContMode = ContinuousMode;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select channels for injected conversion and
+ * to enable/disable continuous mode for injected conversion.
+ * @param hsdadc: SDADC handle.
+ * @param Channel: Channels for injected conversion.
+ * This parameter can be a values combination of @ref SDADC_Channel_Selection.
+ * @param ContinuousMode: Enable/disable continuous mode for injected conversion.
+ * This parameter can be a value of @ref SDADC_ContinuousMode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
+ uint32_t Channel,
+ uint32_t ContinuousMode)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
+ assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
+ {
+ /* Set JCHG[8:0] bits in SDADC_JCHG */
+ hsdadc->Instance->JCHGR = (uint32_t) (Channel & SDADC_LSB_MASK);
+ /* Set or clear JCONT bit in SDADC_CR2 */
+ if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
+ }
+ else
+ {
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
+ }
+ /* Store continuous mode information */
+ hsdadc->InjectedContMode = ContinuousMode;
+ /* Store number of injected channels */
+ hsdadc->InjectedChannelsNbr = SDADC_GetInjChannelsNbr(Channel);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select trigger for regular conversions.
+ * @note This function should not be called if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param Trigger: Trigger for regular conversions.
+ * This parameter can be one of the following value :
+ * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
+ * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_REGULAR_TRIGGER(Trigger));
+
+ /* Check parameters compatibility */
+ if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Store regular trigger information */
+ hsdadc->RegularTrigger = Trigger;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select trigger for injected conversions.
+ * @note This function should not be called if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param Trigger: Trigger for injected conversions.
+ * This parameter can be one of the following value :
+ * @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
+ * @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
+ * @arg SDADC_EXTERNAL_TRIGGER : External trigger.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_INJECTED_TRIGGER(Trigger));
+
+ /* Check parameters compatibility */
+ if((hsdadc->Instance == SDADC1) && (Trigger == SDADC_SYNCHRONOUS_TRIGGER))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Store regular trigger information */
+ hsdadc->InjectedTrigger = Trigger;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to select and configure injected external trigger.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc: SDADC handle.
+ * @param InjectedExtTrigger: External trigger for injected conversions.
+ * This parameter can be a value of @ref SDADC_InjectedExtTrigger.
+ * @param ExtTriggerEdge: Edge of external injected trigger.
+ * This parameter can be a value of @ref SDADC_ExtTriggerEdge.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedExtTrigger,
+ uint32_t ExtTriggerEdge)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_EXT_INJEC_TRIG(InjectedExtTrigger));
+ assert_param(IS_SDADC_EXT_TRIG_EDGE(ExtTriggerEdge));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set JEXTSEL[2:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTSEL);
+ hsdadc->Instance->CR2 |= InjectedExtTrigger;
+
+ /* Store external trigger edge information */
+ hsdadc->ExtTriggerEdge = ExtTriggerEdge;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to enable/disable delay addition for injected conversions.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing)
+ * @param hsdadc: SDADC handle.
+ * @param InjectedDelay: Enable/disable delay for injected conversions.
+ * This parameter can be a value of @ref SDADC_InjectedDelay.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
+ uint32_t InjectedDelay)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_INJECTED_DELAY(InjectedDelay));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set JDS bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JDS);
+ hsdadc->Instance->CR2 |= InjectedDelay;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to configure multimode for regular conversions.
+ * @note This function should not be called if regular conversion is ongoing
+ * and should be could only for SDADC1.
+ * @param hsdadc: SDADC handle.
+ * @param MultimodeType: Type of multimode for regular conversions.
+ * This parameter can be a value of @ref SDADC_MultimodeType.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
+ uint32_t MultimodeType)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Store regular trigger information */
+ hsdadc->RegularMultimode = MultimodeType;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to configure multimode for injected conversions.
+ * @note This function should not be called if injected conversion is ongoing
+ * and should be could only for SDADC1.
+ * @param hsdadc: SDADC handle.
+ * @param MultimodeType: Type of multimode for injected conversions.
+ * This parameter can be a value of @ref SDADC_MultimodeType.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
+ uint32_t MultimodeType)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_MULTIMODE_TYPE(MultimodeType));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_CALIB) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Store regular trigger information */
+ hsdadc->InjectedMultimode = MultimodeType;
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group3 Input and Output operation functions
+ * @brief IO operation Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start calibration.
+ (+) Poll for the end of calibration.
+ (+) Start calibration and enable interrupt.
+ (+) Start conversion of regular/injected channel.
+ (+) Poll for the end of regular/injected conversion.
+ (+) Stop conversion of regular/injected channel.
+ (+) Start conversion of regular/injected channel and enable interrupt.
+ (+) Stop conversion of regular/injected channel and disable interrupt.
+ (+) Start conversion of regular/injected channel and enable DMA transfer.
+ (+) Stop conversion of regular/injected channel and disable DMA transfer.
+ (+) Start multimode and enable DMA transfer for regular/injected conversion.
+ (+) Stop multimode and disable DMA transfer for regular/injected conversion..
+ (+) Get result of regular channel conversion.
+ (+) Get result of injected channel conversion.
+ (+) Get result of multimode conversion.
+ (+) Handle SDADC interrupt request.
+ (+) Callbacks for calibration and regular/injected conversions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to start calibration in polling mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing).
+ * @param hsdadc: SDADC handle.
+ * @param CalibrationSequence: Calibration sequence.
+ * This parameter can be a value of @ref SDADC_CalibrationSequence.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc,
+ uint32_t CalibrationSequence)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
+ hsdadc->Instance->CR2 |= CalibrationSequence;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+
+ /* Set STARTCALIB in SDADC_CR2 */
+ hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
+
+ /* Set SDADC in calibration state */
+ hsdadc->State = HAL_SDADC_STATE_CALIB;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of calibration.
+ * @note This function should be called only if calibration is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param Timeout: Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if(hsdadc->State != HAL_SDADC_STATE_CALIB)
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait EOCALF bit in SDADC_ISR register */
+ while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Set CLREOCALF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
+
+ /* Set SDADC in ready state */
+ hsdadc->State = HAL_SDADC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to start calibration in interrupt mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * (neither calibration nor regular or injected conversion ongoing).
+ * @param hsdadc: SDADC handle.
+ * @param CalibrationSequence: Calibration sequence.
+ * This parameter can be a value of @ref SDADC_CalibrationSequence.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc,
+ uint32_t CalibrationSequence)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(IS_SDADC_CALIB_SEQUENCE(CalibrationSequence));
+
+ /* Check SDADC state */
+ if(hsdadc->State == HAL_SDADC_STATE_READY)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set CALIBCNT[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_CALIBCNT);
+ hsdadc->Instance->CR2 |= CalibrationSequence;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+
+ /* Set EOCALIE bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_EOCALIE;
+
+ /* Set STARTCALIB in SDADC_CR2 */
+ hsdadc->Instance->CR2 |= SDADC_CR2_STARTCALIB;
+
+ /* Set SDADC in calibration state */
+ hsdadc->State = HAL_SDADC_STATE_CALIB;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in polling mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of regular conversion.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param Timeout: Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait REOCF bit in SDADC_ISR register */
+ while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Check if overrun occurs */
+ if((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF)
+ {
+ /* Update error code and call error callback */
+ hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
+ HAL_SDADC_ErrorCallback(hsdadc);
+
+ /* Set CLRROVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
+ }
+ /* Update SDADC state only if not continuous conversion and SW trigger */
+ if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
+ }
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop regular conversion in polling mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in interrupt mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Set REOCIE and ROVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
+
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop regular conversion in interrupt mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
+
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start regular conversion in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param pData: The destination buffer address.
+ * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != NULL);
+ assert_param(Length != 0);
+
+ /* Check that DMA is not enabled for injected conversion */
+ if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length != 1))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
+ }
+
+ /* Set RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATAR, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop regular conversion in DMA mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get regular conversion value.
+ * @param hsdadc: SDADC handle.
+ * @retval Regular conversion value
+ */
+uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
+{
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Return regular conversion value */
+ return hsdadc->Instance->RDATAR;
+}
+
+/**
+ * @brief This function allows to start injected conversion in polling mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to poll for the end of injected conversion.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param Timeout: Timeout value in milliseconds.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc,
+ uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait JEOCF bit in SDADC_ISR register */
+ while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
+ {
+ /* Check the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Return timeout status */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ /* Check if overrun occurs */
+ if((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF)
+ {
+ /* Update error code and call error callback */
+ hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
+ HAL_SDADC_ErrorCallback(hsdadc);
+
+ /* Set CLRJOVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
+ }
+ /* Update remaining injected conversions */
+ hsdadc->InjConvRemaining--;
+ if(hsdadc->InjConvRemaining == 0)
+ {
+ /* end of injected sequence, reset the value */
+ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
+ }
+
+ /* Update SDADC state only if not continuous conversion, SW trigger */
+ /* and end of injected sequence */
+ if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
+ }
+ /* Return function status */
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief This function allows to stop injected conversion in polling mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start injected conversion in interrupt mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Set JEOCIE and JOVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= (uint32_t) (SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
+
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop injected conversion in interrupt mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= (uint32_t) ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
+
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to start injected conversion in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param pData: The destination buffer address.
+ * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != NULL);
+ assert_param(Length != 0);
+
+ /* Check that DMA is not enabled for regular conversion */
+ if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length > hsdadc->InjectedChannelsNbr))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
+ }
+
+ /* Set JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATAR, \
+ (uint32_t) pData, Length) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop injected conversion in DMA mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check SDADC state */
+ if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get injected conversion value.
+ * @param hsdadc: SDADC handle.
+ * @param Channel: Corresponding channel of injected conversion.
+ * @retval Injected conversion value
+ */
+uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel)
+{
+ uint32_t value = 0;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(Channel != NULL);
+
+ /* Read SDADC_JDATAR register and extract channel and conversion value */
+ value = hsdadc->Instance->JDATAR;
+ *Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
+ value &= SDADC_JDATAR_JDATA;
+
+ /* Return injected conversion value */
+ return value;
+}
+
+/**
+ * @brief This function allows to start multimode regular conversions in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param pData: The destination buffer address.
+ * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData,
+ uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != NULL);
+ assert_param(Length != 0);
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is not enabled for injected conversion */
+ else if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length != 1))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_INJ))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMARegularConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
+ }
+ /* Set RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA12R, \
+ (uint32_t) pData, Length);
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->RDATA13R, \
+ (uint32_t) pData, Length);
+ }
+ if(status != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start regular conversion */
+ status = SDADC_RegConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop multimode regular conversions in DMA mode.
+ * @note This function should be called only if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State != HAL_SDADC_STATE_REG) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_RDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop regular conversion */
+ status = SDADC_RegConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get multimode regular conversion value.
+ * @param hsdadc: SDADC handle.
+ * @retval Multimode regular conversion value
+ */
+uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t value = 0;
+
+ /* Check parameters and check instance is SDADC1 */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(hsdadc->Instance == SDADC1);
+
+ /* read multimode regular value */
+ value = (hsdadc->RegularMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
+ hsdadc->Instance->RDATA12R : hsdadc->Instance->RDATA13R;
+
+ /* Return multimode regular conversions value */
+ return value;
+}
+
+/**
+ * @brief This function allows to start multimode injected conversions in DMA mode.
+ * @note This function should be called only when SDADC instance is in idle state
+ * or if regular conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @param pData: The destination buffer address.
+ * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc,
+ uint32_t* pData, uint32_t Length)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(pData != NULL);
+ assert_param(Length != 0);
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check that DMA is not enabled for regular conversion */
+ else if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check parameters compatibility */
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
+ (Length > (hsdadc->InjectedChannelsNbr << 1)))
+ {
+ status = HAL_ERROR;
+ }
+ else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->hdma->Init.Mode == DMA_CIRCULAR))
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State == HAL_SDADC_STATE_READY) || \
+ (hsdadc->State == HAL_SDADC_STATE_REG))
+ {
+ /* Set callbacks on DMA handler */
+ hsdadc->hdma->XferCpltCallback = SDADC_DMAInjectedConvCplt;
+ hsdadc->hdma->XferErrorCallback = SDADC_DMAError;
+ if(hsdadc->hdma->Init.Mode == DMA_CIRCULAR)
+ {
+ hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
+ }
+ /* Set JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
+
+ /* Start DMA in interrupt mode */
+ if(hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2)
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA12R, \
+ (uint32_t) pData, Length);
+ }
+ else
+ {
+ status = HAL_DMA_Start_IT(hsdadc->hdma, (uint32_t)&hsdadc->Instance->JDATA13R, \
+ (uint32_t) pData, Length);
+ }
+ if(status != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Start injected conversion */
+ status = SDADC_InjConvStart(hsdadc);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to stop multimode injected conversions in DMA mode.
+ * @note This function should be called only if injected conversion is ongoing.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
+ /* Check instance is SDADC1 */
+ if(hsdadc->Instance != SDADC1)
+ {
+ status = HAL_ERROR;
+ }
+ /* Check SDADC state */
+ else if((hsdadc->State != HAL_SDADC_STATE_INJ) && \
+ (hsdadc->State != HAL_SDADC_STATE_REG_INJ))
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear JDMAEN bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JDMAEN);
+
+ /* Stop current DMA transfer */
+ if(HAL_DMA_Abort(hsdadc->hdma) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Stop injected conversion */
+ status = SDADC_InjConvStop(hsdadc);
+ }
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to get multimode injected conversion value.
+ * @param hsdadc: SDADC handle.
+ * @retval Multimode injected conversion value
+ */
+uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t value = 0;
+
+ /* Check parameters and check instance is SDADC1 */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+ assert_param(hsdadc->Instance == SDADC1);
+
+ /* read multimode injected value */
+ value = (hsdadc->InjectedMultimode == SDADC_MULTIMODE_SDADC1_SDADC2) ? \
+ hsdadc->Instance->JDATA12R : hsdadc->Instance->JDATA13R;
+
+ /* Return multimode injected conversions value */
+ return value;
+}
+
+/**
+ * @brief This function handles the SDADC interrupts.
+ * @param hsdadc: SDADC handle.
+ * @retval None
+ */
+void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Check if end of regular conversion */
+ if(((hsdadc->Instance->ISR & SDADC_ISR_REOCF) == SDADC_ISR_REOCF) && \
+ ((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE))
+ {
+ /* Call regular conversion complete callback */
+ HAL_SDADC_ConvCpltCallback(hsdadc);
+
+ /* End of conversion if mode is not continuous and software trigger */
+ if((hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER))
+ {
+ /* Clear REOCIE and ROVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_REOCIE | SDADC_CR1_ROVRIE);
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
+ }
+ }
+ /* Check if end of injected conversion */
+ else if(((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF) && \
+ ((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE))
+ {
+ /* Call injected conversion complete callback */
+ HAL_SDADC_InjectedConvCpltCallback(hsdadc);
+
+ /* Update remaining injected conversions */
+ hsdadc->InjConvRemaining--;
+ if(hsdadc->InjConvRemaining ==0)
+ {
+ /* end of injected sequence, reset the value */
+ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
+ }
+ /* End of conversion if mode is not continuous, software trigger */
+ /* and end of injected sequence */
+ if((hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
+ (hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
+ (hsdadc->InjConvRemaining == hsdadc->InjectedChannelsNbr))
+ {
+ /* Clear JEOCIE and JOVRIE bits in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JEOCIE | SDADC_CR1_JOVRIE);
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
+ }
+ }
+ /* Check if end of calibration */
+ else if(((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF) && \
+ ((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE))
+ {
+ /* Clear EOCALIE bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_EOCALIE);
+
+ /* Set CLREOCALF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLREOCALF;
+
+ /* Call calibration callback */
+ HAL_SDADC_CalibrationCpltCallback(hsdadc);
+
+ /* Update SDADC state */
+ hsdadc->State = HAL_SDADC_STATE_READY;
+ }
+ /* Check if overrun occurs during regular conversion */
+ else if(((hsdadc->Instance->ISR & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF) && \
+ ((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE))
+ {
+ /* Set CLRROVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
+
+ /* Update error code */
+ hsdadc->ErrorCode = SDADC_ERROR_REGULAR_OVERRUN;
+
+ /* Call error callback */
+ HAL_SDADC_ErrorCallback(hsdadc);
+ }
+ /* Check if overrun occurs during injected conversion */
+ else if(((hsdadc->Instance->ISR & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF) && \
+ ((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE))
+ {
+ /* Set CLRJOVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
+
+ /* Update error code */
+ hsdadc->ErrorCode = SDADC_ERROR_INJECTED_OVERRUN;
+
+ /* Call error callback */
+ HAL_SDADC_ErrorCallback(hsdadc);
+ }
+ return;
+}
+
+/**
+ * @brief Calibration complete callback.
+ * @param hsdadc: SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_CalibrationCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Half regular conversion complete callback.
+ * @param hsdadc: SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_ConvHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Regular conversion complete callback.
+ * @note In interrupt mode, user has to read conversion value in this function
+ using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
+ * @param hsdadc: SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_ConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Half injected conversion complete callback.
+ * @param hsdadc: SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_InjectedConvHalfCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Injected conversion complete callback.
+ * @note In interrupt mode, user has to read conversion value in this function
+ using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
+ * @param hsdadc: SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_InjectedConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hsdadc: SDADC handle.
+ * @retval None
+ */
+__weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SDADC_ErrorCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DMA half transfer complete callback for regular conversion.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call regular half conversion complete callback */
+ HAL_SDADC_ConvHalfCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA transfer complete callback for regular conversion.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call regular conversion complete callback */
+ HAL_SDADC_ConvCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA half transfer complete callback for injected conversion.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call injected half conversion complete callback */
+ HAL_SDADC_InjectedConvHalfCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA transfer complete callback for injected conversion.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Call injected conversion complete callback */
+ HAL_SDADC_InjectedConvCpltCallback(hsdadc);
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Get SDADC handle */
+ SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
+
+ /* Update error code */
+ hsdadc->ErrorCode = SDADC_ERROR_DMA;
+
+ /* Call error callback */
+ HAL_SDADC_ErrorCallback(hsdadc);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief SDADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### ADC Peripheral State functions #####
+ ===============================================================================
+ [..] This subsection provides functions allowing to
+ (+) Get the SDADC state
+ (+) Get the SDADC Error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function allows to get the current SDADC state.
+ * @param hsdadc: SDADC handle.
+ * @retval SDADC state.
+ */
+HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
+{
+ return hsdadc->State;
+}
+
+/**
+ * @brief This function allows to get the current SDADC error code.
+ * @param hsdadc: SDADC handle.
+ * @retval SDADC error code.
+ */
+uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
+{
+ return hsdadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup SDADC_Private_Functions SDADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief This function allows to enter in init mode for SDADC instance.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t tickstart = 0;
+
+ /* Set INIT bit on SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
+
+ /* Wait INITRDY bit on SDADC_ISR */
+ tickstart = HAL_GetTick();
+ while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function allows to exit from init mode for SDADC instance.
+ * @param hsdadc: SDADC handle.
+ * @retval None.
+ */
+static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
+{
+ /* Reset INIT bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_INIT);
+}
+
+/**
+ * @brief This function allows to get the number of injected channels.
+ * @param Channels : bitfield of injected channels.
+ * @retval Number of injected channels.
+ */
+static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
+{
+ uint32_t nbChannels = 0;
+ uint32_t tmp,i;
+
+ /* Get the number of channels from bitfield */
+ tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
+ for(i = 0 ; i < 9 ; i++)
+ {
+ if(tmp & 1)
+ {
+ nbChannels++;
+ }
+ tmp = (uint32_t) (tmp >> 1);
+ }
+ return nbChannels;
+}
+
+/**
+ * @brief This function allows to really start regular conversion.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check regular trigger */
+ if(hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER)
+ {
+ /* Set RSWSTART bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_RSWSTART;
+ }
+ else /* synchronuous trigger */
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Set RSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_RSYNC;
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Update SDADC state only if status is OK */
+ if(status == HAL_OK)
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
+ HAL_SDADC_STATE_REG : HAL_SDADC_STATE_REG_INJ;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to really stop regular conversion.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t tickstart;
+ __IO uint32_t dummy_read_for_register_reset;
+
+ /* Check continuous mode */
+ if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Clear REOCF by reading SDADC_RDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Clear RCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
+ }
+ /* Wait for the end of regular conversion */
+ tickstart = HAL_GetTick();
+ while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0)
+ {
+ if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if trigger is synchronuous */
+ if(hsdadc->RegularTrigger == SDADC_SYNCHRONOUS_TRIGGER)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Clear RSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_RSYNC);
+
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Check if continuous mode */
+ if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Restore RCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_RCONT;
+ }
+ /* Clear REOCF by reading SDADC_RDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->RDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Set CLRROVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRROVRF;
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_REG) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_INJ;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function allows to really start injected conversion.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Initialize number of injected conversions remaining */
+ hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
+
+ /* Check injected trigger */
+ if(hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER)
+ {
+ /* Set JSWSTART bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_JSWSTART;
+ }
+ else /* external or synchronuous trigger */
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
+ {
+ /* Set JSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 |= SDADC_CR1_JSYNC;
+ }
+ else /* external trigger */
+ {
+ /* Set JEXTEN[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= hsdadc->ExtTriggerEdge;
+ }
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Update SDADC state only if status is OK */
+ if(status == HAL_OK)
+ {
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_READY) ? \
+ HAL_SDADC_STATE_INJ : HAL_SDADC_STATE_REG_INJ;
+ }
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief This function allows to really stop injected conversion.
+ * @param hsdadc: SDADC handle.
+ * @retval HAL status.
+ */
+static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
+{
+ uint32_t tickstart;
+ __IO uint32_t dummy_read_for_register_reset;
+
+ /* Check continuous mode */
+ if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Clear JEOCF by reading SDADC_JDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Clear JCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
+ }
+ /* Wait for the end of injected conversion */
+ tickstart = HAL_GetTick();
+ while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0)
+ {
+ if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if trigger is not software */
+ if(hsdadc->InjectedTrigger != SDADC_SOFTWARE_TRIGGER)
+ {
+ /* Enter init mode */
+ if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
+ {
+ /* Set SDADC in error state and return timeout status */
+ hsdadc->State = HAL_SDADC_STATE_ERROR;
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Check if trigger is synchronuous */
+ if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
+ {
+ /* Clear JSYNC bit in SDADC_CR1 register */
+ hsdadc->Instance->CR1 &= ~(SDADC_CR1_JSYNC);
+ }
+ else /* external trigger */
+ {
+ /* Clear JEXTEN[1:0] bits in SDADC_CR2 register */
+ hsdadc->Instance->CR2 &= ~(SDADC_CR2_JEXTEN);
+ }
+ /* Exit init mode */
+ SDADC_ExitInitMode(hsdadc);
+ }
+ }
+ /* Check if continuous mode */
+ if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
+ {
+ /* Restore JCONT bit in SDADC_CR2 register */
+ hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
+ }
+ /* Clear JEOCF by reading SDADC_JDATAR register */
+ dummy_read_for_register_reset = hsdadc->Instance->JDATAR;
+ UNUSED(dummy_read_for_register_reset);
+
+ /* Set CLRJOVRF bit in SDADC_CLRISR register */
+ hsdadc->Instance->CLRISR |= SDADC_ISR_CLRJOVRF;
+
+ /* Update SDADC state */
+ hsdadc->State = (hsdadc->State == HAL_SDADC_STATE_INJ) ? \
+ HAL_SDADC_STATE_READY : HAL_SDADC_STATE_REG;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
+#endif /* HAL_SDADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c
@@ -0,0 +1,1463 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief SMARTCARD HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the SMARTCARD peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+ (#) Associate a USART to the SMARTCARD handle hsmartcard.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+ and HAL_SMARTCARD_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+ and HAL_SMARTCARD_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+ the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+ error enabling or disabling in the hsmartcard handle Init structure.
+
+ (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+ in the hsmartcard handle AdvancedInit structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ [..] Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARD SMARTCARD
+ * @brief SMARTCARD HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+#define SMARTCARD_TXDMA_TIMEOUTVALUE 22000
+#define SMARTCARD_TIMEOUT_VALUE 22000
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ associated to the SmartCard.
+ [..]
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard.
+ [..]
+ The USART can provide a clock to the smartcard through the SCLK output.
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
+ from the internal peripheral input clock through a 5-bit prescaler.
+ [..]
+ (+) These parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: parity should be enabled,
+ Frame Length is fixed to 8 bits plus parity:
+ the SMARTCARD frame format is given in the following table:
+ (+++) +---------------------------------------------------------------+
+ (+++) | M bit | PCE bit | SMARTCARD frame |
+ (+++) |---------------------|-----------------------------------------|
+ (+++) | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) +---------------------------------------------------------------+
+ (+++) or
+ (+++) +---------------------------------------------------------------+
+ (+++) | M1M0 bits | PCE bit | SMARTCARD frame |
+ (+++) |-----------------------|---------------------------------------|
+ (+++) | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) +---------------------------------------------------------------+
+
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
+
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+ [..]
+ The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+ (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the USART associated to the SmartCard */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmartcard->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_SMARTCARD_MspInit(hsmartcard);
+ }
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ /* Set the SMARTCARD Communication parameters */
+ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+ {
+ SMARTCARD_AdvFeatureConfig(hsmartcard);
+ }
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN);
+ hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* set the USART in SMARTCARD mode */
+ hsmartcard->Instance->CR3 |= USART_CR3_SCEN;
+
+ /* Enable the Peripheral */
+ __HAL_SMARTCARD_ENABLE(hsmartcard);
+
+ /* TEACK and/or REACK to check before moving hsmartcard->State to Ready */
+ return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+
+/**
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check the SMARTCARD handle allocation */
+ if(hsmartcard == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+ hsmartcard->Instance->CR1 = 0x0;
+ hsmartcard->Instance->CR2 = 0x0;
+ hsmartcard->Instance->CR3 = 0x0;
+ hsmartcard->Instance->RTOR = 0x0;
+ hsmartcard->Instance->GTPR = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_SMARTCARD_MspDeInit(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->State = HAL_SMARTCARD_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ [..]
+ (+) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
+
+ (+) Blocking mode APIs are :
+ (++) HAL_SMARTCARD_Transmit()
+ (++) HAL_SMARTCARD_Receive()
+
+ (+) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_SMARTCARD_Transmit_IT()
+ (++) HAL_SMARTCARD_Receive_IT()
+ (++) HAL_SMARTCARD_IRQHandler()
+
+ (+) Non Blocking mode functions with DMA are :
+ (++) HAL_SMARTCARD_Transmit_DMA()
+ (++) HAL_SMARTCARD_Receive_DMA()
+
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SMARTCARD_TxCpltCallback()
+ (++) HAL_SMARTCARD_RxCpltCallback()
+ (++) HAL_SMARTCARD_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @param Timeout : Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+ while(hsmartcard->TxXferCount > 0)
+ {
+ hsmartcard->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Check if a non-blocking receive Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @param Timeout : Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+ /* Check the remain data to be received */
+ while(hsmartcard->RxXferCount > 0)
+ {
+ hsmartcard->RxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ }
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Data Register not empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_TCF);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ /* Set the SMARTCARD state ready to be able to start again the process */
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsmartcard);
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ }
+
+ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET))
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ __HAL_UNLOCK(hsmartcard);
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+ * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+ }
+
+ /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET))
+ {
+ SMARTCARD_Transmit_IT(hsmartcard);
+ }
+
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ handle and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+ communication.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Return the SMARTCARD handle state.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle state
+ */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->State;
+}
+
+/**
+ * @brief Return the SMARTCARD handle error code.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+* @retval SMARTCARD handle Error Code
+*/
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ return hsmartcard->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+
+ if(hsmartcard->TxXferCount == 0)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
+ hsmartcard->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+
+ *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+ if(--hsmartcard->RxXferCount == 0)
+ {
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Handle SMARTCARD Communication Timeout.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag: specifies the SMARTCARD flag to check.
+ * @param Status: The new Flag status (SET or RESET).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsmartcard->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsmartcard->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsmartcard->RxXferCount = 0;
+ hsmartcard->TxXferCount = 0;
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpreg = 0x00000000;
+ SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+ assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+ assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+ * Oversampling is forced to 16 (OVER8 = 0).
+ * Configure the Parity and Mode:
+ * set PS bit according to hsmartcard->Init.Parity value
+ * set TE and RE bits according to hsmartcard->Init.Mode value */
+ tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
+ /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ tmpreg |= USART_CR1_RE;
+ }
+ tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Stop bits are forced to 1.5 (STOP = 11) */
+ tmpreg = hsmartcard->Init.StopBits;
+ /* Synchronous mode is activated by default */
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
+ MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+ {
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ }
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ switch (clocksource)
+ {
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
+ hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PCLK2:
+ hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_SYSCLK:
+ hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+ }
+
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Check if the Transmitter is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the SMARTCARD state*/
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c
@@ -0,0 +1,196 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smartcard_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief SMARTCARD HAL module driver.
+ *
+ * This file provides extended firmware functions to manage the following
+ * functionalities of the SmartCard.
+ * + Initialization and de-initialization function
+ * + Peripheral Control function
+ *
+ *
+ @verbatim
+ =============================================================================
+ ##### SMARTCARD peripheral extended features #####
+ =============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
+
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+ auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+ * @brief SMARTCARD Extension HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Update on the fly the SMARTCARD block length in RTOR register.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param BlockLength: SMARTCARD block length (8-bit long at most)
+ * @retval None
+ */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+}
+
+/**
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/**
+ * @brief Enable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ hsmartcard->Instance->CR2 |= USART_CR2_RTOEN;
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c
@@ -0,0 +1,1941 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_smbus.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief SMBUS HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the System Management Bus (SMBus) peripheral,
+ * based on I2C principles of operation :
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SMBUS HAL driver can be used as follows:
+
+ (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
+ SMBUS_HandleTypeDef hsmbus;
+
+ (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+ (##) Enable the SMBUSx interface clock
+ (##) SMBUS pins configuration
+ (+++) Enable the clock for the SMBUS GPIOs
+ (+++) Configure SMBUS pins as alternate function open-drain
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SMBUSx interrupt priority
+ (+++) Enable the NVIC SMBUS IRQ Channel
+
+ (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
+ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
+ Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
+
+ (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+ (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+
+ (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+
+ (#) For SMBUS IO operations, only one mode of operations is available within this driver :
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+ (++) The associated previous transfer callback is called at the end of abort process
+ (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
+ using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
+ (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+ (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function HAL_SMBUS_GetError()
+
+ *** SMBUS HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in SMBUS HAL driver.
+
+ (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+
+ [..]
+ (@) You can refer to the SMBUS HAL driver header file for more useful macros
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUS SMBUS
+ * @brief SMBUS HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
+ * @{
+ */
+#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /*!< 10 s */
+#define HAL_TIMEOUT_BUSY ((uint32_t)25) /*!< 25 ms */
+#define HAL_TIMEOUT_DIR ((uint32_t)25) /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE ((uint32_t)25) /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF ((uint32_t)25) /*!< 25 ms */
+#define HAL_TIMEOUT_TC ((uint32_t)25) /*!< 25 ms */
+#define HAL_TIMEOUT_TCR ((uint32_t)25) /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS ((uint32_t)25) /*!< 25 ms */
+#define MAX_NBYTE_SIZE 255
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the SMBUSx peripheral:
+
+ (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
+
+ (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+ the selected configuration:
+ (++) Clock Timing
+ (++) Bus Timeout
+ (++) Analog Filer mode
+ (++) Own Address 1
+ (++) Addressing mode (Master, Slave)
+ (++) Dual Addressing mode
+ (++) Own Address 2
+ (++) Own Address 2 Mask
+ (++) General call mode
+ (++) Nostretch mode
+ (++) Packet Error Check mode
+ (++) Peripheral mode
+
+
+ (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+ of the selected SMBUSx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SMBUS according to the specified parameters
+ * in the SMBUS_InitTypeDef and initialize the associated handle.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if(hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
+ assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
+ assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
+ assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
+ assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
+ assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
+ assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
+ assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
+ assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
+ assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsmbus->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspInit(hsmbus);
+ }
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+ /* Configure SMBUSx: Frequency range */
+ hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
+
+ /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+ /* Configure SMBUSx: Bus Timeout */
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
+ hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
+ hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
+
+ /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
+ /* Configure SMBUSx: Own Address1 and ack own address1 mode */
+ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+ if(hsmbus->Init.OwnAddress1 != 0)
+ {
+ if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+ }
+ else /* SMBUS_ADDRESSINGMODE_10BIT */
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
+ }
+ }
+
+ /*---------------------------- SMBUSx CR2 Configuration ------------------------*/
+ /* Configure SMBUSx: Addressing Master mode */
+ if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+ {
+ hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
+ /* AUTOEND and NACK bit will be manage during Transfer process */
+ hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+ /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+ /* Configure SMBUSx: Dual mode and Own Address2 */
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8));
+
+ /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
+ /* Configure SMBUSx: Generalcall and NoStretch mode */
+ hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+
+ /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
+ if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
+ && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
+ {
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+ }
+
+ /* Enable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the SMBUS peripheral.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the SMBUS handle allocation */
+ if(hsmbus == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the SMBUS Peripheral Clock */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_SMBUS_MspDeInit(hsmbus);
+
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
+ hsmbus->State = HAL_SMBUS_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SMBUS MSP.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMBUS data
+ transfers.
+
+ (#) Blocking mode function to check if device is ready for usage is :
+ (++) HAL_SMBUS_IsDeviceReady()
+
+ (#) There is only one mode of transfer:
+ (++) Non-Blocking mode : The communication is performed using Interrupts.
+ These functions return the status of the transfer startup.
+ The end of the data processing will be indicated through the
+ dedicated SMBUS IRQ when using Interrupt mode.
+
+ (#) Non-Blocking mode functions with Interrupt are :
+ (++) HAL_SMBUS_Master_Transmit_IT()
+ (++) HAL_SMBUS_Master_Receive_IT()
+ (++) HAL_SMBUS_Slave_Transmit_IT()
+ (++) HAL_SMBUS_Slave_Receive_IT()
+ (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
+ (++) HAL_SMBUS_DisableListen_IT()
+ (++) HAL_SMBUS_EnableAlert_IT()
+ (++) HAL_SMBUS_DisableAlert_IT()
+
+ (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode:
+ (++) HAL_SMBUS_MasterTxCpltCallback()
+ (++) HAL_SMBUS_MasterRxCpltCallback()
+ (++) HAL_SMBUS_SlaveTxCpltCallback()
+ (++) HAL_SMBUS_SlaveRxCpltCallback()
+ (++) HAL_SMBUS_AddrCallback()
+ (++) HAL_SMBUS_ListenCpltCallback()
+ (++) HAL_SMBUS_ErrorCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if(hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if(Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ }
+
+ /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* In case of Quick command, remove autoend mode */
+ /* Manage the stop generation by software */
+ if(hsmbus->pBuffPtr == NULL)
+ {
+ hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
+ }
+
+ if(Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ }
+ else
+ {
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ /* Else transfer direction change, so generate Restart with new transfer direction */
+ else
+ {
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master/host SMBUS process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
+{
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ /* Keep the same state as previous */
+ /* to perform as well the call of the corresponding end of transfer callback */
+ if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
+ }
+ else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferSize = Size;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ if(Size > MAX_NBYTE_SIZE)
+ {
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = Size;
+ }
+
+ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
+ if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ {
+ SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ /* Set NBYTE to transmit */
+ SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ /* Set SBC bit to manage Acknowledge at each bit */
+ hsmbus->Instance->CR1 |= I2C_CR1_SBC;
+
+ /* Enable Address Acknowledge */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hsmbus->pBuffPtr = pData;
+ hsmbus->XferSize = Size;
+ hsmbus->XferCount = Size;
+ hsmbus->XferOptions = XferOptions;
+
+ /* Set NBYTE to receive */
+ /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
+ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
+ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
+ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
+ if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ {
+ SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else
+ {
+ SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ }
+
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the HOST */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ to avoid the risk of SMBUS interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+
+ /* Enable the Address Match interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Disable the Address Match interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+
+ /* Enable Alert Interrupt */
+ SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+/**
+ * @brief Disable the SMBUS alert mode with Interrupt.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Enable SMBus alert */
+ hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
+ /* Disable Alert Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if target device is ready for communication.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DevAddress Target device address
+ * @param Trials Number of trials
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ __IO uint32_t SMBUS_Trials = 0;
+
+ if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
+
+ do
+ {
+ /* Generate Start */
+ hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
+
+ /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+ /* Wait until STOPF flag is set or a NACK flag is set*/
+ tickstart = HAL_GetTick();
+ while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Check if the NACKF flag has not been set */
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
+ {
+ /* Wait until STOPF flag is reset */
+ if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Device is ready */
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wait until STOPF flag is reset */
+ if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Clear STOP Flag, auto generated with autoend*/
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+
+ /* Check if the maximum allowed number of trials has been reached */
+ if (SMBUS_Trials++ == Trials)
+ {
+ /* Generate Stop */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Wait until STOPF flag is reset */
+ if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ }
+ }while(SMBUS_Trials < Trials);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle SMBUS event interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t tmpisrvalue = 0;
+
+ /* Use a local variable to store the current ISR flags */
+ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
+ tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
+
+ /* SMBUS in mode Transmitter ---------------------------------------------------*/
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ /* Master mode selected */
+ else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ SMBUS_Master_ISR(hsmbus);
+ }
+ }
+
+ /* SMBUS in mode Receiver ----------------------------------------------------*/
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ {
+ /* Slave mode selected */
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ /* Master mode selected */
+ else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Master_ISR(hsmbus);
+ }
+ }
+
+ /* SMBUS in mode Listener Only --------------------------------------------------*/
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
+ && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+ {
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ {
+ SMBUS_Slave_ISR(hsmbus);
+ }
+ }
+}
+
+/**
+ * @brief Handle SMBUS error interrupt request.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the HAL state in case of ALERT error */
+ if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ {
+ if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_SMBUS_STATE_LISTEN if set */
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+}
+
+/**
+ * @brief Master Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Master Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ */
+}
+
+/** @brief Slave Tx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Rx Transfer completed callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param TransferDirection: Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode: Address Match Code
+ * @retval None
+ */
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMBUS error callback.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval None
+ */
+ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ErrorCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SMBUS handle state.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL state
+ */
+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Return SMBUS handle state */
+ return hsmbus->State;
+}
+
+/**
+ * @brief Return the SMBUS error code.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval SMBUS Error Code
+*/
+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+{
+ return hsmbus->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
+ * @brief Data transfers Private functions
+ * @{
+ */
+
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint16_t DevAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ {
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* REenable the selected SMBUS peripheral */
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+ {
+ if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
+ {
+ DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
+
+ if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
+ {
+ /* Call TxCpltCallback() if no stop mode is set */
+ if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+ {
+ if(hsmbus->XferCount == 0)
+ {
+ /* Specific use case for Quick command */
+ if(hsmbus->pBuffPtr == NULL)
+ {
+ /* Generate a Stop command */
+ hsmbus->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ /* Call TxCpltCallback() if no stop mode is set */
+ else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ {
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ {
+ /* Disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+ }
+ else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ {
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+ }
+ }
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint8_t TransferDirection = 0;
+ uint16_t SlaveAddrCode = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ {
+ /* Check that SMBUS transfer finished */
+ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if(hsmbus->XferCount == 0)
+ {
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+ }
+ else
+ {
+ /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
+ /* Clear NACK Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ /* Set HAL State to "Idle" State, mean to LISTEN state */
+ /* So reset Slave Busy state */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Disable RX/TX Interrupts, keep only ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Error callback to prevent upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+ {
+ TransferDirection = SMBUS_GET_DIR(hsmbus);
+ SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
+
+ /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
+ /* Other ADDRInterrupt will be treat in next Listen usecase */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call Slave Addr callback */
+ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+ }
+ else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+ {
+ if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+
+ if(hsmbus->XferCount == 1)
+ {
+ /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
+ /* or only the last Byte of Transfer */
+ /* So reset the RELOAD bit mode */
+ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
+ SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ }
+ else if(hsmbus->XferCount == 0)
+ {
+ /* Last Byte is received, disable Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
+
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+ }
+ else
+ {
+ /* Set Reload for next Bytes */
+ SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+
+ /* Ack last Byte Read */
+ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
+ }
+ }
+ else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ {
+ if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
+ {
+ if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ hsmbus->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hsmbus->XferSize = hsmbus->XferCount;
+ SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
+ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+ }
+ }
+ }
+ else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Datas have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if(hsmbus->XferCount > 0)
+ {
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+
+ if(hsmbus->XferCount == 0)
+ {
+ /* Last Byte is Transmitted */
+ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+ }
+ }
+
+ /* Check if STOPF is set */
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ {
+ if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable RX and TX Interrupts */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
+
+ /* Disable ADDR Interrupt */
+ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
+
+ /* Disable Address Acknowledge */
+ hsmbus->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Clear Configuration Register 2 */
+ SMBUS_RESET_CR2(hsmbus);
+
+ /* Clear STOP Flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+
+ hsmbus->XferOptions = 0;
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the enabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0;
+
+ if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+ {
+ /* Enable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of SMBUS interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
+
+ return HAL_OK;
+}
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0;
+
+ if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ {
+ /* Disable TC, STOP, NACK, TXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
+
+ if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOPI, NACKI */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ {
+ /* Disable TC, STOP, NACK, RXI interrupt */
+ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
+
+ if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+
+ if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ {
+ /* Disable STOPI, NACKI */
+ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+ }
+ }
+
+ if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ {
+ /* Enable ADDR, STOP interrupt */
+ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
+
+ if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ {
+ /* Disable ERR interrupt */
+ tmpisr |= SMBUS_IT_ERRI;
+ }
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
+
+ return HAL_OK;
+}
+/**
+ * @brief Handle SMBUS Communication Timeout.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param Flag Specifies the SMBUS flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State= HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State= HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param hsmbus SMBUS handle.
+ * @param DevAddress specifies the slave address to be programmed.
+ * @param Size specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param Mode New state of the SMBUS START condition generation.
+ * This parameter can be one or a combination of the following values:
+ * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode.
+ * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode.
+ * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode.
+ * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode.
+ * @param Request New state of the SMBUS START condition generation.
+ * This parameter can be one of the following values:
+ * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition.
+ * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0).
+ * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request.
+ * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
+ * @retval None
+ */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
+ assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
+
+ /* Get the CR2 register value */
+ tmpreg = hsmbus->Instance->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
+
+ /* update CR2 register */
+ hsmbus->Instance->CR2 = tmpreg;
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c
@@ -0,0 +1,2790 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+ +-----------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |--------------------|--------------------|--------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |=========================================================================================|
+ | T | Polling | Fcpu/4 | Fcpu/8 | NA | NA | NA | NA |
+ | X |----------------|----------|---------|----------|---------|----------|---------|
+ | / | Interrupt | Fcpu/4 | Fcpu/16 | NA | NA | NA | NA |
+ | R |----------------|----------|---------|----------|---------|----------|---------|
+ | X | DMA | Fcpu/2 | Fcpu/2 | NA | NA | NA | NA |
+ |=========|================|==========|=========|==========|=========|==========|=========|
+ | | Polling | Fcpu/4 | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 |
+ | |----------------|----------|---------|----------|---------|----------|---------|
+ | R | Interrupt | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | Fcpu/4 |
+ | X |----------------|----------|---------|----------|---------|----------|---------|
+ | | DMA | Fcpu/4 | Fcpu/2 | Fcpu/2 | Fcpu/16 | Fcpu/2 | Fcpu/16 |
+ |=========|================|==========|=========|==========|=========|==========|=========|
+ | | Polling | Fcpu/8 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/8 |
+ | |----------------|----------|---------|----------|---------|----------|---------|
+ | T | Interrupt | Fcpu/2 | Fcpu/4 | NA | NA | Fcpu/16 | Fcpu/8 |
+ | X |----------------|----------|---------|----------|---------|----------|---------|
+ | | DMA | Fcpu/2 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/16 |
+ +-----------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_S
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 50
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+ (++) CRC Length, used only with Data8 and Data16
+ (++) FIFO reception threshold
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ uint32_t frxth;
+
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+
+ if(hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Align by default the rs fifo threshold on the data size */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_HF;
+ }
+ else
+ {
+ frxth = SPI_RXFIFO_THRESHOLD_QF;
+ }
+
+ /* CRC calculation is valid only for 16Bit and 8 Bit */
+ if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
+ {
+ /* CRC must be disabled */
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ }
+
+ /* Align the CRC Length on the data size */
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ /* CRC Length aligned on the data size : value set by default */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+ }
+ else
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+ }
+ }
+
+ /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+ Communication speed, First bit, CRC calculation state, CRC Length */
+ hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
+
+ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ hspi->Instance->CR1|= SPI_CR1_CRCL;
+ }
+
+ /* Configure : NSS management */
+ /* Configure : Rx Fifo Threshold */
+ hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
+ hspi->Init.DataSize ) | frxth;
+
+ /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Configure : CRC Polynomial */
+ hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State= HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the SPI peripheral.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if(hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 16 Bit mode */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ while (hspi->TxXferCount > 0)
+ {
+ /* Wait until TXE flag is set to send data */
+ if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ {
+ if(hspi->TxXferCount > 1)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2;
+ }
+ else
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ }
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error:
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ __IO uint16_t tmpreg;
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ /* the receive process is not supported in 2Lines direction master mode */
+ /* in this case we call the TransmitReceive process */
+ /* Process Locked */
+ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
+ }
+
+ /* Set the Rx Fido threshold */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Configure communication direction 1Line and enabled SPI if needed */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ /* Transfer loop */
+ while(hspi->RxXferCount > 0)
+ {
+ /* Check the RXNE flag */
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ {
+ /* read the received data */
+ (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Transfer loop */
+ while(hspi->RxXferCount > 0)
+ {
+ /* Check the RXNE flag */
+ if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ }
+
+ /* Handle the CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* freeze the CRC before the latest data */
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+
+ /* Read the latest data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* the latest data has not been received */
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Receive last data in 16 Bit mode */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else
+ {
+ *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
+
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Flag Error*/
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size: amount of data to be sent and received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+__IO uint16_t tmpreg;
+ uint32_t tickstart = HAL_GetTick();
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Set the Rx Fido threshold */
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+ {
+ /* set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthreshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
+ {
+ /* Check TXE flag */
+ if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ }
+ }
+
+ /* Check RXNE flag */
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
+ {
+ /* check TXE flag */
+ if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ {
+ if(hspi->TxXferCount > 1)
+ {
+ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+
+ /* Enable CRC Transmission */
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ }
+
+ /* Wait until RXNE flag is reset */
+ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ {
+ if(hspi->RxXferCount > 1)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2;
+ if(hspi->RxXferCount <= 1)
+ {
+ /* set fiforxthresold before to switch on 8 bit data size */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ else
+ {
+ (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->RxXferCount--;
+ }
+ }
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
+
+ /* Read CRC from DR to close CRC calculation process */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ /* Clear CRC Flag */
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+
+ errorcode = HAL_ERROR;
+ }
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ /* prepare the transfer */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+ hspi->RxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
+
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Configure communication */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ /* the receive process is not supported in 2Lines direction master mode */
+ /* in this we call the TransmitReceive process */
+ return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
+ }
+
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1;
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2;
+ }
+ }
+ else
+ {
+ hspi->CRCSize = 0;
+ }
+
+ hspi->TxISR = NULL;
+ /* check the data size to adapt Rx threshold and the set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ /* set fiforxthresold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size: amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if(!((hspi->State == HAL_SPI_STATE_READY) || \
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->CRCSize = 0;
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1;
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2;
+ }
+ }
+
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* check if packing mode is enabled and if there is more than 2 data to receive */
+ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
+ {
+ /* set fiforxthresold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0;
+ hspi->RxXferCount = 0;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ /* packing mode is enabled only if the DMA setting is HALWORD */
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Check the even/odd of the data size + crc if enabled */
+ if((hspi->TxXferCount & 0x1) == 0)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1);
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ }
+ }
+
+ /* Enable the Tx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0;
+ hspi->TxXferCount = 0;
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ /* the receive process is not supported in 2Lines direction master mode */
+ /* in this case we call the TransmitReceive process */
+ return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
+ }
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* packing mode management is enabled by the DMA settings */
+ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Enable the Rx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if(!((hspi->State == HAL_SPI_STATE_READY) ||
+ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* check if the transmit Receive function is not called by a receive master */
+ if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Reset CRC Calculation + increase the rxsize */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ /* Reset the threshold bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
+
+ /* the packing mode management is enabled by the DMA settings according the spi data size */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ if((hspi->TxXferSize & 0x1) == 0x0)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = hspi->TxXferCount >> 1;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ }
+ }
+
+ if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if((hspi->RxXferCount & 0x1) == 0x0 )
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
+ }
+ }
+ }
+
+ /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
+ reception request (RXNE) */
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Enable the Rx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Enable the Tx DMA channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Enable the SPI DMA Tx & Rx requests */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmatx);
+ }
+ /* Abort the SPI DMA rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hspi->hdmarx);
+ }
+
+ /* Disable the SPI DMA Tx & Rx requests */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI interrupt request.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if(((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ {
+ hspi->RxISR(hspi);
+ return;
+ }
+
+ /* SPI in mode Transmitter ---------------------------------------------------*/
+ if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ {
+ hspi->TxISR(hspi);
+ return;
+ }
+
+ /* SPI in Error Treatment ---------------------------------------------------*/
+ if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+ {
+ /* SPI Overrun error interrupt occurred -------------------------------------*/
+ if((itflag & SPI_FLAG_OVR) != RESET)
+ {
+ if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ else
+ {
+ return;
+ }
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------------*/
+ if((itflag & SPI_FLAG_MODF) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ----------------------------------------*/
+ if((itflag & SPI_FLAG_FRE) != RESET)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI error callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI handle state.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI handle state */
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->TxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ __IO uint16_t tmpreg;
+
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+ }
+
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
+ hspi->RxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+ __IO int16_t tmpreg;
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ {
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ }
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0;
+ hspi->RxXferCount = 0;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in packing mode */
+ if(hspi->RxXferCount > 1)
+ {
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= 2;
+ if(hspi->RxXferCount == 1)
+ {
+ /* set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+ }
+
+ /* check end of the reception */
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ return;
+ }
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ hspi->CRCSize--;
+
+ /* check end of the reception */
+ if(hspi->CRCSize == 0)
+ {
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in packing Bit mode */
+ if(hspi->TxXferCount >= 2)
+ {
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= 2;
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+ }
+
+ /* check the end of the transmission */
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ return;
+ }
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ __IO uint16_t tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ SPI_CloseRxTx_ISR(hspi);
+}
+
+/**
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ hspi->CRCSize--;
+
+ if(hspi->CRCSize == 0)
+ {
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_8BITCRC;
+ return;
+ }
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint16_t tmpreg;
+
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ SPI_CloseRx_ISR(hspi);
+}
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+
+ if(hspi->RxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_16BITCRC;
+ return;
+ }
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ }
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag : SPI flag to check
+ * @param State : flag state to check
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ while((hspi->Instance->SR & Flag) != State)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State= HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo : Fifo to check
+ * @param State : Fifo state to check
+ * @param Timeout : Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
+{
+ __IO uint8_t tmpreg;
+ uint32_t tickstart = HAL_GetTick();
+
+ while((hspi->Instance->SR & Fifo) != State)
+ {
+ if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ {
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RX transaction complete.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout : Timeout duration
+ * @retval None.
+ */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+{
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Control the BSY flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Empty the FRLVL fifo */
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi: SPI handle
+ * @param Timeout : Timeout duration
+ */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+{
+ /* Control if the TX fifo is empty */
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ /* Control the BSY flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the end of the RXTX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Handle the end of the RX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Handle the end of the TX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable TXE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c
@@ -0,0 +1,133 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+ * @{
+ */
+#define SPI_FIFO_SIZE 4
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) Rx data flush function:
+ (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg;
+ uint8_t count = 0;
+ while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
+ {
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+ if(count == SPI_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c
@@ -0,0 +1,683 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_sram.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief SRAM HAL module driver.
+ * This file provides a generic firmware to drive SRAM memories
+ * mounted as external device.
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver is a generic layered driver which contains a set of APIs used to
+ control SRAM memories. It uses the FMC layer functions to interface
+ with SRAM devices.
+ The following sequence should be followed to configure the FMC to interface
+ with SRAM/PSRAM memories:
+
+ (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+ SRAM_HandleTypeDef hsram; and:
+
+ (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
+ values of the structure member.
+
+ (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+ base register instance for NOR or SRAM device
+
+ (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+ base register instance for NOR or SRAM extended mode
+
+ (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+ mode timings; for example:
+ FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
+ and fill its fields with the allowed values of the structure member.
+
+ (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+ performs the following sequence:
+
+ (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+ (##) Control register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Init()
+ (##) Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Timing_Init()
+ (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
+
+ (#) At this stage you can perform read/write accesses from/to the memory connected
+ to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+ following APIs:
+ (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+ (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+
+ (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
+ (#) You can continuously monitor the SRAM device HAL state by calling the function
+ HAL_SRAM_GetState()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup SRAM SRAM
+ * @brief SRAM HAL module driver
+ * @{
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+ * @{
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Initialization and de_initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to initialize/de-initialize
+ the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Performs the SRAM device initialization sequence
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param Timing: Pointer to SRAM control timing structure
+ * @param ExtTiming: Pointer to SRAM extended mode timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+ /* Check the SRAM handle parameter */
+ if(hsram == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(hsram->State == HAL_SRAM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsram->Lock = HAL_UNLOCKED;
+
+ /* Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspInit(hsram);
+ }
+
+ /* Initialize SRAM control Interface */
+ FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+ /* Initialize SRAM timing Interface */
+ FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+
+ /* Initialize SRAM extended mode timing Interface */
+ FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+
+ /* Enable the NORSRAM device */
+ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Performs the SRAM device De-initialization sequence.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* De-Initialize the low level hardware (MSP) */
+ HAL_SRAM_MspDeInit(hsram);
+
+ /* Configure the SRAM registers with their reset values */
+ FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+ hsram->State = HAL_SRAM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief SRAM MSP Init.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRAM MSP DeInit.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA transfer complete error callback.
+ * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
+ */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @brief Input Output and memory control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### SRAM Input and Output functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to use and control the SRAM memory
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads 8-bit buffer from SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint8_t *)psramaddress;
+ pDstBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 8-bit buffer to SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint8_t * psramaddress = (uint8_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *(__IO uint8_t *)psramaddress = *pSrcBuffer;
+ pSrcBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 16-bit buffer from SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint16_t *)psramaddress;
+ pDstBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 16-bit buffer to SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+{
+ __IO uint16_t * psramaddress = (uint16_t *)pAddress;
+
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *(__IO uint16_t *)psramaddress = *pSrcBuffer;
+ pSrcBuffer++;
+ psramaddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads 32-bit buffer from SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Read data from memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *pDstBuffer = *(__IO uint32_t *)pAddress;
+ pDstBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes 32-bit buffer to SRAM memory.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Write data to memory */
+ for(; BufferSize != 0; BufferSize--)
+ {
+ *(__IO uint32_t *)pAddress = *pSrcBuffer;
+ pSrcBuffer++;
+ pAddress++;
+ }
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reads a Words data from the SRAM memory using DMA transfer.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to read start address
+ * @param pDstBuffer: Pointer to destination buffer
+ * @param BufferSize: Size of the buffer to read from memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @param pAddress: Pointer to write start address
+ * @param pSrcBuffer: Pointer to source buffer to write
+ * @param BufferSize: Size of the buffer to write to memory
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+{
+ /* Check the SRAM controller state */
+ if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Configure DMA user callbacks */
+ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the SRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically SRAM write operation.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Enable write operation */
+ FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically SRAM write operation.
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+ /* Process Locked */
+ __HAL_LOCK(hsram);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_BUSY;
+
+ /* Disable write operation */
+ FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+ /* Update the SRAM controller state */
+ hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hsram);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### SRAM State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the SRAM controller
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the SRAM controller state
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL state
+ */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+ return hsram->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
@@ -0,0 +1,5312 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + Time Base Initialization
+ * + Time Base Start
+ * + Time Base Start Interruption
+ * + Time Base Start DMA
+ * + Time Output Compare/PWM Initialization
+ * + Time Output Compare/PWM Channel Configuration
+ * + Time Output Compare/PWM Start
+ * + Time Output Compare/PWM Start Interruption
+ * + Time Output Compare/PWM Start DMA
+ * + Time Input Capture Initialization
+ * + Time Input Capture Channel Configuration
+ * + Time Input Capture Start
+ * + Time Input Capture Start Interruption
+ * + Time Input Capture Start DMA
+ * + Time One Pulse Initialization
+ * + Time One Pulse Channel Configuration
+ * + Time One Pulse Start
+ * + Time Encoder Interface Initialization
+ * + Time Encoder Interface Start
+ * + Time Encoder Interface Start Interruption
+ * + Time Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + Time OCRef clear configuration
+ * + Time External Clock configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim: TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim: TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim: TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim: TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim: TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim: TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim: TIM handle
+ * @param pData: The source Buffer address.
+ * @param Length: The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim: TIM handle
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
+ * @brief Time Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the Time Output Compare.
+ (+) Stop the Time Output Compare.
+ (+) Start the Time Output Compare and enable interrupt.
+ (+) Stop the Time Output Compare and disable interrupt.
+ (+) Start the Time Output Compare and enable DMA transfer.
+ (+) Stop the Time Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim: TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim: TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim: TIM OC handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData: The source Buffer address.
+ * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
+ * @brief Time PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM OPWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the Time PWM.
+ (+) Stop the Time PWM.
+ (+) Start the Time PWM and enable interrupt.
+ (+) Stop the Time PWM and disable interrupt.
+ (+) Start the Time PWM and enable DMA transfer.
+ (+) Stop the Time PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim: TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim: TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData: The source Buffer address.
+ * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
+ * @brief Time Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the Time Input Capture.
+ (+) Stop the Time Input Capture.
+ (+) Start the Time Input Capture and enable interrupt.
+ (+) Stop the Time Input Capture and disable interrupt.
+ (+) Start the Time Input Capture and enable DMA transfer.
+ (+) Stop the Time Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim: TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim: TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim: TIM Input Capture handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim: TIM Input Capture handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim: TIM Input Capture handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim: TIM Input Capture handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
+ * @brief Time One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the Time One Pulse.
+ (+) Stop the Time One Pulse.
+ (+) Start the Time One Pulse and enable interrupt.
+ (+) Stop the Time One Pulse and disable interrupt.
+ (+) Start the Time One Pulse and enable DMA transfer.
+ (+) Stop the Time One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * @param htim: TIM OnePulse handle
+ * @param OnePulseMode: Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim: TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channels to be disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
+ * @brief Time Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the Time Encoder.
+ (+) Stop the Time Encoder.
+ (+) Start the Time Encoder and enable interrupt.
+ (+) Stop the Time Encoder and disable interrupt.
+ (+) Start the Time Encoder and enable DMA transfer.
+ (+) Stop the Time Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @param htim: TIM Encoder Interface handle
+ * @param sConfig: TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS bits */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+
+ /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
+ tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim: TIM Encoder handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim: TIM Encoder Interface handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim: TIM Encoder Interface handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim: TIM Encoder Interface handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim: TIM Encoder Interface handle
+ * @param Channel: TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim: TIM Encoder Interface handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1: The destination Buffer address for IC1.
+ * @param pData2: The destination Buffer address for IC2.
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ }
+ break;
+
+ case TIM_CHANNEL_ALL:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ default:
+ break;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim: TIM Encoder Interface handle
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if(Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ else if(Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim: TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ HAL_TIM_PeriodElapsedCallback(htim);
+ }
+ }
+ /* TIM Break input event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ HAL_TIMEx_BreakCallback(htim);
+ }
+ }
+ /* TIM Trigger detection event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ HAL_TIM_TriggerCallback(htim);
+ }
+ }
+ /* TIM commutation event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ HAL_TIMEx_CommutationCallback(htim);
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim: TIM Output Compare handle
+ * @param sConfig: TIM Output Compare configuration structure
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim: TIM IC handle
+ * @param sConfig: TIM Input Capture configuration structure
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim: TIM handle
+ * @param sConfig: TIM PWM configuration structure
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+{
+ __HAL_LOCK(htim);
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim: TIM One Pulse handle
+ * @param sConfig: TIM One Pulse configuration structure
+ * @param OutputChannel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+{
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if(OutputChannel != InputChannel)
+ {
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Ouput compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ }
+ break;
+ default:
+ break;
+ }
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim: TIM handle
+ * @param BurstBaseAddress: TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc: TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer: The Buffer address.
+ * @param BurstLength: DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t* BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ default:
+ break;
+ }
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim: TIM handle
+ * @param BurstRequestSrc: TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim: TIM handle
+ * @param BurstBaseAddress: TIM Base address from where the DMA will starts the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc: TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer: The Buffer address.
+ * @param BurstLength: DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim: TIM handle
+ * @param BurstRequestSrc: TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch(BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ }
+ break;
+ case TIM_DMA_CC1:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ break;
+ case TIM_DMA_CC2:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ break;
+ case TIM_DMA_CC3:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ }
+ break;
+ case TIM_DMA_CC4:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ }
+ break;
+ case TIM_DMA_COM:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ }
+ break;
+ case TIM_DMA_TRIGGER:
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Generate a software event
+ * @param htim: TIM handle
+ * @param EventSource: specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+ * @retval HAL status
+ * @note TIM_EVENTSOURCE_BREAK2 isn't relevant for STM32F37xx and STM32F38xx
+ * devices
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim: TIM handle
+ * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_3:
+ {
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_4:
+ {
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim: TIM handle
+ * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+ /* Reset the SMS and TS Bits */
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ }
+ break;
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI2 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR0:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
+ }
+ break;
+ case TIM_CLOCKSOURCE_ITR3:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+ }
+ break;
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim: TIM handle.
+ * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim: TIM handle.
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim: TIM handle.
+ * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the ) and the Slave
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim: TIM handle.
+ * @param Channel: TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0;
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) Timer Period elapsed callback
+ (+) Timer Output Compare callback
+ (+) Timer Input capture callback
+ (+) Timer Trigger callback
+ (+) Timer Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+
+}
+/**
+ * @brief Output Compare callback in non blocking mode
+ * @param htim: TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Input Capture callback in non blocking mode
+ * @param htim: TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base state
+ * @param htim: TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC state
+ * @param htim: TIM Ouput Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM state
+ * @param htim: TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture state
+ * @param htim: TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode state
+ * @param htim: TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode state
+ * @param htim: TIM Encoder handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Private_Functions TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief TIM DMA error callback
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_ErrorCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_PeriodElapsedCallback(htim);
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIM_TriggerCallback(htim);
+}
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx: TIM periheral
+ * @param Structure: TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1 = 0;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Time Ouput Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8);
+
+ if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Time Ouput Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef * sSlaveConfig)
+{
+ uint32_t tmpsmcr = 0;
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+
+ }
+ break;
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ }
+ break;
+
+ case TIM_TS_ITR0:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR1:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR2:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2 = 0;
+ uint32_t tmpccer = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource: The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr = 0;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param ChannelState: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
@@ -0,0 +1,2746 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal bread and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+ * + Time OCRef clear configuration
+ * + Timer remapping capabilities configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending from feature used :
+ (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
+ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
+ (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+#define BDTR_BKF_SHIFT (16)
+#define BDTR_BK2F_SHIFT (20)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config);
+
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config);
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
+ * @param htim: TIM Encoder Interface handle
+ * @param sConfig: TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if(htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the TIM state*/
+ htim->State= HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim: TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim: TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim: TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1, 2 and 3
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim: TIM Hall Sensor handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim: TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim: TIM Hall Sensor handle
+ * @param pData: The destination Buffer address.
+ * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel for Capture 1*/
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim: TIM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare.
+ (+) Stop the Complementary Output Compare.
+ (+) Start the Complementary Output Compare and enable interrupts.
+ (+) Stop the Complementary Output Compare and disable interrupts.
+ (+) Start the Complementary Output Compare and enable DMA transfers.
+ (+) Stop the Complementary Output Compare and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim: TIM OC handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData: The source Buffer address.
+ * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+{
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim: TIM Output Compare handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData: The source Buffer address.
+ * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if((htim->State == HAL_TIM_STATE_BUSY))
+ {
+ return HAL_BUSY;
+ }
+ else if((htim->State == HAL_TIM_STATE_READY))
+ {
+ if(((uint32_t)pData == 0 ) && (Length > 0))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
+
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA Period elapsed callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
+
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim: TIM handle
+ * @param Channel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * output.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Ouput */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim: TIM One Pulse handle
+ * @param OutputChannel: TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Ouput */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+ (+) Enable or disable channel grouping
+
+@endverbatim
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim: TIM handle
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource: the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim: TIM handle
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource: the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation Interrupt Request */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note this function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim: TIM handle
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource: the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim: TIM Output Compare handle
+ * @param sConfig: TIM Output Compare configuration structure
+ * @param Channel: TIM Channels to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
+ * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef* sConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 5 in Output Compare */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 6 in Output Compare */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim: TIM PWM handle
+ * @param sConfig: TIM PWM configuration structure
+ * @param Channel: TIM Channels to be configured
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
+ * STM32F398xx and STM32F303x8 up to 6 PWM channels can be configured
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef* sConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel5*/
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ }
+ break;
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel6 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim: TIM handle
+ * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_Channel_5: TIM Channel 5
+ * @arg TIM_Channel_6: TIM Channel 6
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
+ * STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
+{
+ uint32_t tmpsmcr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ switch (sClearInputConfig->ClearInputSource)
+ {
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Clear the OCREF clear selection bit */
+ tmpsmcr &= ~TIM_SMCR_OCCS;
+
+ /* Clear the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set TIMx_SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+ break;
+
+ case TIM_CLEARINPUTSOURCE_OCREFCLR:
+ {
+ /* Clear the OCREF clear selection bit */
+ htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
+ }
+ break;
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+
+ /* Set the OCREF clear selection bit */
+ htim->Instance->SMCR |= TIM_SMCR_OCCS;
+ }
+ break;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_2:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 2 */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_3:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 3 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_4:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 4 */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_5:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
+ }
+ }
+ break;
+ case TIM_CHANNEL_6:
+ {
+ if(sClearInputConfig->ClearInputState != RESET)
+ {
+ /* Enable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
+ }
+ else
+ {
+ /* Disable the Ocref clear feature for Channel 1 */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim: TIM handle.
+ * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef * sMasterConfig)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim: TIM handle.
+ * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the MMS Bits */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ htim->Instance->SMCR &= ~TIM_SMCR_MSM;
+ /* Set or Reset the MSM Bit */
+ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim: TIM handle
+ * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef
+ structure that contains the BDTR Register configuration information
+ for the TIM peripheral.
+ * @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE,
+ STM32F398xx and STM32F303x8 two break inputs can be configured.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+ {
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+ /* Clear the BDTR bits */
+ tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
+ TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
+ TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
+ TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
+
+ /* Set the BDTR bits */
+ tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
+ tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
+ tmpbdtr |= sBreakDeadTimeConfig->BreakState;
+ tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
+ tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
+ tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
+ tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
+ tmpbdtr |= sBreakDeadTimeConfig->Break2State;
+ tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
+ }
+ else
+ {
+ /* Clear the BDTR bits */
+ tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
+ TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
+ TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
+
+ /* Set the BDTR bits */
+ tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
+ tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
+ tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
+ tmpbdtr |= sBreakDeadTimeConfig->BreakState;
+ tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
+ tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
+ tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
+ }
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim: TIM handle
+ * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
+ sBreakDeadTimeConfig->OffStateIDLEMode |
+ sBreakDeadTimeConfig->LockLevel |
+ sBreakDeadTimeConfig->DeadTime |
+ sBreakDeadTimeConfig->BreakState |
+ sBreakDeadTimeConfig->BreakPolarity |
+ sBreakDeadTimeConfig->AutomaticOutput;
+
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/**
+ * @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
+ * @param htim: TIM handle.
+ * @param Remap1: specifies the first TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
+ * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
+ * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
+ * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
+ * @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
+ * @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
+ * @param Remap2: specifies the second TIMremapping source (if any).
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
+ * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
+ * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
+ * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
+ * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
+ * @arg TIM_TIM16_NONE: Non significant value for TIM16
+ * @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
+ * @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
+ * @retval HAL status
+ */
+#else /* STM32F303xC || STM32F358xx */
+/**
+ * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
+ * @param htim: TIM handle.
+ * @param Remap1: specifies the first TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
+ * @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
+ * @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
+ * @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @param Remap2: specifies the second TIMremapping source (if any).
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
+ * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
+ * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
+ * @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
+ * @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
+ * @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
+ * @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
+ * @retval HAL status
+ */
+#endif /* STM32F303xE || STM32F398xx || */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
+{
+ __HAL_LOCK(htim);
+
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap1));
+ assert_param(IS_TIM_REMAP2(Remap2));
+
+ /* Set the Timer remapping configuration */
+ htim->Instance->OR = Remap1 | Remap2;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+
+
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+#if defined(STM32F302xE) || \
+ defined(STM32F302xC) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Configures the TIM1 and TIM16 Remapping input capabilities.
+ * @param htim: TIM handle.
+ * @param Remap: specifies the TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @retval HAL status
+ */
+#else /* STM32F373xC || STM32F378xx */
+/**
+ * @brief Configures the TIM2 and TIM14 Remapping input capabilities.
+ * @param htim: TIM handle.
+ * @param Remap: specifies the TIM remapping source.
+ * This parameter can be one of the following values:
+ * STM32F373xC, STM32F378xx:
+ * @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
+ * @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
+ * @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
+ * @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
+ * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
+ * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
+ * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
+ * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
+ * @retval HAL status
+ */
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+ __HAL_LOCK(htim);
+
+ /* Check parameters */
+ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_REMAP(Remap));
+
+ /* Set the Timer remapping configuration */
+ htim->Instance->OR = Remap;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || */
+ /* STM32F302xC || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+ /* STM32F373xC || STM32F378xx */
+
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Group channel 5 and channel 1, 2 or 3
+ * @param htim: TIM handle.
+ * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
+ * This parameter can be any combination of the following values:
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
+{
+ /* Check parameters */
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_GROUPCH5(OCRef));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Clear GC5Cx bit fields */
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
+
+ /* Set GC5Cx bit fields */
+ htim->Instance->CCR5 |= OCRef;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
+ * @brief Extension Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extended TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface state
+ * @param htim: TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Private_Functions
+ * @{
+ */
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma : pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
+ HAL_TIMEx_CommutationCallback(htim);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp = 0;
+
+ tmp = TIM_CCER_CC1NE << Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+}
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/**
+ * @brief Timer Ouput Compare 5 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC5E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 16);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 8);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Ouput Compare 6 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config: The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx = 0;
+ uint32_t tmpccer = 0;
+ uint32_t tmpcr2 = 0;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC6E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 20);
+
+ if(IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 10);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c
@@ -0,0 +1,838 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_tsc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Touch Sensing Controller (TSC) peripheral:
+ * + Initialization and De-initialization
+ * + Channel IOs, Shield IOs and Sampling IOs configuration
+ * + Start and Stop an acquisition
+ * + Read acquisition result
+ * + Interrupts and flags management
+ *
+ @verbatim
+================================================================================
+ ##### TSC specific features #####
+================================================================================
+ [..]
+ (#) Proven and robust surface charge transfer acquisition principle
+
+ (#) Supports up to 3 capacitive sensing channels per group
+
+ (#) Capacitive sensing channels can be acquired in parallel offering a very good
+ response time
+
+ (#) Spread spectrum feature to improve system robustness in noisy environments
+
+ (#) Full hardware management of the charge transfer acquisition sequence
+
+ (#) Programmable charge transfer frequency
+
+ (#) Programmable sampling capacitor I/O pin
+
+ (#) Programmable channel I/O pin
+
+ (#) Programmable max count value to avoid long acquisition when a channel is faulty
+
+ (#) Dedicated end of acquisition and max count error flags with interrupt capability
+
+ (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
+ components
+
+ (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..]
+ (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
+
+ (#) GPIO pins configuration
+ (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
+ (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
+ and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
+ using HAL_GPIO_Init() function (see Table 1).
+
+ (#) Interrupts configuration
+ (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
+ and HAL_NVIC_EnableIRQ() and function.
+
+ (#) TSC configuration
+ (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
+
+[..] Table 1. IOs for the STM32L4xx devices
+ (+) +--------------------------------+
+ (+) | IOs | TSC functions |
+ (+) |--------------|-----------------|
+ (+) | PA0 (AF) | TSC_G1_IO1 |
+ (+) | PA1 (AF) | TSC_G1_IO2 |
+ (+) | PA2 (AF) | TSC_G1_IO3 |
+ (+) | PA3 (AF) | TSC_G1_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PA4 (AF) | TSC_G2_IO1 |
+ (+) | PA5 (AF) | TSC_G2_IO2 |
+ (+) | PA6 (AF) | TSC_G2_IO3 |
+ (+) | PA7 (AF) | TSC_G2_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PC5 (AF) | TSC_G3_IO1 |
+ (+) | PB0 (AF) | TSC_G3_IO2 |
+ (+) | PB1 (AF) | TSC_G3_IO3 |
+ (+) | PB2 (AF) | TSC_G3_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PA9 (AF) | TSC_G4_IO1 |
+ (+) | PA10 (AF) | TSC_G4_IO2 |
+ (+) | PA13 (AF) | TSC_G4_IO3 |
+ (+) | PA14 (AF) | TSC_G4_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PB3 (AF) | TSC_G5_IO1 |
+ (+) | PB4 (AF) | TSC_G5_IO2 |
+ (+) | PB6 (AF) | TSC_G5_IO3 |
+ (+) | PB7 (AF) | TSC_G5_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PB11 (AF) | TSC_G6_IO1 |
+ (+) | PB12 (AF) | TSC_G6_IO2 |
+ (+) | PB13 (AF) | TSC_G6_IO3 |
+ (+) | PB14 (AF) | TSC_G6_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PE2 (AF) | TSC_G7_IO1 |
+ (+) | PE3 (AF) | TSC_G7_IO2 |
+ (+) | PE4 (AF) | TSC_G7_IO3 |
+ (+) | PE5 (AF) | TSC_G7_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PD12 (AF) | TSC_G8_IO1 |
+ (+) | PD13 (AF) | TSC_G8_IO2 |
+ (+) | PD14 (AF) | TSC_G8_IO3 |
+ (+) | PD15 (AF) | TSC_G8_IO4 |
+ (+) |--------------|-----------------|
+ (+) | PB8 (AF) | TSC_SYNC |
+ (+) | PB10 (AF) | |
+ (+) +--------------------------------+
+ [..] TSC peripheral alternate functions are mapped on AF9.
+
+ *** Acquisition sequence ***
+ ===================================
+ [..]
+ (+) Discharge all IOs using HAL_TSC_IODischarge() function.
+ (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends
+ of the sampling capacitor and electrodes design.
+ (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function.
+ (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function.
+ If the synchronized mode is selected, the acquisition will start as soon as the signal
+ is received on the synchro pin.
+ (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or
+ HAL_TSC_GetState() function or using WFI instruction for example.
+ (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
+ (+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TSC TSC
+ * @brief HAL TSC module driver
+ * @{
+ */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t TSC_extract_groups(uint32_t iomask);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TSC_Exported_Functions Exported Functions
+ * @{
+ */
+
+/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the TSC.
+ (+) De-initialize the TSC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the TSC peripheral according to the specified parameters
+ * in the TSC_InitTypeDef structure and initialize the associated handle.
+ * @param htsc: TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength));
+ assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength));
+ assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum));
+ assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
+ assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
+ assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
+ assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
+ assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
+ assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
+ assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+ if(htsc->State == HAL_TSC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htsc->Lock = HAL_UNLOCKED;
+ }
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_TSC_MspInit(htsc);
+
+ /*--------------------------------------------------------------------------*/
+ /* Set TSC parameters */
+
+ /* Enable TSC */
+ htsc->Instance->CR = TSC_CR_TSCE;
+
+ /* Set all functions */
+ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
+ htsc->Init.CTPulseLowLength |
+ (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) |
+ htsc->Init.SpreadSpectrumPrescaler |
+ htsc->Init.PulseGeneratorPrescaler |
+ htsc->Init.MaxCountValue |
+ htsc->Init.IODefaultMode |
+ htsc->Init.SynchroPinPolarity |
+ htsc->Init.AcquisitionMode);
+
+ /* Spread spectrum */
+ if (htsc->Init.SpreadSpectrum == ENABLE)
+ {
+ htsc->Instance->CR |= TSC_CR_SSE;
+ }
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
+
+ /* Set the groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
+
+ /* Disable interrupts */
+ htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
+
+ /*--------------------------------------------------------------------------*/
+
+ /* Initialize the TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitialize the TSC peripheral registers to their default reset values.
+ * @param htsc: TSC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
+{
+ /* Check TSC handle allocation */
+ if (htsc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_TSC_MspDeInit(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the TSC MSP.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the TSC MSP.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_MspDeInit could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO Operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start acquisition in polling mode.
+ (+) Start acquisition in interrupt mode.
+ (+) Stop conversion in polling mode.
+ (+) Stop conversion in interrupt mode.
+ (+) Poll for acquisition completed.
+ (+) Get group acquisition status.
+ (+) Get group acquisition value.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the acquisition.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Clear interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Stop discharging the IOs */
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the acquisition in interrupt mode.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_BUSY;
+
+ /* Enable end of acquisition interrupt */
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
+
+ /* Enable max count error interrupt (optional) */
+ if (htsc->Init.MaxCountInterrupt == ENABLE)
+ {
+ __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE);
+ }
+ else
+ {
+ __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE);
+ }
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Stop discharging the IOs */
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+
+ /* Launch the acquisition */
+ __HAL_TSC_START_ACQ(htsc);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the acquisition previously launched in polling mode.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the acquisition previously launched in interrupt mode.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop the acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Disable interrupts */
+ __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
+
+ /* Clear flags */
+ __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
+
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start acquisition and wait until completion.
+ * @note There is no need of a timeout parameter as the max count error is already
+ * managed by the TSC peripheral.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Check end of acquisition */
+ while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
+ {
+ /* The timeout (max count error) is managed by the TSC peripheral itself. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the acquisition status for a group.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index: Index of the group
+ * @retval Group status
+ */
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+ /* Return the group status */
+ return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
+}
+
+/**
+ * @brief Get the acquisition measure for a group.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param gx_index: Index of the group
+ * @retval Acquisition measure
+ */
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
+
+ /* Return the group acquisition counter */
+ return htsc->Instance->IOGXCR[gx_index];
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure TSC IOs
+ (+) Discharge TSC IOs
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure TSC IOs.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param config: pointer to the configuration structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Stop acquisition */
+ __HAL_TSC_STOP_ACQ(htsc);
+
+ /* Disable Schmitt trigger hysteresis on all used TSC IOs */
+ htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
+
+ /* Set channel and shield IOs */
+ htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
+
+ /* Set sampling IOs */
+ htsc->Instance->IOSCR = config->SamplingIOs;
+
+ /* Set groups to be acquired */
+ htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Discharge TSC IOs.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param choice: enable or disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (choice == ENABLE)
+ {
+ __HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
+ }
+ else
+ {
+ __HAL_TSC_SET_IODEF_INFLOAT(htsc);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ /* Return the group acquisition counter */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Get TSC state.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TSC handle state.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ if (htsc->State == HAL_TSC_STATE_BUSY)
+ {
+ /* Check end of acquisition flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Check max count error flag */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+ }
+ }
+ }
+
+ /* Return TSC state */
+ return htsc->State;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief Handle TSC interrupt request.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Check if the end of acquisition occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Clear EOA flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
+ }
+
+ /* Check if max count error occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Clear MCE flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+ /* Conversion completed callback */
+ HAL_TSC_ErrorCallback(htsc);
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+ /* Conversion completed callback */
+ HAL_TSC_ConvCpltCallback(htsc);
+ }
+}
+
+/**
+ * @brief Acquisition completed callback in non-blocking mode.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ConvCpltCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Error callback in non-blocking mode.
+ * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TSC_ErrorCallback could be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TSC_Private_Functions Private Functions
+ * @{
+ */
+
+/**
+ * @brief Utility function used to set the acquired groups mask.
+ * @param iomask: Channels IOs mask
+ * @retval Acquired groups mask
+ */
+static uint32_t TSC_extract_groups(uint32_t iomask)
+{
+ uint32_t groups = 0;
+ uint32_t idx;
+
+ for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++)
+ {
+ if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET)
+ {
+ groups |= ((uint32_t)1 << idx);
+ }
+ }
+
+ return groups;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
@@ -0,0 +1,2096 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) are managed using the macros
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+ in the huart handle AdvancedInit structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+ by calling the HAL_LIN_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
+ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customized HAL_UART_MspInit() API.
+
+ Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+ (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_UART_RxCpltCallback
+ (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_UART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
+ *** UART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in UART HAL driver.
+
+ (+) __HAL_UART_ENABLE: Enable the UART peripheral
+ (+) __HAL_UART_DISABLE: Disable the UART peripheral
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+
+ [..]
+ (@) You can refer to the UART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief UART HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+#define UART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< UART TX or RX enable acknowledge time-out value */
+#define UART_TXDMA_TIMEOUTVALUE 22000
+#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible UART frame formats are as listed in the following table:
+
+ (+++) Table 1. UART frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | UART frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | UART frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init()
+ API follow respectively the UART asynchronous, UART Half duplex, UART LIN mode and
+ multiprocessor configuration procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ huart->Instance->CR3 |= USART_CR3_HDSEL;
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle .
+ * @param huart: UART handle.
+ * @param BreakDetectLength: specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
+ * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if(huart->Init.WordLength != UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ huart->Instance->CR2 |= USART_CR2_LINEN;
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart: UART handle.
+ * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod: specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
+ * @note If the user resorts to idle line detection wake up, the Address parameter
+ * is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length detection
+ * is configured by default to 4 bits only. For the UART to be able to
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the wake up method parameter */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+ {
+ /* If address mark wake up method is chosen, set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+ }
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief DeInitialize the UART peripheral.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0;
+ huart->Instance->CR2 = 0x0;
+ huart->Instance->CR3 = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->State = HAL_UART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the UART MSP.
+ * @param huart: UART handle.
+ * @retval None
+ */
+ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the UART MSP.
+ * @param huart: UART handle.
+ * @retval None
+ */
+ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
+
+ (#) No-Blocking mode API's with Interrupt are :
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
+
+ (#) No-Blocking mode API's with DMA are :
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
+
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @param huart: UART handle.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ while(huart->TxXferCount > 0)
+ {
+ huart->TxXferCount--;
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pData += 2;
+ }
+ else
+ {
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ /* Check if a non-blocking receive Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp;
+ uint16_t uhMask;
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* as long as data have to be received */
+ while(huart->RxXferCount > 0)
+ {
+ huart->RxXferCount--;
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData ;
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ pData +=2;
+ }
+ else
+ {
+ *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ /* Check if a non-blocking transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Transmit Data Register Empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ /* Enable the UART Parity Error Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Data Register not empty Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @note This function starts a DMA transfer in interrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check if UART instance supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Enable the UART transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ huart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note This function starts a DMA transfer in interrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ /* Check if UART instance supports continuous communication using DMA */
+ assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
+
+ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ {
+ if((pData == NULL ) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Enable the DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ huart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Disable the UART DMA Tx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Disable the UART DMA Rx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ /* Disable the UART DMA Tx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ /* Disable the UART DMA Rx request */
+ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ huart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Enable the UART DMA Rx request */
+ huart->Instance->CR3 |= USART_CR3_DMAR;
+ }
+ else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Enable the UART DMA Rx request before the DMA Tx request */
+ huart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Enable the UART DMA Tx request */
+ huart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+ HAL_UART_TxHalfCpltCallback() / HAL_UART_RxHalfCpltCallback ():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
+ generated if the DMA transfer interruption occurs at the middle or at the end of the stream
+ and the corresponding call back is executed.
+ */
+
+ /* Disable the UART Tx/Rx DMA requests */
+ huart->Instance->CR3 &= ~USART_CR3_DMAT;
+ huart->Instance->CR3 &= ~USART_CR3_DMAR;
+
+ /* Abort the UART DMA tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ /* Abort the UART DMA rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+
+ huart->State = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART interrupt request.
+ * @param huart: UART handle.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ HAL_UART_ErrorCallback(huart);
+ }
+
+ /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
+ /* Set the UART state ready to be able to start again the process */
+ huart->State = HAL_UART_STATE_READY;
+ HAL_UARTEx_WakeupCallback(huart);
+ }
+
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
+ {
+ UART_Transmit_IT(huart);
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
+ {
+ UART_EndTransmit_IT(huart);
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param huart: UART handle.
+ * @retval None
+ */
+ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param huart: UART handle.
+ * @retval None
+ */
+ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param huart: UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param huart: UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART error callback.
+ * @param huart: UART handle.
+ * @retval None
+ */
+ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ huart->Instance->CR1 |= USART_CR1_MME;
+
+ huart->State = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
+ * as it may not have been in mute mode at this very moment).
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ huart->Instance->CR1 &= ~(USART_CR1_MME);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart: UART handle.
+ * @retval None
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart: UART handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->State = HAL_UART_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Transmit break characters.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the UART handle state.
+ * @param huart : pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ return huart->State;
+}
+
+/**
+* @brief Return the UART handle error code.
+* @param huart : pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+* @retval UART Error Code
+*/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the UART peripheral.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg = 0x00000000;
+ UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
+ uint16_t brrtemp = 0x0000;
+ uint16_t usartdiv = 0x0000;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+
+ /* Check UART Over Sampling to set Baud Rate Register */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ brrtemp = usartdiv & 0xFFF0;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+ }
+
+ return ret;
+
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart: UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @brief Check the UART Idle State.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Check if the Transmitter is enabled */
+ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->State= HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Handle UART Communication Timeout.
+ * @param huart: UART handle.
+ * @param Flag: specifies the UART flag to check.
+ * @param Status: the Flag status (SET or RESET).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_UART_TxCpltCallback(huart);
+ }
+
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_TxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+ }
+
+ HAL_UART_RxCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_UART_RxHalfCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ huart->RxXferCount = 0;
+ huart->TxXferCount = 0;
+ huart->State= HAL_UART_STATE_READY;
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+
+ if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ {
+
+ if(huart->TxXferCount == 0)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pTxBuffPtr;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ huart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+
+ huart->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_RX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_TxCpltCallback(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = huart->Mask;
+
+ if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ {
+
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ huart->pRxBuffPtr +=2;
+ }
+ else
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ if(--huart->RxXferCount == 0)
+ {
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_RxCpltCallback(huart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart: UART handle
+ * @param WakeUpSelection: UART wake up from stop mode parameters
+ * @retval HAL status
+ */
+void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
@@ -0,0 +1,459 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief Extended UART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx
+ * @brief UART Extension HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length (Fixed to 8-bits only for LIN mode)
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible UART frame formats are as listed in the following table:
+
+ (+++) Table 1. UART frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | UART frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | UART frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_RS485Ex_Init() API follows respectively the UART RS485 mode
+ configuration procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart: UART handle.
+ * @param Polarity: select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg UART_DE_POLARITY_HIGH: DE signal is active high
+ * @arg UART_DE_POLARITY_LOW: DE signal is active low
+ * @param AssertionTime: Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime: Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+{
+ uint32_t temp = 0x0;
+
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
+ * @brief Extended UART Interrupt handling function
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation function #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to manage the UART interrupts
+ and to handle Wake up interrupt call-back.
+
+ (#) Callback provided in No_Blocking mode:
+ (++) HAL_UARTEx_WakeupCallback()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief UART wakeup from Stop mode callback
+ * @param huart: UART handle
+ * @retval None
+ */
+ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control function #####
+ ===============================================================================
+ [..]
+ This subsection provides extended functions allowing to control the UART.
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
+ (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
+ long as UART clock is HSI or LSE
+ (+) HAL_UARTEx_DisableStopMode() API disables the above feature
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @param huart: UART handle.
+ * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
+ * This parameter can be one of the following values:
+ * @arg UART_WAKEUP_ON_ADDRESS
+ * @arg UART_WAKEUP_ON_STARTBIT
+ * @arg UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* check the wake-up from stop mode UART instance */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the wake-up selection scheme */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ {
+ UART_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Wait until REACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Initialize the UART State */
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+
+/**
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Check parameter */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Set UESM bit */
+ SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode.
+ * @param huart: UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Check parameter */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Clear UESM bit */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ huart->State = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart: UART handle.
+ * @param AddressLength: this parameter can be one of the following values:
+ * @arg UART_ADDRESS_DETECT_4B: 4-bit long address
+ * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->State = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->State to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c
@@ -0,0 +1,1911 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_usart.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief USART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
+ * Peripheral (USART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure these USART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) USART interrupts handling:
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+ (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
+
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ (#) Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_USART_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
+ *** USART HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in USART HAL driver.
+
+ (+) __HAL_USART_ENABLE: Enable the USART peripheral
+ (+) __HAL_USART_DISABLE: Disable the USART peripheral
+ (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+ (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+ (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
+
+ [..]
+ (@) You can refer to the USART HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USART USART
+ * @brief USART HAL module driver
+ * @{
+ */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_TXDMA_TIMEOUTVALUE 22000
+#define USART_TIMEOUT_VALUE 22000
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
+ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USART
+ in asynchronous and in synchronous modes.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible USART frame formats are as listed in the following table:
+ (+++) Table 1. USART frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | USART frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | USART frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (++) USART polarity
+ (++) USART phase
+ (++) USART LastBit
+ (++) Receiver/transmitter modes
+
+ [..]
+ The HAL_USART_Init() function follows the USART synchronous configuration
+ procedure (details for the procedure are available in reference manual).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and initialize the associated handle.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ if(husart->State == HAL_USART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_USART_MspInit(husart);
+ }
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_USART_DISABLE(husart);
+
+ /* Set the Usart Communication parameters */
+ if (USART_SetConfig(husart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ husart->Instance->CR2 &= ~USART_CR2_LINEN;
+ husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* Enable the Peripheral */
+ __HAL_USART_ENABLE(husart);
+
+ /* TEACK and/or REACK to check before moving husart->State to Ready */
+ return (USART_CheckIdleState(husart));
+}
+
+/**
+ * @brief DeInitialize the USART peripheral.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
+{
+ /* Check the USART handle allocation */
+ if(husart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_USART_INSTANCE(husart->Instance));
+
+ husart->State = HAL_USART_STATE_BUSY;
+
+ husart->Instance->CR1 = 0x0;
+ husart->Instance->CR2 = 0x0;
+ husart->Instance->CR3 = 0x0;
+
+ /* DeInit the low level hardware */
+ HAL_USART_MspDeInit(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_RESET;
+
+ /* Process Unlock */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the USART MSP.
+ * @param husart: USART handle.
+ * @retval None
+ */
+ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the USART MSP.
+ * @param husart: USART handle.
+ * @retval None
+ */
+ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ data transfers.
+
+ [..] The USART supports master mode only: it cannot receive or send data related to an input
+ clock (SCLK is always an output).
+
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode APIs are :
+ (++) HAL_USART_Transmit()in simplex mode
+ (++) HAL_USART_Receive() in full duplex receive only
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) No-Blocking mode APIs with Interrupt are :
+ (++) HAL_USART_Transmit_IT()in simplex mode
+ (++) HAL_USART_Receive_IT() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_IRQHandler()
+
+ (#) No-Blocking mode APIs with DMA are :
+ (++) HAL_USART_Transmit_DMA()in simplex mode
+ (++) HAL_USART_Receive_DMA() in full duplex receive only
+ (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
+ (++) HAL_USART_DMAPause()
+ (++) HAL_USART_DMAResume()
+ (++) HAL_USART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in No-Blocking mode:
+ (++) HAL_USART_TxCpltCallback()
+ (++) HAL_USART_RxCpltCallback()
+ (++) HAL_USART_TxHalfCpltCallback()
+ (++) HAL_USART_RxHalfCpltCallback()
+ (++) HAL_USART_ErrorCallback()
+ (++) HAL_USART_TxRxCpltCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Simplex send an amount of data in blocking mode.
+ * @param husart: USART handle.
+ * @param pTxData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Check the remaining data to be sent */
+ while(husart->TxXferCount > 0)
+ {
+ husart->TxXferCount--;
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pTxData += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
+ }
+ }
+
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart: USART handle.
+ * @param pRxData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* as long as data have to be received */
+ while(husart->RxXferCount > 0)
+ {
+ husart->RxXferCount--;
+
+ /* Wait until TC flag is set to send dummy byte in order to generate the
+ * clock for the slave to send data.
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * can be written for all the cases. */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pRxData ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ pRxData +=2;
+ }
+ else
+ {
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to TX data buffer.
+ * @param pRxData: pointer to RX data buffer.
+ * @param Size: amount of data to be sent (same amount to be received).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ husart->RxXferSize = Size;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+ husart->RxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+ uhMask = husart->Mask;
+
+ /* Check the remain data to be sent */
+ while(husart->TxXferCount > 0)
+ {
+ husart->TxXferCount--;
+ husart->RxXferCount--;
+
+ /* Wait until TC flag is set to send data */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pTxData;
+ husart->Instance->TDR = (*tmp & uhMask);
+ pTxData += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+ }
+
+ /* Wait for RXNE Flag */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pRxData ;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ pRxData +=2;
+ }
+ else
+ {
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+ are not managed by the USART Transmit Process to avoid the overrun interrupt
+ when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
+ to benefit for the frame error and noise interrupts the usart mode should be
+ configured only for transmit "USART_MODE_TX" */
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart: USART handle.
+ * @param pRxData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Enable the USART Parity Error Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+
+ /* Enable the USART Data Register not empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+
+ /* Send dummy byte in order to generate the clock for the Slave to send the next data */
+ if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF);
+ }
+ else
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to TX data buffer.
+ * @param pRxData: pointer to RX data buffer.
+ * @param Size: amount of data to be sent (same amount to be received).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->RxXferCount = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ /* Computation of USART mask to apply to RDR register */
+ USART_MASK_COMPUTATION(husart);
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Enable the USART Data Register not empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
+
+ /* Enable the USART Parity Error Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @note This function starts a DMA transfer in interrrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+{
+ uint32_t *tmp=0;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+ husart->TxXferCount = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX;
+
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param husart: USART handle.
+ * @param pRxData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @note When the USART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position)
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note This function starts a DMA transfer in interrrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pRxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive mode */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to TX data buffer.
+ * @param pRxData: pointer to RX data buffer.
+ * @param Size: amount of data to be received/sent.
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note This function starts a 2 DMA transfers in interrrupt mode meaning that
+ * DMA half transfer complete, DMA transfer complete and DMA transfer
+ * error interrupts are enabled
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if(husart->State == HAL_USART_STATE_READY)
+ {
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
+
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ husart->State = HAL_USART_STATE_BUSY_TX_RX;
+
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
+
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t*)&pRxData;
+ HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t*)&pTxData;
+ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the USART DMA Tx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Disable the USART DMA Rx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+ /* Disable the USART DMA Tx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ /* Disable the USART DMA Rx request */
+ husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
+{
+ /* Process Locked */
+ __HAL_LOCK(husart);
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Enable the USART DMA Tx request */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+ /* Enable the USART DMA Rx request */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+ }
+ else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
+ /* Enable the USART DMA Rx request before the DMA Tx request */
+ husart->Instance->CR3 |= USART_CR3_DMAR;
+
+ /* Enable the USART DMA Tx request */
+ husart->Instance->CR3 |= USART_CR3_DMAT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+ HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
+ generated if the DMA transfer interruption occurs at the middle or at the end of the stream
+ and the corresponding call back is executed.
+ */
+
+ /* Disable the USART Tx/Rx DMA requests */
+ husart->Instance->CR3 &= ~USART_CR3_DMAT;
+ husart->Instance->CR3 &= ~USART_CR3_DMAR;
+
+ /* Abort the USART DMA tx channel */
+ if(husart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ /* Abort the USART DMA rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle USART interrupt request.
+ * @param husart: USART handle.
+ * @retval None
+ */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+
+ /* USART parity error interrupt occurred ------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* USART frame error interrupt occurred -------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* USART noise error interrupt occurred -------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* USART Over-Run interrupt occurred ----------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ /* Set the USART state ready to be able to start again the process */
+ husart->State = HAL_USART_STATE_READY;
+ }
+
+ /* Call USART Error Call back function if need be --------------------------*/
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ HAL_USART_ErrorCallback(husart);
+ }
+
+ /* USART in mode Receiver --------------------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ /* USART in mode Transmitter -----------------------------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ USART_Transmit_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ /* USART in mode Transmitter (transmission end) -----------------------------*/
+ if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET))
+ {
+ USART_EndTransmit_IT(husart);
+ }
+
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param husart: USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param husart: USART handle
+ * @retval None
+ */
+ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param husart: USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_USART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param husart: USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart: USART handle
+ * @retval None
+ */
+__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_TxRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART error callback.
+ * @param husart: USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief USART Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the USART handle state
+ (+) Return the USART handle error code
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Return the USART handle state.
+ * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle state
+ */
+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+{
+ return husart->State;
+}
+
+/**
+ * @brief Return the USART error code.
+ * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle Error Code
+ */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+{
+ return husart->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @brief USART Private functions
+ *
+@verbatim
+ [..]
+ This subsection provides a set of functions allowing to control the USART.
+ (+) USART_SetConfig() API is used to set the USART communication parameters.
+ (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the USART peripheral.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
+{
+ uint32_t tmpreg = 0x0;
+ USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint16_t brrtemp = 0x0000;
+ uint16_t usartdiv = 0x0000;
+
+ /* Check the parameters */
+ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
+ assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
+ assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
+ assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
+ assert_param(IS_USART_PARITY(husart->Init.Parity));
+ assert_param(IS_USART_MODE(husart->Init.Mode));
+
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
+ * set PCE and PS bits according to husart->Init.Parity value
+ * set TE and RE bits according to husart->Init.Mode value
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
+ MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
+ * set CPOL bit according to husart->Init.CLKPolarity value
+ * set CPHA bit according to husart->Init.CLKPhase value
+ * set LBCL bit according to husart->Init.CLKLastBit value
+ * set STOP[13:12] bits according to husart->Init.StopBits value */
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+ tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
+ tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
+ MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* no CR3 register configuration */
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
+ USART_GETCLOCKSOURCE(husart, clocksource);
+ switch (clocksource)
+ {
+ case USART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_PCLK2:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ brrtemp = usartdiv & 0xFFF0;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ husart->Instance->BRR = brrtemp;
+
+ return ret;
+}
+
+/**
+ * @brief Check the USART Idle State.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
+{
+ /* Initialize the USART ErrorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Check if the Transmitter is enabled */
+ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout Occured */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* REACK bit in ISR is checked only when available (not to be checked on all instances).
+ Bit is defined only for USART instances supporting WakeUp from Stop Mode feature.
+ */
+ if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
+ {
+ /* Check if the Receiver is enabled */
+ if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Initialize the USART state*/
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Handle USART Communication Timeout.
+ * @param husart: USART handle.
+ * @param Flag: specifies the USART flag to check.
+ * @param Status: the Flag status (SET or RESET).
+ * @param Timeout: timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait until flag is set */
+ if(Status == RESET)
+ {
+ while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->TxXferCount = 0;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ husart->Instance->CR3 &= ~(USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ }
+ /* DMA Circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ HAL_USART_TxCpltCallback(husart);
+ }
+ }
+}
+
+
+/**
+ * @brief DMA USART transmit process half complete callback.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART receive process complete callback.
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->RxXferCount = 0;
+
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+ in USART CR3 register */
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+ /* similarly, disable the DMA TX transfer that was started to provide the
+ clock to the slave device */
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ husart->State= HAL_USART_STATE_READY;
+ }
+ /* DMA circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+
+}
+
+/**
+ * @brief DMA USART receive process half complete callback.
+ * @param hdma : DMA handle.
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication error callback.
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->RxXferCount = 0;
+ husart->TxXferCount = 0;
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State= HAL_USART_STATE_READY;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+
+ if(husart->TxXferCount == 0)
+ {
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ husart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+
+ husart->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Wraps up transmission in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+{
+ /* Disable the USART Transmit Complete Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxCpltCallback(husart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @param husart: USART handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask = husart->Mask;
+
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+
+ if(--husart->RxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+ /* Disable the USART Parity Error Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_RxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_TransmitReceive_IT().
+ * @param husart: USART handle.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+{
+ uint16_t* tmp=0;
+ uint16_t uhMask = husart->Mask;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ {
+
+ if(husart->TxXferCount != 0x00)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+ {
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
+ husart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
+ }
+ husart->TxXferCount--;
+
+ /* Check the latest data transmitted */
+ if(husart->TxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ }
+ }
+ }
+
+ if(husart->RxXferCount != 0x00)
+ {
+ if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+ {
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2;
+ }
+ else
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
+ husart->RxXferCount--;
+ }
+ }
+
+ /* Check the latest data received */
+ if(husart->RxXferCount == 0)
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+
+ /* Disable the USART Parity Error Interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+
+ husart->State = HAL_USART_STATE_READY;
+
+ HAL_USART_TxRxCpltCallback(husart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
@@ -0,0 +1,458 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_wwdg.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief WWDG HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Window Watchdog (WWDG) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State functions
+ @verbatim
+ ==============================================================================
+ ##### WWDG specific features #####
+ ==============================================================================
+ [..]
+ Once enabled the WWDG generates a system reset on expiry of a programmed
+ time period, unless the program refreshes the counter (T[6;0] downcounter)
+ before reaching 0x3F value (i.e. a reset is generated when the counter
+ value rolls over from 0x40 to 0x3F).
+
+ (+) An MCU reset is also generated if the counter value is refreshed
+ before the counter has reached the refresh window value. This
+ implies that the counter must be refreshed in a limited window.
+ (+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
+ occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
+ (+) The WWDG counter input clock is derived from the APB clock divided
+ by a programmable prescaler.
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock
+ where T[5;0] are the lowest 6 bits of Counter.
+ (+) WWDG Counter refresh is allowed between the following limits :
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+ (+) Set the WWDG prescaler, refresh window and counter value
+ using HAL_WWDG_Init() function.
+ (+) Start the WWDG using HAL_WWDG_Start() function.
+ When the WWDG is enabled the counter value should be configured to
+ a value greater than 0x40 to prevent generating an immediate reset.
+ (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
+ generated when the counter reaches 0x40, and then start the WWDG using
+ HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback() is executed and user can
+ add his own code by customization of function pointer HAL_WWDG_WakeupCallback().
+ Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) The application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset using
+ HAL_WWDG_Refresh() function. This operation must occur only when
+ the counter is lower than the refresh window value already programmed.
+
+ *** WWDG HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in WWDG HAL driver.
+
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
+ (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup WWDG WWDG
+ * @brief WWDG HAL module driver.
+ * @{
+ */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize the WWDG according to the specified parameters
+ in the WWDG_InitTypeDef and initialize the associated handle.
+ (+) DeInitialize the WWDG peripheral.
+ (+) Initialize the WWDG MSP.
+ (+) DeInitialize the WWDG MSP.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the WWDG according to the specified
+ * parameters in the WWDG_InitTypeDef and initialize the associated handle.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the WWDG handle allocation */
+ if(hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+ assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+
+ if(hwwdg->State == HAL_WWDG_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hwwdg->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_WWDG_MspInit(hwwdg);
+ }
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Set WWDG Prescaler and Window */
+ MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+ /* Set WWDG Counter */
+ MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitialize the WWDG peripheral.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check the WWDG handle allocation */
+ if(hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_WWDG_MspDeInit(hwwdg);
+
+ /* Reset WWDG Control register */
+ hwwdg->Instance->CR = (uint32_t)0x0000007F;
+
+ /* Reset WWDG Configuration register */
+ hwwdg->Instance->CFR = (uint32_t)0x0000007F;
+
+ /* Reset WWDG Status register */
+ hwwdg->Instance->SR = 0;
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the WWDG MSP.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the WWDG MSP.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the WWDG.
+ (+) Refresh the WWDG.
+ (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the WWDG.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Process Locked */
+ __HAL_LOCK(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Enable the peripheral */
+ __HAL_WWDG_ENABLE(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Start the WWDG with interrupt enabled.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Process Locked */
+ __HAL_LOCK(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Enable the Early Wakeup Interrupt */
+ __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
+
+ /* Enable the peripheral */
+ __HAL_WWDG_ENABLE(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Refresh the WWDG.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @param Counter: value of counter to put in WWDG counter
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
+{
+ /* Process Locked */
+ __HAL_LOCK(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+
+ /* Write to WWDG CR the WWDG Counter value to refresh with */
+ MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, Counter);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle WWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+ /* Check if Early Wakeup Interrupt is enable */
+ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ {
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
+ /* Early Wakeup callback */
+ HAL_WWDG_WakeupCallback(hwwdg);
+
+ /* Change WWDG peripheral state */
+ hwwdg->State = HAL_WWDG_STATE_READY;
+
+ /* Clear the WWDG Early Wakeup flag */
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hwwdg);
+ }
+ }
+}
+
+/**
+ * @brief Early Wakeup WWDG callback.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval None
+ */
+__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_WakeupCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the WWDG handle state.
+ * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @retval HAL state
+ */
+HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
+{
+ return hwwdg->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c
new file mode 100644
--- /dev/null
+++ b/drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c
@@ -0,0 +1,1000 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_fmc.c
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 13-November-2015
+ * @brief FMC Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
+ * + Initialization/de-initialization functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### FMC peripheral features #####
+ ==============================================================================
+ [..] The Flexible memory controller (FMC) includes following memory controllers:
+ (+) The NOR/PSRAM memory controller
+ (+) The NAND/PC Card memory controller
+
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static
+ memories and 16-bit PC memory cards. Its main purposes are:
+ (+) to translate AHB transactions into the appropriate external device protocol.
+ (+) to meet the access time requirements of the external memory devices.
+
+ [..] All external memories share the addresses, data and control signals with the controller.
+ Each external device is accessed by means of a unique Chip Select. The FMC performs
+ only one access at a time to an external device.
+ The main features of the FMC controller are the following:
+ (+) Interface with static-memory mapped devices including:
+ (++) Static random access memory (SRAM).
+ (++) NOR Flash memory.
+ (++) PSRAM (4 memory banks).
+ (++) 16-bit PC Card compatible devices.
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+ data
+ (+) Independent Chip Select control for each memory bank
+ (+) Independent configuration for each memory bank
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2015 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/** @addtogroup STM32F3xx_HAL_Driver
+ * @{
+ */
+
+#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup FMC_LL FMC Low Layer
+ * @brief FMC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
+ * @{
+ */
+
+/* ----------------------- FMC registers bit mask --------------------------- */
+/* --- BCRx Register ---*/
+/* BCRx register clear mask */
+#define BCRx_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
+ FMC_BCRx_MTYP | FMC_BCRx_MWID |\
+ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
+ FMC_BCRx_WAITPOL | FMC_BCRx_WRAPMOD |\
+ FMC_BCRx_WAITCFG | FMC_BCRx_WREN |\
+ FMC_BCRx_WAITEN | FMC_BCRx_EXTMOD |\
+ FMC_BCRx_ASYNCWAIT | FMC_BCRx_CBURSTRW))
+/* --- BTRx Register ---*/
+/* BTRx register clear mask */
+#define BTRx_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
+ FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
+ FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
+ FMC_BTRx_ACCMOD))
+
+/* --- BWTRx Register ---*/
+/* BWTRx register clear mask */
+#define BWTRx_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSETx | FMC_BWTRx_ADDHLDx |\
+ FMC_BWTRx_DATASTx | FMC_BWTRx_ACCMODx))
+
+/* --- PCRx Register ---*/
+/* PCRx register clear mask */
+#define PCRx_CLEAR_MASK ((uint32_t)(FMC_PCRx_PWAITEN | FMC_PCRx_PBKEN |\
+ FMC_PCRx_PTYP | FMC_PCRx_PWID |\
+ FMC_PCRx_ECCEN | FMC_PCRx_TCLR |\
+ FMC_PCRx_TAR | FMC_PCRx_ECCPS))
+
+/* --- SRx Register ---*/
+/* SRx register clear mask */
+#define SRx_CLEAR_MASK ((uint32_t)(FMC_SRx_FEMPT))
+
+/* --- PMEMx Register ---*/
+/* PMEMx register clear mask */
+#define PMEMx_CLEAR_MASK ((uint32_t)(FMC_PMEMx_MEMSETx | FMC_PMEMx_MEMWAITx |\
+ FMC_PMEMx_MEMHOLDx | FMC_PMEMx_MEMHIZx))
+
+/* --- PATTx Register ---*/
+/* PATTx register clear mask */
+#define PATTx_CLEAR_MASK ((uint32_t)(FMC_PATTx_ATTSETx | FMC_PATTx_ATTWAITx |\
+ FMC_PATTx_ATTHOLDx | FMC_PATTx_ATTHIZx))
+/* --- PIO4 Register ---*/
+/* PIO4 register clear mask */
+#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 |\
+ FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+ * @{
+ */
+
+/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
+ * @brief NORSRAM Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NORSRAM device driver #####
+ ==============================================================================
+
+ [..]
+ This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
+ to run the NORSRAM external devices.
+
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+ (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
+ (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
+ (+) FMC NORSRAM bank extended timing configuration using the function
+ FMC_NORSRAM_Extended_Timing_Init()
+ (+) FMC NORSRAM bank enable/disable write operation using the functions
+ FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
+
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NORSRAM interface
+ (+) De-initialize the FMC NORSRAM interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the FMC_NORSRAM device according to the specified
+ * control parameters in the FMC_NORSRAM_InitTypeDef
+ * @param Device: Pointer to NORSRAM device instance
+ * @param Init: Pointer to NORSRAM Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
+ assert_param(IS_FMC_MUX(Init->DataAddressMux));
+ assert_param(IS_FMC_MEMORY(Init->MemoryType));
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
+ assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+ assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+ assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
+ assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
+ assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
+ assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
+ assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+
+ /* Disable NORSRAM Device */
+ __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
+ /* Set NORSRAM device control parameters */
+ if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+ {
+ MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE |\
+ Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WrapMode |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst |\
+ Init->ContinuousClock)
+ );
+ }
+ else
+ {
+ MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE |\
+ Init->DataAddressMux |\
+ Init->MemoryType |\
+ Init->MemoryDataWidth |\
+ Init->BurstAccessMode |\
+ Init->WaitSignalPolarity |\
+ Init->WrapMode |\
+ Init->WaitSignalActive |\
+ Init->WriteOperation |\
+ Init->WaitSignal |\
+ Init->ExtendedMode |\
+ Init->AsynchronousWait |\
+ Init->WriteBurst |\
+ Init->ContinuousClock)
+ );
+ }
+
+ /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+ if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+ {
+ Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCRx_BURSTEN | FMC_BCR1_CCLKEN, (uint32_t)(Init->BurstAccessMode |\
+ Init->ContinuousClock));
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitialize the FMC_NORSRAM peripheral
+ * @param Device: Pointer to NORSRAM device instance
+ * @param ExDevice: Pointer to NORSRAM extended mode device instance
+ * @param Bank: NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable the FMC_NORSRAM device */
+ __FMC_NORSRAM_DISABLE(Device, Bank);
+
+ /* De-initialize the FMC_NORSRAM device */
+ /* FMC_NORSRAM_BANK1 */
+ if(Bank == FMC_NORSRAM_BANK1)
+ {
+ Device->BTCR[Bank] = 0x000030DB;
+ }
+ /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
+ else
+ {
+ Device->BTCR[Bank] = 0x000030D2;
+ }
+
+ Device->BTCR[Bank + 1] = 0x0FFFFFFF;
+ ExDevice->BWTR[Bank] = 0x0FFFFFFF;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initialize the FMC_NORSRAM Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device: Pointer to NORSRAM device instance
+ * @param Timing: Pointer to NORSRAM Timing structure
+ * @param Bank: NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+ uint32_t tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+ assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Set FMC_NORSRAM device timing parameters */
+ MODIFY_REG(Device->BTCR[Bank + 1], \
+ BTRx_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\
+ ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\
+ ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) |\
+ (((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV)) |\
+ (((Timing->DataLatency)-2) << POSITION_VAL(FMC_BTRx_DATLAT)) |\
+ (Timing->AccessMode)));
+
+ /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+ if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+ {
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
+ tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV));
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
+ * parameters in the FMC_NORSRAM_TimingTypeDef
+ * @param Device: Pointer to NORSRAM device instance
+ * @param Timing: Pointer to NORSRAM Timing structure
+ * @param Bank: NORSRAM bank number
+ * @param ExtendedMode: FMC Extended Mode
+ * This parameter can be one of the following values:
+ * @arg FMC_EXTENDED_MODE_DISABLE
+ * @arg FMC_EXTENDED_MODE_ENABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+ {
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
+ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ MODIFY_REG(Device->BWTR[Bank], \
+ BWTRx_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime |\
+ ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\
+ ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\
+ (Timing->AccessMode)));
+ }
+ else
+ {
+ Device->BWTR[Bank] = 0x0FFFFFFF;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_NORSRAM_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NORSRAM Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NORSRAM interface.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables dynamically FMC_NORSRAM write operation.
+ * @param Device: Pointer to NORSRAM device instance
+ * @param Bank: NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Enable write operation */
+ SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NORSRAM write operation.
+ * @param Device: Pointer to NORSRAM device instance
+ * @param Bank: NORSRAM bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_DEVICE(Device));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Disable write operation */
+ CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
+ * @brief NAND Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use NAND device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC NAND banks in order
+ to run the NAND external devices.
+
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+ (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
+ (+) FMC NAND bank common space timing configuration using the function
+ FMC_NAND_CommonSpace_Timing_Init()
+ (+) FMC NAND bank attribute space timing configuration using the function
+ FMC_NAND_AttributeSpace_Timing_Init()
+ (+) FMC NAND bank enable/disable ECC correction feature using the functions
+ FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_NAND device according to the specified
+ * control parameters in the FMC_NAND_HandleTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Init: Pointer to NAND Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Init->NandBank));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
+ assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Set NAND device control parameters */
+ if(Init->NandBank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ MODIFY_REG(Device->PCR2, PCRx_CLEAR_MASK, (Init->Waitfeature |\
+ FMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |\
+ ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR)))
+ );
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PCR3, PCRx_CLEAR_MASK, (Init->Waitfeature |\
+ FMC_PCR_MEMORY_TYPE_NAND |\
+ Init->MemoryDataWidth |\
+ Init->EccComputation |\
+ Init->ECCPageSize |\
+ ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |\
+ ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR)))
+ );
+ }
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Initializes the FMC_NAND Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Timing: Pointer to NAND timing structure
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Set FMC_NAND device timing parameters */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ MODIFY_REG(Device->PMEM2, PMEMx_CLEAR_MASK, (Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |\
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |\
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PMEM3, PMEMx_CLEAR_MASK, (Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |\
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |\
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to NAND device instance
+ * @param Timing: Pointer to NAND timing structure
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Set FMC_NAND device timing parameters */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ MODIFY_REG(Device->PATT2, PATTx_CLEAR_MASK, (Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |\
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |\
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PATT3, PATTx_CLEAR_MASK, (Timing->SetupTime |\
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |\
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |\
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the FMC_NAND device
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable the NAND Bank */
+ __FMC_NAND_DISABLE(Device, Bank);
+
+ /* De-initialize the NAND Bank */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Set the FMC_NAND_BANK2 registers to their reset values */
+ WRITE_REG(Device->PCR2, 0x00000018);
+ WRITE_REG(Device->SR2, 0x00000040);
+ WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT2, 0xFCFCFCFC);
+ }
+ /* FMC_Bank3_NAND */
+ else
+ {
+ /* Set the FMC_NAND_BANK3 registers to their reset values */
+ WRITE_REG(Device->PCR3, 0x00000018);
+ WRITE_REG(Device->SR3, 0x00000040);
+ WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT3, 0xFCFCFCFC);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### FMC_NAND Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control dynamically
+ the FMC NAND interface.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Enable ECC feature */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ SET_BIT(Device->PCR2, FMC_PCRx_ECCEN);
+ }
+ else
+ {
+ SET_BIT(Device->PCR3, FMC_PCRx_ECCEN);
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param Bank: NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Disable ECC feature */
+ if(Bank == FMC_NAND_BANK2)
+ {
+ CLEAR_BIT(Device->PCR2, FMC_PCRx_ECCEN);
+ }
+ else
+ {
+ CLEAR_BIT(Device->PCR3, FMC_PCRx_ECCEN);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables dynamically FMC_NAND ECC feature.
+ * @param Device: Pointer to NAND device instance
+ * @param ECCval: Pointer to ECC value
+ * @param Bank: NAND bank number
+ * @param Timeout: Timeout wait value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+{
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait untill FIFO is empty */
+ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ if(Bank == FMC_NAND_BANK2)
+ {
+ /* Get the ECCR2 register value */
+ *ECCval = (uint32_t)Device->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ *ECCval = (uint32_t)Device->ECCR3;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD Controller functions
+ * @brief PCCARD Controller functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use PCCARD device driver #####
+ ==============================================================================
+ [..]
+ This driver contains a set of APIs to interface with the FMC PCCARD bank in order
+ to run the PCCARD/compact flash external devices.
+
+ (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
+ (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
+ (+) FMC PCCARD bank common space timing configuration using the function
+ FMC_PCCARD_CommonSpace_Timing_Init()
+ (+) FMC PCCARD bank attribute space timing configuration using the function
+ FMC_PCCARD_AttributeSpace_Timing_Init()
+ (+) FMC PCCARD bank IO space timing configuration using the function
+ FMC_PCCARD_IOSpace_Timing_Init()
+
+
+@endverbatim
+ * @{
+ */
+
+/** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de_initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the FMC PCCARD interface
+ (+) De-initialize the FMC PCCARD interface
+ (+) Configure the FMC clock and associated GPIOs
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FMC_PCCARD device according to the specified
+ * control parameters in the FMC_PCCARD_HandleTypeDef
+ * @param Device: Pointer to PCCARD device instance
+ * @param Init: Pointer to PCCARD Initialization structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
+ assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
+ /* Set FMC_PCCARD device control parameters */
+ MODIFY_REG(Device->PCR4, \
+ (FMC_PCR4_PTYP | FMC_PCR4_PWAITEN | FMC_PCR4_PWID | FMC_PCR4_TCLR | FMC_PCR4_TAR), \
+ (FMC_PCR_MEMORY_TYPE_PCCARD | \
+ Init->Waitfeature | \
+ FMC_NAND_PCC_MEM_BUS_WIDTH_16 | \
+ (Init->TCLRSetupTime << POSITION_VAL(FMC_PCR4_TCLR)) | \
+ (Init->TARSetupTime << POSITION_VAL(FMC_PCR4_TAR))));
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to PCCARD device instance
+ * @param Timing: Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Set PCCARD timing parameters */
+ MODIFY_REG(Device->PMEM4, PMEMx_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to PCCARD device instance
+ * @param Timing: Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Set PCCARD timing parameters */
+ MODIFY_REG(Device->PATT4, PATTx_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device: Pointer to PCCARD device instance
+ * @param Timing: Pointer to PCCARD timing structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+
+ /* Set FMC_PCCARD device timing parameters */
+ MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ (Timing->WaitSetupTime << POSITION_VAL(FMC_PIO4_IOWAIT4)) | \
+ (Timing->HoldSetupTime << POSITION_VAL(FMC_PIO4_IOHOLD4)) | \
+ (Timing->HiZSetupTime << POSITION_VAL(FMC_PIO4_IOHIZ4))));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the FMC_PCCARD device
+ * @param Device: Pointer to PCCARD device instance
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
+
+ /* Disable the FMC_PCCARD device */
+ __FMC_PCCARD_DISABLE(Device);
+
+ /* De-initialize the FMC_PCCARD device */
+ WRITE_REG(Device->PCR4, 0x00000018);
+ WRITE_REG(Device->SR4, 0x00000040);
+ WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT4, 0xFCFCFCFC);
+ WRITE_REG(Device->PIO4, 0xFCFCFCFC);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#endif /* HAL_FMC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/flash.sh b/flash.sh
new file mode 100755
--- /dev/null
+++ b/flash.sh
@@ -0,0 +1,5 @@
+#!/bin/bash
+arm-none-eabi-size Debug/therm-ng-firmware.elf
+arm-none-eabi-objcopy -O binary Debug/therm-ng-firmware.elf Debug/therm-ng-firmware.bin
+st-flash write Debug/therm-ng-firmware.bin 0x8000000
+
diff --git a/inc/buttons.h b/inc/buttons.h
new file mode 100644
--- /dev/null
+++ b/inc/buttons.h
@@ -0,0 +1,21 @@
+/*
+ * buttons.h
+ *
+ * Created on: Oct 22, 2016
+ * Author: Nicholas Orlando
+ */
+
+#ifndef BUTTONS_H_
+#define BUTTONS_H_
+
+enum _btn_state_id
+{
+ NOT_PRESSED = 0,
+ PRESSED = 1,
+ HELD_SHORT = 2,
+ HELD_LONG = 3,
+};
+
+void freaking_debounce(void);
+
+#endif /* BUTTONS_H_ */
diff --git a/inc/config.h b/inc/config.h
new file mode 100644
--- /dev/null
+++ b/inc/config.h
@@ -0,0 +1,27 @@
+#ifndef CONFIG_H
+#define CONFIG_H
+
+
+
+//////////////////////////////////////////////////////
+// Watchdog Settings
+//////////////////////////////////////////////////////
+//#define WATCHDOG_ENABLE
+
+
+
+
+// Internal macros
+#define hal_init HAL_Init
+#define MAKE32(by3,by2,by1,by0) ((uint32_t)((((((by3<<8)+by2)<<8)+by1)<<8)+by0))
+
+#endif
+
+
+
+
+
+
+
+
+
diff --git a/inc/dma.h b/inc/dma.h
new file mode 100644
--- /dev/null
+++ b/inc/dma.h
@@ -0,0 +1,30 @@
+/*
+ * dma.h
+ *
+ * Created on: Aug 9, 2016
+ * Author: Nicholas Orlando
+ */
+
+#ifndef DMA_H_
+#define DMA_H_
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_hal.h"
+
+/* DMA memory to memory transfer handles -------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_DMA_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#endif /* DMA_H_ */
diff --git a/inc/error.h b/inc/error.h
new file mode 100644
--- /dev/null
+++ b/inc/error.h
@@ -0,0 +1,20 @@
+#ifndef ERROR_H
+#define ERROR_H
+
+// Each error message has an enum entry
+// If adding errors, remember to define a message for each in error.c
+enum error_number
+{
+ ERR_INFO = 0,
+ ERR_GENERIC,
+ ERR_PERIPHINIT,
+ ERR_COMMANDTIMEOUT,
+};
+
+void error_assert(const uint8_t errno);
+void error_assert_info(const uint8_t errno, const char* details);
+uint8_t error_check(const uint8_t errno);
+uint8_t error_occurred(void);
+uint8_t error_count(void);
+
+#endif
diff --git a/inc/flash.h b/inc/flash.h
new file mode 100644
--- /dev/null
+++ b/inc/flash.h
@@ -0,0 +1,23 @@
+#ifndef flash_h
+#define flash_h
+
+#define FLASH_MAGIC_LOC 511
+#define FLASH_MAGIC_VALUE 0xbeef
+
+
+typedef union
+{
+ struct _values {
+ uint16_t can_id;
+ uint16_t tx_period;
+ } values;
+
+ uint16_t data[128];
+} settings_t;
+
+void flash_init(void);
+void flash_savesettings(void);
+void flash_restoresettings(void);
+settings_t* flash_getsettings(void);
+
+#endif // flash_h
diff --git a/inc/gpio.h b/inc/gpio.h
new file mode 100644
--- /dev/null
+++ b/inc/gpio.h
@@ -0,0 +1,28 @@
+#ifndef __gpio_H
+#define __gpio_H
+
+#include "stm32f3xx_hal.h"
+
+
+// Define button push
+#define SW_D_Pin GPIO_PIN_4
+#define SW_D_GPIO_Port GPIOA
+#define SW_B_Pin GPIO_PIN_5
+#define SW_B_GPIO_Port GPIOA
+#define SW_A_Pin GPIO_PIN_6
+#define SW_A_GPIO_Port GPIOA
+#define SW_C_Pin GPIO_PIN_7
+#define SW_C_GPIO_Port GPIOA
+
+#define SW_BTN_Pin GPIO_PIN_0
+#define SW_BTN_GPIO_Port GPIOB
+#define SW_BTN SW_BTN_GPIO_Port , SW_BTN_Pin
+
+#define LED_PIN GPIO_PIN_6
+#define LED_GPIO_Port GPIOB
+#define LED LED_GPIO_Port, LED_PIN
+
+void gpio_init(void);
+void gpio_led_blueblink(uint8_t num_blinks);
+
+#endif
diff --git a/inc/interrupts.h b/inc/interrupts.h
new file mode 100644
--- /dev/null
+++ b/inc/interrupts.h
@@ -0,0 +1,20 @@
+#ifndef __STM32F3xx_IT_H
+#define __STM32F3xx_IT_H
+
+void SysTick_Handler(void);
+void DMA1_Channel2_IRQHandler(void);
+void DMA1_Channel3_IRQHandler(void);
+void DMA1_Channel4_IRQHandler(void);
+void DMA1_Channel5_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void USART1_IRQHandler(void);
+void DMA2_Channel3_IRQHandler(void);
+void DMA2_Channel4_IRQHandler(void);
+void SDADC1_IRQHandler(void);
+void SDADC2_IRQHandler(void);
+
+
+
+
+
+#endif
diff --git a/inc/ssd1306.h b/inc/ssd1306.h
new file mode 100644
--- /dev/null
+++ b/inc/ssd1306.h
@@ -0,0 +1,44 @@
+#ifndef ssd1306_H
+#define ssd1306_H
+
+
+#define OLED_CS_Pin GPIO_PIN_0
+#define OLED_CS_GPIO_Port GPIOA
+#define OLED_RESET_Pin GPIO_PIN_1
+#define OLED_RESET_GPIO_Port GPIOA
+#define OLED_DC_Pin GPIO_PIN_2
+#define OLED_DC_GPIO_Port GPIOA
+
+
+
+#define SSD_RESET OLED_RESET_GPIO_Port,OLED_RESET_Pin
+#define SSD_A0 OLED_DC_GPIO_Port,OLED_DC_Pin
+#define SSD_CS OLED_CS_GPIO_Port,OLED_CS_Pin
+
+#define SSD_Reset_Low() HAL_GPIO_WritePin(SSD_RESET, 0)
+#define SSD_Reset_High() HAL_GPIO_WritePin(SSD_RESET, 1)
+#define SSD_A0_Low() HAL_GPIO_WritePin(SSD_A0, 0)
+#define SSD_A0_High() HAL_GPIO_WritePin(SSD_A0, 1)
+#define SSD_CS_Low() HAL_GPIO_WritePin(SSD_CS, 0)
+#define SSD_CS_High() HAL_GPIO_WritePin(SSD_CS, 1)
+
+
+// EMZ FIXME this won't really work
+#define SPI_SendByte(data) HAL_SPI_Transmit(spi_get(), &data, 1, 100)
+//#define SPI_SendByte(data)
+#define SPI_Wait()
+
+//#define SPI_SendByte(data) SPI_I2S_SendData(SPI1,data)
+//#define SPI_Wait() while(!(SPI1->SR&SPI_FLAG_TXE));while(SPI1->SR&SPI_FLAG_BSY);
+
+void ssd1306_init(void);
+void ssd1306_drawchar(char ascii, unsigned char row, unsigned char xPos);
+void ssd1306_drawcharbig(char ascii, unsigned char row, unsigned char xPos);
+void ssd1306_drawstring(const char *dataPtr, unsigned char row, unsigned char xPos);
+void ssd1306_drawstringbig(const char *dataPtr, unsigned char row, unsigned char xPos);
+void ssd1306_drawlogo();
+void ssd1306_clearscreen();
+
+#endif
+
+// vim:softtabstop=4 shiftwidth=4 expandtab
diff --git a/inc/stm32f3xx_hal_conf.h b/inc/stm32f3xx_hal_conf.h
new file mode 100644
--- /dev/null
+++ b/inc/stm32f3xx_hal_conf.h
@@ -0,0 +1,340 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_hal_conf.h
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2016 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CONF_H
+#define __STM32F3xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+//#define HAL_CAN_MODULE_ENABLED
+//#define HAL_CEC_MODULE_ENABLED
+//#define HAL_NAND_MODULE_ENABLED
+//#define HAL_NOR_MODULE_ENABLED
+//#define HAL_PCCARD_MODULE_ENABLED
+//#define HAL_SRAM_MODULE_ENABLED
+//#define HAL_HRTIM_MODULE_ENABLED
+//#define HAL_OPAMP_MODULE_ENABLED
+//#define HAL_SDADC_MODULE_ENABLED
+//#define HAL_TSC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+//#define HAL_CRC_MODULE_ENABLED
+//#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+//#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+//#define HAL_LCD_MODULE_ENABLED
+//#define HAL_LPTIM_MODULE_ENABLED
+//#define HAL_RNG_MODULE_ENABLED
+//#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+//#define HAL_UART_MODULE_ENABLED
+//#define HAL_USART_MODULE_ENABLED
+//#define HAL_IRDA_MODULE_ENABLED
+//#define HAL_SMARTCARD_MODULE_ENABLED
+//#define HAL_SMBUS_MODULE_ENABLED
+//#define HAL_WWDG_MODULE_ENABLED
+//#define HAL_PCD_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+ /* ########################## HSE/HSI Values adaptation ##################### */
+ /**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+ #if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)16000000) /*!< Value of the External oscillator in Hz */
+ #endif /* HSE_VALUE */
+
+ /**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
+ */
+ #if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+ #endif /* HSE_STARTUP_TIMEOUT */
+
+ /**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+ #if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+ #endif /* HSI_VALUE */
+
+ /**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
+ */
+ #if !defined (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
+ #endif /* HSI_STARTUP_TIMEOUT */
+
+ /**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+ #if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)40000)
+ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+ /**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+ #if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+ #endif /* LSE_VALUE */
+
+ /**
+ * @brief Time out for LSE start up value in ms.
+ */
+ #if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+ #endif /* LSE_STARTUP_TIMEOUT */
+
+ /**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
+ * - External clock not generated on EVAL 373
+ */
+ #if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+ #endif /* EXTERNAL_CLOCK_VALUE */
+
+ /* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+ /* ########################### System Configuration ######################### */
+ /**
+ * @brief This is the HAL system configuration section
+ */
+
+ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+ #define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */
+ #define USE_RTOS 0
+ #define PREFETCH_ENABLE 1
+ #define INSTRUCTION_CACHE_ENABLE 0
+ #define DATA_CACHE_ENABLE 0
+
+ /* ########################## Assert Selection ############################## */
+ /**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+ /* #define USE_FULL_ASSERT 1 */
+
+ /* Includes ------------------------------------------------------------------*/
+ /**
+ * @brief Include module's header file
+ */
+
+ #ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rcc.h"
+ #endif /* HAL_RCC_MODULE_ENABLED */
+
+ #ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f3xx_hal_gpio.h"
+ #endif /* HAL_GPIO_MODULE_ENABLED */
+
+ #ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f3xx_hal_dma.h"
+ #endif /* HAL_DMA_MODULE_ENABLED */
+
+ #ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f3xx_hal_cortex.h"
+ #endif /* HAL_CORTEX_MODULE_ENABLED */
+
+ #ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_adc.h"
+ #endif /* HAL_ADC_MODULE_ENABLED */
+
+ #ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f3xx_hal_can.h"
+ #endif /* HAL_CAN_MODULE_ENABLED */
+
+ #ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f3xx_hal_cec.h"
+ #endif /* HAL_CEC_MODULE_ENABLED */
+
+ #ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_comp.h"
+ #endif /* HAL_COMP_MODULE_ENABLED */
+
+ #ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f3xx_hal_crc.h"
+ #endif /* HAL_CRC_MODULE_ENABLED */
+
+ #ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f3xx_hal_dac.h"
+ #endif /* HAL_DAC_MODULE_ENABLED */
+
+ #ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f3xx_hal_flash.h"
+ #endif /* HAL_FLASH_MODULE_ENABLED */
+
+ #ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f3xx_hal_sram.h"
+ #endif /* HAL_SRAM_MODULE_ENABLED */
+
+ #ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f3xx_hal_nor.h"
+ #endif /* HAL_NOR_MODULE_ENABLED */
+
+ #ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f3xx_hal_nand.h"
+ #endif /* HAL_NAND_MODULE_ENABLED */
+
+ #ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f3xx_hal_pccard.h"
+ #endif /* HAL_PCCARD_MODULE_ENABLED */
+
+ #ifdef HAL_HRTIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_hrtim.h"
+ #endif /* HAL_HRTIM_MODULE_ENABLED */
+
+ #ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2c.h"
+ #endif /* HAL_I2C_MODULE_ENABLED */
+
+ #ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2s.h"
+ #endif /* HAL_I2S_MODULE_ENABLED */
+
+ #ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f3xx_hal_irda.h"
+ #endif /* HAL_IRDA_MODULE_ENABLED */
+
+ #ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_iwdg.h"
+ #endif /* HAL_IWDG_MODULE_ENABLED */
+
+ #ifdef HAL_OPAMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_opamp.h"
+ #endif /* HAL_OPAMP_MODULE_ENABLED */
+
+ #ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f3xx_hal_pcd.h"
+ #endif /* HAL_PCD_MODULE_ENABLED */
+
+ #ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f3xx_hal_pwr.h"
+ #endif /* HAL_PWR_MODULE_ENABLED */
+
+ #ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rtc.h"
+ #endif /* HAL_RTC_MODULE_ENABLED */
+
+ #ifdef HAL_SDADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_sdadc.h"
+ #endif /* HAL_SDADC_MODULE_ENABLED */
+
+ #ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f3xx_hal_smartcard.h"
+ #endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+ #ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f3xx_hal_smbus.h"
+ #endif /* HAL_SMBUS_MODULE_ENABLED */
+
+ #ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f3xx_hal_spi.h"
+ #endif /* HAL_SPI_MODULE_ENABLED */
+
+ #ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_tim.h"
+ #endif /* HAL_TIM_MODULE_ENABLED */
+
+ #ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32f3xx_hal_tsc.h"
+ #endif /* HAL_TSC_MODULE_ENABLED */
+
+ #ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f3xx_hal_uart.h"
+ #endif /* HAL_UART_MODULE_ENABLED */
+
+ #ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f3xx_hal_usart.h"
+ #endif /* HAL_USART_MODULE_ENABLED */
+
+ #ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_wwdg.h"
+ #endif /* HAL_WWDG_MODULE_ENABLED */
+
+ /* Exported macro ------------------------------------------------------------*/
+ #ifdef USE_FULL_ASSERT
+ /**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+ /* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+ #else
+ #define assert_param(expr) ((void)0)
+ #endif /* USE_FULL_ASSERT */
+
+ #ifdef __cplusplus
+ }
+ #endif
+
+ #endif /* __STM32F3xx_HAL_CONF_H */
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/inc/system.h b/inc/system.h
new file mode 100644
--- /dev/null
+++ b/inc/system.h
@@ -0,0 +1,6 @@
+#ifndef SYSTEM_H
+#define SYSTEM_H
+
+void sysclock_init(void);
+
+#endif
diff --git a/inc/watchdog.h b/inc/watchdog.h
new file mode 100644
--- /dev/null
+++ b/inc/watchdog.h
@@ -0,0 +1,7 @@
+#ifndef WATCHDOG_H
+#define WATCHDOG_H
+
+void watchdog_init(void);
+void watchdog_feed(void);
+
+#endif
diff --git a/ldscripts/STM32F302K8_FLASH.ld b/ldscripts/STM32F302K8_FLASH.ld
new file mode 100644
--- /dev/null
+++ b/ldscripts/STM32F302K8_FLASH.ld
@@ -0,0 +1,173 @@
+/*
+*****************************************************************************
+**
+** File : stm32_flash.ld
+**
+** Abstract : Linker script for STM32F302K8 Device with
+** 64KByte FLASH, 16KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Environment : Atollic TrueSTUDIO(R)
+**
+** Distribution: The file is distributed “as is,” without any warranty
+** of any kind.
+**
+** (c)Copyright Atollic AB.
+** You may use this file as-is or modify it according to the needs of your
+** project. This file may only be built (assembled or compiled and linked)
+** using the Atollic TrueSTUDIO(R) product. The use of this file together
+** with other tools than Atollic TrueSTUDIO(R) is not permitted.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 63K
+EEPROM (xrw) : ORIGIN = 0x800FC00, LENGTH = 1K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* EMZ: EEPROM emulation data storage */
+ .eeprom :
+ {
+ . = ALIGN(4);
+ *(.eeprom)
+ . = ALIGN(4);
+ } >EEPROM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/openocd.cfg b/openocd.cfg
new file mode 100644
--- /dev/null
+++ b/openocd.cfg
@@ -0,0 +1,8 @@
+source [find interface/stlink-v2.cfg]
+
+transport select hla_swd
+
+set WORKAREASIZE 0x2000
+source [find target/stm32f3x.cfg]
+
+
diff --git a/src/.hgignore b/src/.hgignore
new file mode 100644
--- /dev/null
+++ b/src/.hgignore
@@ -0,0 +1,6 @@
+syntax: glob
+
+*.o
+*.d
+*.mk
+makefile
\ No newline at end of file
diff --git a/src/buttons.c b/src/buttons.c
new file mode 100644
--- /dev/null
+++ b/src/buttons.c
@@ -0,0 +1,76 @@
+/*
+ * buttons.c
+ *
+ * Created on: Oct 22, 2016
+ * Author: Nicholas Orlando
+ */
+
+#include "stm32f3xx_hal.h"
+#include "stm32f3xx.h"
+#include "gpio.h"
+#include "ssd1306.h"
+#include "buttons.h"
+#include
+
+
+uint32_t last_button_debounce_time = 0; // the system time at which the button values were last checked
+uint32_t debounce_resolution = 5; // period in which to check pin state in milliseconds
+float filter_fraction = 0.2; // a number between 0 and 1, which adjusts the heaviness of the filter.
+ // 0 = never changes and 1 = no filter at all.
+uint8_t l_thresh = 20; //lower threshold for when then button is considered pressed vs not pressed.
+uint8_t u_thresh = 80; //upper threshold for when then button is considered pressed vs not pressed.
+
+uint8_t temp_counter = 0; // temporary counter for testing purposes
+
+float sw_btn_avg = 0; // some sort of running average
+uint8_t sw_btn_state = NOT_PRESSED; // the state of the pin after filtering
+uint8_t sw_btn_old_state = NOT_PRESSED; // the state of the pin after filtering
+
+void freaking_debounce(void)
+{
+ if(HAL_GetTick() - last_button_debounce_time > debounce_resolution)
+ {
+ char buffer[256]; // needed for writing stuff to screen
+
+ //averaging to filter button presses
+ if(HAL_GPIO_ReadPin(SW_BTN) == GPIO_PIN_RESET)
+ {
+ sw_btn_avg = sw_btn_avg + filter_fraction * (100 - sw_btn_avg);
+ }
+ else
+ {
+ sw_btn_avg = sw_btn_avg + filter_fraction * (0 - sw_btn_avg);
+ }
+
+ // check to see if the btn average value has crossed a threshold
+ if(sw_btn_avg < l_thresh)
+ {
+ sw_btn_state = NOT_PRESSED;
+// snprintf(buffer, 256, "NOT_PRESSED");
+// ssd1306_drawstring(buffer, 1, 0);
+ }
+ if(sw_btn_avg > u_thresh)
+ {
+ sw_btn_state = PRESSED;
+// snprintf(buffer, 256, "PRESSED ");
+// ssd1306_drawstring(buffer, 1, 0);
+ }
+
+ // do something when state has changed
+ if((sw_btn_state == PRESSED) && (sw_btn_old_state == NOT_PRESSED))
+ {
+// temp_counter++;
+// snprintf(buffer, 256, "%i", temp_counter);
+// ssd1306_drawstring(buffer, 1, 0);
+ }
+
+
+// snprintf(buffer, 256, "sw-btn-avg: %.1f", sw_btn_avg);
+// ssd1306_drawstring(buffer, 2, 0);
+
+ // save previous button states
+ sw_btn_old_state = sw_btn_state;
+
+ last_button_debounce_time = HAL_GetTick();
+ }
+}
diff --git a/src/dma.c b/src/dma.c
new file mode 100644
--- /dev/null
+++ b/src/dma.c
@@ -0,0 +1,33 @@
+/*
+ * dma.c
+ *
+ * Created on: Aug 9, 2016
+ * Author: Nicholas Orlando
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "dma.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure DMA */
+/*----------------------------------------------------------------------------*/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+ * Enable DMA controller clock
+ */
+void MX_DMA_Init(void)
+{
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
diff --git a/src/error.c b/src/error.c
new file mode 100644
--- /dev/null
+++ b/src/error.c
@@ -0,0 +1,101 @@
+//
+// Error: Provides a simple interface for asserting and checking errors
+//
+
+#include "stm32f3xx_hal.h"
+
+#include
+
+#include "config.h"
+#include "error.h"
+
+static volatile uint32_t err_reg;
+static volatile uint8_t num_errors_asserted = 0;
+
+// Moderately detailed messages corresponding to each error enum
+//static const char * error_message[] =
+//{
+// "Info",
+// "General",
+//};
+
+
+// Set the passed error flag
+void error_assert(const uint8_t errno)
+{
+ // Errno invalid: exceeds bit length of error register
+ if(errno >= 32)
+ return;
+
+ // Don't count info messages as true errors
+ if(errno > ERR_INFO)
+ {
+ // Set error flag
+ err_reg |= (1<= 32)
+ return;
+
+ // Don't count info messages as true errors
+ if(errno > ERR_INFO)
+ {
+ // Set error flag
+ err_reg |= (1< ERR_INFO)
+ {
+ ir_efs_send(outbuf);
+ error_sidechannel_addmsg(outbuf);
+ }
+#endif
+}
+
+
+// Check if the passed error flag has been asserted
+inline uint8_t error_check(const uint8_t errno)
+{
+ return (err_reg & (1< 0;
+}
+
+
+// Return 1 if any error has occurred
+inline uint8_t error_occurred(void)
+{
+ return err_reg > 0;
+}
+
+
+// Return the number of errors that have occurred
+inline uint8_t error_count(void)
+{
+ return num_errors_asserted;
+}
diff --git a/src/flash.c b/src/flash.c
new file mode 100644
--- /dev/null
+++ b/src/flash.c
@@ -0,0 +1,80 @@
+//
+// Flash: Nonvolatile storage for settings / etc
+//
+
+#include "stm32f3xx_hal.h"
+#include "flash.h"
+#include "config.h"
+
+// Takes up 1 page (1k size)
+static __attribute__((__section__(".eeprom"))) uint16_t eeprom_emulation[512];
+settings_t settings;
+
+
+// Initialize flash and restore settings
+void flash_init(void)
+{
+ flash_restoresettings();
+}
+
+
+// Save settings to flash memory
+void flash_savesettings(void)
+{
+ // Unlock flash memory
+ HAL_FLASH_Unlock();
+
+ // Initialize eraser to erase one page of flash
+ FLASH_EraseInitTypeDef eraser =
+ {
+ .TypeErase = TYPEERASE_PAGES,
+ .PageAddress = eeprom_emulation,
+ .NbPages = 1,
+ };
+ uint32_t errvar = 0;
+
+ // Erase flash page
+ HAL_FLASHEx_Erase(&eraser, &errvar);
+
+ // Write new flash data
+ uint16_t writectr;
+ for(writectr = 0; writectr < 128; writectr++)// 128 bytes data
+ {
+ HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, eeprom_emulation+writectr,settings.data[writectr]);
+ }
+
+ // Write magic value to flash
+ HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, eeprom_emulation+FLASH_MAGIC_LOC,FLASH_MAGIC_VALUE);
+
+ // Lock flash memory
+ HAL_FLASH_Lock();
+ HAL_Delay(2);
+}
+
+
+// Restore configuration from flash memory, if any was previously saved
+void flash_restoresettings(void)
+{
+ // Check for magic flash value
+ if(eeprom_emulation[FLASH_MAGIC_LOC] == FLASH_MAGIC_VALUE)
+ {
+ // Read page of flash into settings structure
+ uint16_t readctr = 0;
+ for(readctr = 0; readctr < 128; readctr++)
+ {
+ settings.data[readctr] = eeprom_emulation[readctr];
+ }
+ }
+ // No data in flash! Set defaults here
+ else
+ {
+ settings.values.can_id = 22;
+ }
+}
+
+
+// Accessor to retrieve settings structure
+inline settings_t* flash_getsettings(void)
+{
+ return &settings;
+}
diff --git a/src/gpio.c b/src/gpio.c
new file mode 100644
--- /dev/null
+++ b/src/gpio.c
@@ -0,0 +1,50 @@
+//
+// GPIO: configure general-purpose inputs/outputs
+//
+
+#include "stm32f3xx_hal.h"
+
+#include "gpio.h"
+
+
+// Initialize GPIOs
+void gpio_init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ // GPIO Ports Clock Enable
+ __GPIOA_CLK_ENABLE();
+ __GPIOB_CLK_ENABLE();
+ __GPIOF_CLK_ENABLE();
+
+
+ // Configure LED GPIO pins
+ GPIO_InitStruct.Pin = LED_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
+
+
+ GPIO_InitStruct.Pin = SW_A_Pin|SW_B_Pin|SW_C_Pin|SW_D_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(SW_C_GPIO_Port, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = SW_BTN_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ HAL_GPIO_Init(SW_BTN_GPIO_Port, &GPIO_InitStruct);
+
+
+ /* EXTI interrupt init*/
+ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
+
+ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
+
+ // Define startup State
+ HAL_GPIO_WritePin(LED, 0);
+
+}
diff --git a/src/interrupts.c b/src/interrupts.c
new file mode 100644
--- /dev/null
+++ b/src/interrupts.c
@@ -0,0 +1,52 @@
+//
+// Interrupts: handlers for any needed global interrupts
+//
+
+#include "stm32f3xx_hal.h"
+#include "stm32f3xx.h"
+
+#include "interrupts.h"
+#include "gpio.h"
+
+
+// Systick interrupt
+void SysTick_Handler(void)
+{
+ HAL_IncTick();
+ HAL_SYSTICK_IRQHandler();
+}
+
+void EXTI9_5_IRQHandler(void)
+{
+ HAL_GPIO_EXTI_IRQHandler(SW_B_Pin);
+ HAL_GPIO_EXTI_IRQHandler(SW_A_Pin);
+ HAL_GPIO_EXTI_IRQHandler(SW_C_Pin);
+}
+
+void EXTI15_10_IRQHandler(void)
+{
+ HAL_GPIO_EXTI_IRQHandler(SW_BTN_Pin);
+}
+
+uint32_t last_button_press = 0;
+
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+ switch(GPIO_Pin)
+ {
+ case SW_BTN_Pin:
+ {
+// if(HAL_GetTick() > last_button_press + 100)
+// {
+// HAL_GPIO_TogglePin(LED_RED);
+// HAL_GPIO_TogglePin(GATE_DRIVE);
+// last_button_press = HAL_GetTick();
+// }
+ } break;
+ }
+}
+
+
+
+
+
diff --git a/src/main.c b/src/main.c
new file mode 100644
--- /dev/null
+++ b/src/main.c
@@ -0,0 +1,67 @@
+//
+// Therm Firmware
+// Copyright 2017 Ethan Zonca
+// Author(s): Ethan Zonca
+//
+
+#include "stm32f3xx_hal.h"
+#include "config.h"
+
+#include "watchdog.h"
+#include "system.h"
+#include "gpio.h"
+#include "error.h"
+#include "flash.h"
+#include "ssd1306.h"
+#include "dma.h"
+#include "interrupts.h"
+#include "buttons.h"
+
+int main(void)
+{
+ sysclock_init();
+ hal_init();
+ gpio_init();
+ ssd1306_init();
+ ssd1306_drawlogo();
+ ssd1306_clearscreen();
+
+ flash_init();
+ watchdog_init();
+
+ //just some example code for getting flash values
+// flash_getsettings()->values.can_id = 67;
+//
+// if(flash_getsettings()->values.can_id == 12);
+
+// ssd1306_drawstring(const char *dataPtr, unsigned char row, unsigned char xPos)
+// ssd1306_drawstring("[ ProtoFuse ]", 0, 0);
+
+ float temp_counter = 0;
+
+ // Software timers
+ uint32_t last_screen_update_time = HAL_GetTick();
+
+
+ while (1)
+ {
+ // function that checks all the buttons
+ freaking_debounce();
+
+ // Grab and transmit data
+ if(HAL_GetTick() - last_screen_update_time > 100)
+ {
+ HAL_GPIO_TogglePin(LED_GPIO_Port, LED_PIN);
+ char buffer[256];
+ snprintf(buffer, 256, "Counter: %.1f", temp_counter);
+ ssd1306_drawstring(buffer, 3, 10);
+ ssd1306_drawstring("Therm Next Generation", 0, 0);
+ temp_counter = temp_counter + 0.1;
+ last_screen_update_time = HAL_GetTick();
+ }
+
+ watchdog_feed();
+ }
+}
+
+
diff --git a/src/sbrk.c b/src/sbrk.c
new file mode 100644
--- /dev/null
+++ b/src/sbrk.c
@@ -0,0 +1,22 @@
+//
+// Sbrk: Basic _sbrk implementation to make *printf work
+//
+
+#include
+
+caddr_t _sbrk(int incr)
+{
+extern char end asm("end");
+static char *heap_end;
+char *prev_heap_end;
+
+if (heap_end == 0) {
+heap_end = &end;
+}
+
+prev_heap_end = heap_end;
+
+heap_end += incr;
+
+return (caddr_t)prev_heap_end;
+}
diff --git a/src/ssd1306.c b/src/ssd1306.c
new file mode 100644
--- /dev/null
+++ b/src/ssd1306.c
@@ -0,0 +1,424 @@
+#include "stm32f3xx_hal.h"
+#include "ssd1306.h"
+
+
+SPI_HandleTypeDef hspi1;
+
+
+
+SPI_HandleTypeDef* spi_get()
+{
+ return &hspi1;
+}
+
+
+// Write command to OLED
+static void WriteCommand(unsigned char command)
+{
+ SSD_CS_Low();
+ SSD_A0_Low();
+ SPI_SendByte(command);
+ SSD_CS_High();
+}
+
+// Write data to OLED
+static void WriteData(unsigned char data)
+{
+ SSD_CS_Low();
+ SSD_A0_High();
+ SPI_SendByte(data);
+ SSD_CS_High();
+}
+
+// Initialize OLED
+void ssd1306_init(void)
+{
+ __SPI3_CLK_ENABLE();
+ __GPIOA_CLK_ENABLE();
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ /*Configure GPIO pins : OLED_CS_Pin OLED_RESET_Pin OLED_DC_Pin */
+ GPIO_InitStruct.Pin = OLED_CS_Pin|OLED_RESET_Pin|OLED_DC_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(OLED_DC_GPIO_Port, &GPIO_InitStruct);
+
+
+ // Set up MOSI/MISO/SCK
+ GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+
+ // Set up SPI port for OLED
+ hspi1.Instance = SPI3;
+ hspi1.Init.Mode = SPI_MODE_MASTER;
+ hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+ hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+ hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+ hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+ hspi1.Init.NSS = SPI_NSS_SOFT;
+ hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
+ hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+ hspi1.Init.TIMode = SPI_TIMODE_DISABLED;
+ hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+ hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLED;
+ HAL_SPI_Init(&hspi1);
+
+
+
+ /* Generate a reset */
+ SSD_Reset_Low();
+ uint32_t i;
+ for(i=5000; i>1; i--)
+ SSD_Reset_High();
+
+ WriteCommand(0xAE);
+ WriteCommand(0xD5);
+ WriteCommand(0x80);
+ WriteCommand(0xA8);
+ WriteCommand(0x1F);
+ WriteCommand(0xD3);
+ WriteCommand(0x00);
+ WriteCommand(0x40 | 0x00); // line #0
+ WriteCommand(0x8D);
+ WriteCommand(0x14); //10 or 14 if not externalvcc
+ WriteCommand(0x20);
+ WriteCommand(0x00);
+// WriteCommand(0xA0 | 0x1); // segremap (normal)
+ WriteCommand(0xA0); // segremap (flip)
+// WriteCommand(0xC8); // comscandec (normal)
+ WriteCommand(0xC0); // comscandec (flip)
+ WriteCommand(0xDA); // setcompins
+ WriteCommand(0x02);
+ WriteCommand(0x81); // contrast
+ WriteCommand(0x0F); // contrast value. 8f is a good one.
+ WriteCommand(0xD9);
+ WriteCommand(0xF1); //22 or F1 if not externalvcc
+ WriteCommand(0xDB);
+ WriteCommand(0x40);
+ WriteCommand(0xA4); // dispalyallon_resume
+ WriteCommand(0xA6); // normaldisplay
+
+
+ WriteCommand(0xAF); // display on
+}
+
+
+// Times New Roman font
+static const char fontData[][5] =
+{ // Refer to "Times New Roman" Font Database
+ // Basic Characters
+ {0x00,0x00,0x00,0x00,0x00}, // ( 0) - 0x0020 No-Break Space
+ {0x00,0x00,0x4F,0x00,0x00}, // ( 1) ! - 0x0021 Exclamation Mark
+ {0x00,0x07,0x00,0x07,0x00}, // ( 2) " - 0x0022 Quotation Mark
+ {0x14,0x7F,0x14,0x7F,0x14}, // ( 3) # - 0x0023 Number Sign
+ {0x24,0x2A,0x7F,0x2A,0x12}, // ( 4) $ - 0x0024 Dollar Sign
+ {0x23,0x13,0x08,0x64,0x62}, // ( 5) % - 0x0025 Percent Sign
+ {0x36,0x49,0x55,0x22,0x50}, // ( 6) & - 0x0026 Ampersand
+ {0x00,0x05,0x03,0x00,0x00}, // ( 7) ' - 0x0027 Apostrophe
+ {0x00,0x1C,0x22,0x41,0x00}, // ( 8) ( - 0x0028 Left Parenthesis
+ {0x00,0x41,0x22,0x1C,0x00}, // ( 9) ) - 0x0029 Right Parenthesis
+ {0x14,0x08,0x3E,0x08,0x14}, // ( 10) * - 0x002A Asterisk
+ {0x08,0x08,0x3E,0x08,0x08}, // ( 11) + - 0x002B Plus Sign
+ {0x00,0x50,0x30,0x00,0x00}, // ( 12) , - 0x002C Comma
+ {0x08,0x08,0x08,0x08,0x08}, // ( 13) - - 0x002D Hyphen-Minus
+ {0x00,0x60,0x60,0x00,0x00}, // ( 14) . - 0x002E Full Stop
+ {0x20,0x10,0x08,0x04,0x02}, // ( 15) / - 0x002F Solidus
+ {0x3E,0x51,0x49,0x45,0x3E}, // ( 16) 0 - 0x0030 Digit Zero
+ {0x00,0x42,0x7F,0x40,0x00}, // ( 17) 1 - 0x0031 Digit One
+ {0x42,0x61,0x51,0x49,0x46}, // ( 18) 2 - 0x0032 Digit Two
+ {0x21,0x41,0x45,0x4B,0x31}, // ( 19) 3 - 0x0033 Digit Three
+ {0x18,0x14,0x12,0x7F,0x10}, // ( 20) 4 - 0x0034 Digit Four
+ {0x27,0x45,0x45,0x45,0x39}, // ( 21) 5 - 0x0035 Digit Five
+ {0x3C,0x4A,0x49,0x49,0x30}, // ( 22) 6 - 0x0036 Digit Six
+ {0x01,0x71,0x09,0x05,0x03}, // ( 23) 7 - 0x0037 Digit Seven
+ {0x36,0x49,0x49,0x49,0x36}, // ( 24) 8 - 0x0038 Digit Eight
+ {0x06,0x49,0x49,0x29,0x1E}, // ( 25) 9 - 0x0039 Dight Nine
+ {0x00,0x36,0x36,0x00,0x00}, // ( 26) : - 0x003A Colon
+ {0x00,0x56,0x36,0x00,0x00}, // ( 27) ; - 0x003B Semicolon
+ {0x08,0x14,0x22,0x41,0x00}, // ( 28) < - 0x003C Less-Than Sign
+ {0x14,0x14,0x14,0x14,0x14}, // ( 29) = - 0x003D Equals Sign
+ {0x00,0x41,0x22,0x14,0x08}, // ( 30) > - 0x003E Greater-Than Sign
+ {0x02,0x01,0x51,0x09,0x06}, // ( 31) ? - 0x003F Question Mark
+ {0x32,0x49,0x79,0x41,0x3E}, // ( 32) @ - 0x0040 Commercial At
+ {0x7E,0x11,0x11,0x11,0x7E}, // ( 33) A - 0x0041 Latin Capital Letter A
+ {0x7F,0x49,0x49,0x49,0x36}, // ( 34) B - 0x0042 Latin Capital Letter B
+ {0x3E,0x41,0x41,0x41,0x22}, // ( 35) C - 0x0043 Latin Capital Letter C
+ {0x7F,0x41,0x41,0x22,0x1C}, // ( 36) D - 0x0044 Latin Capital Letter D
+ {0x7F,0x49,0x49,0x49,0x41}, // ( 37) E - 0x0045 Latin Capital Letter E
+ {0x7F,0x09,0x09,0x09,0x01}, // ( 38) F - 0x0046 Latin Capital Letter F
+ {0x3E,0x41,0x49,0x49,0x7A}, // ( 39) G - 0x0047 Latin Capital Letter G
+ {0x7F,0x08,0x08,0x08,0x7F}, // ( 40) H - 0x0048 Latin Capital Letter H
+ {0x00,0x41,0x7F,0x41,0x00}, // ( 41) I - 0x0049 Latin Capital Letter I
+ {0x20,0x40,0x41,0x3F,0x01}, // ( 42) J - 0x004A Latin Capital Letter J
+ {0x7F,0x08,0x14,0x22,0x41}, // ( 43) K - 0x004B Latin Capital Letter K
+ {0x7F,0x40,0x40,0x40,0x40}, // ( 44) L - 0x004C Latin Capital Letter L
+ {0x7F,0x02,0x0C,0x02,0x7F}, // ( 45) M - 0x004D Latin Capital Letter M
+ {0x7F,0x04,0x08,0x10,0x7F}, // ( 46) N - 0x004E Latin Capital Letter N
+ {0x3E,0x41,0x41,0x41,0x3E}, // ( 47) O - 0x004F Latin Capital Letter O
+ {0x7F,0x09,0x09,0x09,0x06}, // ( 48) P - 0x0050 Latin Capital Letter P
+ {0x3E,0x41,0x51,0x21,0x5E}, // ( 49) Q - 0x0051 Latin Capital Letter Q
+ {0x7F,0x09,0x19,0x29,0x46}, // ( 50) R - 0x0052 Latin Capital Letter R
+ {0x46,0x49,0x49,0x49,0x31}, // ( 51) S - 0x0053 Latin Capital Letter S
+ {0x01,0x01,0x7F,0x01,0x01}, // ( 52) T - 0x0054 Latin Capital Letter T
+ {0x3F,0x40,0x40,0x40,0x3F}, // ( 53) U - 0x0055 Latin Capital Letter U
+ {0x1F,0x20,0x40,0x20,0x1F}, // ( 54) V - 0x0056 Latin Capital Letter V
+ {0x3F,0x40,0x38,0x40,0x3F}, // ( 55) W - 0x0057 Latin Capital Letter W
+ {0x63,0x14,0x08,0x14,0x63}, // ( 56) X - 0x0058 Latin Capital Letter X
+ {0x07,0x08,0x70,0x08,0x07}, // ( 57) Y - 0x0059 Latin Capital Letter Y
+ {0x61,0x51,0x49,0x45,0x43}, // ( 58) Z - 0x005A Latin Capital Letter Z
+ {0x00,0x7F,0x41,0x41,0x00}, // ( 59) [ - 0x005B Left Square Bracket
+ {0x02,0x04,0x08,0x10,0x20}, // ( 60) \ - 0x005C Reverse Solidus
+ {0x00,0x41,0x41,0x7F,0x00}, // ( 61) ] - 0x005D Right Square Bracket
+ {0x04,0x02,0x01,0x02,0x04}, // ( 62) ^ - 0x005E Circumflex Accent
+ {0x40,0x40,0x40,0x40,0x40}, // ( 63) _ - 0x005F Low Line
+ {0x01,0x02,0x04,0x00,0x00}, // ( 64) ` - 0x0060 Grave Accent
+ {0x20,0x54,0x54,0x54,0x78}, // ( 65) a - 0x0061 Latin Small Letter A
+ {0x7F,0x48,0x44,0x44,0x38}, // ( 66) b - 0x0062 Latin Small Letter B
+ {0x38,0x44,0x44,0x44,0x20}, // ( 67) c - 0x0063 Latin Small Letter C
+ {0x38,0x44,0x44,0x48,0x7F}, // ( 68) d - 0x0064 Latin Small Letter D
+ {0x38,0x54,0x54,0x54,0x18}, // ( 69) e - 0x0065 Latin Small Letter E
+ {0x08,0x7E,0x09,0x01,0x02}, // ( 70) f - 0x0066 Latin Small Letter F
+ {0x06,0x49,0x49,0x49,0x3F}, // ( 71) g - 0x0067 Latin Small Letter G
+ {0x7F,0x08,0x04,0x04,0x78}, // ( 72) h - 0x0068 Latin Small Letter H
+ {0x00,0x44,0x7D,0x40,0x00}, // ( 73) i - 0x0069 Latin Small Letter I
+ {0x20,0x40,0x44,0x3D,0x00}, // ( 74) j - 0x006A Latin Small Letter J
+ {0x7F,0x10,0x28,0x44,0x00}, // ( 75) k - 0x006B Latin Small Letter K
+ {0x00,0x41,0x7F,0x40,0x00}, // ( 76) l - 0x006C Latin Small Letter L
+ {0x7C,0x04,0x18,0x04,0x7C}, // ( 77) m - 0x006D Latin Small Letter M
+ {0x7C,0x08,0x04,0x04,0x78}, // ( 78) n - 0x006E Latin Small Letter N
+ {0x38,0x44,0x44,0x44,0x38}, // ( 79) o - 0x006F Latin Small Letter O
+ {0x7C,0x14,0x14,0x14,0x08}, // ( 80) p - 0x0070 Latin Small Letter P
+ {0x08,0x14,0x14,0x18,0x7C}, // ( 81) q - 0x0071 Latin Small Letter Q
+ {0x7C,0x08,0x04,0x04,0x08}, // ( 82) r - 0x0072 Latin Small Letter R
+ {0x48,0x54,0x54,0x54,0x20}, // ( 83) s - 0x0073 Latin Small Letter S
+ {0x04,0x3F,0x44,0x40,0x20}, // ( 84) t - 0x0074 Latin Small Letter T
+ {0x3C,0x40,0x40,0x20,0x7C}, // ( 85) u - 0x0075 Latin Small Letter U
+ {0x1C,0x20,0x40,0x20,0x1C}, // ( 86) v - 0x0076 Latin Small Letter V
+ {0x3C,0x40,0x30,0x40,0x3C}, // ( 87) w - 0x0077 Latin Small Letter W
+ {0x44,0x28,0x10,0x28,0x44}, // ( 88) x - 0x0078 Latin Small Letter X
+ {0x0C,0x50,0x50,0x50,0x3C}, // ( 89) y - 0x0079 Latin Small Letter Y
+ {0x44,0x64,0x54,0x4C,0x44}, // ( 90) z - 0x007A Latin Small Letter Z
+ {0x00,0x08,0x36,0x41,0x00}, // ( 91) { - 0x007B Left Curly Bracket
+ {0x00,0x00,0x7F,0x00,0x00}, // ( 92) | - 0x007C Vertical Line
+ {0x00,0x41,0x36,0x08,0x00}, // ( 93) } - 0x007D Right Curly Bracket
+ {0x02,0x01,0x02,0x04,0x02}, // ( 94) ~ - 0x007E Tilde
+ {0x08,0x14,0x2A,0x14,0x22}, // ( 95) << - 0x00AB Left-Pointing Double Angle Quotation Mark
+ {0x00,0x02,0x05,0x02,0x00}, // ( 96) - 0x00B0 Degree Sign
+// {0x44,0x44,0x5F,0x44,0x44}, // ( 97) +- - 0x00B1 Plus-Minus Sign
+// {0x7E,0x20,0x20,0x10,0x3E}, // ( 98) u - 0x00B5 Micro Sign
+// {0x22,0x14,0x2A,0x14,0x08}, // ( 99) >> - 0x00BB Right-Pointing Double Angle Quotation Mark
+// {0x30,0x48,0x45,0x40,0x20}, // (100) ? - 0x00BF Inverted Question Mark
+// {0x22,0x14,0x08,0x14,0x22}, // (101) x - 0x00D7 Multiplcation Sign
+// {0x08,0x08,0x2A,0x08,0x08}, // (102) + - 0x00F7 Division Sign
+// {0x18,0x14,0x08,0x14,0x0C}, // (103) - 0x221E Infinity
+// {0x44,0x4A,0x4A,0x51,0x51}, // (104) < - 0x2264 Less-Than or Equal to
+// {0x51,0x51,0x4A,0x4A,0x44}, // (105) > - 0x2265 Greater-Than or Equal to
+// {0x54,0x14,0x64,0x08,0x70}, // (106) .: - RF Symbol
+// {0x70,0x7C,0x72,0x7C,0x70}, // (107) ^ - Lock symbol
+// {0x70,0x5C,0x52,0x54,0x70}, // (108) / - Unlock symbol
+// {0x0C,0x1E,0x3C,0x1E,0x0C}, // (109) <3 - Heart Symbol
+// {0x18,0x22,0xFF,0x12,0x0C}, // (110) U - USB Symbol
+};
+
+
+static void setStartPage(unsigned char d)
+{
+ WriteCommand(0xB0|d); // Set Page Start Address for Page Addressing Mode
+ // Default => 0xB0 (0x00)
+}
+/* Below are functions used to configure the OLED */
+static void setStartColumn(unsigned char d)
+{
+ WriteCommand(0x00+d%16); // Set Lower Column Start Address for Page Addressing Mode
+ WriteCommand(0x10+d/16); // Set Higher Column Start Address for Page Addressing Mode
+ // Default => 0x10
+}
+
+
+const uint8_t row[4][32] = {
+
+ {0x00,0x00,0x01,0x03,0x07,0x0F,0x1E,0x3C,0x3C,0x7C,0x7C,0x7C,0xFC,0xFF,0xFF,0xFC,0xFC,0xFC,0xFC,0xFF,0x7F,0x7F,0x7F,0x3C,0x3C,0x1C,0x0C,0x06,0x03,0x01,0x00,0x00},
+
+ {0x0F,0x7F,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x3F,0x3F,0x7F,0xFF,0xFF,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x7F,0x0F},
+
+ {0xF0,0xFE,0xFF,0xFF,0xFF,0xC7,0x00,0x00,0x00,0x00,0x87,0xC7,0xC7,0xFF,0xFF,0x00,0x00,0x00,0x00,0x87,0x87,0xC7,0xC3,0x03,0x07,0x07,0x0F,0x7F,0xFF,0xFF,0xFE,0xF0},
+
+ {0x00,0x00,0x80,0xC0,0xE0,0xF0,0xF8,0xFC,0xFC,0xFE,0xFE,0xFE,0xFF,0xFF,0xFF,0x1F,0x1F,0x1F,0x1F,0xFF,0xFE,0xFE,0xFE,0xFC,0xFC,0xF8,0xF0,0xE0,0xC0,0x80,0x00,0x00},
+
+};
+
+void ssd1306_clearscreen()
+{
+ uint8_t i = 0;
+ uint8_t page = 0;
+ for(page = 0; page<4; page++)
+ {
+ setStartPage(page);
+ setStartColumn(0);
+ for(i = 0; i<128; i++)
+ {
+ WriteData(0x00);
+ }
+ }
+ WriteData(0x00);
+}
+
+void ssd1306_drawlogo()
+{
+ uint8_t i = 0;
+ setStartPage(3);
+ setStartColumn(0);
+ for(i = 0; i<32; i++)
+ {
+ WriteData(row[0][i]);
+ }
+
+ WriteData(0x00);
+
+ setStartPage(2);
+ setStartColumn(0);
+ for(i = 0; i<32; i++)
+ {
+ WriteData(row[1][i]);
+ }
+ WriteData(0x00);
+
+ setStartPage(1);
+ setStartColumn(0);
+ for(i = 0; i<32; i++)
+ {
+ WriteData(row[2][i]);
+ }
+ WriteData(0x00);
+
+ setStartPage(0);
+ setStartColumn(0);
+ for(i = 0; i < 32; i++)
+ {
+ WriteData(row[3][i]);
+ }
+ WriteData(0x00);
+}
+
+/* Print a single character from font.cpp */
+void ssd1306_drawchar(char ascii, unsigned char row, unsigned char xPos)
+{
+ const char *srcPointer = (char*)-1;
+
+ srcPointer = &fontData[(ascii-32)][0];
+
+ setStartPage(row);
+ setStartColumn(xPos);
+
+ for(uint8_t i = 0; i < 5; i++)
+ {
+ WriteData(*srcPointer);
+ srcPointer++;
+ }
+ WriteData(0x00);
+}
+
+void ssd1306_drawcharbig(char ascii, unsigned char row, unsigned char xPos)
+{
+ const char *srcPointer = (char*)-1;
+
+ srcPointer = &fontData[(ascii-32)][0];
+
+ setStartPage(row-1);
+ setStartColumn(xPos);
+
+ // Write first row
+ for(uint8_t i = 0; i < 5; i++)
+ {
+ uint8_t data = 0;
+ data |= ((*srcPointer) & 0b1000) << 4; // get top 4 bits
+ data |= ((*srcPointer) & 0b1000) << 3; // get top 4 bits
+
+ data |= ((*srcPointer) & 0b0100) << 3; // get top 4 bits
+ data |= ((*srcPointer) & 0b0100) << 2; // get top 4 bits
+
+ data |= ((*srcPointer) & 0b0010) << 2; // get top 4 bits
+ data |= ((*srcPointer) & 0b0010) << 1; // get top 4 bits
+
+ data |= ((*srcPointer) & 0b0001) << 1; // get top 4 bits
+ data |= ((*srcPointer) & 0b0001); // get top 4 bits
+
+ WriteData(data);
+ WriteData(data);
+
+ srcPointer++;
+ }
+ WriteData(0x00);
+
+ srcPointer -= 5;
+
+ setStartPage(row);
+ setStartColumn(xPos);
+
+ // Write second row
+ for(uint8_t i = 0; i < 5; i++)
+ {
+ uint8_t data = 0;
+ data |= (*srcPointer) & 0b10000000; // get top 4 bits
+ data |= ((*srcPointer) & 0b10000000) >> 1; // get top 4 bits
+
+ data |= ((*srcPointer) & 0b01000000) >> 1; // get top 4 bits
+ data |= ((*srcPointer) & 0b01000000) >> 2; // get top 4 bits
+
+ data |= ((*srcPointer) & 0b00100000) >> 2; // get top 4 bits
+ data |= ((*srcPointer) & 0b00100000) >> 3; // get top 4 bits
+
+ data |= ((*srcPointer) & 0b00010000) >> 3; // get top 4 bits
+ data |= ((*srcPointer) & 0b00010000) >> 4; // get top 4 bits
+
+ WriteData(data);
+ WriteData(data);
+
+ srcPointer++;
+ }
+ WriteData(0x00);
+
+}
+
+void ssd1306_drawstring(const char *dataPtr, unsigned char row, unsigned char xPos)
+{
+ char *srcPointer;
+
+ srcPointer = (char*)dataPtr;
+ ssd1306_drawchar(' ',row,xPos); // NBSP must be written first before the string start
+
+ while(1)
+ {
+ ssd1306_drawchar(*srcPointer,row,xPos);
+ srcPointer++;
+ xPos+=6;
+ if(*srcPointer == 0) break;
+ }
+}
+
+
+void ssd1306_drawstringbig(const char *dataPtr, unsigned char row, unsigned char xPos)
+{
+ char *srcPointer;
+
+ srcPointer = (char*)dataPtr;
+ ssd1306_drawcharbig(' ',row,xPos); // NBSP must be written first before the string start
+
+ while(1)
+ {
+ ssd1306_drawcharbig(*srcPointer,row,xPos);
+ srcPointer++;
+ xPos+=12;
+ if(*srcPointer == 0) break;
+ }
+}
+
+
+// vim:softtabstop=4 shiftwidth=4 expandtab
diff --git a/src/system.c b/src/system.c
new file mode 100644
--- /dev/null
+++ b/src/system.c
@@ -0,0 +1,54 @@
+//
+// System: initialize core system peripherals
+//
+
+#include "stm32f3xx_hal.h"
+
+
+// Configure and start system clocks
+void sysclock_init(void)
+{
+ __SYSCFG_CLK_ENABLE();
+
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+
+
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInit;
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL3;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC1;
+ PeriphClkInit.USBClockSelection = RCC_USBPLLCLK_DIV1;
+ PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_DIV1;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+ /* SysTick_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+
+
+
+ __DMA1_CLK_ENABLE();
+}
diff --git a/src/watchdog.c b/src/watchdog.c
new file mode 100644
--- /dev/null
+++ b/src/watchdog.c
@@ -0,0 +1,40 @@
+//
+// Watchdog: configure and initialize the watchdog peripheral
+//
+
+#include "stm32f3xx_hal.h"
+
+#include "config.h"
+#include "watchdog.h"
+
+#ifdef WATCHDOG_ENABLE
+static IWDG_HandleTypeDef hiwdg;
+uint8_t watchdog_enabled = 0;
+#endif
+
+
+// Initialize the watchdog timer
+void watchdog_init(void)
+{
+#ifdef WATCHDOG_ENABLE
+ // ~2 seconds?
+ hiwdg.Instance = IWDG;
+ hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
+ hiwdg.Init.Window = 4095;
+ hiwdg.Init.Reload = 4095;
+ HAL_IWDG_Init(&hiwdg);
+ watchdog_feed();
+ HAL_IWDG_Start(&hiwdg);
+ watchdog_enabled = 1;
+#endif
+}
+
+
+// Feed the watchdog timer
+void watchdog_feed(void)
+{
+#ifdef WATCHDOG_ENABLE
+ if(watchdog_enabled)
+ HAL_IWDG_Refresh(&hiwdg);
+#endif
+}